Integrated Circuit Device and Method

This application is a continuation application of U.S. patent application Ser. No. 18/343,339, filed Jun. 28, 2023, which claims the benefit of U.S. Provisional Application No. 63/486,739, filed Feb. 24, 2023. The above-referenced applications are herein incorporated by reference in their entireties.

An integrated circuit (“IC”) device includes one or more semiconductor devices represented in an IC layout diagram (also referred to as “layout diagram”). A layout diagram is hierarchical and includes modules which carry out higher-level functions in accordance with the semiconductor device's design specifications. The modules are often built from a combination of cells, each of which represents one or more semiconductor structures configured to perform a specific function. Cells having pre-designed layout diagrams, sometimes known as standard cells, are stored in standard cell libraries (hereinafter “libraries” or “cell libraries” for simplicity) and accessible by various tools, such as electronic design automation (EDA) tools, to generate, optimize and verify designs for ICs.

To reduce the sizes of IC devices, sometimes a layer of semiconductor devices is formed, or bonded, over another layer of semiconductor devices. Examples include complementary field effect transistor (CFET) devices in which an upper or top semiconductor device overlies a lower or bottom semiconductor device in a stack configuration.

The following disclosure provides different embodiments, or examples, for implementing features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not limiting. Other components, materials, values, steps, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Source/drain(s) may refer to a source or a drain, individually or collectively dependent upon the context.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In some embodiments, an IC device includes a power delivery structure configured to provide various power supply voltages, e.g., a positive power supply voltage VDD and a reference voltage such as the ground voltage VSS, to various circuits and/or circuit components of the IC device. The power delivery structure is arranged at both a front side and an opposite, back side of the IC device, and comprises one or more power tap structures configured to provide power from one of the front side and the back side to the other side. A chip area occupied by power tap structures or power tap cells is sometimes referred to as a power tap area.

In some embodiments, a power tap structure is embedded in a functional circuit. In at least one embodiment, a power tap structure is configured by one or more local interconnects of one or more CFET devices. In some embodiments, a power tap cell is embedded in a functional cell. As a result, in one or more embodiments, the power tap area of the IC device is advantageously reduced. In some embodiments, a dielectric material, e.g., a low-k material, is formed around a local interconnect of a CFET device configured as a power tap structure. As a result, in one or more embodiments, it is possible to reduce the impact of parasitic capacitance associated with the local interconnect.

is a block diagram of an IC device, in accordance with some embodiments.

In, the IC devicecomprises, among other things, a macro. In some embodiments, the macrocomprises one or more of a memory, a power grid, a cell or cells, an inverter, a latch, a buffer and/or any other type of circuit arrangement that may be represented digitally in a cell library. In some embodiments, the macrois understood in the context of an analogy to the architectural hierarchy of modular programming in which subroutines/procedures are called by a main program (or by other subroutines) to carry out a given computational function. In this context, the IC deviceuses the macroto perform one or more given functions. Accordingly, in this context and in terms of architectural hierarchy, the IC deviceis analogous to the main program and the macrois analogous to subroutines/procedures. In some embodiments, the macrois a soft macro. In some embodiments, the macrois a hard macro. In some embodiments, the macrois a soft macro which is described digitally in register-transfer level (RTL) code. In some embodiments, synthesis, placement and routing have yet to have been performed on the macrosuch that the soft macro can be synthesized, placed and routed for a variety of process nodes. In some embodiments, the macrois a hard macro which is described digitally in a binary file format (e.g., Graphic Database System II (GDSII) stream format), where the binary file format represents planar geometric shapes, text labels, other information and the like of one or more layout-diagrams of the macroin hierarchical form. In some embodiments, synthesis, placement and routing have been performed on the macrosuch that the hard macro is specific to a particular process node.

The macroincludes a regionwhich comprises a functional circuit with a power tap structure embedded therein. In some embodiments, the regioncomprises a substrate having circuitry formed thereon, in a front-end-of-line (FEOL) fabrication. Furthermore, above and/or below (e.g., on a front side and/or a back side of) the substrate, the regioncomprises various metal layers that are stacked over and/or under insulating layers in a Back End of Line (BEOL) fabrication. The BEOL provides a power network and/or routing for circuitry of the IC device, including the macroand the region.

is a schematic perspective view of an IC device, in accordance with some embodiments. In at least one embodiment, the IC devicecorresponds to the IC deviceand/or includes a circuit region corresponding to the regionin. For simplicity, some components of the IC deviceare omitted or schematically illustrated in. Various components of an IC device are described with respect to.

The IC devicecomprises a power delivery structure, and at least one functional circuitcoupled to and powered by power delivered through the power delivery structure. The power delivery structurecomprises a back side power delivery network schematically represented by a first power railand a second power rail, a plurality of front side power rails,,, a plurality of back side power rails,, and a plurality of power tap structures-.

The power delivery network is arranged on a back side of the IC devicewhich further includes a front side opposite to the back side in a thickness direction (e.g., a Z axis) of the IC device. In some embodiments, the front side and back side of the IC devicecorrespond to a front side and a back side of the functional circuit, and/or to a front side and a back side of a substrate (not shown) on which the functional circuitis arranged. In at least one embodiment, the front side is one of a first side and a second side, and the back side is the other of the first side and the second side. The power delivery network comprises a plurality of back side metal layers and back side via layers as described herein, and is configured to receive power from a power supply, and deliver the received power to the functional circuit. The power supply provides a first power supply voltage, and a second power supply voltage different from the first power supply voltage. The first power railof the power delivery network is configured to receive the first power supply voltage, and deliver the first power supply voltage to the front side power railthrough the back side metal layers and via layers schematically designated at, and the power tap structures,. The second power railof the power delivery network is configured to receive the second power supply voltage, and deliver the second power supply voltage to the back side power railthrough the back side metal layers and via layers schematically designated at. In the example configuration in, the first power supply voltage is VSS and the second power supply voltage is VDD. Other configurations where the first power supply voltage is VDD and the second power supply voltage is VSS within the scopes of various embodiments. Power rails configured to receive and deliver VSS are sometimes referred to herein as VSS power rails, and power rails configured to receive and deliver VDD are sometimes referred to herein as VDD power rails. In some embodiments, the power delivery network comprises multiple VSS power rails and multiple VDD power rails alternatingly arranged in a direction (e.g., Y axis) transverse to a lengthwise direction (e.g., X axis) of the VSS power rails and VDD power rails.

The front side power rails,,are configured to carry the first power supply voltage. In the example configuration in, the first power supply voltage is VSS, and the front side power rails,,are VSS power rails arranged in a front side Mlayer. The IC devicefurther comprises other front side metal layers, such as, M, M, or the like, and front side via layers, such as V, V, or the like, as described herein. The VSS power railis electrically coupled by Vvias, such as, and Mconductive patterns, such as, to deliver VSS received from the VSS power railon the back side to the VSS power rails,. In some embodiments, one or more of the VSS power rails,is configured to receive VSS from a VSS power rail similar to the VSS power rail. For example, as illustrated in, the VSS power railis configured to receive VSS from the back side through the power tap structures,. Other configurations are within the scopes of various embodiments.

The back side power rails,are configured to carry the second power supply voltage. In the example configuration in, the second power supply voltage is VDD, and the back side power rails,are VDD power rails arranged in a back side BMlayer. The IC devicefurther comprises other back side metal layers, such as, BM, BM, or the like, and back side via layers, such as BV, BV, or the like, as described herein. In some embodiments, the VDD power railis configured to receive VDD from the VDD power rail. In at least one embodiment, the VDD power railis configured to receive VDD from a VDD power rail similar to the VDD power rail.

The functional circuitis arranged between the VSS power rails,,and the VDD power rails,in the thickness direction (e.g., the Z axis) of the IC device. The functional circuitis electrically coupled to and powered by one or more of the VSS power rails,,and one or more of the VDD power rails,. In the example configuration in, the functional circuitcomprises a plurality of semiconductor devices coupled to the VDD power railand/or the VSS power rail. The functional circuit, powered by VDD and VSS, is configured to perform one or more functions of the IC device. In some embodiments, the functional circuitcomprises one or more active devices, passive devices, logic circuits, or the like. Examples of logic circuits include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), MUX, Flip-flop, BUFF, Latch, delay, clock, memory, or the like. Example memory cells include, but are not limited to, a static random access memory (SRAM), a dynamic RAM (DRAM), a resistive RAM (RRAIVI), a magnetoresistive RAM (MRAM), a read only memory (ROM), or the like. Examples of active devices or active elements include, but are not limited to, transistors, diodes, or the like. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, resistors, or the like. In some embodiments, a functional circuit of an IC device corresponds to a functional cell, or a set of functional cells, placed in a layout diagram of the IC device, as described herein.

The power tap structures-are each configured to electrically couple a corresponding front side power rail to a conductor on the back side, e.g., a back side conductive pattern or a back side power rail. For example, the power tap structureelectrically couples the VSS power railon the front side to a BMconductive patternon the back side. The BMconductive patternis electrically coupled to the VSS power railof the power delivery network, to deliver VSS to the VSS power railthrough the power tap structure. Similarly, the power tap structureelectrically couples the VSS power railon the front side to a BMconductive patternon the back side. The BMconductive patternis electrically coupled to the VSS power railof the power delivery network, to deliver VSS to the VSS power railthrough the power tap structure. In the example configuration in, the BMconductive patternis physically separated from the BMconductive pattern. In some embodiments, the BMconductive patternand BMconductive patternare integral parts of a further back side power rail, e.g., a VSS power rail, in the BMlayer. In some embodiments, the BMlayer comprises multiple VSS power rails arranged alternatingly with the VDD power rails,. The power tap structures,are configured to provide electrical connections similar to those described with respect to the power tap structures,.

At least one of the power tap structures-is in a functional circuit. In the example configuration in, the power tap structures,are included in the functional circuit. In some embodiments, the power tap structures,comprise local interconnects of CFET devices in the functional circuit. In at least one embodiment, the power tap structures,correspond to power tap cells embedded in functional cells corresponding to the functional circuit. In some embodiments, the functional circuitincludes a single power tap structure, e.g., either of the power tap structures,is omitted. In some embodiments, at least one of the power tap structures,is included in a functional circuit in a manner similar to the power tap structures,being included in the functional circuit. In at least one embodiment, at least one of the power tap structures,is an independent power tap structure not included in a functional circuit. For example, an independent power tap structure corresponds to an independent power tap cell not embedded in a functional cell. In some embodiments, power tap structures, including those included in functional circuits and/or independent power tap structures, are distributed uniformly, or substantially uniformly, across a chip area of the IC device.

In at least one embodiment, as described herein, the inclusion of one or more power tap structures in one or more functional circuits of an IC device, or the inclusion of one or more power tap cells in one or more functional cells of a layout diagram of an IC device, makes it possible to advantageously reduce the power tap area and/or to free routing recourses for signals within or between the functional circuits.

includes schematic views at various layers of a layout diagramA of a circuit region of an IC device, in accordance with some embodiments. In some embodiments, the circuit region corresponds to a portion of the regioninand/or to a portion of the IC device. In some embodiments, the circuit region is a cell, and the layout diagramA is a layout of the cell. In at least one embodiment, the layout diagramA is stored as a standard cell in at least one library on a non-transitory computer-readable recording medium, and is read out and placed into a layout diagram of an IC device to be designed and/or manufactured.

In the example configuration in, the circuit region corresponding to the layout diagramA comprises CFET devices each comprising a top semiconductor device and a bottom semiconductor device. The layout diagramA comprises a top layer (or upper layer)corresponding to one or more top semiconductor devices, and a bottom layer (or lower layer)corresponding to one or more bottom semiconductor devices.

The layout diagramA comprises a boundarywhich is the same for the top layerand the bottom layer. In at least one embodiment, the circuit region is a cell and the boundaryis a cell boundary. Examples of cells include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, OR-AND-Invert (OAI), MUX, Flip-flop, BUFF, Latch, delay, clock, memory such as static random-access memory (SRAM), de-coupling capacitor, analog amplifier, logic driver, digital driver, or the like. The boundarycomprises edges,,,. The edges,are elongated along the X axis, and the edges,are elongated along the Y axis. In some embodiments, the X axis is an example of one of a first direction and a second direction, and the Y axis is an example of the other of the first direction and the second direction. The edges,,,are connected together to form the closed boundary. In a place-and-route operation (also referred to as “automated placement and routing (APR)”) described herein, cells are placed in an IC layout diagram in abutment with each other at their respective boundaries. The boundaryis sometimes referred to as “place-and-route boundary” or “prBoundary.” The rectangular shape of the boundaryis an example. Other boundary shapes for various cells are within the scope of various embodiments.

The top layercomprises a layout of one or more top semiconductor devices of a first type, and the bottom layercomprises a layout of corresponding one or more bottom semiconductor devices of a second type different from the first type. In some embodiments, the first type is one of a P-type and an N-type, and the second type is the other of the P-type and N-type.

Each of the top layerand bottom layercomprises at least one active region. Active regions are sometimes referred to as oxide-definition (OD) regions or source/drain regions, and are schematically illustrated in the drawings with the label “OD.” For example, the top layercomprises an active region OD-, and the bottom layercomprises an active region OD-. In the layout diagramA, the active regions OD-, OD-overlap each other, or are stacked one over another, along a thickness direction of a substrate as described herein, and are commonly referred to as an active region OD.

In at least one embodiment, the active regions OD-, OD-are over a first side, or a front side, of the substrate as described herein. The active regions OD-, OD-are elongated along the X axis. The active regions OD-, OD-include P-type dopants and/or N-type dopants to form one or more circuit elements or semiconductor devices. Examples of circuit elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductors (CMOS) transistors, P-channel metal-oxide semiconductors (PMOS), N-channel metal-oxide semiconductors (NMOS), bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, P-channel and/or N-channel field effect transistors (PFETs/NFETs), FinFETs, planar MOS transistors with raised source/drains, nanosheet FETs, nanowire FETs, or the like. An active region configured to form one or more PMOS devices is sometimes referred to as “PMOS active region,” and an active region configured to form one or more NMOS devices is sometimes referred to as “NMOS active region.” In the example configuration described with respect to, the active region OD-comprises an NMOS active region, and the active region OD-comprise a PMOS active region. In some embodiments, the active region OD-comprises a PMOS active region, and the active region OD-comprise an NMOS active region.

The top layerfurther comprises a plurality of gate regions-, and the bottom layerfurther comprises a plurality of corresponding gate regions-. In the layout diagramA, the gate regions-correspondingly overlap, or are correspondingly stacked over, the gate regions-along the thickness direction of the substrate as described herein. In some embodiments, one or more of the gate regions-is electrically coupled to, or made integral with, the corresponding, underlying one or more of the gate regions-. In some embodiments, one or more of the gate regions-is physically separated, and electrically disconnected, from the corresponding, underlying one or more of the gate regions-.

The gate regions-and gate regions-are correspondingly over the active regions OD-, OD-. The gate regions-,-are elongated along the Y axis. The gate regions-are arranged along the X axis at a regular pitch designated at CPP (contacted poly pitch) in. Likewise, the gate regions-are arranged along the X axis at a regular pitch CPP. CPP is a center-to-center distance along the X axis between two directly adjacent gate regions. Two gate regions are considered directly adjacent (or immediately adjacent) where there are no other gate regions therebetween. CFET devices corresponding to immediately adjacent gate regions are considered as immediately adjacent CFET devices. A width (or cell pitch) of the circuit region (or cell) in the layout diagramA along the X axis is 5 CPPs in the example configuration in. Gates corresponding to the gate regions-,-comprise a conductive material, such as, polysilicon, which is sometimes referred to as “poly.” Other conductive materials for gates, such as metals, are within the scope of various embodiments. Gate regions are sometimes schematically illustrated in the drawings with the label “PO.”

In the example configuration in, the gate regions-,-are functional gate regions which, together with the active regions OD-, OD-, configure a plurality of semiconductor devices or transistors, as described herein. In some embodiments, the gate regions,,,are non-functional, or dummy, gate regions. Dummy gate regions are not configured to form transistors together with the underlying active regions, and/or one or more transistors formed by dummy gate regions together with the underlying active regions are not electrically coupled to other circuitry in the circuit region of the layout diagramA and/or the IC device corresponding to the layout diagramA. In at least one embodiment, non-functional or dummy gates corresponding to dummy gate regions include dielectric material in a manufactured IC device. Other configurations are within the scopes of various embodiments. For example, in one or more embodiments, at least one of the gate regions-,-is a dummy gate region, and/or at least one of the gate regions,,,is a functional gate region.

The edgeof the boundarycoincides with centerlines of the gate regions,. The edgeof the boundarycoincides with centerlines of the gate regions,. Between the edges,and along the Y axis, the circuit region of the layout diagramA contains one NMOS active region, i.e., OD-, and one PMOS active region, i.e., OD-, and is considered to have a height corresponding to one cell height CH. Another cell or circuit region containing along the Y axis two PMOS active regions and two NMOS active regions is considered to have a height corresponding to a double cell height 2 CH, or the like.

The top layerfurther comprises a plurality of semiconductor devices configured by the gate regions-and the active region OD-. The bottom layerfurther comprises a plurality of semiconductor devices configured by the gate regions-and the active region OD-. For simplicity, a semiconductor device or transistor is referred herein by the same reference numeral of the corresponding gate region. For example, the top layercomprises top semiconductor devices-which are NMOS transistors, and the bottom layercomprises bottom semiconductor devices-which are PMOS transistors. In one or more embodiments, the top semiconductor devices include PMOS transistors, and the bottom semiconductor devices include NMOS transistors. The layout diagramA comprises a plurality of CFET devices each comprising a top semiconductor device over a corresponding bottom semiconductor device. For simplicity, a CFET device is referred herein by the same reference numeral of the gate region of the top semiconductor device. For example, the CFET device comprising the top semiconductor devicestacked over the bottom semiconductor deviceis referred to as CFET device.

The layout diagramA further comprises a cut-gate region(e.g., a mask) corresponding to where a gate region is disconnected. Cut-gate regions are sometimes schematically illustrated in the drawings with the label “CPO” (cut-PO). A CPO region is common to both the upper layerand the bottom layer. In the example configuration in, the CPO regionextends along the X axis and transversely to the gate regions-at the upper layerand to the gate regions-at the bottom layer. The gate regions-,-do not extend along the Y axis into the CPO region, and are shorter along the Y axis than the gate regions,. The shape of the CPO regioninis an example. Other CPO region shapes are within the scopes of various embodiments. In an IC device in accordance with some embodiments, a CPO region corresponds to a dielectric material.

In some embodiments, the layout diagramA further comprises source/drain contacts in electrical contact with the corresponding source/drains in the active regions OD-, OD-. Source/drain contacts are sometimes referred to as metal-to-device (MD) contacts. Source/drain contacts of top semiconductor devices at the upper layer are sometimes referred to as MD contacts (not shown). Source/drain contacts of bottom semiconductor devices at the lower layer are sometimes referred to as BMD contacts. For simplicity, an MD contact herein refers to either an MD contact at the upper layer or a BMD contact at the lower layer, unless specified otherwise. An MD contact includes a conductive material over a corresponding source/drain in the corresponding active region to define an electrical connection from one or more devices formed in the active region to other internal circuitry of the IC device or to outside circuitry. MD contacts are arranged alternatingly with the gate regions along the X axis. A pitch, i.e., a center-to-center distance along the X axis, between directly adjacent MD contacts is the same as the pitch CPP between directly adjacent gate regions. Example MD and BMD contacts are described with respect to one or more of.

In some embodiments, the layout diagramA further comprises a source/drain local interconnect (MDLI). An MDLI interconnect is a conductive structure physically arranged between, and electrically coupling, source/drains of a top semiconductor device and the corresponding, underlying bottom semiconductor device. Example MDLI interconnects are described with respect to one or more of.

In some embodiments, the layout diagramA further comprises vias on the corresponding gate regions and/or MD contacts. At the front side or upper layer, a via on a gate region is sometimes referred to as via-to-gate (VG) via, and a via on an MD contact is sometimes referred to as via-to-device (VD) via. At the back side or bottom layer, a via on a gate region is sometimes referred to as a BVG via, and a via on a BMD contact is sometimes referred to as a BVD via. In a manufactured IC device corresponding to the layout diagramA, VD, BVD, VG, BVG vias include a conductive material, e.g., a metal. Other vias configurations are within the scopes of various embodiments. Example VD, BVD, VG vias are described with respect to one or more of.

The VD vias and VG vias are configured to form electrical connections from the corresponding MD contacts and gate regions to conductive patterns in an overlying metal layer, i.e., the Mlayer. Conductive patterns in the Mlayer are indicated herein by a label “M.” The layout diagramA comprises, at the upper layerand in the Mlayer, conductive patterns M, M, M. The conductive pattern Mis configured as a VSS power rail, and extends along the X axis beyond the boundary. In some embodiments, the conductive pattern Mcorresponds to one or more of the VSS power rails,,. The conductive patterns M, Mare configured for signals. In at least one embodiment, the conductive patterns M, Mdo not extend beyond, and are confined within, the boundary. The conductive patterns M, M, Mare correspondingly arranged along Mtracks-. Centerlines of the conductive patterns M, M, Mcoincide with the corresponding Mtracks-. Along the Y axis, the Mtrackis immediately adjacent to the Mtrack, which is immediately adjacent to the Mtrack. Two Mtracks are considered directly adjacent (or immediately adjacent) where there are no other Mtracks therebetween. Mconductive patterns on immediately adjacent Mtracks are considered immediately adjacent. For example, along the Y axis, the conductive pattern Mis immediately adjacent to the conductive pattern Mwhich is immediately adjacent to the conductive pattern M. The conductive pattern Moverlaps the gate regions-,-in the thickness direction. The conductive pattern Moverlaps the gate regions-,-and the active regions OD-, OD-in the thickness direction.

The BVD vias and BVG vias are configured to form electrical connections from the corresponding BMD contacts and gate regions to conductive patterns in a underlying metal layer, i.e., the BMlayer. Conductive patterns in the BMlayer are indicated herein by a label “BM.” The layout diagramA comprises, at the bottom layerand in the BMlayer, conductive patterns BM, BM, BM. The conductive pattern BMis configured as a VDD power rail, and extends along the X axis beyond the boundary. In some embodiments, the conductive pattern BMcorresponds to one or more of the VDD power rails,. In at least one embodiment, the conductive pattern BMcorresponds to one or more of the BMconductive patterns,. In some embodiments, the conductive pattern BMcorresponds to a VSS power rail in the BMlayer, and extends along the X axis beyond the boundary. In at least one embodiment, the conductive patterns BM, BMdo not extend beyond, and are confined within, the boundary. The conductive patterns BM, BM, BMare correspondingly arranged along BMtracks-. Centerlines of the conductive patterns BM, BM, BMcoincide with the corresponding BMtracks-. Along the Y axis, the BMtrackis immediately adjacent to the BMtrack, which is immediately adjacent to the BMtrack. Two BMtracks are considered directly adjacent (or immediately adjacent) where there are no other BMtracks therebetween. BMconductive patterns on immediately adjacent BMtracks are considered immediately adjacent. For example, along the Y axis, the conductive pattern BMis immediately adjacent to the conductive pattern BMwhich is immediately adjacent to the conductive pattern BM. The conductive pattern BMoverlaps the gate regions-,-in the thickness direction. The VDD power rail BMoverlaps the gate regions-,-and the active regions OD-, OD-in the thickness direction.

In some embodiments, the layout diagramA corresponds to a functional circuit. For example, the CFET devices in the layout diagramA are electrically coupled into a functional circuit by one or more MD contacts, MDLI interconnects, VD, BVD, VG, BVG vias, Mconductive patterns, BMconductive patterns, and/or further metal layers and/or via layers on the front side and/or the back side. CFET devices electrically coupled into a functional circuit are sometimes referred to as functional CFET devices. The layout diagramA further comprises an embedded power tap cell corresponding to a power tap structure.

The power tap structure in the layout diagramA comprises a VDR (VD rail) via, a local interconnect (herein referred to as VLI interconnect), a BMD contact, and a BVD via. The VDR viais under and in electrical contact with the conductive pattern or VSS power rail M. The VLI interconnectis under and in electrical contact with the VDR via. The BMD contactis under and in electrical contact with the VLI interconnect. The BVD viais under and in electrical contact with the BMD contact. The BVD viais further over and in electrical contact with the conductive pattern BM. As a result, the VSS power rail Mis electrically coupled in the thickness direction to the conductive pattern BMto receive VSS therefrom.

The VDR viais a VD via and, in some embodiments, is manufactured together with other VD vias. The VSS power rail Moverlaps, in the thickness direction, at least partially the VDR via. In the example configuration in, the VDR viais larger than other VD vias for signals, the VDR viais elongated along the X axis in the same direction as the VSS power rail M, and the VSS power rail Moverlaps, in the thickness direction, an entirety of the VDR via.

The VLI interconnectextends from the top semiconductor devices to the bottom semiconductor devices, and is included in both the upper layerand the bottom layerof the layout diagramA. The VLI interconnectis confined within the CPO region. In a manufactured IC device, the dielectric material corresponding to the CPO regionsurrounds the VLI interconnecton all sides as seen in a plan view, and electrically isolates the VLI interconnectfrom other conductive or circuit features. The VLI interconnectoverlaps at least partially the VDR viaand the BMD contact. In the example configuration in, the VLI interconnectis elongated along the X axis in the same direction as the VSS power rail Mand the VDR via, and has a length of about 2 CPPs along the X axis. In at least one embodiment, a length of the VLI interconnectalong the X axis is at least one CPP.

In the example configuration in, the BMD contactis not formed on or in electrical contact with an active region. In some embodiments, the BMD contactis manufactured together with other BMD contacts which are in electrical contact with an active region in the bottom layer. In some embodiments, the BMD contactis in electrical contact with the active region in the bottom layer. In the example configuration in, the BMD contactand the conductive pattern BMoverlap, in the thickness direction, an entirety of the BVD via.

All features of a power tap structure, i.e., the VDR via, VLI interconnect, BMD contact, BVD via, are confined within the boundaryof the layout diagramA. As such, the layout diagramA is an example of a functional cell having embedded therein a power tap cell. By embedding power tap cells in functional cells, it is possible in one or more embodiments to reduce the number of independent power tap cells, i.e., power tap cells outside functional cells and/or configured for power delivery only and/or without other functions. As a result, it is possible in one or more embodiments to advantageously reduce the power tap area of manufactured IC devices.

In some other approaches where CFET devices are not used, if a power tap cell was to be incorporated or embedded in a functional cell, a gate connection between an NMOS and a PMOS of the functional cell would be disconnected or separated. In contrast, in one or more embodiments with CFET devices, because the gate connection between an NMOS and a PMOS of a CFET device is in the vertical or thickness direction, it is possible to incorporate or embed a power tap cell in a functional cell without separating the gate connection of the NMOS and PMOS.

In some other approaches, an independent power tap cell comprises a feed through via that electrically couples an Mjog of a two-dimensional (2D) Mconductive pattern with a BMjog of a 2D BMconductive pattern. The Mjog and/or BMjog render(s) one or more Mand/or BMconductive patterns adjacent to the 2D Mand/or 2D BMconductive patterns unavailable for other signals, e.g., for connections inside a cell or for cell interconnects. In contrast, in one or more embodiments, by incorporating a power tap cell in a functional cell and/or by configuring a power tap cell without an Mjog and/or a BMjog, it is possible to maximize usage of Mand/or BMrecourses for signals within or between functional cells.

is a schematic perspective view of a circuit region of an IC deviceB, in accordance with some embodiments. In some embodiments, the circuit region of the IC deviceB corresponds to the layout diagramA. For simplicity, corresponding components inare designated by the same reference numerals.

The IC deviceB comprises a power tap structureelectrically coupling the VSS power rail Mat the front side to the conductive pattern BMat the back side. The power tap structurecomprises the VDR via, VLI interconnect, BMD contact, BVD via. In the example configuration in, a portionof the VLI interconnectlands on an upper surfaceof the BMD contact. Another portionof the VLI interconnectlands outside the BMD contactand protrudes, in the thickness direction, below the upper surfaceof the BMD contact. This is an example, and other VLI interconnect configurations are within the scopes of various embodiments. In some embodiments, at least a portion of the VLI interconnectis formed together with the BMD contact.

In the example configuration in, the conductive pattern BMis a VSS power rail in the BMlayer. In at least one embodiment where the structure shown inis repeated along the Y axis, an alternating arrangement of VSS power rails and VDD power rails in the BMlayer is obtained. In some embodiments, the asymmetrical power placement of VSS power rail Mand VDD power rail BMmake it possible to release Mresource for cell interconnects. In at least one embodiment, one or more advantages described herein are achievable by the IC deviceB.

are schematic cross-sectional views of a circuit region of an IC device, in accordance with some embodiments. In some embodiments, the IC devicecorresponds to one or more of the IC device, IC device, layout diagramA, IC deviceB.corresponds to an X axis cross-sectional view taken along line A-A′ in, andcorresponds to a Y axis cross-sectional view taken along line B-B′ in. For simplicity, corresponding components inare designated by the same reference numerals.

As illustrated in, the IC devicecomprises a substratehaving a front side, and a back sideopposite to the front sidein a thickness direction of the substrate. In some embodiments, the substratecomprises a semiconductor material, such as silicon, silicon germanium (SiGe), gallium arsenic, or other suitable semiconductor materials. In some embodiments, the substratecomprises a dielectric material, such as silicon nitride, silicon oxide, ceramic, glass, or other suitable materials. In some embodiments, the substratecomprises a multi-layer structure. In some embodiments, the substrateis omitted, or comprises an insulation layer that replaces an initial semiconductor bulk used during manufacture.

The IC devicefurther comprises CFET devices,over the front sideof the substrate. The CFET deviceis described in detail herein. The CFET deviceis configured similarly to the CFET device.