Stiffener Structure with Beveled Sidewall for Footprint Reduction and Methods for Forming the Same

This application is a divisional of U.S. patent application Ser. No. 17/837,160 entitled “Stiffener Structure With Beveled Sidewall For Footprint Reduction And Methods For Forming The Same” filed Jun. 10, 2022, the entire contents of which are hereby incorporated by reference for all purposes.

Semiconductor dies within chip package structures are becoming increasingly complex, requiring more power and increased thermal regulation mechanisms to operate efficiently and at higher frequencies. Simultaneously, efforts are made to minimize the footprints of semiconductor dies within semiconductor designs, as with chip package structures and accompanying components, despite the increased complexity of new designs. The increased complexity, power requirements, and thermal regulation mechanisms of semiconductor designs ultimately necessitates large device footprints and leaves little room for tertiary components on a package substrate such as surface mount devices (SMDs).

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Unless explicitly stated otherwise, each element having the same reference numeral is presumed to have the same material composition and to have a thickness within a same thickness range.

Various embodiments of the present disclosure are directed to chip package structures, and particularly to beveled stiffener structures within chip package structures. Generally, the various embodiment methods and structures may be used to provide a chip package structure such as a fan-out wafer level package (FOWLP) and fan-out panel level package (FOPLP). While the various embodiments of the present disclosure are described using an FOWLP configuration, implementation of the various embodiment methods and structures in an FOPLP configuration or any other fan-out package configuration are within the contemplated scope of disclosure. The various embodiment chip package structures may have beveled stiffener structures including at least one beveled sidewall. Various embodiments may include at least one tapered inner sidewall, and optionally at least one tapered outer sidewall to reduce the overall footprint of the beveled stiffener structure while retaining the structural integrity of the stiffener structure (i.e., constrain chip package warpage). The beveled stiffener structure may be formed and otherwise shaped to reduce the footprint of a stiffener structure mounted onto a package substrate to provide additional space for other chip package structures uses and components. For example, a beveled stiffener structure may allow for increased surface area for additional surface mount devices (SMDs), such that at least a portion of the SMDs are positioned vertically beneath an overhang of and within a beveled-out portion of the beveled stiffener structure. As another example, the beveled stiffener structure may be formed to be positioned as close to a fan-out package as possible and over an underfill material (e.g., underfill material is beneath an overhang of the beveled stiffener structure), thereby reducing the overall size of the chip package structure on a printed circuit board.

is a vertical cross-sectional view of a region of a structure that includes a first carrier substrate and redistribution structures according to an embodiment of the present disclosure.is a top-down view of the structure of. Referring to, an intermediate structure according to an embodiment of the present disclosure includes a first carrier substrateand redistribution structuresformed on a front side surface of the first carrier substrate. The first carrier substratemay include an optically transparent substrate such as a glass substrate or a sapphire substrate. The diameter of the first carrier substratemay be in a range from 150 mm to 290 mm, although lesser and greater diameters may be used. In addition, the thickness of the first carrier substratemay be in a range from 500 microns to 2,000 microns, although lesser and greater thicknesses may also be used. Alternatively, the first carrier substratemay be provided in a rectangular panel format.

A first adhesive layermay be applied to the front-side surface of the first carrier substrate. In one embodiment, the first adhesive layermay be a light-to-heat conversion (LTHC) layer. The LTHC layer may be a solvent-based coating applied using a spin coating method. The LTHC layer may convert ultraviolet light to heat, which may cause the material of the LTHC layer to lose adhesion. For example, the LTHC layer may include Light-To-Heat Conversion Release Coating (LTHC) Ink™ that is commercially available. Alternatively, the first adhesive layermay include a thermally decomposing adhesive material. For example, the first adhesive layermay include an acrylic pressure-sensitive adhesive that decomposes at an elevated temperature. The debonding temperature of the thermally decomposing adhesive material may be in a range from 150 degrees to 200 degrees Celsius.

Redistribution structuresmay be formed over the first adhesive layer. Specifically, a redistribution structuremay be formed within each unit area UA, which is the area of a repetition unit that is repeated in a two-dimensional array over the first carrier substrate. Each redistribution structuremay include redistribution dielectric layersand redistribution wiring interconnects. The redistribution dielectric layersinclude a respective dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable materials may be within the contemplated scope of disclosure. Each redistribution dielectric layermay be formed by spin coating and drying of the respective dielectric polymer material. The thickness of each redistribution dielectric layermay be in a range from 2 microns to 40 microns, such as from 4 microns to 20 microns. Each redistribution dielectric layermay be patterned, for example, by applying and patterning a respective photoresist layer thereabove, and by transferring the pattern in the photoresist layer into the redistribution dielectric layerusing an etch process such as an anisotropic etch process. The photoresist layer may be subsequently removed, for example, by ashing.

Each of the redistribution wiring interconnectsmay be formed by depositing a metallic seed layer by sputtering, by applying and patterning a photoresist layer over the metallic seed layer to form a pattern of openings through the photoresist layer, by electroplating a metallic fill material (such as copper, nickel, or a stack of copper and nickel), by removing the photoresist layer (for example, by ashing), and by etching portions of the metallic seed layer located between the electroplated metallic fill material portions. The metallic seed layer may include, for example, a stack of a titanium barrier layer and a copper seed layer. The titanium barrier layer may have thickness in a range from 50 nm to 400 nm, and the copper seed layer may have a thickness in a range from 100 nm to 500 nm. The metallic fill material for the redistribution wiring interconnectsmay include copper, nickel, or copper and nickel. Other suitable metallic fill materials are within the contemplated scope of disclosure. The thickness of the metallic fill material that is deposited for each redistribution wiring interconnectmay be in a range from 2 microns to 40 microns, such as from 4 microns to 10 microns, although lesser or greater thicknesses may also be used. The total number of levels of wiring in each redistribution structure(i.e., the levels of the redistribution wiring interconnects) may be in a range from 1 to 10. A periodic two-dimensional array (such as a rectangular array) of redistribution structuresmay be formed over the first carrier substrate. Each redistribution structuremay be formed within a unit area UA, which is a unit of repetition for a two-dimensional array of redistribution structures. The layer including all redistribution structuresis herein referred to as a redistribution structure layer. The redistribution structure layer includes a two-dimensional array of redistribution structures. In one embodiment, the two-dimensional array of redistribution structuresmay be a rectangular periodic two-dimensional array of redistribution structureshaving a first periodicity along a first horizontal direction hdand having a second periodicity along a second horizontal direction hdthat is perpendicular to the first horizontal direction hd. In some embodiments, the redistribution wiring interconnectsmay include alternately stacked wiring portions and via structures.

is vertical cross-sectional view of a region of the structure after formation of redistribution-side metal pad structures and first solder material portions according to an embodiment of the present disclosure.is a top-down view of the structure of. Referring to, at least one metallic material and a first material may be sequentially deposited over the front-side surface of the redistribution structures. The at least one metallic material comprises a material that may be used for metallic pads, such as copper. The thickness of the at least one metallic material may be in a range from 5 microns to 60 microns, such as from 10 microns to 30 microns, although lesser and greater thicknesses may also be used. The first material may comprise a first material suitable for C2 bonding, i.e., for microbump bonding. The thickness of the first material may be in a range from 2 microns to 30 microns, such as from 4 microns to 15 microns, although lesser and greater thicknesses may also be used.

The first material and the at least one metallic material may be patterned into discrete arrays of first solder material portionsand arrays of metal pad structures, which are herein referred to as arrays of redistribution-side metal pad structures. Each array of redistribution-side metal pad structuresis formed within a respective unit area UA. Each array of first solder material portionsis formed within a respective unit area UA. Each first solder material portionmay have a same horizontal cross-sectional shape as an underlying redistribution-side metal pad structures.

In one embodiment, the redistribution-side metal pad structuresmay include, and/or may consist essentially of, copper or a copper-containing alloy. Other suitable materials are within the contemplated scope of disclosure. The thickness of the redistribution-side metal pad structuresmay be in a range from 5 microns to 60 microns, although lesser or greater thicknesses may also be used. The redistribution-side metal pad structuresmay have horizontal cross-sectional shapes of rectangles, rounded rectangles, circles, regular polygons, irregular polygons, or any other two-dimensional curvilinear shape having a closed periphery. In one embodiment, redistribution-side metal pad structuresmay be configured for microbump bonding (i.e., C2 bonding), and may have a thickness in a range from 10 microns to 30 microns, although lesser or greater thicknesses may also be used. In this embodiment, each array of redistribution-side metal pad structures, such as copper pillars or under bump metallurgies (UBM), may be portions of an array of microbumps having a lateral dimension in a range from 10 microns to 25 microns, and having a pitch in a range from 20 microns to 50 microns.

is a vertical cross-sectional view of a region the structure after attaching semiconductor dies according to an embodiment of the present disclosure.is a top-down view of the structure of.is a magnified vertical cross-sectional view of a high bandwidth memory die.

Referring to, a set of at least one semiconductor die (,) may be bonded to each redistribution structure. In one embodiment, the redistribution structuresmay be arranged as a two-dimensional periodic array, and multiple sets of at least one semiconductor die (,) may be bonded to the redistribution structuresas a two-dimensional periodic rectangular array of sets of the at least one semiconductor die (,). Each set of at least one semiconductor die (,) includes at least one semiconductor die. Each set of at least one semiconductor die (,) may include any set of at least one semiconductor die known in the art. In one embodiment, each set of at least one semiconductor die (,) may comprise a plurality of semiconductor dies (,). For example, each set of at least one semiconductor die (,) may include at least one system-on-chip (SoC) dieand/or at least one memory die. Each SoC diemay comprise an application processor die, a central processing unit die, or a graphic processing unit die. In one embodiment, the at least one memory diemay comprise a high bandwidth memory (HBM) die that includes a vertical stack of static random-access memory dies. In one embodiment, the at least one semiconductor die (,) may include at least one system-on-chip (SoC) die and a high bandwidth memory (HBM) die including a vertical stack of static random-access memory (SRAM) dies that are interconnected to one another through microbumps and are laterally surrounded by an epoxy molding material enclosure frame.

Referring to, each semiconductor die (,) may comprise a respective array of die-side metal pad structures (,). For example, each SoC diemay comprise an array of SoC metal pad structures, and each memory diemay comprise an array of memory-die metal pad structures. Each of the semiconductor dies (,) may be positioned in a face-down position such that die-side metal pad structures (,) face the first solder material portions. Each set of at least one semiconductor die (,) may be placed within a respective unit area UA. Placement of the semiconductor dies (,) may be performed using a pick and place apparatus so that each of the die-side metal pad structures (,) is placed on a top surface of a respective one of the first solder material portions.

Generally, a redistribution structureincluding redistribution-side metal pad structuresthereupon may be provided, and at least one semiconductor die (,) including a respective set of die-side metal pad structures (,) may be provided. The at least one semiconductor die (,) may be bonded to the redistribution structureusing first solder material portionsthat are bonded to a respective redistribution-side metal pad structureand to a respective one of the die-side metal pad structures (,). Generally, a first array of metallic joint structures may be formed. Each metallic joint structure may comprise a first metal pad structure (such as a redistribution-side metal pad structure), a second metal pad structure (such as a die-side metal pad structure (,)), and a bump material portion (such as a first solder material portion).

Referring to, a high bandwidth memory (HBM) dieis illustrated, which may be used as a memory diewithin the structures of. The HBM diemay include a vertical stack of static random access memory dies (,,,,) that are interconnected to one another through microbumpsand are laterally surrounded by an epoxy molding material enclosure frame. The gaps between vertically neighboring pairs of the random-access memory dies (,,,,) may be filled with a HBM underfill material portionsthat laterally surrounds a respective set of microbumps. The HBM diemay comprise an array of memory-die metal pad structuresconfigured to be bonded to a subset of an array of redistribution-side metal pad structureswithin a unit area UA. The HBM diemay be configured to provide a high bandwidth as defined under JEDEC standards, i.e., standards defined by The JEDEC Solid State Technology Association.

is a vertical cross-sectional view of a region of the structure after formation of first underfill material portions according to an embodiment of the present disclosure.a top-down view of the structure ofaccording to an embodiment of the present disclosure. Referring to, a first underfill material may be applied into each gap between the redistribution structuresand sets of at least one semiconductor die (,) that may be bonded to the redistribution structures.a top down view of the structure of. The first underfill material may comprise any underfill material known in the art. A first underfill material portionmay be formed within each unit area UA between a redistribution structureand an overlying set of at least one semiconductor die (,). The first underfill material portionsmay also be referred to as microbump underfill fillet portions or microbump underfill material portions. The first underfill material portionsmay be formed by injecting the first underfill material around a respective array of first solder material portionsin a respective unit area UA. Any known underfill material application method may be used, which may be, for example, the capillary underfill method, the molded underfill method, or the printed underfill method. In some embodiments, the outer periphery of the first underfill material portionmay have rounded corners in a plan view. In some embodiments, the outer periphery of the first underfill material portionmay have squared, or perpendicular corners in a plan view.

Within each unit area UA, a first underfill material portionmay laterally surround, and contact, each of the first solder material portionswithin the unit area UA. The first underfill material portionmay be formed around, and contact, the first solder material portions, the redistribution-side metal pad structures, and the die-side metal pad structures (,) in the unit area UA. In some embodiments, the exposed outermost surfaces of the first underfill material portionsurrounding sidewalls of the at least one semiconductor (,) may have a curved or concave shape with varying taper angles formed as a result of the deposition process. In other embodiments, the exposed outermost surfaces of the first underfill material portionsurrounding sidewalls of the at least one semiconductor (,) may have a straight taper or even a convex shape.

Each redistribution structurein a unit area UA comprises redistribution-side metal pad structures. At least one semiconductor die (,) comprising a respective set of die-side metal pad structures (,) is attached to the redistribution-side metal pad structuresthrough a respective set of first solder material portionswithin each unit area UA. Within each unit area UA, a first underfill material portionlaterally surrounds the redistribution-side metal pad structuresand the die-side metal pad structures (,) of the at least one semiconductor die (,).

is a vertical cross-sectional view of a region of the structure after formation of an epoxy molding compound (EMC) matrix according to an embodiment of the present disclosure.is a top-down view of the structure ofaccording to an embodiment of the present disclosure. Referring to, an epoxy molding compound (EMC) may be applied to the gaps between contiguous assemblies of a respective set of semiconductor dies (,) and a first underfill material portion. The EMC may include an epoxy-containing compound that may be hardened (i.e., cured) to provide a dielectric material portion having sufficient stiffness and mechanical strength. The EMC may include epoxy resin, hardener, silica (as a filler material), and other additives. The EMC may be provided in a liquid form or in a solid form depending on the viscosity and flowability. Liquid EMC provides better handling, good flowability, less voids, better fill, and less flow marks. Solid EMC provides less cure shrinkage, better stand-off, and less die drift. A high filler content (such as 85% in weight) within an EMC may shorten the time in mold, lower the mold shrinkage, and reduce the mold warpage. Uniform filler size distribution in the EMC may reduce flow marks, and may enhance flowability. The curing temperature of the EMC may be lower than the release (debonding) temperature of the first adhesive layerif the adhesive layer includes a thermally debonding material. For example, the curing temperature of the EMC may be in a range from 125° C. to 150° C.

The EMC may be cured at a curing temperature to form an EMC matrixM that laterally surrounds and embeds each assembly of a set of semiconductor dies (,) and a first underfill material portion. The EMC matrixM includes a plurality of epoxy molding compound (EMC) die frames that may be laterally adjoined to one another. Each EMC die frame is a portion of the EMC matrixM that is located within a respective unit area UA. Thus, each EMC die frame laterally surrounds and embeds a respective a set of semiconductor dies (,) and a respective first underfill material portion. Young's modulus of pure epoxy is about 3.35 GPa, and Young's modulus of the EMC may be higher than Young's modulus of pure epoxy by adding additives. Young's modules of EMC may be greater than 3.5 GPa.

Portions of the EMC matrixM that overlies the horizontal plane including the top surfaces of the semiconductor dies (,) may be removed by a planarization process. For example, the portions of the EMC matrixM that overlies the horizontal plane may be removed using a chemical mechanical planarization. The combination of the remaining portion of the EMC matrixM, the semiconductor dies (,), the first underfill material portions, and the two-dimensional array of redistribution structurescomprises a reconstituted waferW. Each portion of the EMC matrixM located within a unit area UA constitutes an EMC die frame.

is a vertical cross-sectional view of a region of an intermediate structure after attaching a second carrier substrate and detaching the first carrier substrate according to an embodiment of the present disclosure. Referring to, a second adhesive layermay be applied to the physically exposed planar surface of the reconstituted waferW, i.e., the physically exposed surfaces of the EMC matrixM, the semiconductor dies (,), and the first underfill material portions. In one embodiment, the second adhesive layermay comprise a same material as, or may comprise a different material from, the material of the first adhesive layer. If the first adhesive layercomprises a thermally decomposing adhesive material, the second adhesive layercomprises another thermally decomposing adhesive material that decomposes at a higher temperature, or may comprise a light-to-heat conversion material.

A second carrier substratemay be attached to the second adhesive layer. The second carrier substratemay be attached to the opposite side of the reconstituted waferW relative to the first carrier substrate. Generally, the second carrier substratemay comprise any material that may be used for the first carrier substrate. The thickness of the second carrier substratemay be in a range from 500 microns to 2,000 microns, although lesser and greater thicknesses may also be used.

The first adhesive layermay be decomposed by ultraviolet radiation or by a thermal anneal at a debonding temperature. In embodiments in which the first carrier substrateincludes an optically transparent material and the first adhesive layerincludes an LTHC layer, the first adhesive layermay be decomposed by irradiating ultraviolet light through the transparent carrier substrate. The LTHC layer may be absorb the ultraviolet radiation and generate heat, which decomposes the material of the LTHC layer and cause the transparent first carrier substrateto be detached from the reconstituted waferW. In embodiments in which the first adhesive layerincludes a thermally decomposing adhesive material, a thermal anneal process at a debonding temperature may be performed to detach the first carrier substratefrom the reconstituted waferW.

is a vertical cross-sectional view of a region of the intermediate structure after formation of fan-out bonding pads according to an embodiment of the present disclosure. Referring to, fan-out bonding padsmay be formed by depositing and patterning at least one metallic material that may function as bonding pads. The metallic fill material for the fan-out bonding padsmay include copper. Other suitable materials are within the contemplated scope of disclosure. The thickness of the fan-out bonding padsmay be in a range from 5 microns to 100 microns, although lesser or greater thicknesses may also be used. The fan-out bonding padsmay have horizontal cross-sectional shapes of rectangles, rounded rectangles, or circles. Other suitable shapes are within the contemplated scope of disclosure. In embodiments in which the fan-out bonding padsare formed as C4 (controlled collapse chip connection) pads, the thickness of the fan-out bonding padsmay be in a range from 5 microns to 50 microns, although lesser or greater thicknesses may also be used. Alternatively, the fan-out bonding padsmay be configured for microbump bonding (i.e., C2 bonding), and may have a thickness in a range from 30 microns to 100 microns, although lesser or greater thicknesses may also be used. In such an embodiment, the fan-out bonding padsmay be formed as an array of micropads (such as copper pillars or UBMs) having a lateral dimension in a range from 10 microns to 25 microns, and having a pitch in a range from 20 microns to 50 microns.

The fan-out bonding padsmay be formed on the opposite side of the redistribution structurefrom the EMC matrixM and the two-dimensional array of sets of semiconductor dies (,) relative to the redistribution structure layer. The redistribution structure layer includes a two-dimensional array of redistribution structures. Each redistribution structuremay be located within a respective unit area UA. Each redistribution structuremay comprise redistribution dielectric layers, redistribution wiring interconnectsembedded in the redistribution dielectric layers, and fan-out bonding pads. The fan-out bonding padsmay be located on an opposite side of the redistribution structurefrom the redistribution-side metal pad structuresrelative to the redistribution dielectric layers.

is a vertical cross-sectional view of a region of the intermediate structure after detaching the second carrier substrate according to an embodiment of the present disclosure. Referring to, the second adhesive layermay be decomposed by ultraviolet radiation or by a thermal anneal at a debonding temperature. In embodiments in which the second carrier substrateincludes an optically transparent material and the second adhesive layerincludes an LTHC layer, the second adhesive layermay be decomposed by irradiating ultraviolet light through the transparent carrier substrate. In embodiments in which the second adhesive layerincludes a thermally decomposing adhesive material, a thermal anneal process at a debonding temperature may be performed to detach the second carrier substratefrom the reconstituted waferW.

is a vertical cross-sectional view of a region of the intermediate structure during dicing of a redistribution substrate and the EMC matrix according to an embodiment of the present disclosure. Referring to, the reconstituted waferW including the fan-out bonding padsmay be subsequently diced along dicing channels by performing a dicing process. The dicing channels correspond to the boundaries between neighboring pairs of die areas DA. Each diced unit from the reconstituted waferW comprises a fan-out package. In other words, each diced portion of the assembly of the two-dimensional array of sets of semiconductor dies (,), the two-dimensional array of first underfill material portions, the EMC matrixM, and the two-dimensional array of redistribution structuresconstitutes a fan-out package. Each diced portion of the EMC matrixM constitutes a molding compound die frame. Each diced portion of the redistribution structure layer (which includes the two-dimensional array of redistribution structures) constitutes a redistribution structure.

is a vertical cross-sectional view of an intermediate structure according to an embodiment of the present disclosure.is a top-down view of the intermediate structure ofaccording to an embodiment of the present disclosure. The vertical cross section shown inis along line BB′ in. Referring to, a fan-out packageobtained by dicing the structure at the processing steps ofis illustrated. The fan-out packagecomprises a redistribution structureincluding redistribution-side metal pad structures, at least one semiconductor die (,) comprising a respective set of die-side metal pad structures (,) that is attached to the redistribution-side metal pad structuresthrough a respective set of first solder material portions, a first underfill material portionlaterally surrounding the redistribution-side metal pad structuresand the die-side metal pad structures (,) of the at least one semiconductor die (,).

The fan-out packagemay also comprise a molding compound die framelaterally surrounding the at least one semiconductor die (,) and comprising a molding compound material. In one embodiment, the molding compound die framecomprises sidewalls that are vertically coincident with sidewalls of the redistribution structure, i.e., located within same vertical planes as the sidewalls of the redistribution structure. Generally, the molding compound die framemay be formed around the at least one semiconductor die (,) after formation of the first underfill material portionwithin each fan-out package. The molding compound material contacts a peripheral portion of a planar surface of the redistribution structure.

is a vertical cross-sectional view of an intermediate structure after attaching the fan-out packageto a package substrate according to an embodiment of the present disclosure. Referring to, second solder material portionsmay be attached to the fan-out bonding pads. A package substratemay be bonded to the fan-out packagethrough the second solder material portions. The package substratemay be a cored package substrate including a core substrate, or a coreless package substrate that does not include a package core. Alternatively, the package substratemay include a system-on-integrated package substrate (SoIS) including redistribution layers and/or dielectric interlayers, at least one embedded interposer (such as a silicon interposer). Such a system-integrated package substrate may include layer-to-layer interconnections using bonding material portions, underfill material portions (such as molded underfill material portions), and/or an optional adhesion film (not shown). While the present disclosure is described using an substrate package, it is understood that the scope of the present disclosure is not limited by any particular type of substrate package and may include an SoIS. Other substrate packages are within the contemplated scope of disclosure. The core substratemay include a glass epoxy plate including an array of through-plate holes. An array of through-core via structuresincluding a metallic material may be provided in the through-plate holes. Each through-core via structuremay, or may not, include a cylindrical hollow therein. Optionally, dielectric linersmay be used to electrically isolate the through-core via structuresfrom the core substrate.

The package substratemay include board-side surface laminar circuit (SLC)and a chip-side surface laminar circuit (SLC). The board-side SLCmay include board-side insulating layersembedding board-side wiring interconnects. The chip-side SLCmay include chip-side insulating layersembedding chip-side wiring interconnects. The board-side insulating layersand the chip-side insulating layersmay include a photosensitive epoxy material that may be lithographically patterned and subsequently cured. The board-side wiring interconnectsand the chip-side wiring interconnectsmay include copper that may be deposited by electroplating within patterns in the board-side insulating layersor the chip-side insulating layers.

In one embodiment, the package substrateincludes a chip-side surface laminar circuitcomprising chip-side wiring interconnectsconnected to an array of chip-side bonding padsthat may be bonded to the array of second solder material portions, and a board-side surface laminar circuitincluding board-side wiring interconnectsconnected to an array of board-side bonding pads. The array of board-side bonding padsmay be configured to allow bonding through solder balls. The array of chip-side bonding padsmay be configured to allow bonding through C4 solder balls. Generally, any type of package substratemay be used. While the present disclosure is described using an embodiment in which the package substrateincludes a chip-side surface laminar circuitand a board-side surface laminar circuit, embodiments are expressly contemplated herein in which one of the chip-side surface laminar circuitand the board-side surface laminar circuitis omitted, or is replaced with an array of bonding structures such as microbumps. In an illustrative example, the chip-side surface laminar circuitmay be replaced with an array of microbumps or any other array of bonding structures.

The second solder material portionsattached to the fan-out bonding padsof the fan-out packagemay be disposed on the array of the chip-side bonding padsof the package substrate. A reflow process may be performed to reflow the second solder material portions, thereby inducing bonding between the fan-out packageand the package substrate. In one embodiment, the second solder material portionsmay include C4 solder balls, and the fan-out packagemay be attached to the package substrateusing an array of C4 solder balls. Generally, a second array of metallic joint structures may be formed. Each metallic joint structure may comprise a first metal pad structure (such as a chip-side bonding pad), a second metal pad structure (such as a fan-out bonding pad), and a bump material portion (such as a second solder material portion).

is a vertical cross-sectional view of the intermediate structure after formation of a second underfill material portion according to an embodiment of the present disclosure.is a top-down view of the structure ofaccording to an embodiment of the present disclosure. Referring to, a second underfill material portionmay be formed around the second solder material portionsby applying and shaping a second underfill material. The second underfill material portionmay be formed around the second solder material portionsby applying and shaping the second underfill material. The second underfill material portionmay be formed by injecting the second underfill material around the array of second solder material portionsafter the second solder material portionsare reflowed. Any known underfill material application method may be used, which may be, for example, the capillary underfill method, the molded underfill method, or the printed underfill method.

The second underfill material portionmay be formed between the redistribution structureand the package substrate. According to an aspect of the present disclosure, the second underfill material portionmay be formed directly on each sidewall of the molding compound die frame.

The second underfill material portionmay contact each of the second solder material portions(which may be C4 solder balls or C2 solder caps), and may contact vertical sidewalls of the fan-out package. The second underfill material portion may be formed between the redistribution structureand the package substrate. The second underfill material portion may laterally surround, and contact, the array of second solder material portionsand the fan-out package.

In one embodiment, the second underfill material portionmay include tapered sidewalls that extend continuously from a respective sidewall of the molding compound die frameto a planar surface (such as the top surface) of the package substrate. The taper angle of the tapered sidewalls may be in a range from 10 degrees to 80 degrees, such as from 30 degrees to 60 degrees, although lesser and greater taper angles may also be used. The taper angle may, or may not, be uniform. For example, exposed outermost surfaces of the second underfill material portionsurrounding vertical sidewalls of the fan-out packagemay have a curved or concave shape with varying taper angles formed as a result of the deposition process. In one embodiment, the tapered sidewalls may have a same taper angle (as measured from a vertical direction) throughout.

is a vertical cross-sectional view of an stiffener structure according to an embodiment of the present disclosure.is a top-down view of the stiffener structure ofaccording to an embodiment of the present disclosure. The vertical cross sectional view inis along line BB′ in. Referring to, an unbeveled stiffener structureis illustrated. The unbeveled stiffener structuremay be formed to have a first wall portion, a second wall portion, a third wall portion, and a fourth wall portion. The unbeveled stiffener structuremay be formed using a molding process. In some embodiments, the unbeveled stiffener structuremay be formed as a single piece without a hollowed-out center, and a beveling or drilling tool may be used to hollow out a middle area to form the first wall portion, second wall portion, third wall portion, and fourth wall portion. In some embodiments, the unbeveled stiffener structuremay be formed through a molding process to have a hollowed-out middle area. The unbeveled stiffener structuremay be formed using one or more materials. For example, the unbeveled stiffener structuremay be formed using copper with nickel coating or aluminum alloys, metals such as copper, brass, stainless steel, and aluminum, copper tungsten, ceramic materials, materials containing silicon, composite alloys, polymers, and plastics.

The first wall portionmay extend in a second horizontal direction hdto connect to ends of the third wall portionand the fourth wall portion. The second wall portionmay extend in the second horizontal direction hdto connect to ends of the third wall portionand the fourth wall portion. The third wall portionmay extend in a first horizontal direction hdto connect to ends of the first wall portionand the second wall portion. The fourth wall portionmay extend in the first horizontal direction hdto connect to ends of the first wall portionand the second wall portion

is a vertical cross-sectional view of the stiffener structure ofafter beveling the stiffener structure according to an embodiment of the present disclosure.is a bottom-up view of the beveled stiffener structure ofaccording to an embodiment of the present disclosure. Referring to, a beveled stiffener structureis illustrated. Portions of the first wall portion, second wall portion, third wall portion, and fourth wall portionmay be cut, drilled, beveled, or milled using a milling apparatusto form at least one tapered sidewall.

The milling apparatusmay be used to form at least one tapered sidewall on at least one of the inner sidewalls and outer sidewalls of the first wall portion, second wall portion, third wall portion, and fourth wall portionof the beveled stiffener structure. For illustrative purposes, the beveled stiffener structureincludes beveled inner and outer sidewalls along each wall portion-. However, fewer sidewalls may be beveled depending on the application.

In some embodiments, the beveled stiffener structuremay include a bottom portionbot and a top portiontop. The bottom portionbot may include the portion of the beveled stiffener structurethat is beveled using the milling apparatus. The bottom portionbot may include tapered inner and outer sidewalls. The top portiontop may include the portion of the beveled stiffener structurethat was not beveled. As illustrated, the bottom portionbot is a beveled portion having a height that is equal to the height of the top portiontop. However, in some embodiments, the heights of the bottom portionbot and the top portiontop may be different, such that at least one tapered sidewall on the bottom portionbot may have a vertical height that less than or greater than the vertical non-tapered sidewall of the top portiontop.

The beveled stiffener structuremay include a first inner sidewall-and a first outer sidewall-of the first wall portion, a second inner sidewall-and a second outer sidewall-of the second wall portion, a third inner sidewall-and a third outer sidewall-of the third wall portion, and a fourth inner sidewall-and a fourth outer sidewall-of the fourth wall portion. The first inner sidewall-, second inner sidewall-, third inner sidewall-, and fourth inner sidewall-may be collectively referred to as the inner sidewalls---, and may form an inner rectangularly-shaped ring of the beveled stiffener structure. The first outer sidewall-, second outer sidewall-, third outer sidewall-, and fourth outer sidewall-may be collectively referred to as the outer sidewalls---, and may form an outer rectangularly-shaped ring of the beveled stiffener structurethat surrounds the inner sidewalls---

The inner sidewalls---may each include a tapered sidewall within the bottom portionbot and a vertically-extending sidewall within the top portiontop, in which each vertically-extending sidewall is connected to each tapered sidewall to form each of the inner sidewalls---. The outer sidewalls---may each include a tapered sidewall within the bottom portionbot and a vertically-extending sidewall within the top portiontop, in which each vertically-extending sidewall is connected to each tapered sidewall to form each of the outer sidewalls---

The tapered sidewalls may have a taper angle with respect to a horizontal plane (e.g., bottom surface of the bottom portionbot) that may be in a range from 1 degree to 89 degrees, such as from 30 degrees to 60 degrees, although lesser and greater taper angles may also be used. The taper angle may, or may not, be uniform across each and all tapered sidewalls. The taper angles of the inner sidewalls---and the outer sidewalls---may be equivalent as illustrated. However, in some embodiments, the taper angles of the inner sidewalls---may be different than the taper angles of the outer sidewalls---. In some embodiments, the taper angles of one or more of the inner sidewalls---may be different from each other. In some embodiments, the taper angles of the outer sidewalls---may be different from each other.

A top portion of the top portiontop (i.e., top surface of the top portiontop) along the wall portions-may have a first width W. A bottom portion of the bottom portionbot (i.e., bottom surface of the bottom portionbot) along the wall portions-may have a second width W. The first width Wmay be greater than the second width W. The first width Wmay also be referred to as the horizontal distance between an inner sidewall and an outer sidewall within the top portiontop. For example, the first wall portionand the second wall portionmay have a first width Win a first horizontal direction hd, and the third wall portionand the fourth wall portionmay have a first width Win a second horizontal direction hd. As illustrated, the widths of each wall portion-are equivalent, However, in some embodiments, the widths of each wall portion-may vary. The second width Wmay also be referred to as the horizontal distance between an inner sidewall and an outer sidewall at a bottom portion of the bottom portionbot. For example, the first wall portionand the second wall portionmay have a second width Win a first horizontal direction hd, and the third wall portionand the fourth wall portionmay have a second width Win a second horizontal direction hd. As illustrated, the widths of each wall portion-are equivalent. However, in some embodiments in which the heights and the taper angles of each sidewall vary, the widths of each wall portion-may each also vary.

In some embodiments, the first width Wmay be in a range of 2 to 25 millimeters, such as 5 to 15 millimeters, although lesser or greater widths may be used. In some embodiments, the second width Wmay be in a range of 2 to 25 millimeters, such as 5 to 15 millimeters, although lesser or greater widths may be used.