Multi-Gate Negative Differential Impedance Device for Sram

Embedded memory is important to the performance of modern system-on-a-chip (SoC) technology. Typically, memory assemblies (e.g., static random-access memory (SRAM) and dynamic random-access memory (DRAM)) include one or more memory arrays and control circuitry for the memory arrays in a single layer. Low power and high-density embedded memory is used in many different computer products and further improvements are always desirable.

The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.

Some memory devices may be considered “standalone” devices in that they are included in a chip that does not also include compute logic (where, as used herein, the term “compute logic devices” or simply “compute logic” or “logic devices,” refers to devices, e.g., transistors, for performing computing/processing operations). Other memory devices may be included in a chip along with compute logic and may be referred to as “embedded” memory devices. Using embedded memory to support compute logic may improve performance by bringing the memory and the compute logic closer together and eliminating interfaces that increase latency. Various embodiments of the present disclosure relate to embedded memory arrays, as well as corresponding methods and devices.

Some embodiments of the present disclosure may refer to SRAM and in particular, embedded SRAM (eSRAM). In general, memory cells/arrays described herein may be implemented as standalone SRAM devices, eSRAM devices, non-volatile SRAM devices, or other volatile or non-volatile memory cells/arrays.

An SRAM memory cell includes a plurality of transistors for storing a bit value or a memory state (e.g., logic “1” or “0”) of the cell, and one or more access transistors for controlling access to the cell (e.g., access to write information to the cell or access to read information from the cell). A typical SRAM memory cell is made up of 6 transistors and is, therefore, may be referred to as a “6T SRAM memory cell,” where 4 transistors are used to store a bit value and 2 transistors are access transistors, coupled to a bitline (BL) and a wordline (WL). Various SRAM memory cells have, conventionally, been implemented with transistors being front end of line (FEOL), logic-process based, transistors implemented in an upper-most layer of a semiconductor substrate.

One challenge in SRAM cells resides in that, given a usable surface area of a substrate, there are only so many FEOL transistors that can be formed in that area, placing a significant limitation on the density of memory cells incorporating such transistors. In conventional solutions, attempts to increase memory density have included decreasing the critical dimensions of the memory cells, which requires ever-increasing process complexity and cost, resulting in diminishing returns and expected slow pace of memory scaling for future nodes.

Embodiments of the present disclosure may improve on at least some of the challenges and issues described above by providing a memory cell formed around a single vertical pillar. As described herein, a memory device may include a semiconductor pillar coupled to three independently-controlled gates, e.g., three gates that wrap around the semiconductor pillar at different heights. The semiconductor pillar has a first dopant type (either n-type or p-type) and is formed over a semiconductor region of a second dopant type that is opposite the first. The semiconductor region may be underneath the gates. A more highly-doped region of the first dopant type is formed over the pillar, e.g., as a cap. The cap is located along the pillar at a height above the gates.

The memory device having this structure is a negative differential impedance device. The two ends of the pillar (e.g., the semiconductor region below the pillar and the cap over the pillar) form the two terminals of the negative differential impedance device. In general, a negative differential impedance device has an I-V curve with a region of negative resistance, or more generally, negative impedance. In general, impedance is a measure of opposition to the flow of alternating current in a circuit. Impedance encompasses resistance (which resists the flow of current) and reactance (which arises due to effects of capacitance in inductance).

The memory device described herein device exhibits hysteresis, where, for example, the I-V curve of the device (e.g., the resistance at a particular current level, where resistance may be detected by a drop in voltage across the device) changes in response to a switching voltage. More generally, a resistance, capacitance, and/or charge state of the memory device may change in response to an event (e.g., a charge event or avalanching event) within the memory device. The hysteresis effect causes a state of the device to be stored (e.g., with one I-V curve or impedance state corresponding to 1, and the other I-V curve or impedance state corresponding to 0), so that the device functions as an SRAM cell. A voltage can be applied to the middle gate to switch the device, e.g., to switch between the two IV curves or impedance states. Voltages may be applied to the top and/or bottom gates to apply a bias to the pillar, which can assist in switching the device between the two impedance states. For example, the top and bottom gates, along with the region of the pillar near the top and bottom gates, may act as access transistors for programming the memory device.

The vertical pillars described herein may be small structures, with a low amount of current passing through each individual pillar. In general, when semiconductor-devices operate at lower temperatures, they have improved performance. For example, electron mobility in semiconductors improves at lower temperatures, which can lead to increased drive currents across semiconductor regions, e.g., across a vertical pillar device. In addition, semiconductor devices at lower temperatures generally experience lower leakage than semiconductor devices operating at higher temperatures. These factors can allow small-scale devices to be used when an IC device is operating at a lower temperature.

For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well known features are omitted or simplified in order not to obscure the illustrative implementations.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20% of a target value, unless specified otherwise. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, as used herein, a “logic state” of a ferroelectric memory cell refers to one of a finite number of states that the cell can have, e.g. logic states “1” and “0,” each state represented by a different polarization of the ferroelectric material of the cell. In another example, as used herein, a “READ” and “WRITE” memory access or operations refer to, respectively, determining/sensing a logic state of a memory cell and programming/setting a logic state of a memory cell. In other examples, the term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct electrical or magnetic connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. In yet another example, a “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide. The terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc.

In the following, some descriptions may refer to a particular S/D region or contact being either a source region/contact or a drain region/contact. However, unless specified otherwise, which region/contact of a transistor is considered to be a source region/contact and which region/contact is considered to be a drain region/contact is not important because, as is common in the field of FETs, designations of source and drain are often interchangeable. Therefore, descriptions of some illustrative embodiments of the source and drain regions/contacts provided herein are applicable to embodiments where the designation of source and drain regions/contacts may be reversed.

For convenience, if a collection of drawings designated with different letters are present, e.g.,, such a collection may be referred to herein without the letters, e.g., as “.”

is an electric circuit diagram of an example 6-transistor (6T) memory cell. The SRAM cellincludes transistors M-Mfor storing a bit value or a memory state (e.g., logic “1” or “0”) of the cell, and two access transistors, Mand M, for controlling access to the cell (e.g., access to write information to the cell or access to read information from the cell). Each of the transistors M-Mmay have any transistor architecture (e.g., planar or non-planar, FinFET, nanoribbon/nanowire, etc.).

In the SRAM cell, each bit may be stored on four transistors (M, M, M, M) that form two cross-coupled inverters, each having an inputand an output. The first inverter-may be formed by an NMOS transistor Mand a PMOS transistor M, while the second inverter-may be formed by an NMOS transistor Mand a PMOS transistor M. As shown in, the gate stack-of the transistor Mmay be coupled to the gate stack-of the transistor M, and both of these gate stacks may be coupled to the input-of the first inverter-. On the other hand, the first S/D region-of the transistor Mmay be coupled to the first S/D region-of the transistor M, and both of these first S/D regions-and-may be coupled to the output-of the first inverter-. Similarly, for the second inverter-, the gate stack-of the transistor Mmay be coupled to the gate stack-of the transistor M, and both of these gate stacks may be coupled to the input-of the second inverter-, while the first S/D region-of the transistor Mmay be coupled to the first S/D region-of the transistor M, and both of these first S/D regions-and-may be coupled to the output-of the second inverter-. As also shown in, when the transistors Mand Mare NMOS transistors and when the transistors Mand Mare PMOS transistors as illustrated in, the second S/D regions-and-of the transistors Mand Mmay be coupled to a ground voltage, while the second S/D regions-and-of the transistors Mand Mmay be coupled to a supply voltage, e.g., VDD. In the embodiments of the SRAM cellwhere the NMOS transistors shown inare replaced with PMOS transistors and vice versa, the designation of the ground voltageand the supply voltagewould be reversed as well, all of which embodiments being within the scope of the present disclosure.

The four transistors M-Min the illustrated configuration form a stable storage cell for storing a bit value of 0 or 1. As further shown in, two additional access transistors, Mand M, may serve to control the access to the storage cell of the transistors M-Mduring read and write operations. As shown in, the first S/D region-of the access transistor Mmay be coupled to the output-of the first inverter-. Phrased differently, the first S/D region-of the access transistor Mmay be coupled to each of the first S/D region-of the transistor Mand the first S/D region-of the transistor M. The second S/D region-of the access transistor Mmay be coupled to a first BL-. Thus, each of the first S/D region-of the transistor Mand the first S/D region-of the transistor Mmay be coupled to the first BL-(e.g., via the access transistor M). The gate-of the access transistor Mmay be coupled to a WL.

As further shown in, the first S/D region-of the access transistor Mmay be coupled to the output-of the second inverter-. Phrased differently, the first S/D region-of the access transistor Mmay be coupled to each of the first S/D region-of the transistor Mand the first S/D region-of the transistor M. The second S/D region-of the access transistor Mmay be coupled to a second BL-. Thus, each of the first S/D region-of the transistor Mand the first S/D region-of the transistor Mmay be coupled to the second BL-(e.g., via the access transistor M). The gate-of the access transistor Mmay be coupled to the WL. Thus, the gates-and-of both of the access transistors Mand Mmay be coupled to a single, shared, WL, the WL.

As also shown in, the input-of the first inverter-may be coupled to the first S/D region-of the access transistor M, while the input-of the second inverter-may be coupled to the first S/D region-of the access transistor M. In other words, each of the gate stack-of the transistor Mand the gate stack-of the transistor Mmay be coupled to the first S/D region-of the access transistor M, while each of the gate stack-of the transistor Mand the gate stack-of the transistor Mmay be coupled to the first S/D region-of the access transistor M. Phrased differently, each of the gate stack-of the transistor Mand the gate stack-of the transistor Mmay be coupled to the second BL-(e.g., via the access transistor M), while each of the gate stack-of the transistor Mand the gate stack-of the transistor Mmay be coupled to the first BL-(e.g., via the access transistor M).

The WLand the first and second BLsmay be used together to read and program (i.e., write to) the SRAM cell. In particular, access to the cell may be enabled by the WLwhich controls the two access transistors Mand Mwhich, in turn, control whether the cellshould be connected to the BLs-and-. During operation of the SRAM cell, a signal on the first BL-may be complementary to a signal on the second BL-. The two BLsmay be used to transfer data for both read and write operations. In other embodiments of the SRAM cell, only a single BLmay be used, instead of two bitlines-and-, although having one signal BL and one inverse, such as the two BLs, may help improve noise margins.

During read accesses, the BLsare actively driven high and low by the invertersin the SRAM cell. This may improve SRAM bandwidth compared to DRAM. The symmetric structure of the SRAMs cellalso allows for differential signaling, which may provide an improvement in detecting small voltage swings. Another difference with DRAM that may contribute to making SRAM faster than DRAM is that commercial chips accept all address bits at a time. By comparison, commodity DRAMs may have the address multiplexed in two halves, i.e. higher bits followed by lower bits, over the same package pins in order to keep their size and cost down.

Each of the WLand the BLs, as well as intermediate elements coupling these lines to various terminals described herein, may be formed of any suitable electrically conductive material, which may include an alloy or a stack of multiple electrically conductive materials. In some embodiments, such electrically conductive materials may include one or more metals or metal alloys, with metals such as ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum. In some embodiments, such electrically conductive materials may include one or more electrically conductive alloys oxides or carbides of one or more metals.

is an effective electric circuit diagram of a negative differential impedance memory cell, e.g., the memory devices illustrated in, described below. The SRAM cellincludes transistors Mand M, which are similar to transistors Mand Mof. Transistor Mis coupled to a BL-, which is similar to the BL-, and a WL, which is similar to the WL. Transistor Mis coupled to a BL-, which is similar to the BL-, and to the WL. The SRAM cellfurther includes two cross-coupled inverters-and-, which are positioned relative to the access transistors Mand Min a similar manner to inverters-and-.

The WLand the first and second BLsmay be used together to read and program (i.e., write to) the SRAM cell. In particular, access to the cell may be enabled by the WLwhich controls the two access transistors Mand Mwhich, in turn, control whether the cellshould be connected to the BLs-and-. During operation of the SRAM cell, a signal on the first BL-may be complementary to a signal on the second BL-. The two BLsmay be used to transfer data for both read and write operations. In other embodiments of the SRAM cell, only a single BLmay be used, instead of two bitlines-and-, although having one signal BL and one inverse, such as the two BLs, may help improve noise margins.

During read accesses, the BLsare actively driven high and low by the invertersin the SRAM cell. The SRAM cellmay have the benefits over DRAM described above with respect to.

As described with respect to, each of the WLand the BLs, as well as intermediate elements coupling these lines to various terminals described herein, may be formed of any suitable electrically conductive material, which may include an alloy or a stack of multiple electrically conductive materials. In some embodiments, such electrically conductive materials may include one or more metals or metal alloys, with metals such as ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum. In some embodiments, such electrically conductive materials may include one or more electrically conductive alloys oxides or carbides of one or more metals.

illustrate multi-gate negative differential impedance memory cells constructed around vertical semiconductor pillars., discussed above, is an effective electrical circuit diagram of the memory cells illustrated in., described below, illustrates an example set of I-V curves for the memory cells described herein.

is a cross-section through a set of three memory devices, andis a cross-section in the x-y plane through plan AA′ in, according to some embodiments of the present disclosure. A number of elements referred to in the description of, and with reference numerals are illustrated in these figures with different patterns, with a legend at the bottom of the page showing the correspondence between the reference numerals and patterns. The legend illustrates thatuse different patterns to show a first semiconductor, a second semiconductor, a third semiconductor, a dielectric material, a gate electrode material, and a gate dielectric.

In the drawings, some example structures of various devices and assemblies described herein are shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication.

In general, implementations of the present disclosure may be formed or carried out on a support structure. The semiconductor region, which includes the first semiconductor, may be a support structure or a portion of a support structure, with other features formed over the semiconductor region(e.g., over the support structure). Alternatively, the semiconductor regionis formed over a support structure, or the semiconductor regionis formed within at least a portion of the support structure, e.g., by doping an upper layer of a semiconductor substrate to form the first semiconductorfor the semiconductor region.

In general, the support structure may be, e.g., a substrate, a die, a wafer or a chip. For example, the support structure may be the waferof, discussed below, and may be, or be included in, a die, e.g., the singulated dieof, discussed below. The support structure extends along the x-y plane in the coordinate system shown in. In some embodiments, a support structure may be used during a fabrication process and later removed. For example, the devices(optionally along with one or more layers over the devices, e.g., a metallization stack) may be attached to a second support structure (e.g., a carrier structure), and the support structure over which the devicesare formed may be removed to expose the back side of the devices. The semiconductor region, which may be formed over the support structure or formed in a top portion of the support structure, may remain attached to the devices, e.g., by removing a lower portion of the support structure.

In some embodiments, a support structure may be a substrate that includes silicon and/or hafnium. More generally, the support structure may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride or gallium antimonide, or other combinations of group III-V materials (i.e., materials from groups III and V of the periodic system of elements), group II-VI (i.e., materials from groups II and IV of the periodic system of elements), or group IV materials (i.e., materials from group IV of the periodic system of elements). In some embodiments, the substrate may be non-crystalline. In some embodiments, the support structure may be a printed circuit board (PCB) substrate. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device including one or more nanoribbon transistors, as described herein, may be built falls within the spirit and scope of the present disclosure.

illustrates cross-sections through three memory devices,, and, referred to jointly as memory devicesand also referred to as memory cellsor devices. Each deviceis formed around a respective pillar,, or. Each devicefurther includes a capformed over the pillar. For example, the deviceincludes a capover the pillar. A set of three gates,, andare coupled to the pillarsat different heights in the z-direction along the pillars. The gatesmay be considered a portion of each of the devices. The pillarsare formed over the semiconductor region. A portion of the semiconductor regionunder each pillarmay be considered a portion of the respective memory device, e.g., a portion of the semiconductor regionunder the pillaris considered a portion of the memory device

The pillarsinclude the second semiconductor, and the capsinclude the third semiconductor. Each of the first semiconductor, second semiconductor, and third semiconductorany suitable semiconductor material. In general, the first semiconductorand second semiconductormay have opposite charge carrier types (i.e., one is n-type and the other p-type). The third semiconductorhas the same charge carrier type as the second semiconductor, and the third semiconductormay be more highly doped than the second semiconductor.

In conductor and semiconductor materials, a charge carrier is a particle or quasiparticle that can move within the material, carrying a conductive charge and resulting in a net motion of particles through the material. In some semiconductors, the main charge carriers are electrons, while in others, the main charge carriers are electron holes (i.e., electron vacancies), generally referred to as holes. A semiconductor material or semiconductor region with holes as the primary charge carrier is referred to as p-type, and a semiconductor material or semiconductor region with electrons as the primary charge carrier is referred to as n-type. Doping may be used to create a p-type or n-type material; for example, silicon can be doped such that it is either n-type or p-type.

In general, the second semiconductormay have a relatively low level of a dopant, e.g., a lower dopant concentration than the third semiconductorand, in some cases, lower than the first semiconductor. For example, the first semiconductoris a highly-doped n-type material, the second semiconductoris a p-type material, and the third semiconductoris a more highly-doped p-type material. As another example, the first semiconductoris a highly-doped p-type material, the second semiconductoris a low-doped n-type material, and the third semiconductoris a highly-doped n-type material. The third semiconductormay have a dopant concentration of about 1×10cmor higher, e.g., 1×10cm. The first semiconductormay have a similarly high doping concentration. The second semiconductormay have a lower dopant concentration, e.g., between 1×10cmand 1×10cm.

One or more of the semiconductors,, andmay include a monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, one or more of the semiconductors,, andmay include a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb).

For some embodiments, one or more of the semiconductors,, andmay include a III-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, one or more of the semiconductors,, andmay be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InGaAs embodiments, the In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., InGaAs). For other embodiments, one or more of the semiconductor materials may be a group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, one or more of the semiconductors,, andmay have a Ge content between 0.6 and 0.9, and may be at least 0.7.

In some embodiments, one or more of the semiconductors,, andmay be a thin-film material, such as a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, one or more of the semiconductors,, andmay include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, and black phosphorus. Suitable dopants for one or more of the semiconductors,, andmay include gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, magnesium, etc.

As noted above, the pillarsare formed over the semiconductor region. For example, a layer of the second semiconductormay be formed over the semiconductor region, followed by a layer of the third semiconductor, thus forming a stack of semiconductor materials. Regions of the stack of semiconductor materials for forming the pillarsmay be blocked, while other regions of the second semiconductorand third semiconductorare removed, e.g., through etching. In some embodiments, the capsmay be deposited over the pillarsafter etching the pillars.

The pillarsare semiconductor regions that extend in the z-direction in the coordinate system shown, e.g., in a direction perpendicular to a support structure. Said another way, the semiconductor regiongenerally extends in the x-direction and y-direction (e.g., the semiconductor regionextends in the x-direction in), and the pillarsextend in a direction (here, the z-direction) that is perpendicular to the x- and y-directions. In the example of, the semiconductor regionhas an upper surface that extends in the x-direction and y-direction, and the pillarsextend perpendicular to the upper surface of the semiconductor region. The pillarsextend in parallel to each other, e.g., pillars,, andeach extend in the z-direction.

The pillarsmay have a height in the range of 50 to 500 nanometers. The capsmay have a height in the range of 5 to 100 nanometers. The pillarsand capsmay have a diameter (measured in the x-direction or y-direction) of between 20 and 100 nanometers, in some embodiments. The pillarsmay be arranged at a pitch, where the pitchrefers to a center-to-center distance between the closest adjacent structures (e.g., between the pillarsand). The pitchof the pillars may be, in some examples, between 30 and 500 nanometers. In the example of, the pillarsare arranged in a hexagonal pattern. In other embodiments, the pillarsmay be arranged in a different pattern, e.g., in a square or rectangular pattern.

A layer of gate dielectricmay be deposited around the pillars. As illustrated in, two layersandof the gate dielectricare on either side of the pillar, between the pillarand the gates. As illustrated in, the gate dielectricmay enclose or encircle the sidewall of the pillars. In the example of, a layer of the gate dielectricis over the semiconductor region, e.g., the gate dielectric regionis over the semiconductor regionin an area between the pillarsand. In the example of, the gate dielectricdoes not extend to the tops of the caps; in other embodiments, the gate dielectricmay extend up the sidewalls of the caps.

The gate dielectricmay include one or more high-k dielectric materials and may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectricmay include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectricduring manufacture of the devicesto improve the quality of the gate dielectric. In some embodiments, the gate dielectricmay have a thickness between about 0.5 nanometers and 3 nanometers, including all values and ranges therein, e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers.

The set of three gates,, andare electrically coupled to the pillarsat different heights in the z-direction along the pillars. Each of the gatesincludes the gate electrode material, which is a conductive material; the gatesare conductive structures, which are coupled to the pillarsthrough the gate dielectric. The gate dielectricis between the pillarsand the gates. A first gateis over the semiconductor regionand, in particular, over the layer of gate dielectric(e.g., the gate dielectric region) formed over the semiconductor region. The first gatesurrounds a lower portion or base of each of the pillars. A second gateis over the first gate, around or near to a center portion of the pillars. The second gatesurrounds a middle portion of each of the pillars. A third gateis near the top of the pillars, under the capsand over the second gate. The third gatesurrounds an upper portion of each of the pillars. The gates,, andextend in parallel to each other; each of the gates,, andextend in the x-direction (as shown in) and in the y-direction as shown in) at different z-heights. The gatesextend perpendicular to the pillars, which extend in the z-direction, as discussed above.

Layersandof the dielectric materialare between adjacent ones of the gates. In particular, layerof the dielectric materialis between the first gateand the second gate, and layerof the dielectric materialis between the third gateand the second gate. The gates,, andare thus physically separated and electrically independent, and may be independently controlled.