Finfet Having a Gate Dielectric Comprising a Multi-Layer Structure Including an Oxide Layer with Different Thicknesses on Side and Top Surfaces of the Fins

This application is a continuation application of U.S. application Ser. No. 18/083,576, filed on Dec. 19, 2022. The prior application Ser. No. 18/083,576 claims the priority benefit of U.S. application Ser. No. 16/942,781, filed on Jul. 30, 2020, now patented as U.S. Pat. No. 11,532,718, issued on Dec. 20, 2022. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

As the semiconductor devices keep scaling down in size, three-dimensional multi-gate structures, such as the fin-type field effect transistor (FinFET), have been developed to replace planar CMOS devices. A characteristic of the FinFET device lies in that the structure has one or more silicon-based fins that are wrapped around by the gate to define the channel of the device. The gate wrapping structure further provides better electrical control over the channel.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

The embodiments of the present disclosure describe the exemplary manufacturing processes of a three-dimensional structure with height differences and the structure(s) fabricated there-from. Certain embodiments of the present disclosure describe the exemplary manufacturing processes of fin field-effect transistor (FinFET) devices and the FinFET devices fabricated there-from. The FinFET device may be formed on a monocrystalline semiconductor substrate, such as a bulk silicon substrate in certain embodiments of the present disclosure. In some embodiments, the FinFET device may be formed on a silicon-on-insulator (SOI) substrate or a GOI (germanium-on-insulator) substrate as alternatives. Also, in accordance with the embodiments, the silicon substrate may include other conductive layers, doped regions or other semiconductor elements, such as transistors, diodes or the like. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure.

is an exemplary flow chart showing the process steps of a method of fabricating a semiconductor device in accordance with some embodiments of the present disclosure. The various process steps of the process flow illustrated inmay comprise multiple process steps as discussed below.toare the perspective views and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some embodiments of the disclosure. It is to be noted that the process steps described herein cover a portion of the manufacturing processes used to fabricate a semiconductor device, such as a FinFET device.

is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In step Sinand as shown in, a semiconductor substrateis provided. In one embodiment, the semiconductor substratecomprises a crystalline silicon substrate (e.g., wafer). The semiconductor substratemay comprise various doped regions depending on design requirements (e.g., p-type semiconductor substrate or n-type semiconductor substrate). In some embodiments, the doped regions may be doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The doped regions may be configured for an n-type FinFET, or alternatively configured for a p-type FinFET. In some alternative embodiments, the semiconductor substratemay be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

In one embodiment, a pad layerand a mask layerare sequentially formed on the semiconductor substrate. The pad layermay be a silicon oxide thin film formed, for example, by thermal oxidation process. The pad layermay act as an adhesion layer between the semiconductor substrateand the mask layer. The pad layermay also act as an etch stop layer for etching the mask layer. In at least one embodiment, the mask layeris a silicon nitride layer formed, for example, by low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The mask layeris used as a hard mask during subsequent photolithography processes. In certain embodiments, a patterned photoresist layerhaving a predetermined pattern is formed on the mask layer

is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In step Sinand as shown in, the substrateis patterned to form trenchesin the substrateand finsare formed between the trenches. For example, the mask layerand the pad layerwhich are not covered by the patterned photoresist layerare sequentially etched to form a patterned mask layer′ and a patterned pad layer′ so as to expose the underlying semiconductor substrate. By using the patterned mask layer′, the patterned pad layer′ and the patterned photoresist layeras a mask, portions of the semiconductor substrateare exposed and etched to form the trenchesand the semiconductor fins. In some embodiments, the semiconductor finsare covered by the patterned mask layer′, the patterned pad layer′ and the patterned photoresist layer. Two adjacent trenchesare spaced apart by a spacing. For example, the spacing between trenchesmay be smaller than about 30 nm. In other words, two adjacent trenchesare spaced apart by a corresponding semiconductor fin. The number of the finsshown inis merely for illustration, in some alternative embodiments, two or more parallel semiconductor fins may be formed in accordance with actual design requirements.

In some embodiments, a height of the semiconductor finsand the depth of the trenchrange from about 5 nm to about 500 nm. After the trenchesand the semiconductor finsare formed, the patterned photoresist layeris then removed. In one embodiment, a cleaning process may be performed to remove a native oxide of the semiconductor substrateand the semiconductor fins. The cleaning process may be performed using diluted hydrofluoric (DHF) acid or other suitable cleaning solutions.

andare perspective views of the semiconductor device at one of various stages of the manufacturing method. In step Sinand as shown into, a plurality of insulatorsare formed in the trenchesof the semiconductor substrate. As illustrated in, in some embodiments, an insulating materialis first formed over the semiconductor substrateto cover the semiconductor finsand to fill up the trenches. Besides covering the semiconductor fins, the insulating materialis also covering the patterned pad layer′ and the patterned mask layer′. In some embodiments, the insulating materialmay include silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-K dielectric material. It should be noted that the low-K dielectric materials are generally dielectric materials having a dielectric constant lower than 3.9. The insulating materialmay be formed by high-density-plasma chemical vapor deposition (HDP-CVD), sub-atmospheric chemical vapor deposition (SACVD) or by spin-on processes.

Referring to, after forming the insulating material, etching processes are performed to remove a portion of the insulating material, the patterned mask layer′ and the patterned pad layer′ until the semiconductor finsare exposed. In some embodiments, the insulating materialfilled in the trenchesis partially removed by the etching process such that the insulatorsare formed on the semiconductor substrate. For example, each insulatoris located between two adjacent semiconductor fins. In one embodiment, the etching process may be a wet etching process with hydrofluoric acid (HF) or a dry etching process. In some embodiments, the top surfacesT of the insulatorsare lower than the top surfacesT of the semiconductor fins. The semiconductor finsprotrude from the top surfacesT of the insulators. The height difference between the top surfacesT of the semiconductor finsand the top surfacesT of the insulatorsranges from about 15 nm to about 50 nm. In some embodiments, the protruded portions of the semiconductor finsinclude a channel regionA and source/drain regionsB located aside the channel regionA. In certain embodiments, the source/drain regionsB of the semiconductor finsare of substantially the same height as that of the channel regionA of the fins.

is a perspective view of the semiconductor device at one of various stages of the manufacturing method.is a sectional view illustrating the semiconductor device oftaken along the line A-A′. In step Sinand as shown inand, a liner structureis formed on the plurality of insulatorsand across the semiconductor fins. In the exemplary embodiment, the liner structureincludes a cap portionA, sidewall portionsB and base portionsC. The cap portionA is covering the top surfacesT of the semiconductor finsand joined with the sidewall portionsB. The sidewall portionsB are covering sidewallsSD of the semiconductor fins. In some embodiments, the sidewall portionsB may include a first sidewall portionB-and a second sidewall portionB-covering opposite sidewallsSD of a semiconductor fin. The cap portionA may be joining the first sidewall portionB-to the second sidewall portionB-. Furthermore, the base portionsC are covering the insulatorsand joined with the sidewall portionsB. For example, the base portionsC may be joined with the first sidewall portionB-and/or the second sidewall portionB-.

As illustrated inand, a maximum thickness of the cap portionA is T, a thickness of the sidewall portionsB is T, and a thickness of the base portionsC is T. In some embodiments, the maximum thickness Tof the cap portionA is greater than the thickness Tof the sidewall portionsB. In some embodiments, the maximum thickness Tand the thickness Tsatisfies the relationship: 0.08≤[(T−T)/T]≤0.26. Furthermore, the thickness Tof the base portionsC is substantially equal to the thickness Tof the sidewall portionsB. In the exemplary embodiment, by controlling the thicknesses of the cap portionA, the sidewall portionsB and the base portionsC T, Tand Tin such a range, an issue of over-etching on the semiconductor finsor the formation of pits on the semiconductor finsmay be prevented. In some embodiments, if [(T−T)/T] is smaller than 0.08, then the impact on the formation of pits on the semiconductor finsbecomes worse. In some other embodiments, if [(T−T)/T] is greater than 0.26, then it increases the manufacturing time during subsequent etching process, and increases the manufacturing cost.

In the exemplary embodiment, the liner structureis formed by performing a deposition process and a plasma treatment process, for example. In some embodiments, the deposition process includes introducing a plurality of precursors over a surface of the plurality of insulatorsand on the semiconductor finsto form a liner layer (not shown). In certain embodiments, the deposition process is a plasma-enhanced atomic layer deposition (PEALD) process, and the plurality of precursors is silicon-containing precursors. In one embodiment, the silicon-containing precursors is SAM-24 (HSi[N(CH)]). Furthermore, in some embodiments, the plasma-enhanced atomic layer deposition process may be performed at a plasma power of 15 W to 800 W. In certain embodiments, the plasma-enhanced atomic layer deposition process may be performed at a plasma power of 500 W to 650 W to form the liner layer. The plasma-enhanced atomic layer deposition process is performed at a plasma power of 500 W to 650 W so that the liner layer having the desired thickness is ensured. In one embodiment, the plasma-enhanced atomic layer deposition process may be performed at a plasma power of 600 W.

Moreover, in some embodiments, the plasma treatment process includes treating the liner layer with a plasma selected from the group consisting of helium, argon, oxygen and hydrogen for 20 to 40 seconds under a source power of 500 W to 1500 W to form the liner structure. In some embodiments, the plasma treatment process includes a decoupled plasma oxidation process to form an oxide layer (e.g. such as silicon oxide) constituting the liner structure. In some embodiments, the plasma treatment process is performed to increase the thickness of the cap portionA of the liner structure. In other words, after the plasma treatment process, the liner structureincluding the cap portionA, the sidewall portionsB, and the base portionsC may be formed.

is a perspective view of the semiconductor device at one of various stages of the manufacturing method.is a sectional view illustrating the semiconductor device oftaken along the line B-B′. In step Sinand as shown inand, a dielectric layeris conformally formed over the liner structureand across the semiconductor fins. In some embodiments, a thickness of the dielectric layeris maintained to be the same along the base portionsC, the sidewall portionsB and the cap portionA of the liner structure. In other words, a thickness of the dielectric layeron the sidewall portionsB is the same as a thickness of the dielectric layeron the cap portionA. In certain embodiments, the dielectric layeris formed to cover the channel regionA and the source/drain regionsB of the semiconductor fins. In some embodiments, the liner structureis sandwiched in between the insulatorsand the dielectric layer, or sandwiched in between the semiconductor finsand the dielectric layer. In some embodiments, the material of the dielectric layermay be silicon oxide, silicon nitride, silicon carbonitride or the like. In some embodiments, the method of forming the dielectric layermay be an atomic layer deposition method. In some alternative embodiments, the formation of a dielectric layeron the insulatorsmay be omitted.

is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In step Sinand as shown in, a dummy gate stackis formed on the dielectric layerand across the semiconductor fins. The dummy gate stackmay include a polysilicon stripA and a hard mask stripB. In some embodiments, the dummy gate stackis formed by forming a dummy layer (including a polysilicon layer and a hard mask layer) over the dielectric layerand across the semiconducfigtor fins, and patterning the dummy layer to form the polysilicon stripA and the hard mask stripB. In the exemplary embodiment, although one dummy gate stackis illustrated herein, it should be noted that the number of dummy gate stackis not limited to one and may be more than one. In some embodiments, the extension direction of the dummy gate stack(the polysilicon stripA and the hard mask stripB) is arranged to be perpendicular to the extension direction of the semiconductor fins, and the dummy gate stackis arranged across the semiconductor finsand covers the channel regionA of the semiconductor fins. In one embodiment, the material of the hard mask stripB includes silicon nitride, silicon oxide or the combination thereof.

Referring still to, after forming the dummy gate stack, spacer structuresare formed on two opposite sides of the dummy gate stack. In some embodiments, the spacer structuresare located on the dielectric layerand are covering sidewalls of the polysilicon stripA and the hard mask stripB. In some embodiments, the spacer structuresmay be formed by conformally forming a spacer material layer over the dielectric layerand over the dummy gate stack, then performing an etching process on the spacer material layer to form the spacer structures. In some embodiments, the spacer material layer is formed of one or more dielectric materials, such as silicon nitride, silicon carbon oxynitride (SiCON), silicon carbonitride (SiCN) or combinations thereof. The spacer material layer may be a single layer or a multilayered structure. In some embodiments, the spacer material layer is formed by depositing a blanket layer of one or more dielectric materials. In one embodiment, the spacer material layer has a thickness ranging from 3 nm to 10 nm.

is a perspective view of the semiconductor device at one of various stages of the manufacturing method.is a sectional view illustrating the semiconductor device oftaken along the line C-C′. Referring toand, after forming the dummy gate stackand the spacer structures, the dielectric layeris patterned so that side surfacesSD of the dielectric layerare aligned with side surfaces of the spacer structure. In some embodiments, portions of the dielectric layernot covered by the dummy gate stackand the spacer structuresare removed. In certain embodiments, the dielectric layermay be patterned or removed by, for example, anisotropic etching, isotropic etching, and/or through atomic layer etching (ALE) processes.

Referring toand, on the channel regionA (see) of the semiconductor fins, the liner structurestill includes the cap portionA, sidewall portionsB and the base portionsC, wherein the cap portionA has the greatest thickness T. In some embodiments, portions of the liner structurelocated on the source/drain regionsB (see) of the semiconductor finsmay be patterned and removed along with the dielectric layer. For example, after the patterning process, the cap portionA, the sidewall portions and the base portionsC of the liner structurelocated on the source/drain regionsB are removed. In other words, the liner structureon the source/drain regionsB may be removed by selective etching processes to reveal the semiconductor fins. In certain embodiments, side surfacesSD of the liner structuremay be aligned with the side surfacesSD of the dielectric layerafter the patterning process.

is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In step Sinand as shown in, strained material portionsmay be formed on the source/drain regionsB (see) of the semiconductor fins. In some embodiments, the strained material portionsare formed over portions of the semiconductor finsthat are revealed by the dummy gate stack. In some embodiments, the strained material portionscovers and contacts the semiconductor fins. In some embodiments, the strained material portionsare located on two opposite sides of the dummy gate stack.

In the exemplary embodiment, the strained material portions(or a high doped low resistance material) is grown on the source/drain regionsB of the semiconductor finsto strain or stress the semiconductor fins. Thus, the strained material portionscomprises a source disposed at a side of the dummy stack gateand a drain disposed at the other side of the dummy gate stack. The source covers an end of the semiconductor finsand the drain covers the other end of the semiconductor fins. In some embodiments, the strained material portionsmay be doped with a conductive dopant. In one embodiment, the strained material portionsinclude materials such as SiGe, and is epitaxial-grown with a p-type dopant for straining a p-type FinFET. That is, the strained material portionsis doped with the p-type dopant to be the source and the drain of the p-type FinFET. The p-type dopant comprises boron or BF, and the strained material portionsmay be epitaxial-grown by LPCVD process with in-situ doping. In another embodiment, the strained material portionsinclude materials such as SiC, SiP, a combination of SiC/SiP, or SiCP, and is epitaxial-grown with an n-type dopant for straining an n-type FinFET. That is, the strained material portionsis doped with the n-type dopant to be the source and the drain of the n-type FinFET. The n-type dopant comprises arsenic and/or phosphorus, and the strained material portionsmay be epitaxial-grown by LPCVD process with in-situ doping. The strained material portionsmay be a single layer or a multi-layer.

is a perspective view of the semiconductor device at one of various stages of the manufacturing method. In step Sinand as shown in, an interlayer dielectric layeris formed on the insulatorsand covering the strained material portions. In some embodiments, the interlayer dielectric layeris formed adjacent to the spacer structures. In some embodiments, the interlayer dielectric layerincludes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon doped silicon oxide (e.g., SiCOH), polyimide, and/or a combination thereof. In some other embodiments, the interlayer dielectric layerincludes low-K dielectric materials. Examples of low-K dielectric materials include BLACK DIAMOND® (Applied Materials of Santa Clara, Calif.), Xerogel, Acrogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), Flare, SILK® (Dow Chemical, Midland, Mich.), hydrogen silsesquioxane (HSQ) or fluorinated silicon oxide (SiOF), and/or a combination thereof. It is understood that the interlayer dielectric layermay include one or more dielectric materials and/or one or more dielectric layers.

In some embodiments, the interlayer dielectric layeris formed to a suitable thickness by flowable CVD (FCVD), CVD, high density plasma CVD (HDPCVD), sub-atmospheric CVD (SACVD), spin-on, sputtering, or other suitable methods. Specifically, an interlayer dielectric material layer (not illustrated) is formed to cover the insulatorsand the dummy gate stackfirst. Subsequently, the thickness of the interlayer dielectric material layer is reduced until a top surface of the dummy gate stackis exposed, so as to form the interlayer dielectric layer. The process of reducing the thickness of the interlayer dielectric material layer is achieved by a chemical mechanical polishing (CMP) process, an etching process, or other suitable process. The disclosure is not limited thereto.

is a perspective view of the semiconductor device at one of various stages of the manufacturing method.is a sectional view illustrating the semiconductor device oftaken along the line D-D′. In step Sinand as shown inand, a gate stackis formed by replacing the dummy gate stackwith the gate stack. In some embodiments, the polysilicon stripA and the hard mask stripB located on the channel regionA of the semiconductor finsare removed. In one embodiment, the polysilicon stripsA and the hard mask stripsB are removed by anisotropic etching, whereas the spacer structures, the liner structureand the dielectric layerare retained. After removing the dummy gate stack, a gate stackis formed over the channel regionA of the semiconductor fins, and over the liner structureand on the dielectric layer.

As illustrated inand, the gate stackincludes a gate dielectric layerA and a gate electrode layerB, and the gate stackis located in between the spacer structures. In an embodiment, the gate dielectric layerA is formed within the recesses between the spacer structuresand on the dielectric layer, and over the channel regionsA of the semiconductor fins. In some embodiments, the gate dielectric layerA is conformally formed on the dielectric layerand over the liner structure. In some embodiments, a thickness of the gate dielectric layerA is maintained to be the same along the base portionsC, the sidewall portionsB and the cap portionA of the liner structure.

In some embodiments, the material of the gate dielectric layerA includes silicon oxide, silicon nitride or the combination thereof. In some embodiments, the gate dielectric layerA includes a high-k dielectric material, and the high-k dielectric material has a k value greater than about 3.9 and includes a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb and combinations thereof. In some embodiments, the gate dielectric layerA is formed by atomic layered deposition, molecular beam deposition (MBD), physical vapor deposition (PVD) or thermal oxidation. After forming the gate dielectric layerA, the gate electrode layerB is formed on the gate dielectric layerA, over the channel regionA of the semiconductor finsand fills the remaining recesses between the spacer structures. In certain embodiments, the gate dielectric layerA is formed in between the gate electrode layerB and the dielectric layer.

In some embodiments, the gate electrode layerB includes a metal-containing material, such as Al, Cu, W, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi or a combination thereof. Depending on whether the semiconductor device is a p-type FinFET or an n-type FinFET, the materials of the gate dielectric layerA and/or the gate electrode layerB are appropriately chosen. Optionally, a chemical mechanical polishing (CMP) process is performed to remove the excess portions of gate dielectric layerA and the gate electrode layerB. The spacer structuresare located on sidewalls of the gate dielectric layerA and the gate electrode layerB. In other words, the dummy gate stackis replaced, and the gate stackis formed. In some embodiments described herein, the gate stackis a replacement metal gate, but the structure(s) of the gate stack(s) or the fabrication processes thereof are not limited by these embodiments. Up to here, a semiconductor device SMaccording to some embodiments of the present disclosure is accomplished.

toare perspective and sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure. The embodiment shown intois similar to the embodiment shown into, hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein. The difference between the embodiments is that the dielectric layeris omitted.

In the exemplary embodiment, the same steps described intomay be performed to form the liner structureover the insulatorsand across the semiconductor fins. Referring to, after forming the liner structure, a dummy gate stackis formed on the liner structureand across the semiconductor fins. For example, the dummy gate stackcovers the channel regionA of the semiconductor fins. Furthermore, spacer structuresare formed over the liner structureon two opposite sides of the dummy gate stack.

Referring to, in a next step, the liner structureis patterned so that side surfacesSD of the liner structureare aligned with side surfaces of the spacer structure. In some embodiments, portions of the liner structurenot covered by the dummy gate stackand the spacer structuresare removed. In certain embodiments, the liner structuremay be patterned or removed by, for example, anisotropic etching, isotropic etching, and/or through atomic layer etching (ALE) processes.

Referring to, the same steps may be performed to form strained material portionson the source/drain regionsB of the semiconductor fins, whereby the strained material portionscovers and contacts the semiconductor fins. Similarly, an interlayer dielectric layeris formed on the insulatorsand covering the strained material portions.

is a perspective view of the semiconductor device at one of various stages of the manufacturing method.is a sectional view illustrating the semiconductor device oftaken along the line E-E′. Referring toand, after forming the interlayer dielectric layer, the dummy gate stackmay be removed and replaced with gate stack. As such, a semiconductor device SMaccording to some other embodiments of the present disclosure is accomplished. Referring toand, on the channel regionA (see) of the semiconductor fins, the liner structurestill includes the cap portionA, sidewall portionsB and the base portionsC. For example, the liner structureis sandwiched in between the semiconductor finsand the gate dielectric layerA.

toare the perspective and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure. The embodiment shown intois similar to the embodiment shown into, hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein. The difference between the embodiments is in the material of the semiconductor fins.

Referring to, the same steps described intomay be performed to form the semiconductor fins, and insulatorsin between the semiconductor fins. In the previous embodiments, the semiconductor finsmay be silicon fins, for example. However, the disclosure is not limited thereto, and into, the semiconductor finsare silicon-germanium (SiGe) fins, for example. In the exemplary embodiment, when the semiconductor finsare silicon germanium fins, an additional capping layermay be formed to cover the semiconductor fins. In some embodiments, the capping layermay be a silicon capping layer. In some embodiments, the capping layeris formed over the semiconductor finsby low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). For example, the capping layercovers the top surfacesT and sidewallsSD of the semiconductor fins. In some embodiments, the capping layer(silicon capping layer) is used to prevent the oxidation on the semiconductor finsduring the formation of the liner structureperformed in a subsequent step. In certain embodiments, the capping layerprevents the formation of silicon germanium oxide (SiGeOx), which may affect the mobility of the semiconductor device.

Referring to, after forming the capping layer, the same steps described intomay be performed to form the liner structureover the capping layer, and to form the dielectric layerover the liner structure. Thereafter, a dummy gate stackand spacer structuresare formed on the dielectric layer, whereby the dummy gate stackis located in between the spacer structures.

is a perspective view of the semiconductor device at one of various stages of the manufacturing method.is a sectional view illustrating the semiconductor device oftaken along the line F-F′. Referring toand, after forming the dummy gate stackand the spacer structures, the dielectric layeris patterned so that side surfacesSD of the dielectric layerare aligned with side surfaces of the spacer structure. Similarly, portions of the liner structurelocated on the source/drain regionsB (see) of the semiconductor finsmay be patterned and removed along with the dielectric layer.

Referring toand, on the channel regionA (see) of the semiconductor fins, the liner structurestill includes the cap portionA, sidewall portionsB and the base portionsC. Furthermore, in some embodiments, the capping layermay be retained on the source/drain regionsB (see) of the semiconductor fins. However, the disclosure is not limited thereto. For example, in some alternative embodiments, the capping layeron the source/drain regionsB may be removed to reveal the semiconductor finsbefore forming the strained material portions. As illustrated inand, in some embodiments, the capping layeris sandwiched in between the liner structureand the channel regionA of the semiconductor fins. In certain embodiments, the liner structureis sandwiched in between the capping layerand the dielectric layer.

Referring to, the same steps may be performed to form strained material portionson the source/drain regionsB of the semiconductor fins, whereby the strained material portionscovers and contacts the capping layer(silicon capping layer). Similarly, an interlayer dielectric layeris formed on the insulatorsand covering the strained material portions.

is a perspective view of the semiconductor device at one of various stages of the manufacturing method.is a sectional view illustrating the semiconductor device oftaken along the line G-G′. Referring toand, after forming the interlayer dielectric layer, the dummy gate stackmay be removed and replaced with gate stack. As such, a semiconductor device SMaccording to some other embodiments of the present disclosure is accomplished. Referring toand, on the channel regionA (see) of the semiconductor fins, the liner structurestill includes the cap portionA, sidewall portionsB and the base portionsC. For example, the liner structureis located in between the capping layerand the gate stack. In certain embodiments, the liner structureis sandwiched in between the capping layerand the dielectric layer.

toare the perspective views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure. The embodiment shown intois similar to the embodiment shown into, hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein. The difference between the embodiments is in the way of patterning the liner structure.

is a stage of manufacturing a semiconductor device similar to that described in, whereby a dummy gate stackand spacer structuresare formed on the dielectric layer. Referring to, after forming the dummy gate stackand the spacer structures, the dielectric layeris patterned so that side surfacesSD of the dielectric layerare aligned with side surfaces of the spacer structure. In some embodiments, portions of the liner structurelocated on the source/drain regionsB (see) of the semiconductor finsmay be patterned and removed along with the dielectric layer. For example, after the patterning process, the liner structureincludes the cap portionA located on the source/drain regionsB of the semiconductor fins, whereas the sidewall portions and the base portionsC are removed. In certain embodiments, sidewalls of the finsare also revealed after the patterning process. In some embodiments, through the patterning or etching processes, a thickness of the cap portionA on the source/drain regionsB is also reduced. In the exemplary embodiment, since the cap portionA initially has a thickness greater than that of the sidewall portionsB and the base portionsC, the cap portionA may be retained on the semiconductor finsafter the patterning/etching processes.

Referring to, the same steps may be performed to form strained material portionson the source/drain regionsB of the semiconductor fins, whereby the cap portionA may be covered by the strained material portions. In certain embodiments, the cap portionA of the liner structureis disposed over the source/drain regionsB of the semiconductor finsand sandwiched in between the strained material portionsand the semiconductor fin. Similarly, an interlayer dielectric layeris formed on the insulatorsand covering the strained material portions. Referring to, after forming the interlayer dielectric layer, the dummy gate stackmay be removed and replaced with gate stack. As such, a semiconductor device SMaccording to some other embodiments of the present disclosure is accomplished.

toare the perspective and cross-sectional views illustrating various stages of a method of fabricating semiconductor devices in accordance with some other embodiments of the disclosure. The embodiment shown intois similar to the embodiment shown into, hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein. The difference between the embodiments is in the design of the semiconductor fins.

is a stage of manufacturing a semiconductor device similar to that described in, whereby the liner structureand the dielectric layerare pattered so that their side surfaces (SD/SD) may be aligned with side surfaces of the spacer structure. Referring to, after patterning the liner structureand the dielectric layer, the semiconductor finsexposed by the dummy gate stackand the spacer structuresare removed/recessed to form a plurality of recessed portions Rc. For example, portions of the semiconductor finsmay be removed by, anisotropic etching, isotropic etching, or a combination thereof. In some embodiments, portions of the semiconductor finsare recessed below the top surfaces of the insulators. In some embodiments, a depth of the recessed portions Re is less than a thickness of the insulators. In other words, the semiconductor finsexposed by the dummy gate stackand the spacer structuresare not entirely removed, and the remaining semiconductor finslocated in the recessed portion Rc form the source/drain regions of the semiconductor fins.

Referring to, in a next step, strained material portionsmay be formed over the recessed portions Rc of the semiconductor fins. In some embodiments, the strained material portionsextends beyond the top surfaces of the insulators. The strained material portionsis similar to that described in, thus its detailed discussion will be omitted herein. Referring to, the same steps may be performed to form an interlayer dielectric layeron the insulatorsand covering the strained material portions. Subsequently, the dummy gate stackmay be removed and replaced with gate stack. As such, a semiconductor device SMaccording to some other embodiments of the present disclosure is accomplished.

is a cross-sectional view illustrating a semiconductor device in accordance with some alternative embodiments of the disclosure. The semiconductor device illustrated inis similar to the semiconductor device SMillustrated in, hence the same reference numerals are used to refer to the same or like parts, and its detailed description will be omitted herein. The difference between the embodiments is in the design of the liner structure.

In the previous embodiments, the liner structureis formed with a cap portionA having a substantially planar top surface. However, the disclosure is not limited thereto. Referring to, the cap portionA of the liner structurehas a curved top surface. In the exemplary embodiment, a tip of the cap portionA has the maximum thickness T, while a side of the cap portionA joined with the first sidewall portionB-has thickness T, and another side of the cap portionA joined with the second sidewall portionB-has thickness T. The thicknesses Tand Tbeing smaller than the thickness T. In other words, a thickness of the liner structureincreases from the first sidewall portionB-to the cap portionA and decreases from the cap portionA to the second sidewall portionB-.