Multi-Function Substrate

This application is a Continuation of U.S. application Ser. No. 18/741,863, filed on Jun. 13, 2024, which is a Continuation of U.S. application Ser. No. 17/869,827, filed on Jul. 21, 2022 (now U.S. Pat. No. 12,113,071, issued on Oct. 8, 2024), which is a Divisional of U.S. application Ser. No. 17/189,709, filed on Mar. 2, 2021 (now U.S. Pat. No. 11,532,642, issued on Dec. 20, 2022), which claims the benefit of U.S. Provisional Application No. 63/124,983, filed on Dec. 14, 2020. The contents of the above-referenced patent applications are hereby incorporated by reference in their entirety.

Integrated circuits have traditionally been formed on bulk semiconductor substrates. A bulk semiconductor substrate is a substrate that comprises a free standing semiconductor material (e.g., silicon). In recent years, semiconductor-on-insulator (SOI) substrates have emerged as an alternative to bulk semiconductor substrates. An SOI substrate comprises a handle substrate, an insulating layer (e.g., a buried oxide) over the handle substrate, and an active semiconductor layer over the insulating layer.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In modern day integrated chip fabrication, devices (e.g., transistor devices, passive devices, etc.) are typically formed in either bulk substrates or SOI (semiconductor-on-insulator) substrates. However, it has been appreciated that the different structures of bulk substrates and SOI substrates have different characteristics, which may be advantageous to different types of devices. For example, some types of devices, such as low noise amplifiers (LNA), transmit/receive (T/R) switches, or the like, may have a better performance when formed within a thin active semiconductor layer of an SOI substrate. Other types of devices, such as core CMOS devices (e.g., core NMOS devices and/or core PMOS devices within a processor), I/O CMOS devices, high-voltage devices, or the like, may have a better performance when formed on a thicker layer of semiconductor material of a bulk substrate. Because different types of devices may perform better in different types of substrates, a single type of substrate may not be able to provide optimal performance for different types of devices on a same die.

To fabricate a die that provides good performance for different types of devices, a multi-function substrate having different regions with different structures may be used. For example, a multi-function substrate may comprise both bulk regions and SOI regions. A multi-function substrate may be formed by selectively patterning an SOI substrate to remove an insulating layer and an active semiconductor layer, and to expose an upper surface of a base substrate. A selective epitaxial growth of a semiconductor material is subsequently performed on the exposed upper surface of the base substrate. However, the patterning process used to remove the insulating layer and the active semiconductor layer may expose defects (e.g., crystal originated particle (COP) defects) that are present along the upper surface of the base substrate. These defects may negatively affect a growth of the overlying semiconductor material and lead to degradation in performance of devices subsequently formed within the semiconductor material.

The present disclosure, in some embodiments, relates to an integrated chip comprising a multi-function substrate having different regions (e.g., a bulk region and an SOI region) with different structures. The integrated chip comprises a base substrate having an upper surface that is substantially devoid of COP defects. In some embodiments, the base substrate may comprise an epitaxial layer disposed over a high resistivity semiconductor body (e.g., a semiconductor body having a resistivity of greater than approximately 1 kΩ-cm). Within a first region, an active semiconductor layer is separated from the epitaxial layer by a dielectric layer. Within a second region, a semiconductor material is disposed on the epitaxial layer. Having a single substrate comprising different regions with different structures allows for different types of devices to be formed within a single die. By forming both different types of devices on a single die, the performance of an integrated chip can be improved. Furthermore, by having a base substrate with an upper surface that is substantially devoid of COP defects, the negative effect of the defects on the semiconductor material can be mitigated.

illustrates a cross-sectional view of some embodiments of an integrated chiphaving a multi-function substrate (e.g., a localized BOX substrate).

The integrated chipcomprises a substratehaving a first regionand a second region. The first regionand the second regionof the substratehave different structures (e.g., stacks of one or more different layers/materials) that provide for different characteristics (e.g., performance) to different types of devices. In some embodiments, the first regionmay comprise an SOI region (e.g., a region having an active semiconductor layer separated from a base substrate by an insulating material), while the second regionmay comprise a bulk region (e.g., a region having a semiconductor material continuously extending between upper and lower surfaces of the substrate). In some embodiments, the substratemay comprise a die, a wafer, or the like.

Within the first region, the substratecomprises a polysilicon layerdisposed over a base substrate, a dielectric layer(e.g., a buried oxide (BOX) layer) disposed over the polysilicon layer, and an active semiconductor layerdisposed over the dielectric layer. Within the second region, the substratecomprises a semiconductor materialdisposed over the base substrate. The semiconductor materialhas a greater thickness than that of the active semiconductor layer. In some embodiments, the base substratemay have an upper surfacethat is substantially devoid of defects (e.g., COP defects). In some embodiments, the semiconductor materialmay directly contact the base substrate.

A gap fill structureis laterally arranged between the first regionand the second region. In various embodiments, the gap fill structuremay comprise a dielectric material (e.g., an oxide, a nitride, or the like), a semiconductor material (e.g., doped silicon, un-doped silicon, doped germanium, un-doped germanium, amorphous silicon, polysilicon, or the like), and/or the like. In some embodiments, the gap fill structurecovers a sidewall of the active semiconductor layerand a sidewall of the semiconductor material. In some additional embodiments, the gap fill structurecontinuously extends from along the sidewall of the active semiconductor layerto along sidewalls of the dielectric layerand/or the polysilicon layer.

The different structures of the first regionand the second regionallow for the substrateto provide for different characteristics on different parts of a same integrated chip (e.g., a same integrated chip die). By having different structures that provide different characteristics on different parts of a same integrated chip, the integrated chipis able to provide for good performance to different types of devices. For example, the relatively thin active semiconductor layerand the dielectric layerwithin the first regionmay suppress body capacitance, reduce cross-talk, and/or provide for good performance (e.g., allow high speed and/or low power operation) to an RF device (e.g., a LNA, T/R switch, or the like), while the relatively thick semiconductor materialwithin the second regionmay prevent floating body effects and provide for good performance to a digital device (e.g., a core CMOS device, an I/O CMOS device, a high voltage device, or the like).

illustrates a cross-sectional view of some additional embodiments of an integrated chiphaving a multi-function substrate.

The integrated chipcomprises a substratehaving a first regionand a second region. In some embodiments, the first regioncomprises a polysilicon layerdisposed on a base substrate, a dielectric layerdisposed on the polysilicon layer, and an active semiconductor layerdisposed on the dielectric layer. In other embodiments (not shown), the polysilicon layermay be omitted, such that the dielectric layeris disposed directly onto the base substratewithin the first region. In some embodiments, the base substratemay comprise a high-resistivity substrate (e.g., a substrate having a resistivity that is greater than or equal to approximately 1 kΩ-cm), and the polysilicon layermay comprise a trap-rich (TR) polysilicon layer (e.g., a polysilicon layer having a trap density of greater than approximately 10cmeV, greater than approximately 10cmeV, or other similar values). The density of traps within the polysilicon layeris configured to reduce RF (radio frequency) second harmonic distortion of devices within the first region. In some embodiments, the polysilicon layermay have a first thicknessthat is in a range of between approximately 0.1 micron (μm) and approximately 0.2 μm, between approximately 2 μm and approximately 0.5 μm, between approximately 1 μm and approximately 2 μm, between approximately 0 μm and approximately 3 μm, of approximately 1.5 μm, or other similar values.

In some embodiments, the polysilicon layermay comprise grain sizes-that are in a range of between approximately 50 nm and approximately 300 nm, between approximately 90 nm and approximately 230 nm, or other similar values. The relatively small grain sizes-allow for the polysilicon layerto effectively trap charge carriers and provide for good isolation and/or to decrease cross-talk between devices within the first region. In some embodiments, the grain sizes-may increase as a thickness of the polysilicon layerincreases. For example, in some embodiments, the polysilicon layermay have a first grain sizenear a bottom of the polysilicon layer(e.g., along the interface between the polysilicon layerand the base substrate) and a second grain size, which is larger than the first grain size, near a top of the polysilicon layer(e.g., along the interface between the polysilicon layerand the dielectric layer). In some embodiments, the first grain sizemay be in a range of between approximately 15% and approximately 30% of the second grain size. For example, in some embodiments, the first grain sizemay be approximately 90 nm and the second grain sizemay be approximately 230 nm.

In some embodiments, the base substratemay be doped within a dopant species having a first doping type. In some additional embodiments, a part of the polysilicon layermay be doped with the dopant species having the first doping type. In some embodiments, the dopant species within the polysilicon layermay have a maximum doping concentration that is greater than approximately 1e12 at/cm, greater than approximately 1e13 at/cm, less than approximately 1.4e13 at/cm, approximately 1e15 at/cm, or other similar values. In some embodiments, the polysilicon layermay have a gradient doping concentration that decreases as a distance from a lower surface of the polysilicon layerincreases. For example, the doping concentration may decrease from the maximum doping concentration along the lower surface of the polysilicon layerto an intrinsic doping concentration at a distance over the lower surface.

In some embodiments, the dielectric layermay comprise an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride, silicon oxynitride, etc.), or the like. In some embodiments, the dielectric layermay have a second thicknessthat is in a range of between approximately 200 Angstroms (Å) and approximately 2 μm, between approximately 200 nm and approximately 1 μm, or other similar values. In some embodiments, the active semiconductor layermay comprise silicon, germanium, or the like. In some embodiments, the active semiconductor layermay have a third thicknessthat is less than or equal to approximately 2 kÅ, less than or equal to approximately 1 kÅ, that is approximately 750 Å, or other similar values.

A gap fill structurelaterally separates the first regionfrom the second region. In some embodiments, the gap fill structuremay comprise a dielectric material, a semiconductor material, and/or the like. The gap fill structuremay have a widththat is between approximately 0 μm and approximately 20 μm, between approximately 1 μm and approximately 10 μm, or other similar values. In some embodiments, the widthof the gap fill structuremay increase as a distance over the base substrateincreases, so that an upper surface of the gap fill structureis wider than a lower surface of the gap fill structure. In some embodiments, the gap fill structuremay have a height that extends from a top surface of the active semiconductor layerto below a bottom surface of the active semiconductor layer. In some embodiments, the gap fill structuremay further extend below a bottom surface of the dielectric layerand/or to below a bottom surface of the polysilicon layer(e.g., to directly between sidewalls of the base substrate).

In some embodiments, the second regioncomprises a semiconductor materialdisposed over an upper surfaceof the base substrate. In some embodiments, the upper surfaceof the base substratemay be substantially devoid of defects. In some additional embodiments, one or more defectsmay be arranged within the base substrateat positions that are vertically separated from the upper surfaceby a regionof the base substratethat is substantially devoid of defects (e.g., COP defects). In such embodiments, because the defectsare vertically separated from the semiconductor materialby the regionthat is substantially devoid of defects, the defectsdo not negatively impact growth of the semiconductor material.

The semiconductor materialmay be a same material as the base substrate. For example, the semiconductor materialmay comprise silicon, germanium, or the like. In some embodiments, the semiconductor materialmay have a fourth thicknessthat is substantially equal to a sum of the thicknesses of the polysilicon layer, the dielectric layer, and the active semiconductor layer. In some embodiments, the fourth thicknessmay be greater than approximately 1 μm, greater than approximately 2 μm, greater than approximately 5 μm, or other similar values. In some embodiments, the semiconductor materialcontacts the base substrate.

In some embodiments, the active semiconductor layermay have an upper surfacethat is substantially co-planar (e.g., co-planar within a tolerance of a chemical mechanical planarization process) with an upper surfaceof the semiconductor material. The substantially planar upper surfaces of the active semiconductor layerand the semiconductor materialallow for good depth of focus on subsequently performed lithographic processes. For example, lithography processes used to form interconnects within an inter-level dielectric (ILD) layer over the first regionand the second regioncan be performed without depth of focus issues.

Although the disclosed substrateis illustrated as having a single first region (e.g.,) and a single second region (e.g.,), it will be appreciated that in some embodiments the disclosed substratemay have multiple first regions (e.g., multiple SOI regions) and multiple second regions (e.g., multiple bulk regions) having different structures. For example, in some embodiments, the substratemay comprise a wafer having a plurality of first regionsand a plurality of second regionsarranged on different parts of the wafer. In other embodiments, the substrate may comprise a die having a plurality of first regionsand a plurality of second regions.

It will be appreciated that the first regionand the second regionmay have various shapes in different embodiments.illustrate top-views of various embodiments of a disclosed multi-function substrate. It will be appreciated thatare not limiting examples of a first regionand a second region, and that the first regionand/or the second regionmay have different shapes than those shown inin alternative embodiments.

In some embodiments, shown in top-viewof, the first regionmay comprise a substantially rectangular shaped region and the second regionmay comprise a rectangular shaped region.

In some alternative embodiments, shown in top-viewof, the first regionmay comprise a substantially “T” shaped region.

In yet other alternative embodiments, shown in top-viewof, the first regionmay comprise a multi-sided shaped region (e.g., a polygonal shaped region). In some embodiments, the first regionmay have an asymmetric shape.

illustrates a cross-sectional view of some additional embodiments of an integrated chiphaving a multi-function substrate.

The integrated chipcomprises a substratehaving a base substrateincluding a first regionand a second region. In some embodiments, the base substratemay comprise an epitaxial layerarranged on a semiconductor bodywithin the first regionand within the second region. In some embodiments, the semiconductor bodyand the epitaxial layercontinuously extend from within the first regionto within the second region. In other embodiments, the epitaxial layermay be discontinuous between the first regionand the second region. For example, the epitaxial layermay be interrupted by a gap fill structure, which extends into and/or through the epitaxial layer. In some embodiments, the gap fill structuremay vertically contact the epitaxial layer. Within the first region, a polysilicon layeris disposed on the epitaxial layer, a dielectric layeris disposed on the polysilicon layer, and an active semiconductor layeris disposed on the dielectric layer. Within the second region, a semiconductor materialis disposed on the epitaxial layer.

In some embodiments, the semiconductor bodymay be doped within a dopant species having a first doping type. In some additional embodiments, a part of the epitaxial layermay be doped with the dopant species having the first doping type. In some embodiments, the dopant species within the epitaxial layermay have a maximum doping concentration that is greater than approximately 1e12 at/cm. Such a doping concentration will give the epitaxial layera relatively high resistivity (e.g., greater than approximately 1 kΩ-cm) to improve performance of devices within the first region. In some embodiments, the epitaxial layermay have a gradient doping concentration that decreases as a distance from a lower surface of the epitaxial layerincreases. For example, the doping concentration may decrease from the maximum doping concentration along the lower surface of the epitaxial layerto an intrinsic doping concentration at a distance over the lower surface.

In some embodiments, the semiconductor bodyand the epitaxial layermay comprise a same semiconductor material, such as silicon, germanium, or the like. In some embodiments, the semiconductor bodymay comprise one or more defectsarranged along a part of an upper surface of the semiconductor bodythat is directly below the epitaxial layerand the semiconductor material. In some embodiments, the one or more defectsmay comprise crystal originated particle (COP) defects. In some embodiments, the epitaxial layermay contact the one or more defectsarranged the upper surface of the semiconductor body.

It has been appreciated that a thicknessof the epitaxial layermay reduce defects along a top of the epitaxial layer. For example, an epitaxial layerhaving a thicknessof greater than approximately 500 nm will have fewer defects along an upper surface than an epitaxial layerhaving a thickness of greater than 100 nm. In some embodiments, the epitaxial layermay have a thicknessthat is greater than approximately 100 nm, greater than approximately 200 nm, in a range of between approximately 100 nm and approximately 500 nm, between approximately 100 nm and approximately 1 μm, or other similar values.

In some embodiments, the upper surface of the epitaxial layerwithin the second regionmay be substantially devoid of COP defects. Because the upper surface of the epitaxial layerwithin the second regionis substantially devoid of COP defects, the epitaxial layeris able to mitigate negative impacts of the one or more defects in the base substrateand improve performance of devices within the second region. In some embodiments, the epitaxial layermay also reduce a formation time and/or a thickness of the semiconductor materialwithin the second region, thereby leading to lower total thickness variation (TTV) between the first regionand the second regionand/or a lower fabrication cost.

illustrate cross-sectional views of some additional embodiments of integrated chips,and, having a multi-function substrate.

The integrated chipofand the integrated chipofrespectively comprise a substratehaving a first regionand a second region. A first deviceis disposed within an active semiconductor layerarranged along an upper surface of the substratewithin the first region, and a second deviceis disposed within a semiconductor materialarranged along the upper surface of the substratewithin the second region. The first deviceis a different type of device than the second device. For example, in some embodiments the first devicemay comprise a low noise amplifier (LNA), a transmit/receive (T/R) switch, or the like, and the second device may comprise a core CMOS device (e.g., core NMOS device and/or core PMOS device within a processor), an I/O CMOS device, a high-voltage device, or the like.

Although the integrated chipofand the integrated chipofillustrate a single device within the first regionand the second region, it will be appreciated that the first regionand the second regionmay respectively comprise a plurality of devices. For example, the first regionand/or the second regionmay have widths that are on the order of millimeters (mm) wide, so that the regions comprise a plurality of devices.

In some embodiments, the first devicewithin the first regionand the second devicewithin the second regionmay be laterally separated by an isolation structuredisposed within the substrate. In some embodiments, the isolation structuremay comprise a shallow trench isolation (STI) structure comprising one or more dielectric materials disposed within a trench in the substrate. In some embodiments, the isolation structuremay extend to the base substrate. In other embodiments (not shown), the isolation structuremay have a bottommost surface that is separated from the base substrateby one or more layers (e.g., a gap fill structure, a semiconductor material, etc.)

An inter-level dielectric (ILD) structureis disposed over the substrateand extends over both the first regionand the second region. In some embodiments, the ILD structurecomprises a plurality of stacked ILD layers disposed over the substrate. In some embodiments, the plurality of stacked ILD layers may comprise one or more of silicon dioxide, silicon nitride, carbon doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphorus silicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), a porous dielectric material, or the like.

The ILD structuresurrounds a plurality of interconnects-. In some embodiments, the plurality of interconnects-may comprise one or more of a middle of line (MOL) interconnect, a conductive contact, an interconnect wire, an interconnect via, or the like. In some embodiments, the plurality of interconnects-may comprise one or more of copper, tungsten, ruthenium, aluminum, or the like. Having the plurality of interconnects-within the ILD structurecoupled the different types of devices within the first regionand the second region, provides the integrated chipsandwith good performance since the interconnects are relatively short (e.g., shorter than interconnects between an SOI die and a bulk die) and thereby provide for relatively low resistances.

illustrates a cross-sectional view of some additional embodiments of an integrated chiphaving a multi-function substrate.

The integrated chipcomprises a substratehaving an epitaxial layerdisposed over a semiconductor bodywithin a first regionand within a second region. Within the first region, a polysilicon layeris disposed over and recessed within the epitaxial layer. In some embodiments, a bottommost surface of the polysilicon layeris separated from the semiconductor bodyby the epitaxial layer. In such embodiments, a sidewallof the polysilicon layeris arranged along a sidewall of the epitaxial layer. In some embodiments, the polysilicon layermay be recessed to a first distancebelow an upper surface of the epitaxial layer. In some embodiments, the first distancemay be in a range of greater than approximately 100 nm, greater than approximately 50 nm, or other similar values. In some embodiments, the polysilicon layermay have an upper surface that is substantially co-planar with an upper surface of the epitaxial layer.

A gap fill structureextends through a semiconductor materialto contact an upper surface of the epitaxial layer. In some embodiments, the gap fill structuremay completely cover sidewalls of the semiconductor material, a dielectric layer, and an active semiconductor layer. In some embodiments, the gap fill structurecomprises a spacerand a gap fill materialarranged along a sidewall of the spacer. In some embodiments, the gap fill materialmay cover a sidewall of the semiconductor materialand the spacermay cover sidewalls of the dielectric layerand the active semiconductor layer. In some embodiments, the gap fill materialmay comprise a semiconductor material such as silicon, germanium, or the like. In some embodiments, the spacermay comprise one or more dielectric materials, such as an oxide, a nitride, a carbide, or the like.

illustrates a cross-sectional view of some additional embodiments of an integrated chiphaving a multi-function substrate.

The integrated chipcomprises a polysilicon layerrecessed within the epitaxial layer. The polysilicon layerprotrudes outward from the epitaxial layerto a second distanceabove an upper surface of the epitaxial layer, so that the polysilicon layercontinuously extends from along a sidewall of the epitaxial layerto above an uppermost surface of the epitaxial layer. In some embodiments, a gap fill materialmay cover a sidewall of a semiconductor materialand a spacermay cover sidewalls of the polysilicon layer, a dielectric layerover the polysilicon layer, and an active semiconductor layerover the dielectric layer. In some embodiments, the polysilicon layermay protrude outward from the epitaxial layerto a second distanceabove an upper surface of the epitaxial layer.

illustrates a cross-sectional view of some additional embodiments of an integrated chiphaving a multi-function substrate.

The integrated chipcomprises a polysilicon layerrecessed within the epitaxial layer. In some embodiments, a polysilicon layeris recessed below an upper surface of the epitaxial layer. In some embodiments, the epitaxial layermay extend along sidewalls of the polysilicon layerand a dielectric layerover the polysilicon layer. In some embodiments, the polysilicon layermay have an uppermost surface that is recessed a third distancebelow an uppermost surface of the epitaxial layer, so that the epitaxial layercontinuously extends from below the uppermost surface of the polysilicon layerto above the uppermost surface of the polysilicon layer.

It will be appreciated that in some embodiments, the disclosed integrated chip (e.g., shown in) may comprise a gap fill structurethat includes a gap fill materialand not a spacer. For example,illustrates a cross-sectional view of some embodiments of an integrated chiphaving a multi-function substrate having a gap fill structurethat does not have a spacer.

The integrated chipcomprises a polysilicon layerrecessed within the epitaxial layer. Within a first region, a dielectric layeris over the polysilicon layerand an active semiconductor layeris over the dielectric layer. Within a second region, a semiconductor materialis over the epitaxial layer. A gap fill structureis disposed laterally between the first regionand the second region. In some embodiments, the gap fill structurecomprises the gap fill materialwithout the spacer, such that the gap fill structureis a gap fill material. The gap fill materialmay continuously extend from a sidewall of the dielectric layerto a sidewall of the semiconductor material. In some embodiments, the gap fill materialmay comprise a semiconductor material, such as silicon, germanium, or the like. In some embodiments, the gap fill materialmay be partially polysilicon and partially silicon, due to imperfect growth of the gap fill materialalong sidewalls of the dielectric layerand/or the polysilicon layer.

illustrates a cross-sectional view of some additional embodiments of an integrated chiphaving a multi-function substrate.

The integrated chipcomprises a substratehaving a first regionand a second region. Within the first region, a polysilicon layeris disposed on a semiconductor body, a dielectric layeris disposed over the polysilicon layer, and an active semiconductor layeris disposed over the dielectric layer. Within the second region, an epitaxial layeris disposed on the semiconductor bodyand a semiconductor materialis disposed over the epitaxial layer.

In some embodiments, the polysilicon layerhas an outermost sidewall that faces and/or contacts an outermost sidewall of the epitaxial layer. In some such embodiments, the polysilicon layerand the epitaxial layerhave lower surfaces that contact the semiconductor body. In some additional embodiments, the polysilicon layerand the epitaxial layerhave lower surfaces that are substantially co-planar. In some embodiments, the polysilicon layerhas an upper surface that is a first distanceover an upper surface of the epitaxial layer.