Display Device and Multiplexing Driving Method Thereof

This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0067944 filed at the Korean Intellectual Property Office on May 24, 2024, the entire contents of which are incorporated herein by reference.

Example embodiments relate to a display device and a multiplexing driving method thereof. As a resolution of a display device increases, a size of a source driver that drives the display increases. The source driver includes a plurality of amplifiers connected to a plurality of data lines to supply a plurality of data signals. As the number of the plurality of amplifiers increases, the size of the source driver also increases. To suppress an increase in the size of the source driver, each amplifier may drive two or more data lines. If each amplifier drives the two or more data lines every horizontal period, there is a problem in which an artifact occurs due to a difference in a charge rate of a pixel through the two or more data lines. The charge rate of the pixel may be defined as a ratio between a level of the data signal and a signal level written in the pixel when the data signal is written in the pixel through the data line.

Example embodiments are directed to a display device configured for improving a display image quality in a multiplexing driving method in which each amplifier of the display device drives two or more data lines, and a multiplexing driving method of the display device.

A display device, according to example embodiments, includes a plurality of gate lines and a plurality of data lines, a plurality of first pixels, each first pixel being connected to a first data line of the plurality of data lines and the plurality of gate lines; a plurality of second pixels, each second pixel being connected to a second data line of the plurality of data lines and the plurality of gate lines; a source driver configured to provide a first data signal to the first data line during a first time period in a horizontal period and provide a second data signal to the second data line during a second time period in the horizontal period; and a timing controller configured to: generate first compensation grayscale data by compensating for a first original grayscale data corresponding to an input grayscale for each of the plurality of first pixels based on the input grayscale and a color of each of the first pixels, multiplex the first compensation grayscale data for each of the plurality of first pixels and a second original grayscale data for each of the plurality of second pixels, and provide the multiplexed data to the source driver.

A display device, according to example embodiments, includes a first data line and a second data line; a plurality of first pixels connected to the first data line; a plurality of second pixels connected to the second data line; a source driver configured to multiplex and output a first data signal and a second data signal for the first data line and the second data line during each horizontal period; and a timing controller configured to: generate a compensation dataset according to a driving environment of the display device, generate first compensation grayscale data by compensating for first original grayscale data corresponding to an input grayscale for each of the plurality of first pixels by using a grayscale compensation value based on the input grayscale and a color of each of the first pixels in the compensation dataset, and provide the first compensation grayscale data to the source driver, wherein the first data signal is provided to the first data line.

According to example embodiments, a multiplexing driving method of the display device including a plurality of first pixels connected to a first data line and a plurality of second pixels connected to a second data line includes: generating a compensation dataset corresponding to a driving environment of the display device among a plurality of compensation datasets; detecting grayscale compensation values corresponding to two input grayscales adjacent to first original grayscale data of one of the plurality of first pixels in the compensation dataset and interpolating the two detected grayscale compensation values to generate first grayscale compensation value; generating first compensation grayscale data using the first original grayscale data and the first grayscale compensation value; supplying a first data signal according to the first compensation grayscale data to the first data line; and supplying a second data signal according to second original grayscale data of one of the plurality of second pixels to the second data line.

Example embodiments are directed to a display device configured for improving a display image quality in a multiplexing driving method, and a multiplexing driving method of the display device.

Example embodiments are directed to a display device that may control a method for generating a plurality of first data signals and a plurality of second data signals provided to a plurality of first data lines and a plurality of second data lines among a plurality of data lines. In a multiplexing driving method, the display device may supply the plurality of first data signals to the plurality of first data lines, and the plurality of first data signals may be charged by the plurality of first data lines. For example, the plurality of first data signals may be charged by a plurality of parasitic capacitors of the plurality of first data lines. Each voltage of a plurality of voltages provided to each of the plurality of first data lines may be written in each of a plurality of first pixels connected to the plurality of first data lines. The display device may write the plurality of second data signals in each of a plurality of second pixels connected to the plurality of second data lines through each of the plurality of second data lines. The display device may compensate for an input grayscale for the first pixel to compensate for a luminance displayed by the first pixel based on a luminance displayed by the second pixel. The display device may compensate for an input grayscale for the second pixel to compensate for a luminance displayed by the second pixel based on a luminance displayed by the first pixel.

is a block diagram showing an electronic device, according to some example embodiments.

As shown in, the electronic devicemay include a host central processing unit (CPU), a display device, and a memory device. The electronic devicemay include at least one of various electronic devices including a display such as a smartphone, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a desktop personal computer (PC), a laptop personal computer (PC), a netbook computer, a workstation, a server, a mobile medical device, a smart glass, a head mounted device (HMD), or the like.

The host CPUmay execute a plurality of application software controlling an overall operation of the electronic deviceon an operating system (OS). The host CPUmay generate frame data, or may receive frame data. The host CPUmay directly transmit the frame data to the display device, or may store the frame data in a memory. The host CPUand the display devicemay be integrated and implemented, or may be implemented as a separate device coupled through an interface between the display deviceand the host CPU.

The memorymay write data or may read and output data according to a command of the host CPU. The memorymay store data necessary for an operation of the display devicetogether with the frame data. The display devicemay request from the memorydata necessary for driving (e.g., operating) the display device, and the memorymay read data corresponding to the request and output the read data to the display device. Alternatively, the display devicemay request from the memorydata necessary for driving (e.g., operating) the display device, the host CPUmay transmit a command corresponding to the request to the memory, and the memorymay read and output the data according to the command.

Data transmission and reception between the host CPU, the display device, and the memorymay be performed through a bus. Data transmission and reception between components in the electronic devicemay be performed using a wire other than the bus.

is a block diagram schematically showing a configuration of the display device, according to some example embodiments.

The display devicemay include a display processor, a timing controller, a source driver, a gate driver, and a display panel. A display driving IC (DDI) may include the source driverand the gate driver, or may further include the timing controller.

The display processormay receive the frame data from the host CPUtogether with a frame update command, may perform image signal processing on the frame data in response to the frame update command to generate an image signal IS, may generate a control signal DCON for driving the display device, and may provide the image signal IS and the control signal DCON to the timing controller. The image signal processing may include converting the frame data to generate an image signal suitable for displaying using the display panelbased on a characteristic of the display panel. The image signal IS may be a signal indicating an image to be displayed by the display device, and the control signal DCON may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a main clock signal, or the like required for the display deviceto display the image signal IS. The display processormay include a graphic processing unit (GPU), a visual processing unit (VPU), or the like that may convert the frame data into the image signal IS.

The timing controllermay generate an image data signal IMD for a plurality of pixels PX according to the image signal IS for each frame provided from the display processor. The timing controllermay provide the image data signal IMD to the source driveraccording to the horizontal synchronization signal at every frame defined by the vertical synchronization signal.

The timing controllermay generate the image data signal IMD by processing the image signal IS. The image signal IS may include grayscale data indicating a grayscale of each of the plurality of pixels and address data indicating a position of each of the plurality of pixels. The timing controllermay determine whether the grayscale of the grayscale data is compensated based on the position of each pixel. If the timing controllerdetermines the compensation of the grayscale, the timing controllermay determine compensation grayscale data corresponding to the grayscale data in a compensation dataset corresponding to a driving environment of the display device. The timing controllermay combine the compensation grayscale data with the grayscale data, may determine a gain according to a position of the pixel, and may generate the image data signal according to the compensation grayscale data and the gain. If the timing controllerdetermines that there is no grayscale compensation, the timing controllermay generate the grayscale data as the image data signal. The driving environment of the display devicemay include factors that affect driving of the display device, such as a temperature of the display device, an operating frequency of the display device, a brightness of the display specified by a user, and the like.

The timing controllermay generate a source control signal CONS that controls an operation of the source driverand a gate control signal CONG that controls an operation of the gate driveraccording to the control signal.

The source drivermay convert the image data signal into a plurality of data signals for a plurality of data lines DL_-DL_m according to the source control signal CONS every horizontal period, and may output the plurality of data signals to the plurality of data lines DL_-DL_m.

The gate drivermay generate a gate signal with an ON level according to the gate control signal CONG every horizontal period to output the gate signal to the gate line corresponding to the gate signal. The gate drivermay supply a plurality of gate signals having ON levels to a plurality of gate lines GL_-GL_n in a sequential or non-sequential order every frame. Depending on an ON-level pulse of the gate signal, switching transistors of the plurality of pixels PX connected to the gate line corresponding to the gate signal may be turned ON. Then, the plurality of data signals supplied through the plurality of data lines DL_-DL_m may be written in the plurality of pixels.

According to the source control signal CONS and the gate control signal CONG, a timing at which the source driversupplies the plurality of data signals to the plurality of data lines DL_-DL_m and a timing at which the gate driversupplies the gate signal with the ON level to each of the plurality of gate lines may be synchronized with each other.

Referring briefly toand, illustrated are circuit diagrams showing pixel circuits, according to some example embodiments.

illustrates a circuit of the pixel PX including an organic light-emitting diode (OLED) as a light-emitting device, according to some example embodiments. As shown in, the pixel PX may include a switching transistor M, a driving transistor M, and a capacitor C. A gate of the switching transistor Mis connected to the gate line GL_j, one end of the switching transistor Mis connected to the data line DL_j, and the other end of the switching transistor Mis connected to a gate of the driving transistor M. A voltage ELVDD for driving the pixel PX is supplied to a source of the driving transistor M, and a drain of the driving transistor Mis connected to an anode of the OLED. A voltage ELVSS may be supplied to a cathode of the OLED. If the switching transistor Mis turned ON by the gate signal with the ON level supplied through the gate line GL_i, the data signal of the data line DL_j may be stored in the capacitor C. The driving transistor Mmay supply a driving electric current to the OLED according to a voltage stored in the capacitor C. Because the switching transistor Mis a p-channel type transistor, the ON level of the gate signal may be a low level.

illustrates a circuit of the pixel PX using a liquid crystal (LC) as a display element, according to some example embodiments. The pixel PX may include a switching transistor T, a liquid crystal element Clc, and a capacitor Cs. A gate of the switching transistor Tis connected to the gate line GL_i, one end of the switching transistor Tis connected to the data line DL_j, and the other end of the switching transistor Tis connected to one end of each of the liquid crystal element Clc and the capacitor Cs. A common voltage VCOM may be supplied to the other end of each of the liquid crystal element Clc and the capacitor Cs. If the switching transistor Tis turned on by the gate signal with the ON level supplied through the gate line GL_i, the data signal of the data line DL_j may be stored in the capacitor Cs, and the liquid crystal element Clc may adjust a direction of light according to the data signal. Because the switching transistor Tis an n-channel type transistor, the ON level of the gate signal may be a high level.

The circuit of the pixel PX shown in each ofandis merely an example, provided for the sake of discussion, and it will be understood that different circuit configurations of the pixel PX are equally applicable without departing from the scope of the disclosure.

Returning to, the display panelmay display an image according to the plurality of data signals and the plurality of gate signals provided from the source driverand the gate driver. In example embodiments, the display panelmay be implemented as a thin film transistor liquid crystal display (TFT-LCD) panel, a light emitting diode (LED) display panel, an organic LED (OLED) display panel, an active matrix (AMOLED) display panel, a flexible display panel, or the like. In example embodiments, the display panelmay be implemented as a low-temperature polycrystalline oxide (LTPO) panel.

The display panelmay include the plurality of data lines DL_-DL_m, a plurality of gate lines GL_-GL_n, and the plurality of pixels PX. The plurality of data lines DL_-DL_m may be disposed along a first direction, the plurality of gate lines GL_-GL_n may be disposed along a second direction transverse to the first one direction, the plurality of pixels PX may be disposed in a matrix form at the intersection of corresponding data lines and gate lines, and each pixel PX may be connected to the corresponding data line and the gate line. The plurality of pixels PX may be divided into row units according to a disposition direction of each of the plurality of gate lines GL_-GL_n, and this is referred to as a pixel row. The plurality of pixels PX may be divided into column units according to a disposition direction of each of the plurality of data lines DL_-DL_m, and this is referred to as a pixel column. Each of the plurality of pixels PX may be one color among a red (R) pixel, a green (G) pixel, and a blue (B) pixel. For the sake of discussion, the pixel is defined as a unit that displays one color. Each of the plurality of pixels PX may store the data signal supplied to each pixel through the data line in synchronization with the gate signal supplied to each pixel through the gate line, and may emit light with a grayscale according to the data signal. The pixel may be a light-emitting element, and may include an organic light-emitting diode or a liquid crystal element.

illustrates configurations of the source driverand the display panel, according to some example embodiments.

For the sake of explanation,illustrates four data lines DL_, DL_, DL_, and DL_among the plurality of data lines DL_-DL_m, two amplifiers_and_, and a portion of a source multiplexing circuit.

According to the multiplexing driving method, the source drivermay supply the plurality of data signals to a plurality of first data lines (e.g., DL_and DL_) among the plurality of data lines DL_, DL_, DL_, and DL_during a first time period of one horizontal period and may supply a plurality of second data signals to a plurality of second data signals (e.g., DL_and DL_) among the plurality of data lines DL_, DL_, DL_, and DL_during a second time period of one horizontal period.

A plurality of red pixels Rand Rand a plurality of blue pixels Band Bare alternately connected to the first data line DL_among the plurality of first data lines DL_and DL_, and a plurality of blue pixels Band Band a plurality of red pixels Rand Rare alternately connected to the second data line DL_among the plurality of second data lines DL_and DL_. A plurality of green pixels G, G, G, and Gare connected to the first data line DL_among the plurality of first data lines DL_and DL_, and a plurality of green pixels G, G, G, and Gare connected to the second data line DL_among the plurality of second data lines DL_and DL_. As described above, the red (R) pixel, the green (G) pixel, and the blue (B) pixel may be arranged in a pattern in which pixel columns with four data line units are repeated. A pattern of the pixels shown inis merely an example, and example embodiments are not limited thereto.

A voltage charged in each of a plurality of parasitic capacitors CP_and CP_connected to each of the plurality of first data lines DL_and DL_may be written in the pixel. A parasitic capacitor is also formed in each of the plurality of second data lines DL_and DL_, but, for the sake of discussion, the parasitic capacitor of each of the plurality of second data lines DL_and DL_is not considered to be involved in writing of the data signal in the pixel so that the parasitic capacitor of each of the plurality of second data lines is omitted in.

As shown in, the source drivermay include a driving control circuit, a shift register, a level shifter, a decoder, an output amplification circuit, and the source multiplexing circuit.

The driving control circuitmay generate a clock signal or control signals for controlling an operation of each component of the source driveraccording to the source control signal CONS to provide the control signal corresponding to each component. For example, the driving control circuitmay be configured to generate and provide two multiplexing signals CLA and CLB that control a multiplexing operation of the source multiplexing circuit.

The shift registermay store the image data signal IMD by shifting the image data signal IMD in a unit of one pixel, and may provide a plurality of pixel-unit image data of one pixel row to the level shifteraccording to a latch signal provided from the driving control circuit. The pixel-unit image data are referred to as pixel data.

The level shiftermay shift a digital signal level constituting each of a plurality of pixel data corresponding to one pixel row to provide the shifted level to the decoder. For example, an operating voltage range of the decodermay be higher than an operating voltage range of the shift register. Therefore, the level shiftermay increase a digital signal level constituting each of a plurality of grayscale data to a digital signal level that may be processed by the decoder.

The decodermay receive the plurality of pixel data from the level shifter, and may convert each of the plurality of pixel data that is a digital signal into each of the plurality of data signals that is an analog signal. The decodermay generate a plurality of grayscale voltages corresponding to each of a plurality of grayscales using a plurality of gamma voltages and a plurality of resistor strings. The decodermay generate each of the plurality of data signals by selecting one of the plurality of grayscale voltages according to each of the plurality of pixel data. The decodermay be implemented as a digital-analog converter that converts the pixel data that is a digital signal into the data signal that is an analog signal.

The output amplification circuitmay include a plurality of amplifiers_and_, and each of the plurality of amplifiers_and_may receive each of the plurality of data signals from the decoderto output each of the plurality of data signals. Each of the plurality of amplifiers_and_may be implemented as an operational amplifier. An output of the operational amplifier may be connected (e.g., feedback) to a negative input terminal (−) thereof, a positive input terminal (+) of the operational amplifier may be connected to the decoder, and the data signal may be input to the positive input terminal (+).

The source multiplexing circuitmay include a plurality of switching elements_,_,_, and_connected between the plurality of amplifiers_and_and the plurality of data lines DL_-DL_. The plurality of switching elements_,_,_, and_may perform a switching operation according to one of the multiplexing signals CLA and CLB provided from the driving control circuit. For example, the plurality of switching elements_and_may perform a switching operation according to the multiplexing signal CLA, and the plurality of switching elements_and_may perform a switching operation according to the multiplexing signal CLB. The plurality of switching elements_and_may be turned on during a first time period in which the multiplexing signal CLA is at an ON level, and the plurality of switching elements_and_may be turned on during a second time period in which the multiplexing signal CLB is at an ON level.

One end of the switching element_may be connected to the data line DL_, and the other end of the switching element_may be connected to an output end of the amplifier_. One end of the switching element_may be connected to the data line DL_, and the other end of the switching element_may be connected to an output end of the amplifier_. One end of the switching element_may be connected to the data line DL_, and the other end of the switching element_may be connected to an output end of the amplifier_. One end of the switching element_may be connected to the data line DL_, and the other end of the switching element_may be connected to an output end of the amplifier_.

is a timing diagram showing waveforms of the multiplexing signal and the gate signal, according to some example embodiments.

shows a waveform of a gate clock signal GCK included in the gate control signal CONG. The gate driver (or a gate driving circuit)may sequentially generate a plurality of gate signals VG, VG, VG, and VGin a unit of one period of the gate clock signal GCK to provide the generated gate signals to the plurality of gate lines GL_, GL_, GL_, and GL_. As shown in, the plurality of gate signals VG, VG, VG, and VGmay sequentially have ON levels in a time period T-T, a time period T-T, a time period T-T, and a time period T-T. Althoughshows that an ON level of each of the gate signals is a low level, the ON level of each of the gate signals may be changed according to a channel type of the switching transistor of the circuit of the pixel PX.

In a time period TP, the multiplexing signal CLA may be at an ON level on so that the plurality of switching elements_and_are turned ON. Then, the plurality of amplifiers_and_may be connected to the plurality of data lines DL_and DL_, respectively. In the time period TP, the decodermay supply each of a plurality of data signals VD_and VD_to each of the plurality of amplifiers_and_, and each of the plurality of amplifiers_and_may supply each of the plurality of data signals VD_and VD_to each of the plurality of data lines DL_and DL_. In example embodiments, the data signal VD_may be grayscale data to be written in a blue pixel Bconnected to the gate line GL_and the data line DL_, and the data signal VD_may be grayscale data to be written in a green pixel Gconnected to the gate line GL_and the data line DL_. Because the gate signal VGis at the ON level in the time period TP, the plurality of data signals VD_and VD_may be charged in the parasitic capacitors CP_and CP_of the plurality of data lines DL_and DL_, respectively. If the gate signal VGis at the ON level in the time period T-T, the voltage charged in each of the parasitic capacitors CP_and CP_may be supplied to each of the blue pixel Band the green pixel G. As shown in, the time period TPand the time period T-Tdo not overlap.

In a time period TP, the multiplexing signal CLB may be turned ON so that the plurality of switching elements_and_are turned ON. Then, the plurality of amplifiers_and_may be connected to the plurality of data lines DL_and DL_, respectively. In the time period TP, the decodermay supply each of a plurality of data signals VD_and VD_to each of the plurality of amplifiers_and_, and each of the plurality of amplifiers_and_may supply each of the plurality of data signals VD_and VD_to each of the plurality of data lines DL_and DL_. In example embodiments, the data signal VD_may be grayscale data to be written in a red pixel Rconnected to the gate line GL_and the data line DL_, and the data signal VD_may be grayscale data to be written in a green pixel Gconnected to the gate line GL_and the data line DL_. Because the gate signal VGis at the ON level in the time period T-Tand the time period TPand the time period T-Toverlap, each of the plurality of data signals VD_and VD_may be supplied to each of the red pixel Rand the green pixel Gthrough each of the plurality of data lines DL_and DL_.

The plurality of switching elements_and_may be turned ON by the multiplexing signal CLA with an ON level in a time period TP, and each of the plurality of amplifiers_and_may be connected to each of the plurality of data lines DL_and DL_. In the time period TP, the decodermay supply each of the plurality of data signals VD_and VD_to each of the plurality of amplifiers_and_, and each of the plurality of amplifiers_and_may supply each of the plurality of data signals VD_and VD_to each of the plurality of data lines DL_and DL_. In this case, the data signal VD_may be grayscale data to be written in a red pixel Rconnected to the gate line GL_and the data line DL_, and the data signal VD_may be grayscale data to be written in a green pixel Gconnected to the gate line GL_and the data line DL_. Because the gate signal VGis at an OFF level in the time period TP, the plurality of data signals VD_and VD_may be charged in the parasitic capacitors CP_and CP_of the plurality of data lines DL_and DL_, respectively. If the gate signal VGis at the ON level in the time period T-T, the voltage charged in each of the parasitic capacitors CP_and CP_may be supplied to each of the red pixel Rand the green pixel G.

The plurality of switching elements_and_may be turned ON by the multiplexing signal CLB with an ON level in a time period TP, and each of the plurality of amplifiers_and_may be connected to each of the plurality of data lines DL_and DL_. In the time period TP, the decodermay supply each of the plurality of data signals VD_and VD_to each of the plurality of amplifiers_and_, and each of the plurality of amplifiers_and_may supply each of the plurality of data signals VD_and VD_to each of the plurality of data lines DL_and DL_. In this case, the data signal VD_may be grayscale data to be written in a blue pixel Bconnected to the gate line GL_and the data line DL_, and the data signal VD_may be grayscale data to be written in a green pixel Gconnected to the gate line GL_and the data line DL_. Because the gate signal VGis at the ON level in the time period T-Tand the time period TPand the time period T-Toverlap, each of the plurality of data signals VD_and VD_may be supplied to each of the blue pixel Band the green pixel Gthrough each of the plurality of data lines DL_and DL_.

The plurality of switching elements_and_may be turned ON by the multiplexing signal CLA with an ON level in a time period TP, and each of the plurality of amplifiers_and_may be connected to each of the plurality of data lines DL_and DL_. In the time period TP, the decodermay supply each of the plurality of data signals VD_and VD_to each of the plurality of amplifiers_and_, and each of the plurality of amplifiers_and_may supply each of the plurality of data signals VD_and VD_to each of the plurality of data lines DL_and DL_. In this case, the data signal VD_may be grayscale data to be written in a blue pixel Bconnected to the gate line GL_and the data line DL_, and the data signal VD_may be grayscale data to be written in a green pixel Gconnected to the gate line GL_and the data line DL_. Because the gate signal VGis at an OFF level in the time period TP, the plurality of data signals VD_and VD_may be charged in the parasitic capacitors CP_and CP_of the plurality of data lines DL_and DL_, respectively. If the gate signal VGis at the ON level in the time period T-T, the voltage charged in each of the parasitic capacitors CP_and CP_may be supplied to each of the blue pixel Band the green pixel G.

The plurality of switching elements_and_may be turned ON by the multiplexing signal CLB with an ON level in a time period TP, and each of the plurality of amplifiers_and_may be connected to each of the plurality of data lines DL_and DL_. In the time period TP, the decodermay supply each of the plurality of data signals VD_and VD_to each of the plurality of amplifiers_and_, and each of the plurality of amplifiers_and_may supply each of the plurality of data signals VD_and VD_to each of the plurality of data lines DL_and DL_. In this case, the data signal VD_may be grayscale data to be written in a red pixel Rconnected to the gate line GL_and the data line DL_, and the data signal VD_may be grayscale data to be written in a green pixel Gconnected to the gate line GL_and the data line DL_. Because the gate signal VGis at the ON level in the time period T-Tand the time period TPand the time period T-Toverlap, each of the plurality of data signals VD_and VD_may be supplied to each of the red pixel Rand the green pixel Gthrough each of the plurality of data lines DL_and DL_.

The plurality of switching elements_and_may be turned ON by the multiplexing signal CLA with an ON level in a time period TP, and each of the plurality of amplifiers_and_may be connected to each of the plurality of data lines DL_and DL_. In the time period TP, the decodermay supply each of the plurality of data signals VD_and VD_to each of the plurality of amplifiers_and_, and each of the plurality of amplifiers_and_may supply each of the plurality of data signals VD_and VD_to each of the plurality of data lines DL_and DL_. In this case, the data signal VD_may be grayscale data to be written in a red pixel Rconnected to the gate line GL_and the data line DL_, and the data signal VD_may be grayscale data to be written in a green pixel Gconnected to the gate line GL_and the data line DL_. Because the gate signal VGis at an OFF level in the time period TP, the plurality of data signals VD_and VD_may be charged in the parasitic capacitors CP_and CP_of the plurality of data lines DL_and DL_, respectively. If the gate signal VGis at the ON level in a time period T-T, the voltage charged in each of the parasitic capacitors CP_and CP_may be supplied to each of the red pixel Rand the green pixel G.