Power Performance Area Attractive Multiple Transistor Anti-Fuse Bit Cell Layout Structure

This application is a continuation of and claims priority to U.S. patent application Ser. No. 18/519,452, filed Nov. 27, 2023, which claims the benefit of and priority to U.S. Provisional Patent Application No. 63/517,784, filed Aug. 4, 2023, the disclosures of each of which are incorporated by reference herein in their entireties for all purposes.

Integrated circuits (ICs) sometimes include one-time-programmable (OTP) memories to provide non-volatile memory (NVM) in which data are not lost when the IC is powered off. One type of the OTP devices includes anti-fuse memories. The anti-fuse memories include a number of anti-fuse memory cells (or bit cells), whose terminals are disconnected before programming, and are shorted (e.g., connected) after the programming. The anti-fuse memories may be based on metal-oxide-semiconductor (MOS) technology. For example, an anti-fuse memory cell may include a programming MOS transistor (or MOS capacitor) and at least one reading MOS transistor coupled in series. A gate dielectric of the programming MOS transistor may be broken down to cause the gate and the source or drain of the programming MOS transistor to be interconnected. Depending on whether the gate dielectric of the programming MOS transistor is broken down, different data bits can be presented by the anti-fuse memory cell through reading a resultant current flowing through the programming MOS transistor and reading MOS transistor. The anti-fuse memories have the advantageous features of reverse-engineering proofing since the programming states of the anti-fuse cells cannot be determined through reverse engineering.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over, or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” “top,” “bottom” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Bit cells are the smallest unit of data storage in a digital memory device, and may be manufactured using circuits that can store a single bit of information. Bit cells can be configured to represent one of two logical states, such as a logic low (e.g., logic 0) and logic high (e.g., logic 1). Bit cells are arranged in arrays to form memory chips, which are used in a wide variety of electronic devices and circuits that implement memory storage. Anti-fuse bit cells are a type of one-time programmable (OTP) bit cell that use the phenomenon of dielectric breakdown to store a single bit of information. Dielectric breakdown is a process in which an insulating material, such as a dielectric, is subjected to a voltage breaks it down such that it becomes conductive.

Traditional approaches to defining anti-fuse bit cells result in several issues. For example, near the edge of the oxide defined (OD) region of semiconductor material, transistors of bit cells suffer from the length of OD (LOD) effect. The LOD effect is a phenomenon in which the electrical characteristics of the transistors that make up the bit cell are affected by the distance between the transistor's gate and the edge of the OD region. The LOD effect can have a significant impact on the performance of memory cells, and is therefore undesirable. Additionally, traditional two-transistor anti-fuse bit cell layout structures are not area effective, resulting in wasted space on semiconductor dies.

Embodiments of the present disclosure utilize a continuous active OD region to define multiple-transistor bit cells to eliminate the LOD effect while improving device performance and reducing overall memory cell area. The techniques described herein utilize continuous active OD regions, upon which multiple bit cells can be defined. Each bit cell may include a pair of reading devices and a programming device defined therebetween. Dummy gate metal material layers may be provided near the edge of the continuous active region to eliminate the LOD effect, thereby improving device performance. In some implementations, voltage-relaxing devices may be included in the bit cell to reduce the effect of voltage stress during programming.

By having multiple pairs of reading transistors, various advantages as for reading/programming performance of the disclosed memory cell can be offered. For example, one of the reading transistors in each pair is symmetrically disposed on both sides of a corresponding one of the programming transistors. As such, upon any of the programming transistors being precedingly programmed, the symmetrically coupled reading transistors can significantly decrease the resistance value of an equivalent resistor coupled to the programmed resistor (e.g., the broken-down programming transistor).

illustrates a block diagram of an example layoutA for a bit cellof a memory array, in accordance with some embodiments. The example layout is a top down layout, in which multiple continuous active regionsA andB are defined. The continuous active regionsA andB may sometimes be referred to herein as the OD regionsA andB. The OD regionsA andB may include any suitable semiconductor material, for example, silicon. Alternatively, the OD regionsA andB may include other elementary semiconductor material such as, for example, germanium. The continuous active regionsA andB may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The continuous active regionsA andB may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the continuous active regionsA andB includes an epitaxial layer. For example, the substrate may have an epitaxial layer overlying a bulk semiconductor. Furthermore, the continuous active regionsA andB may include a semiconductor-on-insulator (SOI) structure.

As shown, each of the continuous active regionsA andB extend along the X direction as single continuous regions of material, upon which programming devices and reading devices are defined (as described in further detail in connection with). In the example shown in, a bit cellis formed by defining a first metal gate structurefor a first programming device (e.g., a programming transistor). Two additional metal gate structuresA andB are formed to define reading devices (e.g., reading transistors) on either side of the programming device. Further details of the programming devices and the reading devices are described in connection with. The first metal gate structureand the reading metal gate structuresA andB are defined along the direction Y, which is perpendicular to the direction X (e.g., along which the continuous active regionsA andB extend). The gate metal may be separated from the continuous active regionsA andB by a thin layer of a dielectric material, which in some implementations may be a high-k dielectric material. The gate structures described herein may therefore include multiple layers, for example, a gate dielectric layer and a gate metal. Any suitable material may be utilized to form the gate metal of the gate structures described herein, including, for example, polysilicon (PO), or any other metal material described herein.

As shown, the devices formed using the first metal gate structureand the reading metal gate structuresA andB share source/drain region(s). In this example, the programming device includes a source/drain region that is shared with a corresponding source/drain region of each of the reading devices. These source/drain regions may each be coupled to corresponding metal-to-diffusion layers, which may be used to route signals from the source/drain regions of the devices described herein to other circuits. Although not shown here, the first metal gate structure, the reading metal gate structuresA andB, and/or any of the metal-to-diffusion layersmay be coupled to various interconnects to couple the bit cellto other logical circuits. Signals used to activate (e.g., program and/or read from) the bit cellare described in connection with.

As shown, the continuous active regionsA andB may include one or more conductive viasdefined therethrough, which in this example are shown as coupled to the outer source/drain nodes of the reading devices of each bit cell. The conductive vias, as well as any of the other metal materials described herein, including any gate metals, metal-to-diffusion layers, or interconnect metals, may be formed from, or may otherwise include, aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chrome, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. The conductive vias may couple one or more of the source/drain nodes of the pairs of reading transistors with interconnects (e.g., a corresponding bit line), as described herein.

Although two continuous active regionsA andB are shown here it, should be understood that any number of continuous active regions may be provided along the Z direction and formed according to the techniques described herein, to create memory arrays of any suitable size. As shown, various materials in the layout are shown as separated by the dielectric material(e.g., an isolation structure). For example, a region of the dielectric materialelectrically isolates the continuous active regionA from the continuous active regionB, thereby defining two rows of programming and reading devices as shown in this orientation. Additionally, the same regions of the dielectric materialmay separate portions of the first metal gate structureand the reading metal gate structuresA andB, thereby isolating the gate structures (and devices formed therefrom) on the continuous active regionA from those formed on the continuous active regionB. In some implementations, the dielectric materialmay isolate only the continuous active regionsA andB from one another, rather than the first metal gate structureand the reading metal gate structuresA andB, enabling devices formed on each of the continuous active regionsA andB to share gate metal. Example dielectric materials used to form the regions of the dielectric material may include, but are not limited to, oxide materials or other non-conductive materials (e.g., isolators).

In this example configuration, three bit cellsare shown on each of the continuous active regionsA andB, thereby forming a total of six depicted bit cells. The first metal gate structureand the reading metal gate structuresA andB form the top left bit cellon the continuous active regionA and the bottom left bit cell on the continuous active regionB. The second metal gate structureand the second reading metal gate structuresA andB form the top middle bit cellon the continuous active regionA and the bottom middle bit cell on the continuous active regionB. The third metal gate structureand the second reading metal gate structuresA andB form the top right bit cellon the continuous active regionA and the bottom right bit cell on the continuous active regionB. Although three bit cellsare shown on each of the continuous active regionsA andB, it should be understood that any number of bit cells may be formed by providing corresponding metal gate layers, metal-to-diffusion layers, and conductive vias along the X direction. An example circuit diagram showing the electrical connections between each of the programming and reading devices of the bit cellsis shown in.

Referring to, illustrated is an example circuit diagramB of a portion of memory array shown via the layoutA of, in accordance with some embodiments. In the illustrated example of, anti-fuse bit cellsA,B,C,D,E, andF are shown. Although six anti-fuse memory cellsA-F are shown, it should be appreciated that the memory array can have any number of anti-fuse memory cells, while remaining within the scope of present disclosure.

The bit cellsA-F can be arranged as an array, as shown in. In, the bit cellsA,B, andC may be disposed in the same row (e.g., defined on the same continuous active region, such as the continuous active regionA as shown in) but in respectively different columns. The bit cellsD,E, andF may be disposed in the same row (e.g., defined on the continuous active regionB as shown in) but in respectively different columns. With such a configuration, each of the bit cells can be operatively coupled to the access lines (e.g., WLP, WLR, WLP, WLR, WLP, WLR, BL, BL, etc.) in the corresponding row and column, respectively.

For example in, the bit cellA and the bit cellD are operatively coupled to a first programming word line WLPand a first reading word line WLR, and to a bit line BL. The bit cellA is operatively coupled to a bit line BLand the bit cellD is operatively coupled to a bit line BL. The bit cellB and the bit cellE are operatively coupled to a second programming word line WLPand a second reading word line WLR. The bit cellB is operatively coupled to the bit line BLand the bit cellE is operatively coupled to the bit line BL. The bit cellC and the bit cellF are operatively coupled to a third programming word line WLPand a third reading word line WLR. The bit cellC is operatively coupled to the bit line BLand the bit cellF is operatively coupled to the bit line BL.

Each of the access lines (e.g., WLP, WLR, WLP, WLR, WLP, WLR, BL, BL, etc.) may be operatively coupled to a corresponding I/O circuit that transmits corresponding signals to select bit cellsfor programming or reading operations. These operations may be performed by applying predetermined patterns of logic selection to each of the access lines. The bit cellA is selected as a representative example in the following discussions of such operations.

As shown in, the bit cellA includes a programming device(sometimes referred to as a programming transistor), and a pair of reading devicesA andB (sometimes referred to as a pair of reading transistorsA andB). The programming transistoris coupled to the reading transistorsA andB, respectively, in series. One source/drain terminal of the programming transistoris serially coupled to a source/drain terminal of one of the corresponding pair of reading transistorsA andB; and the other source/drain terminal of the programming transistoris serially coupled to a source/drain terminal of the other of the corresponding pair of reading transistorsA andB.

The other source/drain terminals of the reading transistorsA andB are commonly coupled to the nodesA andB, which connect said source/drain terminals to the bit line BL. The nodesA andB may also be operatively connected to a source/drain terminal of a reading device of an adjacent bit cell. In this example, the nodeB is operatively coupled to a reading device of the bit cellB, as shown. As shown, the programming transistoris gated by the programming line WLP(e.g., a gate terminal of the programming transistoris coupled to WLP). The reading transistorsA andB are gated by the reading line WLR(e.g., respective gate terminals of the reading transistorsA andB are coupled to the reading line WLR).

Each of other bit cells (e.g.,B,C,D,E,F) may be configured substantially similar as the bit cellA, and thus, the bit cellsB throughF are briefly described as follows. The bit cellD includes a bit cell that is also gated by the programming line WLP. The bit cellB and the bit cellE include a programming device gated by the programming line WLP. The bit cellC and the bit cellF each include programming devices gated by WLP.

In some implementations, the programming/reading devices of the bit cellsA-F may include an n-type metal-oxide-semiconductor field-effect-transistor (n-type MOSFET) or sometimes referred to as an NMOS transistor. However, it should be understood that each of the programming/reading devices may include a p-type metal-oxide-semiconductor field-effect-transistor (p-type MOSFET), while remaining within the scope of present disclosure. It should be understood that the programming/reading devices described herein may include or otherwise be any type of transistor or switching device that is suitable for use in a bit cell.

To program the bit cellA, the reading transistorsA andB are turned on by supplying a high enough voltage (e.g., a positive voltage corresponding to a logic high state) to their respective gate terminals via the reading line WLR. Prior to, concurrently with or subsequently to the reading transistorsA toB being turned on, a sufficiently high voltage (e.g., a breakdown voltage (VBD) which is sometimes referred to as a programming voltage) is applied to the programming line WLP, and a low enough voltage (e.g., a positive voltage or ground voltage corresponding to a logic low state) is applied to the bit line BL. The low voltage (applied on the bit line BL) can be passed to the source/drain terminals of the programming device. As such, the programming voltage VBD can be concurrently present across the source terminal and the gate terminal of the programming transistorand across the drain terminal and the gate terminal of the programming transistor. The breakdown voltage across these terminals causes the gate dielectric layer of the programming deviceto break down.

After the gate dielectric layer of the programming deviceis broken down, the electrical behavior of the portion of the gate dielectric layer interconnecting the gate terminal and its source/drain terminals is equivalently resistive. For example, such a portion of the gate dielectric layer of the programming transistormay function as a resistor. Before the programming operation (e.g., before the gate dielectric layer of either of the programming transistorsis broken down), no conduction path exists between the bit line BLand the programming line WLP, even if the reading devicesA andB are turned on. After the programming operation has completed, a conduction path exists between the bit line BLand the programming line WLP(e.g., via the broken-down programming transistor, which operates as a resistor) when the reading devicesA andB are turned on.

When the programming transistorsbreaks down, a conduction path is established, and a sudden increase of voltage can be present on the source terminal and drain terminal of the programming transistor, which can induce a sudden increase of voltage on the bit line BL. Accordingly, a voltage level at the source terminal and drain terminal of the programming transistorcan be increased such that the programming process on the programming transistorcan be automatically stopped (as a voltage drop across its gate and source terminals is decreased). Consequently, the bit cellA can be programmed to a first logic state or a second logic state.

In some embodiments, a reading process for the bit cellA can include concurrently applying a relatively low level of a voltage (sometimes referred to as a reading voltage) on the gate of the programming device. If the programming transistoris broken down, an observable decrease of reading voltage may be present across the broken-down programming transistor. In contrast, if the programming transistoris not broken down, the reading voltage applied on the non-broken-down programming transistor may remain substantially unchanged. In an example where the programming transistoris broken down, an observable drop in the reading voltage applied on WLPmay be detected. As a result, a logic state of the cellA can be determined accordingly. Similar approaches can be utilized to program any of the bit cellsB toF, for example, by applying corresponding voltage signals to corresponding bit lines BLor BL, to corresponding programming lines WLP, WLP, or WLP, and to corresponding reading lines WLR, WLR, or WLR, to break down a desired programming device.

Referring to, illustrated is a cross-sectional layout diagramA showing an example bit cellssimilar to the bit cellsdescribed in connection with. In this example, the cross-sectional layout diagramA shows front side metal layers formed to couple to the programming devices and the reading devices of the bit cellsdefined on the continuous active region. In this example, the continuous active regionmay be similar to one of the continuous active regionsA orB, as described in connection with. Although two bit cellsare shown in this example, it should be understood that the continuous active regionmay include any number of bit cells defined thereon. Likewise, the bit cellsdefined on the continuous active regionmay include any number of transistors, including bit cells having more than three transistors as described in connection with

The bit cellis shown as including a programming device gate structure, which may be similar to the gate structureof, which positioned between two reading device gate structuresA andB, which may be similar to the pair of reading device gate structuresA andB of. As shown, a metal-to-diffusion regionsare formed on the continuous active region, such that one of the metal-to-diffusion regionsis formed on a source/drain terminal of the reading device having the reading device gate structureA and another of the metal-to-diffusion regionsis formed on a source/drain terminal of the reading device having the reading device gate structureB.

The metal-to-diffusion regionsare shown as coupled to corresponding conductive vias, which operatively couple the metal-to-diffusion regions(and therefore the source/drain terminals of the reading devices). As designated by the curved lines in, any number of layers of interconnect, each of which may include corresponding metal layers, may be coupled to one or more of the metal-to-diffusion regionsto achieve the desired logic for read and programming operations, as described herein. In this example, three metal layers,, andare shown, each connected to various structures in the stack of materials forming the bit cellsby corresponding conductive vias. For example, the metal layeris coupled to the metal-to-diffusion regionsby the conductive viasand the metal layer, which is patterned in this cross sectional view to have several portions perpendicular to the metal layer, is coupled to the metal layerusing the conductive vias. Additionally, the third metal layeris shown as coupled to the second metal layerusing the conductive vias.

Each of the three metal layers,, andmay be patterned such that they can operate as one or more of the corresponding bit lines BLand/or BLdescribed in connection with. Although not shown here, one or more metal layers may be provided to couple to (e.g., using one or more conductive vias) the programming device gate structureto provide the programming voltage (e.g., VDB) or the read voltage. Likewise, although not shown here, one or more metal layers may be provided to couple to each of the gate structuresA andB of the reading devices, to enable reading and programming for the device. In this example, each of the layers are formed via front-side metallization, in which metal layers are deposited on the front side (e.g., upward in the Y direction) of the device. An example that includes both front-side metallization and back-side metallization is shown in.

illustrates a cross-sectional layout diagramB, which depicts the memory device shown infollowing back-side metallization. As shown, in addition to the front-side metal layers,, anddescribed in connection with, the memory device is depicted including the back-side metal layersand, which may be formed via a back-side metallization process. Each of the front-side metallization process used to form the front-side metal layers,, andand the back-side metallization process used to form the back-side metal layersand, may include cleaning, deposition, patterning, and planarization processes. Although not shown here for visual clarity, the whitespace gaps formed between each of the layers of material may include a dielectric material.

In this example, the first back-side metal layeris operatively coupled to the metal-to-diffusion regionsby the backside vias (VB). The backside viasmay be formed by creating conductive regions through the entirety of the continuous active region, which are coupled to the metal-to-diffusion regions, as shown. In this example, a second back-side metal layeris operatively coupled to the metal-to-diffusion regionsusing corresponding conductive vias. Although two back-side metal layersandare shown here, it should be understood that any number of back-side metal layers may be provided in order to implement desired logical functionality. In some implementations, back-side metal layers may not be utilized, with only front-side metallization being performed, as shown in.

The cross-sectional layoutB also shows regions of the continuous active regioncorresponding to source/drain regions(sometimes referred to herein as “epitaxial structures”). The source/drain regionscan include epitaxial structures that operate as source/drains of the corresponding transistors described herein. The source/drain regionsmay be defined to form N-type or P-type devices. For example, N-type and p-type FETs may be formed by implanting different types of dopants to the source/drain regionsof the continuous active regionof the device to form the necessary junction(s). The source/drain regionsmay be defined as the regions upon which the gate structures are not present. In one example, N-type devices can be formed by implanting arsenic (As) or phosphorous (P), and p-type devices can be formed by implanting boron (B).

In some embodiments, the continuous active regionis formed in a stack structure protruding from a major surface of a substrate. The stack can include a number of semiconductor nanostructures (e.g., nanosheets) extending along the X-direction and vertically separated from each other. Portions of the semiconductor structures in the stack that are overlaid by the gate structures (e.g., the gate structures,A-B, etc.) remain, while other portions are replaced with a number of epitaxial structures. The remaining portions of the semiconductor structures (e.g., beneath the gate structures) can be configured as the channel of a corresponding transistor, the epitaxial structures coupled to both sides (or ends) of the remaining portions of the semiconductor structures can be configured as source/drain structures (or terminals) of the transistor, and a portion of the gate structure (e.g., the gate structures,A-B) that overlays (e.g., straddles) the remaining portions of the semiconductor structures can be configured as a gate structures (or terminal) of the transistor.

For example in, the portion of the continuous active regionthat is overlaid by the gate structuremay include a number of nanostructures vertically separated from each other, which can function as the channel of a first transistor. The portions of the continuous active regionthat are disposed on opposite sides of the gate structureare replaced with epitaxial structures, as shown. Furthering this example, such epitaxial structurescan function as source/drain terminals (“D” and “S” of) of the programming transistor. The gate structure can function as a gate terminal (“G” of) of the programming transistor.

Referring to, illustrated is a block diagram of an example layoutA for a bit cellof a memory array that includes voltage-relaxing devices, in accordance with some embodiments. Similar to the layout shown in, the layoutA is a top-down layout, in which multiple continuous active regionsA andB are defined. The continuous active regionsA andB may sometimes be referred to herein as the OD regionsA andB. The continuous active regionsA andB may be similar to the continuous active regionsA andB of, and may include any suitable semiconductor material, for example, silicon, or any other type of semiconductor material described herein.

As shown, each of the continuous active regionsA andB extend along the X direction as single continuous regions of material, upon which programming devices and reading devices are defined (as described in further detail in connection with). In the example shown in, a bit cellis formed by defining a first metal gate structurefor a first programming device (e.g., a programming transistor). Two gate structuresA andB are formed to define voltage-relaxing devices (e.g., voltage-relaxing transistors) on either side of the programming device. Additional metal gate structuresA andB are also formed to define reading devices (e.g., reading transistors) on either side of the voltage-relaxing devices, as shown, such that the voltage-relaxing devices are each positioned between a respective reading device and the programing device. Further details of the programming devices, the voltage-relaxing devices, and the reading devices are described in connection with.

The first metal gate structure, the voltage-relaxing gate structuresA andB, and the reading metal gate structuresA andB are defined along the direction Y, which is perpendicular to the direction X (e.g., along which the continuous active regionsA andB extend). The gate metal may be separated from the continuous active regionsA andB by a thin layer of a dielectric material, which in some implementations may be a high-k dielectric material. The gate structures described herein may therefore include multiple layers, for example, a gate dielectric layer and a gate metal. Any suitable material may be utilized to form the gate metal of the gate structures described herein, including, for example, PO, or any other metal material described herein.

As shown, the devices formed using the first metal gate structure(sometimes referred to as the programming metal gate structure) and voltage-relaxing metal gate structuresA andB share source/drain region(s). Likewise, each of the voltage-relaxing devices share a respective source/drain region with an adjacent one of the reading devices. As shown, the source/drain regions of each of the voltage-relaxing devices, as well as each of the reading devices, may be coupled to a corresponding metal-to-diffusion layer. The metal-to-diffusion layersmay be similar to the metal-to-diffusion layerofand may be used to route signals from the source/drain regions of the devices described herein to other circuits. Although not shown here, the programming metal gate structure, the voltage-relaxing metal gate structureA andB, and the reading metal gate structuresA andB, and/or any of the metal-to-diffusion layersmay be coupled to various interconnects to couple the bit cellto other logical circuits. Signals used to activate (e.g., program and/or read from) the bit cellare described in connection with.

As shown, the continuous active regionsA andB may include one or more conductive viasdefined therethrough, which in this example are shown as coupled to the outer source/drain nodes of the reading devices of each bit cell. The conductive vias, as well as any of the other metal materials described herein, including any gate metals, metal-to-diffusion layers, or interconnect metals, may be formed from, or may otherwise include, aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chrome, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof.

The conductive vias may couple one or more of the source/drain nodes of the pairs of reading transistors with interconnects (e.g., a corresponding bit line), as described herein.

Although two continuous active regionsA andB are shown here it, should be understood that any number of continuous active regions that extend continuously along the X direction may be provided along the Z direction, as shown, and may be formed according to the techniques described herein, to create memory arrays of any suitable size. As shown, various materials in the layoutA are shown as separated by the dielectric material. For example, a region of the dielectric materialelectrically isolates the continuous active regionA from the continuous active regionB, thereby defining two rows of programming and reading devices as shown in this orientation. Additionally, the same regions of the dielectric materialmay separate portions of the first metal gate structure, the voltage-relaxing gate structuresA andB, and the reading metal gate structuresA andB, thereby isolating the gate structures (and devices formed therefrom) on the continuous active regionA from those formed on the continuous active regionB. In some implementations, the dielectric materialmay isolate only the continuous active regionsA andB from one another, rather than the first metal gate structure, the voltage-relaxing gate structuresA andB, and the reading metal gate structuresA andB, enabling devices formed on each of the continuous active regionsA andB to share gate metal.

In this example configuration, two bit cellsare shown on each of the continuous active regionsA andB, thereby forming a total of four depicted bit cells. The first metal gate structure, the voltage-relaxing metal gate structuresA andB, and the reading metal gate structuresA andB form the top left bit cellon the continuous active regionA and the bottom left bit cell on the continuous active regionB. The second metal gate structure, the second voltage-relaxing gate structuresA andB, and the second reading metal gate structuresA andB form the top right bit cellon the continuous active regionA and the bottom right bit cell on the continuous active regionB. Although two bit cellsare shown on each of the continuous active regionsA andB, it should be understood that any number of bit cells may be formed by providing corresponding metal gate layers, metal-to-diffusion layers, and conductive vias along the X direction. An example circuit diagram showing the electrical connections between each of the programming and reading devices of the bit cellsis shown in.

Referring to, illustrates an example circuit diagramB of a portion of memory array corresponding to the layoutA of, in accordance with some embodiment. In the illustrated example of, anti-fuse bit cellsA,B,C, andD are shown. Although four anti-fuse memory cellsA-D are shown, it should be appreciated that the memory array can have any number of anti-fuse memory cells, while remaining within the scope of present disclosure.

The bit cellsA-D can be arranged as an array, as shown in. In, the bit cellsA andB may be disposed in the same row (e.g., defined on the same continuous active region, such as the continuous active regionA as shown in) but in respectively different columns. The bit cellsC andD may be disposed in the same row (e.g., defined on the continuous active regionB as shown in) but in respectively different columns. With such a configuration, each of the bit cells can be operatively coupled to the access lines (e.g., WLP, WLB, WLR, WLP, WLBWLR, BL, BL, etc.) in the corresponding row and column, respectively.

For example in, the bit cellA and the bit cellC are operatively coupled to a first programming word line WLP, a first voltage-relaxing word line WLB, and a first reading word line WLR, and to a bit line BL. The bit cellA is operatively coupled to a bit line BLand the bit cellC is operatively coupled to a bit line BL. The bit cellB and the bit cellC are operatively coupled to a second programming word line WLP, a second voltage-relaxing word line WLB, and a second reading word line WLR. The bit cellB is operatively coupled to the bit line BLand the bit cellC is operatively coupled to the bit line BL.

Each of the access lines (e.g., WLP, WLB, WLR, WLP, WLBWLR, BL, BL, etc.) may be operatively coupled to a corresponding I/O circuit that transmits corresponding signals to select bit cellsfor programming or reading operations. These operations may be performed by applying predetermined patterns of logic selection to each of the access lines. The bit cellA is selected as a representative example in the following discussions of such operations.

As shown in, the bit cellA includes a programming device(sometimes referred to as a programming transistor), a pair of voltage-relaxing devicesA andB (sometimes referred to as a pair of voltage-relaxing transistorsA andB), and a pair of reading devicesA andB (sometimes referred to as a pair of reading transistorsA andB). The programming transistorand the voltage-relaxing transistorsA andB are connected in series, as shown, which themselves are coupled to the reading transistorsA andB, respectively, in series.

One source/drain terminal of the programming transistoris serially coupled to a source/drain terminal of one of the corresponding pair of voltage-relaxing transistorsA andB; and the other source/drain terminal of the programming transistoris serially coupled to a source/drain terminal of the other of the corresponding pair of voltage-relaxing transistorsA andB. One source/drain terminal of the voltage-relaxing transistorA is serially coupled to a source/drain terminal of the reading transistorA; and the source/drain terminal of the voltage-relaxing transistorB is serially coupled to a source/drain terminal of the reading transistorB, as shown.

The other source/drain terminals of the reading transistorsA andB are commonly coupled to the nodesA andB, which connect said source/drain terminals to the bit line BL. The nodesA andB may also be operatively connected to a source/drain terminal of a reading device of an adjacent bit cell. In this example, the nodeB is operatively coupled to a reading device of the bit cellB, as shown. As shown, the programming transistoris gated by the programming line WLP(e.g., a gate terminal of the programming transistoris coupled to WLP). The voltage-relaxing transistorsA andB are gated by the voltage-relaxing word line WLB(e.g., respective gate terminals of the voltage-relaxing transistorsA andB are coupled to the voltage-relaxing word line WLB). The reading transistorsA andB are gated by the reading line WLR(e.g., respective gate terminals of the reading transistorsA andB are coupled to the reading line WLR).