Method for Improving Control Gate Uniformity During Manufacture of Processors with Embedded Flash Memory

Flash memories have some particular advantages and benefits, as compared to other types of solid-state non-volatile memory structures. Many of these advantages and benefits are related, for example, to improved read, write, and/or erase speeds, power consumption, compactness, cost, etc. Flash memories are commonly used in high-density data storage devices configured for use with cameras, cell phones, audio recorders, portable USB data storage devices—often referred to as thumb drives or flash drives—etc. Typically, in such applications, a flash memory is manufactured on a dedicated microchip, which is then coupled with another chip or chips containing the appropriate processor circuits, either together in a single package, or in separate packages configured to be electrically coupled.

Processors with embedded flash memories are a more recent development. In such devices, a flash memory array is manufactured together with logic and control circuitry on a single chip. This arrangement is often used in microcontroller units (MCU), i.e., small computer devices integrated onto single chips, which are typically designed to repeatedly perform a limited number of specific tasks. MCUs are often used in smart cards, wireless communication devices, automobile control units, etc. Integration of memory with related processing circuitry can improve processing speed while reducing package size, power consumption, and cost.

The following disclosure provides various embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In the drawings, some elements are designated with a reference number followed by a letter, e.g., “In such cases, the letter designation is used where it may be useful in the corresponding description to refer to or to differentiate between specific ones of a number of otherwise similar or identical elements. Where the description omits the letter from a reference, and refers to such elements by number only, this can be understood as a general reference to any or all of the elements identified by that reference number, unless other distinguishing language is used.

Reference to a semiconductor substrate can include within its scope any elements that are formed or deposited on a substrate, unless the context clearly limits the scope further. For example, reference to planarizing a surface of a semiconductor substrate can refer to planarizing one or more layers of material deposited or otherwise formed on the actual base material of the substrate, including, for example polysilicon layers, metallic layers, dielectric layers, or a combination of materials, layers, and/or elements.

A microcontroller unit (MCU) typically includes a number of discrete devices, such as, e.g., a central processing unit (CPU) core, static random access memory (SRAM) arrays (or modules), flash memory modules, a system integration module, a timer, an analog-to-digital converter (ADC), communication and networking modules, power management modules, etc. Each of these devices, in turn, comprises a number of passive and active electronic components, such as, e.g., resistors, capacitors, transistors, and diodes. A large number of these components, particularly the active components, are based on various types of metal-oxide semiconductor field effect transistors (MOSFET), or variations thereof. In a MOSFET, conductivity in a channel region extending between source and drain terminals is controlled by an electric field in the channel region, produced by a voltage difference between a control gate and the body of the device.

is a diagrammatic side sectional view of a portion of a device, such as, e.g., an MCU, during manufacture on a semiconductor material substrate, according to an embodiment. The deviceincludes a processor with an embedded flash memory arrayand other processor circuitsformed on the semiconductor substrate. The other processor circuitsinclude a plurality of transistorsconfigured for a variety of different functions, but which, for the purposes of the present disclosure, will be referred to as logic transistors, each of which includes a control gateisolated from a channel regionby a gate dielectric. Source and drain regions,are formed at opposite ends of the channel regions. Isolation regionselectrically isolate various components of the deviceto prevent interference between different elements during operation.

The flash memory arrayis positioned within a recessed region, and isolated by a shallow trench isolation (STI) regionThe memory arrayincludes a plurality of flash memory cellsthat are, in many respects similar to the logic transistors, each having a control gate, a channel region, and a gate dielectric. However, each of the flash memory cellsalso includes a floating gatepositioned between the control gateand the gate dielectric. In the embodiment shown, an erase gate dielectricis positioned between each floating gateand a corresponding erase gate. Alternating source and drain regions,are interleaved between memory cellsso that each memory cell shares a sourcewith an adjacent memory cell on one side and a drainwith an adjacent memory cell on the opposite side. Select gatesare positioned between the drainsand the control and floating gates,of each memory cell. Various layers of material,are shown in general outline, which are not configured to act as conductors or semiconductors in the device. These layers may comprise dielectrics, resist overlays, passivation layers, etch stop layers, spacers, etc., and include a dielectric layerpositioned between each of the floating gatesand the respective control gateof the memory cells.

Because of the similarities in the structures of the logic transistorsand the flash memory cells, they would be of similar heights except for the added height of the floating gatesand corresponding dielectric layersof the memory cells. This can be a problem because, at several points during the manufacturing process, chemical/mechanical polishing (CMP) procedures are performed to produce a substantially flattened surface for succeeding process steps. A CMP procedure that reduces the control gatesof the logic transistorsto the appropriate height can damage the taller control gatesof the memory cells.

One solution is to form the memory arrayin a recessed region, in which a surfaceof the semiconductor substratewithin the recessed region is reduced in height, relative to a surfaceof the substrate outside the recessed region, by a distance about equal to the total thickness of the floating gatesand the dielectricThis difference in height between the surfacesandmay be termed a step height or step height differential between the surfaceof the recessed regionin which memory cells of the memory arrayare formed and the surfaceof the periphery around the recessed region in which other components are formed. According to an embodiment, the recessed regionis formed via an etching procedure, in which the surface of the semiconductor substrateis etched evenly across the intended recessed region to a desired depth, resulting in a substantially planar surfaceon which the memory cellsare subsequently formed.

According to an alternative embodiment, a layer of semiconductor material is deposited or grown on the surface of the substrateoutside the intended recessed region, raising the surfaceto a desired height above the recessed surface. For the purposes of the present disclosure, reference to the formation of a recessed region includes any process that results in a defined region having a depth, relative to the surrounding substrate, about equal to the height difference between floating gate transistors and MOSFET transistors that do not employ floating gates.

As noted above, the logic transistorsoperate by application of an electric field over the respective channel region, thereby changing the conductivity of the channel region. The electric field is produced by application of a voltage potential between the control gateand the semiconductor body. A MOSFET can be configured either to increase or decrease conductivity when an electric field of a selected polarity is present. Typically, transistors in a logic circuit are designed to function like switches, turning on or off in response to an electric field of a selected strength, and controlling a flow of current in the channel region.

In the memory cells, during a write operation, electrons can be forced to tunnel through the gate dielectricto the floating gate, where they can remain trapped indefinitely, by applying a write voltage to the control gatewhile applying a voltage potential across the channel region. If there is a sufficient number of electrons trapped on the floating gate, the electrons can block an electric field produced by the control gate, preventing the control gate from acting to change conductivity in the channel region. Thus, the presence of electrons can be detected by applying a voltage potential across the drain and source regions,while applying a read voltage to the control gateto produce an electric field, and testing for a current flow in the channel region. Typically, a binary value of one is the default setting of a flash memory cell at the time of manufacture and before programming, while a binary value of zero is indicated if channel current is unaffected by a read voltage at the control gate. A binary zero value on a flash memory cell can be erased—i.e., returned to a one—by applying a sufficiently powerful erase voltage to the erase gate. This causes electrons trapped on the floating gatesof the memory cellsadjacent to the energized erase gateto tunnel out through the erase gate dielectricsto the erase gate. In practice, there are many more memory cellsadjacent to the erase gate, extending along rows lying perpendicular to the view of. During an erase operation, each of those memory cells is erased, hence the term flash memory.

As advances in technology enable ever smaller and more compact features, power and voltage requirements are reduced while memory density and speed increase. However, a problem that has arisen with the reduction in size is that a very small variation in gate dimensions can have a progressively increasing impact on performance, because such a variation represents a larger change, relative to the proportionately smaller nominal gate dimensions. This becomes a greater issue as technology nodes drop below 65 nm, 40 nm, and 28 nm scales.

are diagrammatic side sectional views of the substrateat respective stages of the manufacturing process, showing, in particular, the recessed regionduring the formation of the control and floating gates,of the memory arrayof the deviceof. The diagrams shown in, and the corresponding description, are only isolated steps in the manufacturing process, and are not intended to provide information regarding the manufacturing process in general.

Initially, as shown in, a protective layeris formed on the surfaceof the semiconductor material substrate, and can include a plurality of layers of, for example, silicon oxide, silicon nitride, etc. Isolation regionsare formed in the substrate, and a hard mask layeris deposited. The recessed regionis then formed in an anisotropic etch process. An oxide layeris formed on the substrate surfacewithin the recessed regionand a polysilicon layeris grown over the oxide layer. The oxide and polysilicon layers,comprise the materials from which the gate dielectricsand floating gatesof the memory arraywill eventually be formed.

Proceeding to the stage shown in, a dielectric layeris deposited over the substrate, followed by a polysilicon layerand a protective layer. The dielectric and polysilicon layers,comprise the materials from which the dielectric layersand control gatesof the memory arraywill eventually be formed, while the protective layerwill be patterned with the dielectric and polysilicon layers to form protective caps over the gate stacks to protect the control and floating gates during later process steps. According to an embodiment, the protective layeris a hard mask material—typically an oxide, nitride, amorphous carbon, a combination of such materials, etc. The term hard mask material refers to a layer (or layers) of material that is substantially resistant to selected ones of the processes that will be employed following the formation of the mask. The resistance to selected ones of the processes that will be employed following the formation of the mask can be a result of the composition of the hard mask material or a combination of the composition of the hard mask material and the thickness of the hard mask material. The thickness of the hard mask material can vary and embodiments of the present disclosure are not limited to the specific thicknesses described below. In various embodiments, the hard mask material includes a silicon nitride (SiN) layer of 400 angstroms to 500 angstroms (Å), a silicon dioxide (SiO2) layer of 1000 Å to 1200 Å, and a SiN layer of 700 Å to 900 Å. In some embodiments the hard mask material includes a SiN layer of 440 Å, a SiO2 layer of 1100 Å, and a SiN layer of 800 Å. In these embodiments, the total thickness of the hard mask material formed by these layers is 2340 Å which is greater than a depth of the recessed region, where the recessed region has a depth of greater than 300 Å. The thickness of these layers is based on an etching electivity of a subsequent etching process described below with reference to. In various embodiments, the total thickness of the hard mask material formed by these layers ranges from 2100 Å to 2600 Å and is chosen to be greater than a depth of the recessed region, where the recessed region has a depth of greater than 300 Å.

In, a bottom anti-reflection coating (BARC)is applied over the protective layer, followed by a patterning film layer. The patterning film layerwill be patterned to produce an etch mask, with the BARCpositioned between the substrate and the patterning film layer to prevent damage to the film layer caused by reflections from the surface of the substrateduring the patterning of the film. The BARC is typically applied via a spin-coating process, while, depending upon the type of patterning film, the patterning filmmay be applied via any of several processes, including, for example, deposition processes such as thermal deposition or chemical vapor deposition (CVD). As shown in, the BARCtends to deposit more thickly around the edges () of the recessed regionthan in the center (). If the patterning film is applied by spin-coating, it too will likely be thicker at the edges () than in the middle of the recessed region ().

Turning finally to, after patterning of the patterning film layer, an etching process is performed, producing a plurality of gate stacks, each having a protective cap, a control gate, and a dielectric layerRemnants of the oxide layer, the polysilicon layer, and the protective layerremain around the periphery of the recessed region. The gate dielectricsand floating gateswill be etched from their parent layers,during a later step, after additional process steps are performed, including the deposition of further dielectric layers.

As shown in, the gate stacksnear the center of the recessed regionare narrower than the gate stackscloser to the edges of the region. This is caused by the thicker BARC and patterning film layer portionsnear the edges of the recessed region, as described above with reference to. Typically, BARC material is considered to be conformal, and the impact of small variations in thickness caused by surface features of the substrate has been negligible. As scales continue to drop, the impact of small variations in thickness caused by surface features of the substrate may become a significant problem, particularly at technology nodes below, e.g., the 65 nm, 40 nm, and 28 nm scales. This is because the dimensions of the control and floating gates,have a direct impact on critical operating characteristics of the devices, such as read and write speeds, program and erase state voltage and current, and power consumption, etc.

In order to utilize the memory cellsnear the edges of the recessed region, the operating parameters of the entire memory arraycan be modified, to ensure that data is not lost or corrupted because the memory cells near the edges of the recessed region are not properly written or erased. Modifying the operating parameters of the entire memory cell in this manner can result in less than optimal performance of the entire array. One alternative is to leave the cells nearest the edges of the recessed regioninactive—or leave the edge region empty—but this will result in a loss of capacity. The reduced total capacity may be minimal if all of the memory cells of a device are in a single array, but many MCU devices are designed to place smaller memory arrays adjacent to circuits that will be using them, to increase throughput speed. In such devices, smaller memory arrays are positioned at multiple locations on the device. Consequently, the total area of the edge regions is much larger than in a single array, so the lost capacity is also much greater.

The inventors have also recognized that the problem could be eliminated if the BARC were deposited on a substantially planar surface. However, planarizing the surface at the process stage shown inis problematic. A CMP process would have a tendency to produce dishing over the recessed region, and other planarizing processes are inapplicable or would require many additional process steps.

Embodiments described hereafter with reference toreduce or eliminate the BARC layer thickness variations and the associated variation in gate uniformity described above.are diagrammatic side sectional views of the substrateat respective stages of a manufacturing process, according to an embodiment, showing formation of the control and floating gates,of the memory arrayof the deviceof. In particular, the process ofcontinue from the stage described above with reference to, and replace the portion of the process described with reference to. Thus, proceeding from the stage of,shows the deposition of a sacrificial layerover the protective layer. According to embodiments of the present disclosure, the sacrificial layeris a photoresist layer that is applied in a spin coating process, with a thickness that is sufficient to completely fill the depression in the protective layerover the recessed region. The sacrificial layeris self-leveling, meaning that, as applied, its upper surfaceis substantially planar, without requiring further processing. A thickness of the sacrificial layeris about 1000 Å per spin-coating process in one embodiment of the present disclosure. The thickness of the sacrificial layeris not limited to being about 1000 Å per spin-coating process and can be greater or less thanA per spin-coating process. The sacrificial layeris not limited to being a photoresist layer, and may be other flowable materials in further embodiments of the present disclosure. In addition, the flowable material of the sacrificial layeris not limited to being applied through a spin coating process, with other suitable processes being utilized to apply the flowable material in further embodiments.

As shown in, a non-selective etch process is performed, etching the surface of the substrate back into the protective layer, while completely removing the sacrificial layer. The chemistry of the etching process is selected such that the etch rates of the sacrificial layerand of the protective layerare substantially equal. Consequently, the etching process proceeds evenly across the surface of the substrate, leaving a planarized faceon the surface of the protective layer. A patterning film layerand a BARC layerare then deposited at uniform thicknesses over the planarized surfaceof the protective layer. The BARC layeris typically a suitable flowable material and is formed through a spin-coating process while the patterning film layeris formed through a suitable process such as a chemical vapor deposition (CVD) process, as discussed above for corresponding layers in relation to. The upper surfaceis said to be substantially planar in embodiments of the present disclosure, where the term “substantially” indicates the upper surface is sufficiently planar to enable the subsequent formation of the patterning film layerand BARC layerhaving reduced thickness variations to thereby enable the formation of control gates having uniform thicknesses as described above.

Other processes may be utilized to remove the sacrificial layerand to partially remove the protective layer. The portion of the protective layerremaining after the etching of the surface of the substrate to remove the sacrificial layerand partially remove the protective layer depends on the specific etching process utilized. In one embodiment, the etching process partially removes the protective layerto leave a remaining portion of the protective layer having a depth of 1500-2000 angstroms. The described embodiments of the present disclosure, which apply the sacrificial layerthrough spin coating and remove the sacrificial layer and partially remove the protective layer, improve the uniformity of the BARC layerdeposited across the center and periphery portions of the flash memory array(). This uniformity of the BARC layerenables the formation of gate stacks() having uniform thicknesses for the gate stacks in the center and in the periphery portions of the flash memory array.

According to an embodiment, the etch of the sacrificial layerproceeds directly following the deposition and—if necessary—planarizing of the sacrificial layer, without any intervening process steps. According to another embodiment, one or more process steps are performed between the deposition of the sacrificial layerand its subsequent removal in the etch procedure. These intervening process steps can include processes that are unrelated to the formation of the memory array.

Proceeding to, the patterning film layeris patterned to form an etch mask, and the protective, polysilicon and dielectric layers,,are etched to form gate stacksIn contrast with the gate stacksandof, the gate stacksofare substantially equal in width, owing to the uniform thickness of the BARC layerand the patterning film layer, which, in turn, is due to the planarized face ofof the protective layer.

are diagrammatic side sectional views of the substrate, showing a small portion of the recessed region, and illustrating the manufacturing process through a stage in which the gate stacksof the memory array are substantially complete. In, one or more dielectric layersare deposited over the gate stacks. In, the floating gatesand gate dielectricsare formed in an etching process in which the gate stacksact as self-aligned masks. Finally, in, an oxide is formed over the gate stacksand etched to leave protective dielectric layerson the sides of the gate stacks.

are flow chart outlining methods of manufacture, according to respective embodiments, that are consistent with processes described above with reference to.

outlines a method, according to an embodiment, in which, at step, the recessed regionis formed in the semiconductor substrate. The first dielectric layeris formed over the substratewithin the recessed regionin step, and the first polysilicon layeris formed over the first dielectric layerin step. In step, the second dielectric layeris formed, followed by formation of the second polysilicon layerin step. In step, the protective layeris formed over the second polysilicon layer. In step, the sacrificial layeris formed over the protective layer, self-leveling to form the planar upper surface. In step, in a non-selective etch process the sacrificial layeris removed, together with a portion of the protective layer, planarizing the exposed surfaceof the protective layer. The patterning film layeris deposited on the surfaceof the protective layerand the anti-reflective coatingis deposited over the substrate, in respective stepsand, and the patterned film layeris patterned in step. Finally, a plurality of control gatesare defined in an etch process regulated by the patterned film layer, in step.

is a flow chart outlining a methodfor providing a planarized surface in a manufacturing process, according to another embodiment. In step, the protective layeris deposited over a non-planar surface on the semiconductor substrate. In step, the self-leveling sacrificial layeris formed over the protective layer, forming a planar upper surface. In step, a non-selective etch procedure is performed in which the entirety of the sacrificial layerand a portion of the protective layerare removed to leave a planarized surfaceof the remaining portion of the protective layer.

The embodiments shown and described herein provide improvements to a process for manufacturing microelectronic devices that include embedded flash memory arrays. According to various embodiments, prior to defining control and floating gate stacks of the memory arrays in recessed regions on a semiconductor substrate, a planar surface is provided on the substrate over layers of material from which the gate stacks are to be formed, for deposition of an anti-reflective coating and of a patterning film at an even thickness. This is beneficial because the anti-reflective coating, in particular, has a tendency to vary in thickness when it is deposited over a non-planar surface, which in turn, can contribute to non-uniformity of control and floating gate dimensions. The dimensions of the control and floating gates have a direct impact on critical operating characteristics of a memory device, such as read, write, and erase speeds, program and erase state voltage and current levels, power consumption, etc. If gate dimensions vary within a memory array, a typical practice is to operate the entire array based on the operating characteristics of the weakest cells. Thus, significant variation in dimensions is a problem because, if even a small percentage of the cells in an array require higher voltages and/or longer read and write times, the entire array is operated at the same levels, resulting in a loss of efficiency and speed for the entire array. By providing the planar surface, non-uniformity in gate dimensions of the memory arrays is reduced or eliminated. This, in turn, results in arrays with higher overall speed and efficiency.

According to an embodiment, the improvements include forming a protective layer over a non-planar surface of a semiconductor substrate, in particular, for example, over a recessed region of the semiconductor substrate, in which an embedded memory array is to be formed. A sacrificial layer is then deposited over the protective layer, to a depth sufficient to permit formation of a substantially planar surface on the sacrificial layer. The sacrificial layer is then etched to a depth that removes the sacrificial layer and leaves a planar surface formed in the protective layer.

According to another embodiment, the method includes forming a recessed region in a semiconductor substrate, and forming gate materials for a plurality of floating gates and control gates of a memory array, in layers over the recessed region. A protective layer is then formed over the gate materials in the recessed region, and planarized to improve uniformity of gate dimensions. An etch mask is formed over the planarized protective layer, and gate stacks of the memory array are formed in the recessed region, by etching the gate materials. According to an embodiment, planarizing the protective layer includes depositing a self-leveling sacrificial layer over the protective layer to produce a substantially planar surface, then etching the surface at an even rate, and to a depth sufficient to remove the sacrificial layer, which results in a planar surface on the protective layer.

According to another embodiment, the method includes forming a protective layer over a stack of gate-material layers in a recessed region of a semiconductor substrate. A self-leveling sacrificial layer is then deposited over the protective layer to a depth sufficient to produce a planarized surface of the semiconductor substrate, and the sacrificial layer is etched back at an even rate to a depth sufficient to produce a substantially planar surface on the protective layer.

Ordinal numbers, e.g., first, second, third, etc., are used in the claims according to conventional claim practice, i.e., for the purpose of clearly distinguishing between claimed elements or features thereof, etc. Ordinal numbers may be assigned arbitrarily, or assigned simply in the order in which elements are introduced. The use of such numbers does not suggest any other relationship, such as order of operation, relative position of such elements, etc. Furthermore, an ordinal number used to refer to an element in a claim should not be assumed to correlate to a number used in the specification to refer to an element of a disclosed embodiment on which that claim reads, nor to numbers used in unrelated claims to designate similar elements or features.

While the method and process steps recited in the claims may be presented in an order that corresponds to an order of steps disclosed and described in the specification, except where explicitly indicated, the order in which steps are presented in the specification or claims is not limiting with respect to the order in which the steps may be executed.

The abstract of the present disclosure is provided as a brief outline of some of the principles of the invention according to one embodiment, and is not intended as a complete or definitive description of any embodiment thereof, nor should it be relied upon to define terms used in the specification or claims. The abstract does not limit the scope of the claims.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.