Single Metal Gate with Dual Effective Work Function Gate Metal Scheme

There has been a continuous demand for increasing computing power in electronic devices including smart phones, tablets, desktop computers, laptop computers and many other kinds of electronic devices. Integrated circuits provide the computing power for these electronic devices. One way to increase computing power in integrated circuits is to include transistors that have different threshold voltages.

The formation of gate electrodes may include the deposition of various conductive layers. However, for 3D transistors such as FinFET transistors and gate all around (GAA) transistors, it may be difficult to deposit and selectively remove various conductive layers for different types of transistors. The result of this is that the threshold voltages of the various device regions may not be in accordance with design specifications. This can lead to nonfunctioning transistors, poor wafer yields, and electronic devices that do not function properly. The threshold voltage of the resulting device regions may not be accurate as designed.

In the following description, many thicknesses and materials are described for various layers and structures within an integrated circuit die. Specific dimensions and materials are given by way of example for various embodiments. Those of skill in the art will recognize, in light of the present disclosure, that other dimensions and materials can be used in many cases without departing from the scope of the present disclosure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the described subject matter. Specific examples of components and arrangements are described below to simplify the present description. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, one skilled in the art will understand that the disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components and fabrication techniques have not been described in detail to avoid unnecessarily obscuring the descriptions of the embodiments of the present disclosure.

Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising,” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.”

The use of ordinals such as first, second and third does not necessarily imply a ranked sense of order, but rather may only distinguish between multiple instances of an act or structure.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least some embodiments. Thus, the appearances of the phrases “in one embodiment”, “in an embodiment”, or “in some embodiments” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise.

Embodiments of the present disclosure provide an integrated circuit with simplified gate electrode structures for both NMOS and PMOS transistors. In particular, a single gate metal may be used for both NMOS and PMOS transistors. An effective work function layer can be formed for NMOS transistors by depositing a thin layer of the gate metal followed by deposition of a semiconductor material, such as silicon or other suitable materials. The semiconductor layer is removed at the PMOS transistors. The gate metal is then deposited on both the NMOS and the PMOS regions. The semiconductor layer combined with the initial thin deposition of the gate metal results in an effective work function for the NMOS transistors. At the PMOS transistors, the gate electrode may include a single gate metal in contact with the gate dielectric layers. The result is that the gate resistance of the NMOS transistors is improved by utilizing the semiconductor plus thin gate metal as a work function layer. Furthermore, the transistor can be scaled down and the cell height can be reduced due to the single gate metal utilized for both the NMOS and PMOS transistors. The physical gate metal boundary is the same as the actual gate metal boundary due to the lack of diffusion. This leads to properly functioning integrated circuits, higher wafer yields, and better functioning electronic devices.

is a cross-sectional view of an integrated circuitat an intermediate stage of processing, in accordance with some embodiments. In, NMOS transistorsand PMOS transistorsare at an intermediate stage of processing. As will be set forth in more detail below, the process for forming the integrated circuitresults in transistorsandhaving different threshold voltages.

a illustrates a single NMOS transistorand a single PMOS transistor. However, in practice, the integrated circuitwill include a large number of NMOS transistorsand PMOS transistors. As shown in the figures and described herein, various reference numbers may include the suffix “a”. Reference numbers with the suffix “a” typically will be referred to materials or structures, or the portions of materials or structures that particularly are associated with the NMOS transistor. As shown in the figures and described herein, various reference numbers may include the suffix “b”. Reference numbers with the suffix “b” typically will refer to materials or structures, or portions of materials or structures that are particularly associated with the PMOS transistor. The following description may in some cases refer to reference numbers without the suffix “a” or “b” when the aspect of the material or the structure being described is not particular either the NMOS transistoror the PMOS transistor

Figures herein may include reference axes X, Y, and Z. In, the axis Y corresponds to the horizontal direction. The axis Z corresponds to the vertical direction. The X axis will correspond to the direction into and out of the drawing sheet.

The transistorsandmay correspond to gate all around transistors. The gate all around transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the gate all around structure. Furthermore, the gate all around transistors may each include a plurality of semiconductor nanostructures corresponding to channel regions of the transistors. The semiconductor nanostructures may include nanosheets, nanowires, or other types of nanostructures. The gate all around transistors may also be termed nanostructure transistors.

The transistorsandare formed in the same integrated circuit, though they may be located at different regions of the integrated circuit. The transistorsandmay be adjacent to each other as shown inor may be in different regions of the integrated circuit.

The integrated circuitincludes a semiconductor substrate. In one embodiment, the semiconductor substrateincludes a single crystalline semiconductor layer on at least a surface portion. The substratemay include a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. The substratemay include various regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity). The dopants are, for example boron (BF) for an n-type transistor and phosphorus for a p-type transistor.

The integrated circuitmay include one or more insulating features, such as shallow trench isolationsseparating the transistorsfrom the transistors, or separating the transistorsfrom each other and the transistorsfrom each other. The shallow trench isolationcan be utilized to separate groups of transistor structures formed in conjunction with the semiconductor substrate. The shallow trench isolationcan include a dielectric material. The dielectric material for the shallow trench isolation may include silicon oxide, silicon nitride, silicon oxynitride (SION), SIOCN, SICN, fluorine-doped silicate glass (FSG), or a low-K dielectric material, formed by LPCVD (low pressure chemical vapor deposition), plasma enhanced-CVD or flowable CVD. Other materials and structures can be utilized for the shallow trench isolationwithout departing from the scope of the present disclosure.

The transistorsandeach include a plurality of channel regions/. The channel regionscorresponds to the channel region of the transistor. The channel regionscorrespond to channel regions of the transistor. Though not shown in, upon completion of the transistorsand, each of the channel regions/of the transistorsandwill extend between source/drain regions of the transistorsand. In, the transistorsandeach include three vertically stacked channel regions/. However, in practice, the transistorsandmay each include more than two vertically stacked channel regions/. The channel regions/may correspond to semiconductor nanostructures. The semiconductor nanostructures can include semiconductor nanosheets, semiconductor nanowires, or other types of semiconductor nanostructures.

The channel regions/are formed over the substrate. The channel regions/may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP. In one embodiment, the channel regions/are the same semiconductor material as the substrate. Other semiconductor materials can be utilized for the channel regions/without departing from the scope of the present disclosure.

The width of the channel regions/in the Y direction can be between 14 nm and 60 nm. The length of the channel regions in the X direction (i.e., the distance between source/drain regions of a transistor/) can be between 8 nm and 15 nm. The thickness of the channel regions/in the Z direction can be between 4 nm and 8 nm. The distance between the channel regions/in the Z direction can be between 5.5 nm and 15 nm. Other dimensions can be utilized for the channel regions/without departing from the scope of the present disclosure.

In, each semiconductor nanosheet/of the transistorsandis covered by an interfacial dielectric layer/. The interfacial dielectric layer/may be used in order to create a good interface between the channel regions/and subsequent dielectric layers, as will be described in further detail below. The interfacial dielectric layer/can assist in suppressing the mobility degradation of charge carries in the channel regions/that serve as channel regions of the transistorsand. At the stage of processing shown in, the interfacial dielectric layerand the interfacial dielectric layermay have a same thickness. For example, the thickness of the interfacial dielectric layersinmay be between 10 Å and 17 Å. However, when processing is complete, as will be described in more detail below, the thickness of the interfacial dielectric layermay be reduced relative to the thickness of the interfacial dielectric layer. The final thickness of the interfacial dielectric layermay be between 8 Å and 15 Å. Other dimensions can be utilized for the interfacial dielectric layers/without departing from the scope of the present disclosure.

The interfacial dielectric layer/can include a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interfacial dielectric layer/can include a comparatively low-K dielectric with respect to high-K dielectric materials such as hafnium oxide or other high-K dielectric materials that may be used in gate dielectrics of transistors. High-K dielectrics can include dielectric materials with a dielectric constant higher than the dielectric constant of silicon oxide. In the example of, the interfacial dielectric layer/is silicon dioxide, though other materials can be utilized without departing from the scope of the present disclosure.

The interfacial dielectric layer/can be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. One consideration in selecting a thickness for the interfacial dielectric layer/is to leave sufficient space to deposit and etch various materials between the channel regions/, as will be explained in more detail below. Other materials, deposition processes, and thicknesses can be utilized for the interfacial dielectric layer/without departing from the scope of the present disclosure.

The transistorsandeach include a high-K gate dielectric layer/. The high-K gate dielectric layer/is positioned on the interfacial dielectric layer/around each of the channel regions/. The interfacial dielectric layer/separates the high-K gate dielectric layer/from the channel regions/. The high-K gate dielectric layer/and the interfacial dielectric layer/collectively form a gate dielectric of the transistorsand. The high-K gate dielectric layer/and the interfacial dielectric layer/physically separate the channel regions/from the gate metals that will be deposited in subsequent steps. The high-K gate dielectric layer/and the interfacial dielectric layer/isolate the gate metals from the channel regions/that correspond to the channel regions of the transistors.

The high-K gate dielectric layer/includes one or more layers of a dielectric material, such as HfO, HfSiO, HfSiON, HfTaO, HTIO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO—AlO) alloy, other suitable high-k dielectric materials, and/or combinations thereof. The high-K gate dielectric layer/may be formed by CVD, ALD, or any suitable method. In one embodiment, the high-K gate dielectric layer/is formed using a highly conformal deposition process such as ALD in order to ensure the formation of a gate dielectric layer having a uniform thickness around each channel region/. In one embodiment, the thickness of the high-k dielectric is in a range from about 1 nm to about 2 nm. Other thicknesses, deposition processes, and materials can be utilized for the high-K gate dielectric layer/without departing from the scope of the present disclosure.

The transistorsandeach include a layer/of a gate metal on the high-K gate dielectric layer/. In, the layer/of the gate metal surrounds each of the channel regions/. The layer/of the gate metal is a conductive material having a thickness between 2 Å and 10 Å. The layer/of the gate metal can include TiN, W, WCN, Ru, Mo, or other suitable conductive materials. The layer/of the gate metal can be deposited by PVD, ALD, CVD, or other suitable deposition processes. As will be set forth in more detail below, the layer/of the gate metal is a same material as a subsequent gate metal layer or gate fill material that will be deposited at both the transistorand the transistor. Other materials, thicknesses, and deposition processes can be utilized for the layer/of the gate metal without departing from the scope of the present disclosure.

The transistorsandeach include a semiconductor layer/positioned on the layer/of the gate metal. The semiconductor layer/surrounds each of the channel regions/. The semiconductor layer/can include silicon, silicon germanium, or other suitable semiconductor materials. In the example shown herein the semiconductor layer/is silicon. As will be set forth in more detail below, the position of the semiconductor layer/can adjust the effective work function of the transistorsand. The semiconductor layer/can be deposited by ALD, CVD, PVD, or other suitable deposition processes. The thickness of the semiconductor layer/may be between 1 Å and 5 Å. In some embodiments, the total thickness of the layer/of the gate metal and the semiconductor layer/is between 3 Å and 15 Å. One example, the total thickness is between 3 Å and 8 Å. Other materials, deposition processes, and dimensions can be utilized for the semiconductor layer/without departing from the scope of the present disclosure.

In some embodiments, there may be intermixing between the layer/of the gate metal and the semiconductor layer/. In an example in which the layer/of the gate metal is titanium nitride and the semiconductor layer/is silicon, the thin layer of SiTiN may form. In some embodiments, there is an intermixing layer of SiTiN at the N-channel transistor, but not at the P-channel transistor

is an enlarged view of a channel regionof, in accordance with some embodiments. Because at the stage of processing ofthere is not yet a difference in the material surrounding the channel regions/, no suffixes are given for the layers in. The enlarged view ofillustrates an oxide layeron the semiconductor layer. The oxide layer may correspond to a native oxide layer that grows on the semiconductor layer. In an example in which the semiconductor layeris silicon, the oxide layermay be silicon oxide and may have a thickness between 1 Å and 5 Å. Other materials and dimensions can be utilized for the oxide layerwithout departing from the scope of the present disclosure.

In, dielectric plugs/have been formed between the channel regions/. In particular, the dielectric plugs/are in contact with the semiconductor layer/between adjacent channel regions/. The plugs/may substantially fill the gaps between adjacent channel regions/. In one example, the dielectric plugs/can include one or more of AlOx (where x represents the concentration of oxygen), ZrO, SiN, or other suitable materials.

The dielectric plugs/may be formed by initially conformally depositing a dielectric material on all exposed surfaces of the semiconductor layer/. The deposition can be accomplished by ALD, CVD, PVD, or other suitable deposition processes. After deposition of the dielectric material, an etchback process may be performed to remove the dielectric material from all locations except directly between the channel regions/. The etching process can include a timed etch, a wet etch, dry etch, or other types of etching processes. The result is that the dielectric plugs/shown in.

Ina layer of photoresisthas been deposited. The photoresist layercan include multiple layers of photoresist including a bottom layer and the top layer. The layer of photoresistcan be deposited by standard photoresist deposition techniques including vapor deposition, spread deposition, spin-on coating, or by other suitable process.

In, the photoresist layerhas been patterned. The layer of photoresistis patterned to expose the structures of the transistor. The structures of the transistorare covered by the layer of photoresist. The layer of photoresistcan be patterned by exposing the layer of photoresistto light via a photolithography mask. Accordingly, the layer of photoresistcan be deposited and patterned using standard photolithography techniques.

In, an etching process has been performed on the integrated circuit. In particular, the etching process has been performed on the portion of the integrated circuitthat is not covered by the photoresist. The etching process etches the dielectric plugsfrom the transistor. The etching process also removes the semiconductor layer. In practice, a separate etching process may be utilized for removing the semiconductor layerafter removing the dielectric plugs. The result is that the layerof the gate metal is exposed. The etching process can include a wet etch, a dry etch, an atomic layer etching (ALE) process, a timed etch, or other suitable etching techniques. Because the transistoris still covered in the photoresist, the etching process does not remove the dielectric plugsat the region of the transistor

In, the photoresist layerhas been removed. The photoresist layercan be removed by an ashing process. The ashing process completely removes the photoresist layer. An etching process has also been performed to remove the dielectric plugs. The etching process can include a wet etch, a dry etch, a timed etch, or other types of etching processes. Other suitable methods may be utilized for removing the photoresist and the dielectric plugswithout departing from the scope of the present disclosure.

In, an annealing process has been performed. The annealing process can include raising a temperature of the integrated circuit to between 700° C. and 900° C. This annealing process can repair defects in the high-K gate dielectric layer/. The annealing process may be referred to as a post-metal annealing process.

In, a dipole semiconductor cap layerhas been deposited at the areas of both the transistorand the transistor. The semiconductor cap layeris deposited directly on the semiconductor layerat the transistor. The semiconductor cap layeris deposited directly on the layerof the gate metal of the transistor. The semiconductor cap layercan include a dielectric material such as silicon nitride, silicon oxide, silicon carbide, or other suitable dielectric materials. Alternatively, the semiconductor cap layercan include a semiconductor material such as silicon, silicon germanium, or other suitable semiconductor materials. After deposition of the semiconductor cap layer, a thermal annealing process may be performed. The thermal annealing process can be performed by raising the temperature of the integrated circuitto between 800° C. and 950° C. The thermal annealing process can further repair defects in the high-K gate dielectric layer/. The repair may result from reformation of a crystal structure after previous damage, by migration of material to damaged areas, or from other mechanisms. The high temperatures of the thermal annealing process may enable such repairing.

In, the semiconductor cap layerhas been removed. The semiconductor cap layer can be removed by an etching process. The etching process can include a wet etch, a dry etch, a timed etch, or other types of etching processes. The result is that the semiconductor layeris exposed at the transistor. The layerof the gate metal is exposed at the transistor

is an enlarged view of one of the channelsof the transistorat the stage of processing shown in. The interfacial dielectric layer, the high-K gate dielectric layer, and the layerof the gate metal are present. Dashed lines indicate the layers have been removed. In particular, the semiconductor layerand the oxide layerhave been removed from the channel regionsof the transistor

In, an etching process has been performed on the integrated circuit, in accordance with some embodiments. The etching process etches the layerof the gate metal from the transistor. In particular, the etching process removes the layerof the gate metal with respect to the material of the semiconductor layer. The result is that the high-K gate dielectric layerof the transistoris exposed. The etching process can include a wet etch, a dry etch, a timed etch, or other suitable etching processes. Althoughillustrates the removal of the layerof the gate metal from the transistor, in some embodiments the layerof the gate metal is not removed. For example,below illustrates an example in which the layerof the gate metal has not been removed.

is an enlarged view of a channelof the transistorand the channel regionof the transistorat the stage of processing shown in relation to, in accordance with some embodiments.illustrates the presence of the interfacial dielectric layer, the high-K gate dielectric layer, the layerof the gate metal, the semiconductor layer, and the oxide layer. The oxide layermay be very thin and is not shown in. The same layers are present on the channel regionas are shown in.

Ina gate fill layerof the gate metal has been deposited at both the transistorand the transistor. The gate fill layeris the same gate metal as the layersandof the gate metal. In some embodiments, the gate fill layerincludes TiN, W, WCN, Ru, Mo, or other suitable conductive materials. The gate fill layercan be deposited by PVD, ALD, CVD, or other suitable deposition processes. In some embodiments, the oxide layeris removed from the semiconductor layerprior to deposition of the gate fill layerof the gate metal.

In some embodiments, the metal gate boundary at the center point between the NMOS transistorand the PMOS transistorhas a dimension D to either side of the center point. The dimension D can be between 0 nm and 5 nm.

In some embodiments, after processing the high-K gate dielectric layersandhave a same thickness based, in part, on the lack of patterning of the gate fill layer. In some embodiments, the interfacial dielectric layeris thinner than the interfacial dielectric layer

The integrated circuitshown in relation tomay have various benefits in relation to other potential circuit structures and processes. For example, one potential circuit structure utilizes aluminum-based metals as work function layers for the NMOS transistor. However, the aluminum is easily oxidized and aluminum oxide is a high resistance. This can result in a high gate resistance as the devices scale-down. Furthermore, aluminum is easy to diffuse, potentially leading to a worse metal gate boundary. Additionally, utilizing multiple different metals from the gate structures can result in difficulties in patterning the gate metals. Accordingly, in some embodiments the integrated circuituses only a single gate metal. The layerof the gate metal and the gate fill layerare the same material. The effective work function of the transistor(and, therefore, the threshold voltage of the transistor) are adjusted by the presence of the semiconductor layerin the transistor. The structure of the PMOS transistoris very simple with either the gate fill layeror both the gate fill layer and the layerof the gate metal being present. The gate resistance may be less than or equal to 200 ohms/sq.

is an enlarged view of a portion of the integrated circuitat the stage of processing shown in, in accordance with some embodiments. The enlarged view ofillustrates a single channel regionof the transistorand a single channel regionof the transistor. The gate fill layeris in contact with the semiconductor layerat the transistorand with the high-K gate dielectric layerat the transistor

is a cross-sectional view of a portion of the integrated circuit, in accordance with some embodiments. In the view of, the horizontal direction is the X direction and the vertical direction is the Z direction.more clearly illustrates the gate structure above the channel regionsand. In particular, the gate trench above the channel regionsincludes the high-K gate dielectric layer, the layerof the gate metal, the semiconductor layer, and the gate fill layer. The gate trench is bounded by a dielectric layer. The gate trench above the channel regionsincludes the high-K gate dielectric layerand the gate fill layer. Only a single channel regionsandis shown for each transistorand. In practice, the additional stacked channel regions/are below the channel regionsandshown in.

is a cross-sectional view of the integrated circuit, according to one embodiment. The view ofillustrates more fully the overall structure of a gate all around transistor. The structures of the transistorsandmay be substantially similar to the structure of the transistorshown in. However,does not illustrate the presence of the semiconductor layeror the layerof the gate metal. Furthermore,illustrates only two channel regions. Nevertheless, structures and principles shown incan be utilized for the transistorsand

illustrates dielectric barriersbetween the semiconductor substrateand the source/drain regions. The dielectric barrierscan be utilized to electrically isolate the source/drain regionsfrom the semiconductor substrate. The dielectric material for the dielectric barriersmay include silicon oxide, silicon nitride, silicon oxynitride (SION), SIOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material, formed by low pressure CVD (LPCVD), plasma-enhanced CVD or flowable CVD, Other materials and structures can be utilized for the dielectric barrierswithout departing from the scope of the present disclosure.