Light Emitting Device and Image Forming Apparatus

The present disclosure relates to a light emitting device and an image forming apparatus.

There is proposed a print head (OLED-PH) for an image forming apparatus, which uses an organic light emitting diode (OLED) as a light emitting source. Japanese Patent Laid-Open No. 2022-162410 describes a light emitting device in which an OLED and a driving transistor for driving the OLED are formed on one substrate. Since the OLED and the driving transistor can be formed on the same substrate, miniaturization and cost reduction are possible.

In Japanese Patent Laid-Open No. 2022-162410, a data holding circuit configured to hold data for controlling light emission and non-light emission of each OLED is arranged. It is considered that the data holding circuit requires memory circuits for holding data, each of which is in a one-to-one correspondence with the OLED. In Japanese Patent Laid-Open No. 2022-162410, no consideration is given to the arrangement of memory circuits.

Some embodiments of the present disclosure provide a technique advantageous in miniaturization of a light emitting device.

According to some embodiments, a light emitting device that comprises, on a rectangular substrate having long sides in a row direction and shot sides in a column direction, pixels arranged to form rows and columns and a scanning circuit, wherein each of the pixels includes a light emitting element and a driving circuit configured to drive the light emitting element, the scanning circuit includes data holding circuits provided so as to respectively correspond to the columns, each data holding circuit includes memory circuits each configured to hold data for controlling the driving circuits arranged in the pixels in a corresponding column, and the memory circuits in each data holding circuit include a first memory circuit and a second memory circuit arranged to align in the row direction, is provided.

Further features of the various embodiments will become apparent from the following description of embodiments with reference to the attached drawings. The following description of embodiments are described by way of example.

Example embodiments of the present disclosure will be described hereinafter in detail, with reference to the accompanying drawings. It is to be understood that the following embodiments are not intended to limit the claims of the present disclosure, and that not all of the combinations of the aspects that are described according to the following embodiments are necessarily required with respect to the means to solve the issues according to the present disclosure. Further, in the accompanying drawings, the same or similar configurations are assigned the same reference numerals, and redundant descriptions are omitted.

With reference to, a light emitting device according to an embodiment of the present disclosure will be described. In the following description, an example will be described in which an organic light emitting diode (OLED) is used as a light emitting element arranged in the light emitting device. However, the present disclosure is not limited to the light emitting device using the OLED, and is also applicable to light emitting devices including current-driven light emitting elements in general.

is a sectional view showing an example of the arrangement of a light emitting deviceaccording to this embodiment.shows a section including a light emitting elementand a transistorconnected to the light emitting element. The light emitting elementand the transistorconstitute a pixel, and the transistorcan form a part of a driving circuit to be described later. The transistormay be provided in, for example, a substratemade of a semiconductor such as silicon. The transistoris formed by including a gate, a drain, and a source.

The drainof the transistorand the light emitting elementare connected by a wiring pattern. The wiring patterncan include contact plugstoand conductive patternsto. An insulating layeris provided between the wiring patterns. It can also be said that the wiring patternis arranged in the insulating layer. In, the insulating layeris shown as one layer, but the insulating layermay have a stacked structure in which layers are stacked.

The light emitting elementis formed by including the conductive pattern, an organic compound layerincluding a light emitting layer, and an electrode. The conductive patternis an electrode independent for each light emitting element(pixel), and can also be called a lower electrode or the like. The electrodemay be shared by the light emitting elements(pixels), and is a transparent electrode. Since the electrodeis transparent, light from the organic compound layercan be extracted to the outside. A protection layeris provided on the electrodeto suppress deterioration of the light emitting element(organic compound layer). In the light emitting device, a combination of the light emitting elementand the transistor(driving circuit) can be repeatedly arranged in the row direction and the column direction.

A structurehaving a large stepped portion in a layer immediately below the organic compound layeris formed between the respective light emitting elements. With the structure, the electrodeis formed to provide electrical connection while the organic compound layeris electrically isolated for each light emitting element(pixel).

The connection with the electrode (the sourceor the drain) included in the transistoris not limited to the arrangement shown in. In accordance with the polarity of the conductive pattern(light emitting element) or the polarity of the transistor, the sourceand drainof the transistormay be interchanged. It is only required that one of the sourceand drainof the transistoris electrically connected to the light emitting element.

The transistoris not limited to be provided in the substratemade of a semiconductor such as single-crystal silicon. For example, the transistormay be a thin film transistor (TFT) which is formed in an active layer using a semiconductor formed on the surface of an insulating substrate made of glass, a plastic, or the like. Examples of the material for the active layer are single-crystal silicon, non-single-crystal silicon such as amorphous silicon or microcrystal silicon, and a non-single-crystal oxide semiconductor such as indium zinc oxide or indium gallium zinc oxide.

shows a circuit block showing an example of the arrangement of the light emitting deviceaccording to this embodiment. The light emitting deviceincludes an interface circuit, a register, a reference current generation circuit, a programmable current source, a bias current source, a current control circuit, a pixel driving unit, and a scanning circuit. The scanning circuitis formed by including a data holding unitand a column selection unit.

The interface circuitreceives mode information for accessing the power supply or the register from outside the light emitting device, information concerning image data, or the like, and outputs a data signal to the registeror the scanning circuit. The programmable current sourceuses the output current of the reference current generation circuitas a reference, and outputs, to the bias current source, a current corresponding to a digital value supplied from the register. The driving current for the pixel driving unitis controlled by the set value of the register. The bias current sourcesupplies, to the current control circuit, an output current corresponding to the set value set by the register. The current control circuitgenerates the bias voltage of the pixel driving unit.

The data holding unitof the scanning circuitis formed by including data holding circuits. The data holding circuit holds data corresponding to each light emitting element, and controls light emission and non-light emission of the light emitting element. The column selection unitof the scanning circuitis formed by including column selection circuits. Based on the data signal from the interface circuit, the column selection unitselects the holding circuit to write data out of the data holding circuits and, as a result, controls the light emission and non-light emission timings of the light emitting element. The pixel driving unitis formed by including driving circuits. Each driving circuit is connected to the light emitting element. The driving current for each driving circuit is decided by the bias voltage supplied from the current control circuit, and the driving circuit controls light emission or non-light emission of the light emitting elementby a signal supplied from the data holding unit. Details of the pixel driving unitand the scanning circuitwill be described later.

is a view showing an example of the arrangement of the bias current source, the current control circuit, the pixel driving unit, and the light emitting element. A light emission current adjusting method and light emission control for the light emitting elementwill be described below.

As shown in, driving circuitsare arranged in the pixel driving unit. Light emitting elements Oto Oik are arranged as the light emitting elements. Each of the driving circuitsis connected to the corresponding light emitting element O to drive the light emitting element O. A pixel PIX is formed by including the corresponding driving circuitand light emitting element O. The driving circuitsinclude transistors Mto Mik for controlling currents flowing through the light emitting elements Oto Oik, and transistors Mto Mifor controlling light emission or non-light emission of the light emitting elements Oto Oik. From the data holding unitholding data corresponding to each light emitting element, a signal corresponding to the data is supplied to the control terminal of corresponding one of the transistors Mto Mi. Thus, light emission or non-light emission of each of the light emitting elements Oto Oik is controlled. The transistors Mto Mik are series-connected to the corresponding transistors Mto Mi, respectively. Similarly, the transistors Mto Miare series-connected to the corresponding light emitting elements Oto Oik, respectively. Each of the transistors Mto Micorresponds to the transistorshown in.

An output current Iof the programmable current sourceis connected to the drain terminal of a transistor Mconstituting the bias current source. The transistor Mis diode-connected, and a potential Vbn decided by the current Iis commonly applied to the gate terminals of transistors Mto Mi constituting the bias current source.

The pixels PIX arranged in the light emitting deviceare divided into circuit blockseach including a predetermined number of the pixels PIX. In a circuit block, the drain terminal of a transistor Mconstituting the current control circuitand the drain terminal of the transistor Mconstituting the bias current sourceare connected in series. The gate terminal of the transistor Mis connected to the drain terminal of the transistor Mvia a buffer B. The buffer Bis, for example, a voltage buffer having a gain of 1, and has a role of absorbing fluctuations in the gate potentials of the transistors Mto Mcaused by the light emission control operations of the driving circuits. The transistor Mis diode-connected via the buffer B, and a potential Vbpdecided by a current Iis commonly applied to the gate terminals of the transistors Mto Meach constituting the driving circuitof the pixel PIX.

The gate-source voltage is the same among the transistors Mto M, so that the same driving current can be supplied to the light emitting elements Oto Oarranged in the circuit block. That is, the transistors Mto Mfunction as constant current sources. Although not shown in, a driving voltage is applied to the gate terminals of the transistors Mto Mfrom the data holding circuit arranged in the data holding unit. Thus, whether to supply a current to each of the light emitting elements Oto Ois controlled. As a result, light emission or non-light emission of each of the light emitting elements Oto Ois controlled. That is, the transistors Mto Mfunction as switches.

If the driving circuitis influenced by fluctuations in the power supply potential, the current for driving the light emitting element O changes, which can cause, for example, unevenness in an output image of an image forming apparatus including the light emitting device. In the bias current source, the transistor Mand the transistors Mto Mi are arranged close to each other to form a current mirror circuit. This forms an arrangement that is less influenced by fluctuations in power supply lines PVDD and VSS. As a result, by employing the circuit arrangement according to this embodiment, it is possible to suppress unevenness in an output image of the image forming apparatus including the light emitting device. Similarly, in the circuit block, the transistor Mand the transistors Mto Mare arranged close to each other to form a current mirror circuit. This can suppress unevenness in an output image of the image forming apparatus including the light emitting device.

Each of circuit blockstohas an arrangement similar to the arrangement of the circuit block. That is, the light emitting elements Oto Oare driven to emit light by the driving circuitsincluding the transistors Mto Mand the transistors Mto M. The light emitting elements Oito Oik are driven to emit light by the driving circuitsincluding the transistors Mito Mik and the transistors Mito Mi

shows an example of the arrangement of the pixel driving unitcorresponding to the light emitting elements O in N rows and three columns, and the column selection unitand the data holding unitconstituting the scanning circuit. As will be described later with reference to, the pixels PIX are arranged to form rows and columns on the rectangular substratehaving long sides in the row direction and short sides in the column direction. The circuit shown inis a circuit corresponding to the pixels PIX in N rows and three columns among the pixels PIX.

Each of column driving circuitstois formed by N driving circuitsrespectively corresponding to N light emitting elements O arranged in the pixels PIX in each column. Each of the column driving circuitstodrives N light emitting elements O arranged in each column.

The data holding unitof the scanning circuitincludes data holding circuitstoprovided so as to respectively correspond to the columns in which the pixels PIX are arranged. As will be described later, each of the data holding circuitstoincludes memory circuitsthat respectively hold data for controlling the driving circuitsarranged in the pixels PIX in the corresponding column. The data holding circuitstoare electrically connected to the corresponding column driving circuitsto, respectively, and control the driving circuitsarranged in the column driving circuitsto

The column selection unitof the scanning circuitincludes column selection circuitsto. Each of the column selection circuitstoselects the data holding circuitto write data for controlling the column driving circuit. The column selection circuitis formed by including a flip-flop circuit and a logic element.

The interface circuitsupplies the scanning circuitwith a start pulse P_ST, a latch pulse PLATCH, and a data signal DATA<N:0> for controlling light emission or non-light emission of the light emitting element O.exemplarily shows the operation of the scanning circuitincluding the data holding unitand the column selection unit. From time to, a clock signal CLK starts to be supplied. The interface circuitsupplies, to the column selection unit, the start pulse P_ST which becomes active level at time t. The column selection circuitstoarranged in the column selection unitgenerate column selection signals SELto SEL, which do not overlap each other, by sequentially transferring pulse signals to the subsequent stages in synchronization with the clock signal CLK.

During the period from time tto time t, the column selection signal SELis at active level, and the latch pulse PLATCH becomes active level at time t. The data holding circuitof the data holding unitobtains and holds a value Dof the data signal DATA<N:0> at time t. In accordance with the data Dheld by the data holding circuit, each driving circuitarranged in the column driving circuitcontrols light emission of the corresponding light emitting element O.

During the period from time tto time t, the column selection signal SELis at active level, and the latch pulse PLATCH becomes active level at time t. The data holding circuitof the data holding unitobtains and holds a value Dof the data signal DATA<N:0> at time t. In accordance with the data Dheld by the data holding circuit, each driving circuitarranged in the column driving circuitcontrols light emission of the corresponding light emitting element O.

During the period from time tto time t, the column selection signal SELis at active level, and the latch pulse PLATCH becomes active level at time t. The data holding circuitof the data holding unitobtains and holds a value Dof the data signal DATA<N:0> at time t. In accordance with the data Dheld by the data holding circuit, each driving circuitarranged in the column driving circuitcontrols light emission of the corresponding light emitting element O. Subsequently, the above-described operations can be repeated in a similar manner.

The memory circuitsare arranged in each of the data holding circuitsto. A latch circuit shown inis an example of the memory circuit. The latch circuit shown inis a latch circuit having a reset function and using five NMOS transistors and five PMOS transistors. Since one latch circuit functions as one memory circuit, N latch circuits (memory circuits) are required to hold data for controlling N light emitting elements O.

is a view showing an example of the arrangement of the circuit block shown in. The respective elements constituting the light emitting deviceare arranged on the rectangular substratehaving long sides in the row direction and short sides in the column direction. In addition to the components shown in,shows padstofor external connection, which are connected to the interface circuit.

In the pixel driving unit, M driving circuitsare arranged at a predetermined resolution pitch in the row direction as the longitudinal direction. Furthermore, with M driving circuitsin one row, N driving circuits(for N rows) are arranged at a predetermined resolution pitch in the column direction as the lateral direction. The light emitting element O is arranged on the upper layer of each driving circuit.

The column selection unitand the data holding unitconstituting the scanning circuitare arranged along the row direction of the light emitting device. Therefore, the scanning circuitoccupies a large area in the light emitting device. Reducing the area occupied by the column selection unitand the data holding unitreduces the area of the light emitting device. In the rectangular light emitting device, the size in the row direction can be decided by the resolution pitch and the number of the pixels PIX arranged therein. On the other hand, reducing the size in the column direction as the lateral direction by reducing the area of the scanning circuitor the like significantly contributes to improvement in yield of the light emitting devicesobtained from one substrate. Hence, a significant cost reduction effect can be obtained by reducing the size in the column direction.

shows an example of the arrangement of the column driving circuitcorresponding to the pixels PIX arranged in one column, the data holding circuit, and the column selection circuit. The arrangement shown inis an arrangement example in which two rows of the pixels PIX are arranged in one column. In each column in which the pixels PIX are arranged, the data holding circuitcorresponding to each column is arranged between the driving circuit(column driving circuit) and the column selection circuit.

Two driving circuitsare arranged in the column driving circuit. The corresponding light emitting elements O are arranged at positions overlapping the driving circuits, thereby forming two rows of pixels PIX. The driving circuitsare arranged corresponding to the light emitting elements O of the pixels PIX forming one column, and therefore can be arranged along the column direction as shown in.

In the data holding circuit, two memory circuitsandare arranged to hold data for controlling the two driving circuits. In this case, the memory circuitsandare arranged to align in the row direction as shown in. In a case of the light emitting deviceused in an image forming apparatus or the like, the light emitting element O has a size (42 μm to 5.3 μm) corresponding to the resolution of the light emitting device, for example, 600 dpi to 4800 dpi. The arrangement interval between the driving circuits(column driving circuits) in the row direction is generally approximately the same as the arrangement interval between the light emitting elements O. On the other hand, in a case of the light emitting deviceusing a semiconductor substrate made of silicon or the like, elements such as transistors can be arranged in a layout finer than the arrangement interval between the driving circuits(column driving circuits). Accordingly, the length of the memory circuitin the row direction can be made smaller than the length decided by the arrangement interval of the driving circuits(column driving circuits) in the row direction. It can also be said that the length of the driving circuit(column driving circuit) in the row direction is larger than the length of the memory circuitin the row direction, among the memory circuits, arranged corresponding to each driving circuit(column driving circuit). Hence, by arranging the memory circuitsandin the row direction for the column driving circuitin one column, the length of the data holding circuitin the column direction can be made smaller than in a case of arranging the memory circuitsandin the column direction.

By arranging the memory circuitsandin the row direction in this manner, the size of the light emitting devicecan be reduced. Thus, more light emitting devicescan be obtained from one substrate. As a result, an effect of suppressing the manufacturing cost of the light emitting devicecan be obtained.

shows an example of the arrangement of the column driving circuit, the data holding circuit, and the column selection circuit, in which three rows of the pixels PIX are arranged in one column. Three driving circuitscorresponding to the number of the pixels PIX arranged in one column are arranged in the column driving circuit. The driving circuitscan be arranged along the column direction, as in the arrangement shown in. In the data holding circuit, three memory circuitstoare arranged to hold data for controlling the three driving circuits.

In the driving circuitsarranged in one column, there is a need to align the driving timings of the corresponding light emitting elements O. This is because, if the light emission timings of the light emitting elements O are not aligned, the light emission time changes among the pixels PIX, which can affect the quality of an image formed by the image forming apparatus including the light emitting device. Therefore, the data holding circuitsthat supply signals for controlling the driving circuitsmay be arranged in the row direction at approximately the same arrangement interval as the column driving circuits.

In the arrangement shown in, the memory circuitsandare arranged to align in the column direction. The memory circuitsandare arranged to align in the row direction. Similarly, the memory circuitsandare arranged to align in the row direction. In this case, the outer edge shape of the memory circuitis different from the outer edge shapes of the memory circuitsandin a planar view. The outer edge shape of the memory circuitand the outer edge shape of the memory circuitmay be the same. That is, the memory circuitstoin each data holding circuitmay include a first type memory circuit including the memory circuitand second type memory circuits including the memory circuitsand

For example, the length of the outer edge shape of the first type memory circuitin the column direction is different from the length of the outer edge shape of each of the second type memory circuitsandin the column direction. More specifically, the length of the outer edge shape of the first type memory circuitin the column direction is larger than the length of the outer edge shape of each of the second type memory circuitsandin the column direction. In addition, the aspect ratio obtained by dividing the length in the column direction by the length in the row direction, of the outer edge shape of the first type memory circuit, is different from the aspect ratio obtained by dividing the length in the column direction by the length in the row direction, of the outer edge shape of each of the second type memory circuitsand. More specifically, the aspect ratio obtained by dividing the length in the column direction by the length in the row direction, of the outer edge shape of the first type memory circuit, is higher than the aspect ratio obtained by dividing the length in the column direction by the length in the row direction, of the outer edge shape of each of the second type memory circuitsandis arranged. In this case, as shown in, the length of the outer edge shape of the first type memory circuitin the row direction may be smaller than the length of the outer edge shape of each of the second type memory circuitsandin the row direction. On the other hand, the memory circuitand the memory circuitmay have the same length in the column direction, the same length in the row direction, or the same aspect ratio obtained by dividing the length in the column direction by the length in the row direction.

By employing the arrangement as shown in, it is possible to arrange the memory circuitstoin the data holding circuitin accordance with the available space, rather than forming the data holding circuitfrom only the memory circuitshaving the same outer edge shape. Accordingly, the arrangement density of the memory circuitstoin the data holding circuitcan be improved. When the arrangement density of the memory circuitstois improved, the length of the light emitting devicein the column direction can be reduced, so that the size of the light emitting devicecan be reduced. As a result, more light emitting devicescan be obtained from one substrate, and an effect of suppressing the manufacturing cost of the light emitting devicecan be obtained.

shows an example of the arrangement of the column driving circuit, the data holding circuit, and the column selection circuit, in which four rows of the pixels PIX are arranged in one column. Four driving circuitscorresponding to the number of the pixels PIX arranged in one column are arranged in the column driving circuit. In the data holding circuit, four memory circuitstoare arranged to hold data for controlling the four driving circuits.

In the arrangement shown in, the memory circuits,, andare arranged to align in the column direction. The memory circuitsandare arranged to align in the row direction, the memory circuitsandare arranged to align in the row direction, and the memory circuitsandare arranged to align in the row direction. The memory circuitcan be the first type memory circuit described above, and the memory circuitstocan be the second type memory circuits described above. That is, the outer edge shape of the memory circuitis different from the outer edge shapes of the memory circuitsto. On the other hand, the memory circuitstomay have the same outer edge shape.

Similar to the arrangement shown in, the memory circuitstohaving different outer edge shapes are used. With this, as compared to a case of forming the data holding circuitfrom only the memory circuitshaving the same outer edge shape, it is possible to improve the arrangement density and arrange the data holding circuitwith a smaller area. As described above, in each of the columns in which the pixels PIX are arranged, the driving circuitsarranged in the pixels PIX in the corresponding column are arranged to align in the column direction. In this case, as shown in, the length in the column direction where the driving circuitsare arranged may be larger than the length in the column direction where the memory circuitsare arranged. In other words, the length occupied by the memory circuitsin the column direction may be smaller than the length occupied by the driving circuitsin the column direction.

is a view showing an example of the arrangement of the four memory circuitstoincluded in the data holding circuitshown in. The latch circuit shown inis arranged as each of the memory circuitsto, and each of the memory circuitstois configured to use five NMOS transistors and five PMOS transistors. In this embodiment, the NMOS transistor is formed by including a region where an n-type semiconductor region and the gate electrode overlap, and the PMOS transistor is formed by including a region where a p-type semiconductor region and the gate electrode overlap. The arrangement shown inshows an example in which the gate electrodes of the respective transistors are arranged along the column direction. It can also be said that transistors constituting each of the memory circuitstoin each data holding circuitare arranged to cause a current to flow in the row direction in a channel region. In this case, as shown in, all transistors constituting each of the memory circuitstomay be arranged to cause a current to flow in the row direction in the channel region. This can reduce the length of each of the memory circuitstoin the row direction.

In the arrangement shown in, all transistors in the memory circuitstoare used as elements constituting the memory circuits. On the other hand, in the memory circuit, one NMOS transistor and one PMOS transistor are arranged as a redundant element. As can be understood from the difference in the outer edge shape described above, the circuit layout of the first type memory circuitmay be different from the circuit layout of each of the second type memory circuitsto. In this embodiment, the circuit layout refers to the positional relationship among the elements arranged in the circuit.