System and Method for Devices with Dummy Metal Traces

The present application is a Divisional application to U.S. Patent Application No. 17/834,837 filed June 7, 2022, which claims priority to U.S. Provisional Patent Application No. 63/248,278, which was filed September 24, 2021, is titled “Method for Creating Planar Surfaces on Routed Ceramic Substrates And PCBS,” and which Applications are hereby incorporated herein by reference in their entireties.

Ceramic substrates are types of substrates useful for integrated circuits in electronic devices. A ceramic substrate is a processed electrical device carrier where a conductive material, such as copper or tungsten, is bonded to the surface of a ceramic substrate, such as an alumina or aluminum nitride substrate, at a certain high temperature. Compared with other material, ceramic substrates can be thin, provide high electrical insulation, high strength and stiffness, and high thermal conductivity, and have soft solderability and high adhesion strength. Ceramic substrates are suitable for electronic devices with high heat generation, such as high-brightness lamp or light emitting devices (LEDs), laser phosphor, laser-based projection devices, and solar cells, and are also useful in weather resistance devices for outdoor environments.

In accordance with at least one example of the disclosure, a method includes forming patterns of metallic traces on ceramic sheets, printing metal according to the patterns on the ceramic sheets to form the metallic traces including functional metallic traces and dummy metallic traces, forming vias through the ceramic sheets, and stacking and aligning the ceramic sheets to form a ceramic substrate.

In accordance with at least one example of the disclosure, a method includes obtaining a substrate layer. The method also includes forming metallic traces on the substrate layer, where the metallic traces include functional metallic traces, first dummy metallic traces, and second dummy metallic traces, where the first dummy metallic traces have a first density, the second dummy metallic traces have a second density, and the second density is different than the first density.

In accordance with at least one example, of the disclosure, a method includes forming first metallic traces on a first ceramic sheet, the first metallic traces including first functional traces and first dummy traces and forming second metallic traces on a second ceramic sheet, the second metallic traces including second functional traces and second dummy traces. The method also includes stacking the second ceramic sheet on the first ceramic sheet to produce a ceramic substrate.

In integrated circuits, circuit traces can be routed onto layers within ceramic substrates that provide electrical insulation, heat dissipation, and structural support. The layers which include routed metallic traces are also referred to herein as routing layers. Dies, which are silicon chips containing electrical circuits and electronic components, can be attached onto ceramic substrates by epoxy or solder materials. A circuit device can include one or more layers of ceramic substrates, which may be stacked on top of each other. Ceramic substrates can also be attached to circuit boards, also referred to herein as PCBs.

Ceramic substrates are examples of substrates that are useful for electronic devices because of the strength and heat dissipation properties of ceramic materials. For example, ceramic substrates are useful for electronic devices with relatively high heat generation compared to other electronic devices, such as high intensity lamps or light emitting diodes (LEDs), laser phosphor and/or direct laser-based projection devices, and photovoltaic cells. Circuit boards that include ceramic substrates are useful in electronic devices with high heat dissipation requirements in comparison to other devices. Examples of devices with ceramic substrates include display devices, such as a spatial light modulator (SLM) displays. SLM displays may include micro-electromechanical systems (MEMS) based display devices such as digital micromirror devices (DMDs) that include adjustable tilting micromirrors for projecting images or video for display. Other examples SLM displays include liquid crystal on silicon (LCoS) devices and liquid crystal displays (LCDs). Such displays can also include devices with ceramic substrates. Examples of MEMS devices with ceramic substrates also include MEMS sensor devices such as for gas sensors and radio frequency (RF) MEMS devices such as for RF and microwave transceivers. Each micromirror projects a pixel of the image to be displayed. The micromirrors are tilted by applying voltages to the micromirrors to project dark, bright, or shades of light per pixel. A DMD projection-based display system can also include light sources, such as laser light sources, of different wavelengths that provide color modes of the image. The light sources are operated to project color modes of light on the DMD to form the image. Other examples of devices with ceramic substrates include cooling and heating devices, power control devices, automotive electronics, aerospace and military electronic components, solar panel components, telecommunications switches, and lasers.

A ceramic substrate can be a mixture of ceramic and binder materials. Examples of ceramic materials include (but are not limited to) alumina (AlO), aluminum nitride (AlN), beryllium oxide (BeO), and silicon carbide (SiC). Examples of binder materials include (but are not limited to) epoxy and glass materials, organic binders such as butyl resin or acrylic acid ester, water soluble polyvinyl acetals and/or acrylic acid esters, and other binding agents. Circuit traces of conductive materials, such as copper or tungsten, can be routed on ceramic substrates for carrying electric current. The circuit traces can be formed by metal patterning processes of integrated circuit manufacturing, such as for PCBs. Metal patterning processes can include a combination of metal deposition, metal removal, and photolithography. For example, a resist layer is first patterned, such as by a photolithography process, on top of a metal layer on the substrate. The exposed metal under the patterned resist layer is then etched with a chemical etching process. The patterned resist layer is then removed by a chemical solution, which provides a remaining patterned metal layer on the surface. In another metal patterning process, the metal is deposited over a patterned resist layer. The resist layer under the metal is then removed, such as by lift off chemical process, to provide a patterned metal layer. In other examples, circuit traces can be formed by a screen printing process of a conductive material on the surface of a ceramic substrate. The conductive material, which can be in liquid or paste form laden with conductive copper or tungsten particles, is transferred through a patterned screen to the surface of the ceramic substrate. During a stage of ceramic substrate processing, the substrate is then heated, in a heating process, to evaporate the liquid, leaving the conductive material as a conductor in the form of circuit traces on the surfaces of the layers that form the substrate. The circuit traces of conductive materials are also referred to herein as metallic traces.

Manufacturing processes for packaging electrical circuits with one or more ceramic substrates include multiple steps. For example, the steps include a tape casting step for producing ceramic sheets as a mixture of ceramic and binder materials. The ceramic sheets can be cut, such as into rectangular or square shaped sheets, for further processing. The steps include punching holes into one or more of the ceramic sheets to provide cavities and/or vias through the ceramic sheets. The steps also include forming and routing metallic traces, by circuit patterning processes, on the surfaces of the ceramic sheets. Examples of conductive materials that are useful for metallic traces on ceramic substrates include copper and tungsten. The vias in the ceramic sheets can be filled or plated with the same conductive material as the metallic traces to provide electrical interconnections between the one or more layers of the ceramic substrates. Multiple ceramic sheets can be properly aligned and stacked on top of each other. The consistency and surface energy of the layer material causes the layers to adhere to each other, such as by mechanical pressing. In other examples, the stacked ceramic sheets can be laminated, which is a process by which the stacked ceramic sheets are bonded together by a bonding material. The steps also include dividing and shaping the stacked and bonded layers of ceramic sheets into separate ceramic substrates, each composed of multiple layers of ceramic sheets with routed metallic traces. The ceramic substrates can be cofired, which is a process by which the ceramic substrates are exposed to a certain temperature, and plated with metal, such as nickel, gold, and/or palladium to prevent any exposed metallic traces from corrosion. Dies can then be attached, by epoxy materials, on the surfaces of the ceramic substrates or in cavities that form sockets in the ceramic substrates. The epoxy attaching the ceramic substrates with the die can be cured by thermal or ultraviolet light energy to bind the components together.

The steps for printing and packaging electrical circuits with ceramic substrates may cause non-planar surfaces in one or more layers of the ceramic substrates. For example, the distribution of the routed metallic traces can provide areas that are empty of metallic traces or that include a lower density of metallic traces in the layers. The density of metallic traces in an area of the surface or layer represents the ratio of the parts of the area which are filled with metallic traces to the gap parts or the parts that are not filled with metallic traces.  The ratio can depend on the line width and spacing of the metallic traces. The lack of metallic traces or the reduced metallic density in some areas can cause surface variations in the layers, creating non-planar surfaces in the ceramic substrate or a stack of layers within the ceramic substrates. For example, a stack of layers within a ceramic substrate can include raised surfaces above areas where the density of metallic traces is relatively higher with respect to surrounding surfaces. Surfaces above or below areas where the routing of metallic traces is relatively sparse or nonexistent can also appear depressed with respect to surrounding surfaces.

The non-planar surfaces can cause stress areas in the epoxy which is useful to attach dies to the ceramic substrates. This stress may be transferred to the die and other components attached to the substrate. For example, the stress on the die can be caused by epoxy shrinkage during curing and substrate shaping steps of the manufacturing process. Because ceramic substrate materials can be structurally stronger than die materials, the stress can cause a die that is attached to a ceramic substrate to conform to the shape of the ceramic substrate, which can damage the die. The stress on the die can increase if the size of the die increases, if the thickness of the epoxy under the die increases, or if the die bonding process is more brittle.

This description includes various examples of providing planar surfaces or reducing non-planar surfaces in ceramic substrates that include one or more layers of conductive and/or insulating materials. To provide the planar surfaces or reduce the non-planar surfaces, dummy metallic traces are routed on the layers within a ceramic substrate, which also includes functional metallic traces that are routed to provide electrical connections according to the design of the electrical circuit. The current carrying metallic traces that are routed to provide electrical connections are also referred to herein as functional metallic traces. The metallic traces that are routed to provide planar surfaces or reduce non-planar surfaces are also referred to herein as dummy metallic traces. The dummy metallic traces are routed with the current carrying metallic traces to increase the density of metallic traces, provide a more uniform density of the metallic traces or materials on one or more layers, and/or reduce gaps across the surface of layers within the ceramic substrate. The uniform density of the metallic traces represents the similarity of the metallic density across the surface. The routed dummy metallic traces can provide uniform density of metallic traces in one or more separate areas, such as in gap areas on the surface, or across the entire surface. The dummy metallic traces may be equally spaced in the one or more separate areas to provide this uniform density. The line width of the metallic traces that form the dummy metallic traces can also determine the density of the dummy metallic traces. The line width and spacing of the dummy metallic traces in an area on the surface determine a ratio of an area portion that is filled with the dummy metallic traces to a gap portion that is not filled, and accordingly the metallic density in this area. Routing the dummy metallic traces with the functional metallic traces on the surfaces of the layers also reduces variation of density of metallic traces and variation of layer thickness across the surfaces. The dummy metallic traces can be routed with the current carrying metallic traces in each layer where there is a gap or reduced density of metallic traces or other materials across the surface. Accordingly, the dummy metallic traces can reduce non-planar surfaces or increase surface flatness across the layers of ceramic substrates. The density of metallic traces in a layer is also referred to herein as metallic density.

The density of the dummy metallic traces is determined based on the density of the functional metallic traces around or in a same area of the dummy metallic traces on the surface of the layer. In examples, the density of the dummy metallic traces is matched, such as by a percentage, to the density of the functional metallic traces around or in the same area of the dummy metallic traces. In this case, different areas of the surface can have different average densities of dummy and functional metallic traces. For example, the density of the dummy metallic traces can be within at least 50 percent (%) of the density of the functional metallic traces. In this case, the density of the dummy metallic traces is at least half of the density of the functional metallic traces on the surface. In other examples, the average density of metallic traces is matched across the entire surface. To match the average metallic density across the entire surface, the density of functional traces in the filled areas on the surface is determined. Accordingly, dummy metallic traces are routed in the gap areas to provide an average density across the surface based on the density of the functional metallic traces in the filled areas.  In a stack of layers within a ceramic substrate, the average density can be matched based on the density of the functional metallic traces on a layer by layer basis.

For example, in a stack of layers within a ceramic substrate, if the density of the functional metallic traces in a first layer of the ceramic substrate is lower than the densities of other layers, the density of routed dummy metallic traces in the first layer matches this lower density and may also be lower than the density of dummy metallic traces in other layers.  If the density of the functional metallic traces in a second layer of the ceramic substrate is higher than the densities of other layers, the density of routed dummy metallic traces in the second layer matches this higher density and may also be higher than the density of dummy metallic traces in other layers. The line spacing of metallic traces in the first layer that has relatively lower metallic density may also be larger than the line spacing of the metallic traces in the second layer with the relatively higher metallic density. Dummy metallic traces can also be routed with functional metallic traces in the same area in a layer. For example, dummy metallic traces can be routed in spaces between functional metallic traces in the same area if the density of the functional metallic traces in this area is less than the metallic density in other areas in the same layer. The dummy metallic traces are routed with the functional metallic traces to increase the average metallic density in the area or to match the average metallic density of the other filled areas.

The average metallic density can vary for different devices and circuit designs. For example, extended graphic array (XGA) or wide XGA (WXGA) devices with single data rate (SDR) or double data rate (DDR) interfaces may have fewer functional metallic traces in comparison to other display devices with higher pixel resolution. In relatively lower pixel resolution display devices, fewer dummy metallic traces can be routed to fill relatively larger gap areas and provide a relatively lower average metallic density, in comparison to other higher pixel resolution display devices. Display devices with higher pixel resolution, such asK orK display devices with high speed serial interfaces (HSSIs) may have more functional metallic traces than lower pixel resolution display devices. Accordingly, more dummy metallic traces can be routed in higher pixel resolution display devices to fill relatively smaller gap areas and provide a relatively higher average metallic density, in comparison to lower pixel resolution display devices.

The dummy metallic traces are not for carrying current and accordingly are not grounded and not connected to the current carrying metallic traces, electronic components, or vias. The routing of the dummy metallic traces in the layers may depend on the locations of the vias. For example, to avoid contact with the vias, the dummy metallic traces are excluded from areas where the vias extend through the layers. The dummy metallic traces routed outside the areas where the vias are located may be separated from the vias by distances which mitigate or avoid electrical interreference with current that may be carried in the vias. The locations of the vias may be based on the circuit design, and subsequently the routing of the dummy metallic traces is determined to excluded the locations of the vias. In other examples, the dummy metallic traces can be connected to a ground plane through direct contact with vias, which can extend through one or more layers, such as to reduce noise or reduce ground loops of functional metallic traces.

The dummy metallic traces can be routed in a pattern or a combination of patterns, such as in the shape of cross-hatched traces, line traces, square patches, diamond patches, rectangle patches, or other shapes that can be formed by the manufacturing process. The dummy metallic traces can also be formed of the same conductive material and with the same steps of printing as the current carrying metallic traces. In other examples, the dummy metallic traces can be formed of one or more other conductive or non-conductive materials and by one or more other processes.

The examples herein describe routing the dummy metallic traces with functional metallic traces in one or more layers on ceramic substrates. In other examples, the dummy metallic traces can also be routed with functional metallic traces in one or more layers on other types of substrates. For example, the dummy metallic traces can be routed with functional metallic traces in one or more layers in PCBs with substrates made of a dielectric or non-conductive materials, such as a combination of glass and epoxy. Examples of PCB substrates include flame retardant (FR type) substrates, composite epoxy materials (CEM) substrates, high-pressure fiberglass laminate (G type) substrates, aluminum or insulated metal (IMS) substrates, polytetrafluoroethylene (PTFE) substrates, polyimide substrates, and organic substrates. In examples, the dummy metallic traces can be routed with functional metallic traces in one or more layer in SiCBs with silicon substrates. Routing the dummy metallic traces in one or more layers in a stack of layers on such substrates can increase overall flatness across the layers.

is a block diagram of a display systemincluding a display devicewith a circuit board, in accordance with various examples. The circuit boardincludes a ceramic substratewith one or more layers of conductive and/or insulating materials that form planar surfaces. The ceramic substrateis useful for heat dissipation in the display device. The display devicemay also include a die(e.g., chip) mounted onto the ceramic substrate. The materials include functional or current carrying metallic traceson the surface of one or more layers of the ceramic substrate. The one or more layers also include dummy metallic traces. The dummy metallic traces are traces that are routed in the same layers with the functional metallic traces to provide planar surfaces on the substrate, which reduces stress and accordingly defect or damage to the die.

The display systemmay be a projection-based display system for projecting images or video. The display systemincludes a projection-based display deviceconfigured to project a modulated light beamonto an image projection surface. Examples of the image projection surfaceinclude a wall or a display screen. For example, the display screen may be a screen of an augmented reality (AR) or virtual reality (VR) display, a three-dimensional (3D) display, the ground or road for a headlight display, a projection surface in a vehicle such as for a windshield projection display, or other display surfaces for display devices. The modulated light beammay be modulated by the display deviceto project still images or moving images, such as video, onto the image projection surface. The modulated light beammay be formed as a combination of light beams corresponding to multiple color modes provided by the display device. The display devicemay include light sources (not shown) for providing the light beams at different wavelengths. The light beams at different wavelengths provide respective color components of the image and can be spatially modulated to form the image on the image projection surface. The display devicemay include an SLMmounted to the ceramic substrateand having optical components (not shown) for modulating the light beams from the light sources to provide the images or video on the image projection surface.

The SLMincludes the dieattached onto the ceramic substratethat is coupled to the circuit board. The ceramic substratehas a planar surface including both the functional metallic tracesand the dummy metallic traces. The display devicemay also include a controllercoupled to the SLMfor controlling the components of the display deviceto display the images or video. The SLMand the controllercan be integrated on the circuit board, which may be a PCB. For example, the SLMand the controllermay be system on chips (SoCs) embedded on the circuit board. In other examples, the SLMand the controllermay be embedded on separate circuit boards. In other examples, the controlleror other chips (not shown) may also be attached to one or more ceramic substratesand coupled to the circuit board.

shows a stack of routing layerswithin a ceramic substratewithout dummy metallic traces, in accordance with various examples. For example, the stack of routing layersof the ceramic substratecan be part of an integrated circuit or an electronic device. The routing layersare described as an example of the relationship between the variations in the density of metallic traces or other materials across the routing layersand the variations in the surfaces within the stack of routing layersin the ceramic substrate. The routing layerscan be ceramic sheets and include routed metallic traces. The routing layersinclude a first routing layer, a second routing layer, and a third routing layer. In other examples, there may be in the stack of routing layersas few as one routing layer or as many routing layers as necessary to accommodate all the routed metallic traces required by the circuit design. The first routing layer, second routing layer, and third routing layerare shown separately on the left side of. In examples, the first routing layerincludes first functional metallic traces, the second routing layerincludes second functional metallic traces, and the third routing layerincludes third functional metallic traces. The first routing layer, second routing layer, and third routing layeralso include viasthat interconnect one routing layer to another. The first, second, and third functional metallic traces,, andform one or more electrical circuits within the ceramic substrate. For example, the first, second, and third functional metallic traces,, andare line traces of a conductive material for carrying current in the stack of routing layerswithin the ceramic substrateand can be connected to electronic components (not shown).

The first routing layer, second routing layer, and third routing layerare stacked on top of each other to form the ceramic substrate, as shown on the right side of. The first routing layer, second routing layer, and third routing layerare also aligned to extend the viasthrough the ceramic substrate. The viasmay be filled with the same conductive material useful to print the conductive metallic traces and electrically coupled to the first, second, and third functional metallic traces,, and. For example, multiple viasmay provide either power, grounding, or discrete signals to the first, second, and third functional metallic traces,, and.

The stack of routing layersalso includes a combined areaof low metallic density with respect to the remaining areas through the first, second, and third routing layers,, andcombined. The combined areaof low metal density includes lower density areas of the first, second, and third functional metallic traces,, andwith respect to the remaining areas. The combined areais an overlap between a first lower metal density areawith respect to the remaining areas in the first routing layer, a second lower metal density areawith respect to the remaining areas in the second routing layer, and a third lower metal density areawith respect to the remaining areas in the third routing layer. The first lower metal density areaincludes a lower density of first functional metallic traceswith respect to the remaining areas of the first routing layer. The second lower metal density areaincludes a lower density of second functional metallic traceswith respect to the remaining areas of the second routing layer. The third lower metal density areaincludes a lower density of third functional metallic traceswith respect to the remaining areas of the third routing layer.

shows surface variations across the routing layersof the ceramic substratewithout dummy metallic traces, in accordance with various examples. The surface variations shown inacross the routing layersof the ceramic substratedemonstrate the effect of gaps or of reduced variations of density of metallic traces or other materials on the flatness across the routing layersthat form the ceramic substrate. The surface variations are shown for each of the first routing layer, second routing layer, and third routing layer. As shown, the first routing layeris sectioned into five sections of different layer thickness. The sections are labeled A, B, C, D, and Eand have layer thicknesses that increase in that order. For example, section Ahas the lowest layer thickness and section Ehas the highest layer thickness. Similarly, the second routing layeris sectioned into five sections of different layer thickness, which are labeled A, B, C, D, and Eand have layer thicknesses that increase in that order. The third routing layeris also sectioned into five sections of different layer thickness, which are labeled A, B, C, D, and Eand have layer thicknesses that increase in that order.

For example, because of the lower metal density of the first lower metal density areaon the first routing layer, a surface areaof the first routing layer, which overlaps with portions of sections A, B, Cand D, can be depressed with respect to the remaining areas of the first routing layer. Because of the lower metal density of the second lower metal density areaon the second routing layer, a surface areaof the second routing layer, which primarily overlaps with portions of section B, can be depressed with respect to the remaining areas of the second routing layer. Because of the lower metal density of the third lower metal density areaon the third routing layer, a surface areaof the third routing layer, which primarily overlaps with portions of sections A, B, C, and D, can be depressed with respect to the remaining areas of the third routing layer. Accordingly, the combined areaincan also be a depressed area with respect to the remaining areas of the routing layersthat form the ceramic substrate. The differences between the layer thicknesses of the respective areas of the first routing layer, second routing layer, and third routing layercan cause non-planar surfaces in the routing layersand accordingly in the ceramic substrate.

show a top view and a cross sectional view, respectively, of a stack of routing layerswithin a ceramic substratewith dummy metallic traces, in accordance with various examples. The routing layersof the ceramic substratecan be useful for integrated circuits or electronic devices with high heat dissipation and/or high strength or stiffness requirements such as display devices. For example, the ceramic substratemay correspond to the ceramic substratein the display device. The routing layersof the ceramic substrateinclude a first routing layer, a second routing layer, and a third routing layer. In other examples, there may be in the stack of routing layersas few as one routing layer or as many routing layers as necessary to accommodate all the routed metallic traces required by the circuit design. For example, the ceramic substratecan include four or eight routing layers. The number of routing layerscan also reach tens of layers, such as up to approximatelylayers. The first routing layer, second routing layer, and third routing layerare shown separately on the left side of.shows cross sectional views for the ceramic substrateand the first routing layer 402, second routing layer, and third routing layer. In examples, the first routing layerincludes first functional metallic traces, the second routing layerincludes second functional metallic traces, and the third routing layerincludes third functional metallic traces. The first, second, and third routing layers,, andalso include viasthat interconnect between the routing layers. The first, second, and third functional metallic traces,, andform one or more electrical circuits within the stack of routing layersthat form the ceramic substrate. For example, the first, second, and third functional metallic traces,, andare line traces of a conductive material for carrying current in the stack of routing layersof the ceramic substrateand can be connected to electronic components (not shown).

The first routing layeralso includes first dummy metallic tracesthat are routed on the first routing layeroutside the areas of the first functional metallic traces. The first dummy metallic tracescan be routed in areas that do not include the first functional metallic traces. The first dummy metallic tracescan also be routed in areas that are sparsely routed with first functional metallic tracesor with other structures in comparison to areas with higher material density on the surface of the first routing layer. For example, the first dummy metallic tracescan include a first part, a second part, and a third part, each of which may be separate parts of the first dummy metallic tracesthat are routed in three respective separate areas on the surface of the first routing layer. The first dummy metallic tracesin the first, second, and third parts,, andmay have the same pattern. For example, the pattern of the first dummy metallic tracesmay be cross-hatched traces, line traces, or metallic patches in each of the first, second, and third parts,, and. In other examples, the first dummy metallic tracesin the first, second, and third parts,, andmay have different patterns. In other examples, the first dummy metallic tracesmay be distributed in fewer or more than three parts on the surface of the first routing layeraccording to the requirements of the routing design.

Other examples of patterns of the first dummy metallic tracesinclude lines, crossed lines, patches or grids of any geometry, such as in the shape of squares, rectangles, circles, triangles, or other shapes. The pattern of the first dummy metallic tracescan be similar or different to the pattern of the first functional metallic traces. For example, the first functional metallic tracescan be patterned as lines of metallic traces, and the first dummy metallic tracescan be patterned similarly as line traces, cross-hatched traces, or metallic patches.

The number of parts of the dummy metallic tracescan depend on the number of gap areas between the functional metallic traces. For example, the number of parts of the dummy metallic tracescan match the number of gap areas between the functional metallic traces. As shown in, the first, second, and third parts,, andare routed in three respective gap areas between the functional metallic traces. In other examples, the number of parts of the dummy metallic tracescan match the number of areas that are filled with the functional metallic traces. The dummy metallic tracescan be routed around each area filled with functional metallic traces.

In examples, the densities of the first dummy metallic tracesin the first, second, and third parts,, andmay be different. The densities of the first dummy metallic tracesin the first, second, and third parts,, anddepend on and match the densities of the first functional metallic tracesaround the first, second, and third parts,, and, respectively. Accordingly, if the density of the first functional metallic tracesare different in respective areas around the first, second, and third parts,, and, the densities of the first dummy metallic tracesaround the respective areas are also different. For example, if a first area around the first parthas a higher density of first functional metallic tracesthan a second area around the third part, the matching density of the first dummy metallic tracesis also higher in the first partrelative to the third part. The line width and spacing of the first dummy tracesin the areas on the surface determine the density of the first dummy metallic traces. For example, if the first dummy metallic traces are line traces or cross-hatched traces, the line width and spacing determine the ratio of metallic traces to gaps, and accordingly the metallic density, in the areas.

In other examples, the average densities of the first functional metallic tracesand the first dummy metallic tracesare similar across the entire surface of the first routing layer, including the respective areas around the first, second, and third parts,, and. In this case, the densities of the first dummy metallic tracesin the first, second, and third parts,, andmay be determined according to the respective densities of the first functional metallic tracesaround the respective areas to provide an average density of metallic traces across the entire surface of the first routing layer.

The first dummy metallic tracesare provided, with the first functional metallic traces, on the surface of the first routing layerto provide a more uniform density and distribution of the metallic traces or of materials on the surface, increase the density of metallic traces, and/or reduce gaps across the surface of the first routing layer. To provide this uniform density of metallic traces, the first dummy metallic tracesare equally spaced in the respective areas of the first, second, and third parts,, and. The first dummy metallic tracescan also have equal line width. For example, the first dummy metallic tracesare comprised of line traces or crossing line traces (e.g., cross-hatched traces) which are metal lines of approximately the same width that are formed by the same fabrication process. The height (thickness) of the first dummy metallic tracesis also equal to the height of the first functional metallic traceson the surface of the first routing layer. For example, the first dummy metallic tracesand the first functional metallic tracesinclude metal lines of approximately the same height that are formed by the same fabrication process. The variations between the approximately equal width and spacing of the metal lines may be based on the limitations and uncertainties in the fabrication process. For example, the approximately equal width or spacing can vary to up to 10% or 15% between the metal lines. A threshold of the variation in the width or spacing of the metal lines by the fabrication process can be tolerated according to quality requirements of manufacturing and device design. The line width and spacing of the first dummy metallic tracesmay be equal or different in the different areas. This also reduces variation of density of metallic traces and variation of layer thickness across the surface. Accordingly, the first dummy metallic traceswith the first functional metallic tracescan increase surface flatness across the first routing layer. The first dummy metallic tracesare electrically isolated in the first, second, and third parts,, andand are not connected to any of the first functional metallic traces, the vias (not shown), or to electronic components (not shown) on or in the routing layersthat form the ceramic substrate.

The second routing layeralso includes second dummy metallic tracesthat are routed on the second routing layeroutside the areas of the second functional metallic traces. The second dummy metallic tracescan be routed in areas that do not include the second functional metallic tracesor that are sparsely routed with metallic traces or populated with other structures in comparison to areas with higher material density on the surface of the second routing layer. For example, the second dummy metallic tracescan include a first part, a second part, and a third partof the second dummy metallic tracesthat are routed outside the second functional metallic traces. The first, second, and third parts,, andmay be separate parts of the second dummy metallic tracesthat are routed in three respective separate areas on the surface of the second routing layer. The second dummy metallic tracesin the first parts 415a, second part, and third partmay have the same pattern. For example, similar to the patterns of the first dummy metallic tracesin the first routing layer, the pattern of the second dummy metallic tracesin the second routing layermay be cross-hatched traces, line traces, or metallic patches in each of the first, second, and third parts,, and. In other examples, the second dummy metallic tracesin the first, second, and third parts,, andmay have different patterns. The second dummy metallic tracesin the second routing layermay also have different patterns than the first dummy metallic tracesin the first routing layer. In other examples, the second dummy metallic tracesmay be distributed in fewer or more than three parts on the surface of the second routing layer.

The second dummy metallic tracesare provided, with the second functional metallic traces, on the surface of the second routing layerto provide a more uniform density and distribution of the metallic surfaces or of materials on the surface, increase the density of metallic traces, and/or reduce gaps across the surface of the second routing layer. The second dummy metallic tracesare equally spaced in the respective areas of the first, second, and third parts,, and. The second dummy metallic tracescan also have equal line width. The height (thickness) of the second dummy metallic tracesis also equal to the height of the second functional metallic traceson the surface of the second routing layer. The line width and spacing of the second dummy metallic tracesmay be equal or different in the different areas. Accordingly, the second dummy metallic traceswith the second functional metallic tracescan reduce surface variations on the second routing layer. The second dummy metallic tracesare electrically isolated in the first, second, and third parts,, andand are not connected to any of the second functional metallic traces, the vias, or to electronic components (not shown) on or in the routing layersof the ceramic substrate. The second dummy metallic tracesare also not connected to any other metallic traces or electronic components in other routing layers of the ceramic substrate.

The densities of the second dummy metallic tracesin the first, second, and third parts,, andcan also match the densities of the second functional metallic tracesaround the respective areas. In other examples, the average densities of the second functional metallic tracesand the first dummy metallic tracescan be equal across the entire surface of the second routing layer, including the areas of the first, second, and third parts,, and.

The routing layersof the ceramic substratemay also include any number of routing layers that include dummy metallic traces (not shown). The third routing layerand any dummy routing layers within the ceramic substrate, as the routing design requires, can be configured similar to the same design features for the first and second routing layersand.

The third routing layerincludes third dummy metallic traces. The third dummy metallic tracesare provided, with the third functional metallic traces, on the third routing layerto provide a more uniform density and distribution of the metallic traces or of materials on the surface, increase the density of metallic traces, and/or reduce gaps across the third routing layer. Accordingly, the third dummy metallic traceswith the third functional metallic tracescan increase the surface flatness across the third routing layer. The line width and spacing of the third dummy metallic tracesmay be equal or different in the different areas. The third dummy metallic tracesare equally spaced in the respective areas of the first, second, and third parts,, and. The third dummy metallic tracescan also have equal line width. The height (thickness) of the third dummy metallic tracesis also equal to the height of the third functional metallic traceson the surface of the third routing layer. The third dummy metallic tracescan be electrically isolated in multiple parts, such as first, second, and third parts,, and, and are not connected to any of the third functional metallic traces, the vias, or to electronic components (not shown) on or in the routing layers. The third dummy metallic tracesare also not connected to any other metallic traces or electronic components in other routing layers of the stack of routing layersin the ceramic substrate.

Each of the first, second, and third routing layers,, and, and similarly any other layers of the routing layers, can be formed by forming metallic traces on a ceramic sheet. For example, the metallic traces can be formed by a metal patterning process including metal deposition, such as for PCBs, or by a screen printing process with a conductive material paste. The first, second, and third routing layers,, andare stacked on top of each other to form the ceramic substrate, as shown on the right side of. The first, second, and third routing layers,,and any other layers of the routing layersare aligned, stacked and mechanically pressed together. This causes the routing layersto adhere to each other and form the ceramic substrateas a homogeneous structure. In other examples, the routing layerscan be stacked and laminated to form the ceramic substrate.

For example, as shown in the cross sectional view of, the metallic traces on a surface of a routing layermay be covered by another routing layerthat is stacked on top of the metallic traces. For example, the third routing layerthat is stacked on top of the second routing layercovers the second functional metallic tracesand the second dummy metallic traceson the surface of the second routing layer, including the first, second and third parts,, and. Similarly, the second routing layerthat is stacked on top of the first routing layercovers the first functional metallic tracesand the first dummy metallic traceson the surface of the first routing layer, including the first, second and third parts,, and. In other examples, the routing layerscan be laminated and bonded by epoxy layers that are placed between the routing layers. For example, a respective epoxy layer that bonds the second routing layerto the first routing layercovers the first functional metallic tracesand the first dummy metallic traceson the surface of the first routing layer. Similarly, a respective epoxy layer that bonds the third routing layerto the second routing layercovers the second functional metallic tracesand the second dummy metallic traceson the surface of the second routing layer. The first, second, and third routing layers,, andare layers of a ceramic material.

The first, second, and third routing layers,, andare also aligned to extend the viasthrough the first, second, and third layers,, and. The viasmay be electrically coupled to the first, second, and third functional metallic traces,, andand filled or plated with the same conductive material. For example, the viasmay provide either power, grounding, or discrete signals to the first, second, and third functional metallic traces,, and.

Increasing surface flatness across the first, second, and third routing layers,, andwith the first, second, and third dummy metallic traces,, and, respectively, also reduces layer thickness variation and increases surface flatness throughout and across the stack of routing layerswithin the ceramic substrate. This reduces stresses due to the non-uniform thickness of epoxy that attaches a dieto the ceramic substratein the area where the die may be attached, also referred to herein as a die attach area. The die attach area is a location of the surface upon which the dieis attached to one of the routing layers. For example, the diecan be a SLM die such as a DMD chip attached to the ceramic substrateon the surface of the third routing layer, as shown in the cross sectional view of. In this case, the stress is reduced in the attached component and the bond lines which attach that component. Reducing the stress induced across the die attach area also reduces the stress on the backside area of the ceramic substrate, where a land grid array (LGA) can be provided for electrical contacts. In this case, the electrical interface contact distance of the LGA is also reduced, which increases the reliability of the signal connection through the LGA.

shows a PCBincluding multiple layers of dielectric and conductive materials. The PCBincludes a substratepositioned between a first conductive layerand a second conductive layeron opposite sides of the substrate. For example, the first conductive layerand second conductive layercan be copper layers that can carry current and which are separated by the substrate. The substratecan be composed of woven glass and epoxy and is an electrically isolating layer between the first conductive layerand the second conductive layer. The PCBalso includes a first routing layeron a surface of the first conductive layeropposite to the substrate, and a second routing layeron a surface of the second conductive layeropposite to the substrate. The first routing layerand similarly the second routing layercan be dielectric layers that include on their respective surfaces metallic traces that form one or more circuits in the PCB.

The PCBalso includes viasthat extend through the layers of the PCBand can connect one or more circuits on opposite sides of the PCB. The first routing layerincludes functional metallic tracesand dummy metallic traces. As shown in, the functional metallic tracesand the dummy metallic tracesare routed in respective separate areas on the surface of the first routing layer. The functional metallic tracesare configured to carry current in one or more circuits on both sides of the PCB. In examples, the dummy metallic tracesare routed on the first routing layeroutside the areas of the functional metallic traces. The dummy metallic tracescan also be routed in areas that are sparsely routed with functional metallic traces. The dummy metallic tracesrouted in the different areas may have the same pattern or may have different patterns. The second routing layercan also include, on the surface, functional metallic traces and dummy metallic traces (not shown). The functional metallic traceson the surface of the first routing layerand the functional metallic traces (not shown) on the second routing layercan be connected to the vias, which may provide either power, grounding, or discrete signals to the electrical circuits in the PCB. The PCBinis a dual side PCB that have one or more circuits on both sides. In other examples, PCBs can have one or more circuits in one or more routing layers that are stacked on one side of the PCB substrate. The one or more routing layers can include functional and dummy metallic traces configured similar to the functional and dummy metallic tracesand, respectively.

The pattern of the dummy metallic tracescan be similar to or different from the pattern of the functional metallic traces. For example, the functional metallic tracescan be patterned as lines of metallic traces, and the dummy metallic tracescan be patterned similarly as line traces or can be cross-hatched traces, line traces, or metallic patches.

The dummy metallic tracesare provided, with the functional metallic traces, on the surface of the first routing layerto provide a more uniform density and distribution of the metallic traces or of materials on the surface, increase the density of metallic traces, and/or reduce gaps across the surface of the first routing layer. To provide this uniform density of metallic traces, the dummy metallic tracesare equally spaced in each of the respective areas. The dummy metallic tracescan also have equal line width. The height (thickness) of the dummy metallic tracesis also equal to the height of the functional metallic traceson the surface of the first routing layer. The line spacing of the dummy metallic tracesmay be equal or different in the different areas.

The densities of the dummy metallic tracesmay match the densities of the functional metallic traces. Accordingly, if the density of the functional metallic tracesare different in respective areas on the first routing layer, the densities of the dummy metallic tracesare also different around the respective areas. For example, if the functional metallic traceshave a higher metallic density in a first area on the surface than in a second area on the surface, the density of the dummy metallic tracesaround the first area is also higher than the density of the dummy metallic tracesaround the second area.

In other examples, the average densities of the functional metallic tracesand the dummy metallic tracescan be equal across the entire surface of the first routing layer. In this case, the densities of the dummy metallic tracesin separate areas may be determined according to the respective densities of the functional metallic tracesaround the respective separate areas to provide an average density of metallic traces across the entire surface of the first routing layerand.

is a diagram showing a routing layer in a silicon-based circuit board (SiCB) with dummy metallic traces, in accordance with various examples.shows a SiCBincluding a silicon substrateand a routing layeron the silicon substrate. The routing layercan be a dielectric layer that includes functional metallic tracesthat form one or more circuits in the SiCB. The routing layeralso includes dummy metallic tracesthat are routed on the surface around the functional metallic traces. The dummy metallic tracescan be routed in areas that are not routed by functional metallic tracesor sparsely routed with functional metallic traces. In other examples, SiCBs can have multiple routing layers stacked on top of each other on the silicon substrate. The routing layers can include functional and dummy metallic traces configured similar to the functional and dummy metallic tracesand, respectively.

The dummy metallic tracesmay have the same pattern or may have different patterns on different areas of the surface of the routing layer. The pattern of the dummy metallic tracescan be similar to or different from the pattern of the functional metallic traces. For example, the functional metallic tracescan be line traces, and the dummy metallic tracescan also be line traces, can be cross-hatched traces, line traces, or metallic patches.