Heterogeneous Integration Structure to Solve Ivr Overshoot Problem

This application claims the benefit of the following provisionally filed U.S. Patent application: Application No. 63/654,353, filed on May 31, 2024, and entitled “HETEROGENEOUS INTEGRATION STRUCTURE TO SOLVE IVR OVERSHOOT PROBLEM,” which application is hereby incorporated herein by reference.

Voltage regulators are used in integrated circuits to provide power. The voltage regulators have the ability of regulating power supply voltages. In a package, the voltage regulators may be formed as discrete dies, which are bonded to a printed circuit board. The voltages generated by the voltage regulators are provided to the integrate circuit components that are also bonded to the printed circuit board.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A package including an Integrated Voltage Regulator (IVR) and a Resistor-Capacitor (RC) component and the method of forming the same are provided. In accordance with some embodiments of the present disclosure, an IVR and a RC component are embedded in a package. The IVR and the RC component may be embedded in a core of a package substrate, a build-up structure of a package substrate, an underfill, a redistribution structure, a layer for allocating Local Silicon Interconnect (LSI) dies, and/or the like. The RC component is located close to the IVR. Furthermore, the RC component may be located in the path between the IVR and the powered devices powered by the regulated voltages, so that the resistance of the connection lines may be reduced. By adopting the IVR and the RC component, the transient overshoot of the IVR may be reduced.

Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

illustrate the views of intermediate stages in the formation of a package including an IVR and a RC component in accordance with some embodiments of the present disclosure. The corresponding processes are also reflected schematically in the process flow shown in.

illustrates carrierand release filmformed on carrier. Carriermay be a glass carrier, a silicon wafer, an organic carrier, or the like. Release filmmay be formed of a polymer-based material (such as a Light-To-Heat-Conversion (LTHC) material), which is capable of being decomposed under heat-carrying radiation such as a laser beam, so that carriermay be de-bonded from the overlying structures that will be formed in subsequent processes.

A build-up structure(also referred to as redistribution structureor interconnect structure) is formed over carrier. The respective process is illustrated as processin the process flowas shown in. The build-up structureincludes a plurality of dielectric layersand a plurality of Redistribution Lines (RDLs)formed over the release film. Dielectric layersmay be formed of a polymer(s), which may also be a photo-sensitive material(s) such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, that may be patterned using a photo-lithography process including a light-exposure process and a development process.

RDLsmay be formed through plating. The formation of RDLsmay include forming a metal seed layer (not shown), forming a patterned mask (not shown) such as a photoresist over the metal seed layer, and then performing a metal plating process on the exposed seed layer. The patterned mask and the portions of the metal seed layer covered by the patterned mask are then removed, leaving RDLs. In accordance with some embodiments, the metal seed layer includes a titanium layer and a copper layer over the titanium layer. The metal seed layer may be formed using, for example, Physical Vapor Deposition (PVD) or a like process. The plating may be performed using, for example, an electrochemical plating process or an electro-less plating process. The plated material may comprise copper.

Next, as shown in, metal postsare formed. The respective process is illustrated as processin the process flowas shown in. The formation process may include forming a metal seed layer, forming a plating mask (not shown, may be a photoresist) over the metal seed layer, patterning the plating mask to reveal the underlying metal seed layer, and then plating a metallic material in the openings of the plating mask. The plating mask is then removed, followed by an etching process to remove the portions of the metal seed layer previously covered by the plating mask.

Metal postsare alternatively referred to as through-vias since they will penetrate through the subsequently formed encapsulating material (which may be a molding compound). The plated metallic material may be copper or a copper alloy. Metal postsmay have substantially vertical and straight edges. In accordance with alternative embodiments, conductive pipes (also referred to as Plated Through-Holes (PTHs)) are formed. The formation of the PTHs may be essentially the same as the formation of metal posts.

further illustrates the placement/attachment of IVR die. The respective process is illustrated as processin the process flowas shown in. IVR diemay be attached to redistribution structure, for example, through die-attach film, which is an adhesive film. IVR dieincludes electrical connectorsA andB (collectively referred to as electrical connectors), which may include an input node and an output node. Electrical connectorsA andB may be metal pillars in accordance with some embodiments.

illustrates the circuit diagram of an example IVR diein accordance with some embodiments. The input nodeA of IVR dieis used for receiving a high input voltage Vi, such as 15 V, 9V, or the like input voltage Vi is also shown inin accordance with some embodiments. Through the drive IC and other circuits, other power supply voltages such as 5V, 3.3V, 1.2V, 0.9V, and 0.75V, and/or the like, are generated at output node(s)B, which are also the electrical connector(s)B inin accordance with some embodiments.

Next, referring to, IVR dieand metal postsare encapsulated in encapsulant. The respective process is illustrated as processin the process flowas shown in. Encapsulantfills the gaps between neighboring metal postsand IVR die. Encapsulantmay include glass fiber, prepreg (which comprises epoxy, resin, and/or glass fiber), resin coated Copper (RCC), glass, plastic (such as PolyVinylChloride (PVC), Acrylonitril, Butadiene & Styrene (ABS), Polypropylene (PP), Polyethylene (PE), PolyStyrene (PS), Polymethyl Methacrylate (PMMA), Polyethylene Terephthalate (PET), Polycarbonates (PC), Polyphenylene sulfide (PPS), flex (polyimide), molding compound, molding underfill, epoxy, resin, or combinations thereof.

When formed of a molding compound, encapsulantmay include a base material, which may be a polymer, a resin, an epoxy, or the like, and filler particles in the base material. The filler particles may be the dielectric particles of SiO, AlO, silica, or the like, and may have spherical shapes. Also, the spherical filler particles may have a plurality of different diameters.

A planarization process such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process is then performed to thin encapsulant, until metal postsand IVR dieare exposed. Due to the planarization process, the top ends of through-viasare substantially level (coplanar) with the top surfaces of electrical connectors, and are substantially coplanar with the top surface of encapsulant. Throughout the description, metal postsare also referred to as through-viassince they penetrate through encapsulant. Encapsulantacts as the dielectric core (and is also referred to as dielectric core) in the respective package substrate.

illustrates the formation of redistribution structure(also referred to as an interconnect structure), which includes dielectric layersand RDLs. The respective process is illustrated as processin the process flowas shown in. Redistribution structureis alternatively referred to as build-up structureor interconnect structure. The formation of redistribution structuremay be essentially the same as that of redistribution structure. Dielectric layersmay be formed of an organic material such as PBO, polyimide, or the like.

Referring to, openingis formed in the dielectric layersin redistribution structure. The respective process is illustrated as processin the process flowas shown in. In accordance with some embodiments, the formation process may include an etching process, in which an etching mask (such as a photoresist) is formed to define the size and the position of opening. In accordance with alternative embodiments, the formation of openingincludes a laser ablation process. A metal padmay be formed as an etch stop layer (or the stop layer for the laser ablation). The metal padis also formed in the same processes in which a corresponding layer of RDLsis formed. The metal padmay be electrically floating, or may have electrical connection function, for example, with currents flowing through.

In accordance with alternative embodiments, openingpenetrates through dielectric layers, with a top surface of encapsulantbeing exposed and used as the etch stop layer.

also illustrates the placement of RC componentinside opening. The respective process is illustrated as processin the process flowas shown in. In accordance with some embodiments, the placement is achieved by using die-attach film, which adheres RC componentto metal pad. In accordance with alternative embodiments, the openingis formed so that RC componentmay be tightly fit in opening, with the sidewalls of RC componentin physical contact with the sidewalls of dielectric layers. The sidewalls of RC componentmay be spaced apart from, or may be in physical contact with RDLsin accordance with some embodiments. RC componentmay include electrical connectors(includingA andB), for example.

RC componentmay have various structures. For example,illustrates that RC componentmay include a plurality of resistorsand a plurality of capacitors. A resistorand a capacitormay form a unit, and the RC componentmay include a plurality of units that are connected in parallel.

illustrates a single-RC RC componentthat includes a single resistorand a single capacitorin accordance with some embodiments. It is appreciated that the IVRand RC componentmay have many applicable forms other than illustrated in, and the corresponding IVRand RC componentsare also in the scope of the present disclosure.

In accordance with some embodiments, as shown in, gap-filling regionis formed to fill the rest of opening. The respective process is illustrated as processin the process flowas shown in. In accordance with some embodiments, gap-filling regionis formed of or comprise an underfill, a polymer, a resin, an epoxy, or the like. The gap-filling regionis dispensed into openingand then cured as a solid after the dispensing, followed by a planarization process to level its top surface with the top surface of redistribution structureand electrical connectors. Gap-filling regionis in physical contact with dielectric layers, and may or may not be in physical contact with some of the RDLson the opposing sides of gap-filling region. Gap-filling regionmay also be in physical contact with the top surface of metal padin accordance with some embodiments.

The structure over release filmis referred to as a (wafer-level) package substratein accordance with some embodiments, which may include one or a plurality of package substrates therein. In accordance with some embodiments, package substratemay be de-bonded from carrier. The respective process is illustrated as processin the process flowas shown in. The de-bonding process may include projecting a radiation (such as a laser beam) on release film, which laser beam penetrates through carrier. Release filmis thus decomposed, and package substratemay be de-bonded from carrier.

In accordance with some embodiments, as shown in, under-bump metallurgiesand solder regionsand may be formed on the bottom side of package substrate. One of solder regionsis electrically connected to IVR diein order to provide the input voltage to IVR die. Package substratesmay include a plurality of identical package substrates′ therein, each including an IVR dieand a RC component.

In accordance with alternative embodiments, the de-bonding of package substratefrom carriermay be performed in a subsequent process, for example, at a time after package component(also referred to as a package) has been bonded to package substrate.

In accordance with some embodiments, the package substratemay be singulated in a sawing process, so that the plurality of discrete package substrates′ therein are separated from each other. In accordance with alternative embodiments, the sawing of package substrateinto discrete package substrates′ may be performed in a subsequent process, for example, after a plurality of package componentshave been bonded to package substrates′.

further illustrates package component(also referred to as a package) in accordance with some embodiments. The formation of package componentmay include forming redistribution structure, which includes a plurality of dielectric layersand redistribution lines. The materials and the formation processes of the dielectric layersand the redistribution linesmay be essentially the same as that of the dielectric layersand the redistribution lines, respectively, in redistribution structure. Solder regionsmay be formed underlying and electrically connected to the redistribution lines.

Through-viasare formed over and electrically connecting to the redistribution lines. The formation process may be essentially the same as that of through-vias, which formation process may include plating through-viasdirectly from the metal pads in redistribution lines.

In accordance with some embodiments, device diesare bonded to redistribution structure. Device diesmay include LSI dies, which are used to electrically interconnect the overlying package components. Device diesmay also include passive device dies such as deep-trench capacitor dies. In accordance with some embodiments, the LSI dies include semiconductor substrate, and through-substrate vias (TSV, also referred to as through-silicon vias). The TSVsand through-viaselectrically connect the redistribution linesto the overlying redistribution lines.

Through-viasand device diesare encapsulated in encapsulant, which may include molding compound, molding underfill, or may include inorganic materials such as a silicon nitride layer and a silicon oxide region over the silicon nitride layer.

Package componentmay further include redistribution structureover device dies. Redistribution structuremay include a plurality of dielectric layersand a plurality of redistribution lines. The materials and the formation processes of the dielectric layersand the redistribution linesmay be essentially the same as that in redistribution structure.

Package components(including package componentsA andB) are bonded to redistribution structure. The respective process is illustrated as processin the process flowas shown in. The bonding of package componentsto redistribution structuremay be performed through solder bonding, metal-to-metal direct bonding, hybrid bonding (including both of metal-to-metal direct bonding and fusion bonding), or the like.

Package componentsA (also referred to as device dies when including device dies therein) may be High-bandwidth memory (HBM) stacks. Package componentsB may be discrete device dies, System-on-Chip (SoC) dies, or the like. Package componentsB may also include Deep-Trench Capacitors (DTCs), active device dies, Independent Passive Devices (IPDs).

In accordance with some embodiments, package componentsmay be encapsulated in encapsulant, which may include a molding compound, a molding underfill or the like. There may also be underfills in the gaps between the package componentsand the underlying redistribution structure.

illustrates the bonding of package component(also referred to as a package) to package substrate′ in accordance with some embodiments. Packageis thus formed. The bonding may be achieved through solder bonding using solder regions. Underfillis also dispensed in the gap between package substrate′ and package component.

In accordance with some embodiments in which package substrate′ has already been sawed into package substrate, a die-on-die bonding is performed, and a single package componentmay be bonded to a discrete package substrate′. In accordance with these embodiments, the edges of the single package componentmay extend laterally beyond the corresponding edges of the package substrate′, vertically aligned to the corresponding edges of the package substrate′, or laterally recessed from the corresponding edges of the package substrate′.

In accordance with alternatively embodiments, a die-on-wafer bonding process is performed, in which a plurality of package componentsare bonded to the package substrate(including a plurality of package substrates′ that have not been sawed apart) that is at the wafer level. After the plurality of package componentsare bonded to the package substrate, an additional encapsulating process may be performed to encapsulate the plurality of package componentsin an additional encapsulant, which additional encapsulant is over and physically contacting the wafer-level package substrate. A sawing process is then performed to saw the resulting package into a plurality of identical packages, each including one package substrate′ and one package component.

In accordance with the embodiments in which the die-on-wafer bonding is performed, the edges of the package componentare laterally recessed from the corresponding edges of the underlying package substrate′. The outer edges of the additional encapsulant (not shown) are vertically aligned to the edges of the underlying package substrate′.

illustrates the bonding of packageto package componentto form package. Package componentmay include a printed circuit board, another package substrate, or the like. In the resulting package, the input voltage, which may be a relatively high voltage, may be provided from package componentinto package substrate′. The voltage input path from package componentinto IVR dieis illustrated by arrowin accordance with some embodiments.

Arrowsillustrate the voltage conduction path of the output voltage from IVR dieto powered devices, which include package componentsin accordance with some embodiments. The output voltage(s), which may be 3.3V, 1.2V, 0.9V, and 0.75V, and/or the like are conducted through redistribution linesto RC component, and further conducted to solder regionsand redistribution lines. Through through-viasand/or TSVsin device dies, the output voltages are further conducted to redistribution lines, and to package components.

In accordance with some embodiments, due to the insertion of RC componentinto the path between IVR dieand package components, the transient overshoot of the IVR output is reduced. For example,illustrates the output voltages of IVRs as a function of time. Lineillustrates the voltage transient before it reaches stable state when the IVR dieis not connected to RC component. Lineillustrates the voltage transient before it reaches stable state when the IVR dieis connected to RC component. It is observed the transient overshoot represented by linehas much higher magnitude than the transient overshoot represented by line, and lasts longer. The transient overshoot may cause the damage to the powered devices and thus cause serious reliability issues. Accordingly, the package in accordance with the embodiments of the present disclosure is more reliable.

In addition, as shown in, inductors LPand LPrepresent the parasitic inductance of the metal lines in the conduction paths(). By inserting the RC componentin the path between the IVR dieand package component(which is represented as the load resistance Rload), the parasitic inductance is also reduced.

illustrates an amplified view of a portion of the packagein, wherein the illustrated portion includes the IVR dieand the RC component. The redistribution linesare shown as including metal lines and metal vias interconnecting the metal lines.

illustrates a cross-sectional view of packagein accordance with alternative embodiments of the present disclosure. Unless specified otherwise, the materials, the structures, and the formation processes of the components in these embodiments (and the subsequent embodiments shown in) are essentially the same as the like components denoted by like reference numerals in the preceding embodiments. The details regarding the materials, the structures, and the formation processes provided in each of the embodiments throughout the description may be applied to any other embodiment whenever applicable, and may not be repeated.

In, IVR die, instead of located in dielectric core, is located in redistribution structure, and may be, or may not be, in contact with dielectric layers. The details in the placement of IVR diemay be essentially the same as the placement of RC componentas shown in, and the details are not repeated herein. IVR diemay be encapsulated in encapsulant, or may tightly fit in the opening in redistribution structure, and thus in physical contact with dielectric layers. IVR diemay or may not be in physical contact with redistribution lines.

RC componentis located in redistribution structure. In accordance with some embodiments, after the formation of redistribution structure, an opening is formed in redistribution structure, and RC componentis placed in the opening, and flip-bonded to redistribution lines. An encapsulant such as an underfill(not shown in, refer to) is then dispensed to encapsulate RC component. Underfillmay have some portion directly over RC component, as shown in, or may be removed from the regions directly over RC component.

As shown by the voltage conduction paths, the RC componentis also inserted into the path for conducting the voltage output from IVR dieto package component, and hence may reduce the transient overshoot.

illustrates an amplified view of a portion of the packagein, wherein the illustrated portion includes the RC component. The redistribution linesare shown as including metal lines and metal vias interconnecting the metal lines.