Methods and Apparatus to Drive Inductor-Capacitor (lc) Circuitry with Subharmonic Injection

This description relates generally to driving inductor-capacitor (LC) circuitry and, more particularly, to methods and apparatus to drive LC circuitry with subharmonic injection.

As electronics continue to become increasingly complex, circuitry has become capable of operating at high speeds with decreasing package sizes. Transmission speeds of communication systems continue to increase as electronics continue to advance. Thus, transmitter circuitry has to accurately generate transmission signals at high speeds based on clock circuitry that generates accurate, high-frequency clock signals. The clock circuitry generates a high-frequency clock signal by multiplying a relatively lower frequency clock signal. The high-frequency clock signal allows the transmitter circuitry to accurately generate transmissions at high frequencies.

For methods and apparatus to drive LC circuitry with subharmonic injection, an example apparatus includes first frequency multiplier circuitry having a terminal; and second frequency multiplier circuitry including: first current source circuitry having a terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the terminal of the first current source circuitry, the control terminal of the first transistor coupled to the terminal of the first frequency multiplier circuitry; second current source circuitry having a terminal; a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the terminal of the second current source circuitry; an inductor having a first terminal and a second terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the inductor; and an amplifier having a terminal coupled to the second terminal of the first transistor, the second terminal of the second transistor, the second terminal of the inductor, and the second terminal of the capacitor. Other examples are described.

For methods and apparatus to drive LC circuitry with subharmonic injection, an example apparatus includes first frequency multiplier circuitry having a terminal; and second frequency multiplier circuitry having a first terminal and a second terminal, the first terminal of the second frequency multiplier circuitry coupled to the terminal of the first frequency multiplier circuitry, the second frequency multiplier circuitry configured to generate a clock signal having a duty cycle; duty cycle estimation circuitry having a first terminal and a second terminal, the duty cycle estimation circuitry configured to estimate the duty cycle of the clock signal; and duty cycle correction circuitry having a first terminal, a second terminal, and a third terminal, the first terminal of the duty cycle correction circuitry coupled to the second terminal of the second frequency multiplier circuitry, the second terminal of the duty cycle correction circuitry coupled to the first terminal of the duty cycle estimation circuitry, the third terminal of the duty cycle correction circuitry is coupled to the second terminal of the duty cycle estimation circuitry, the duty cycle correction circuitry configured to adjust the duty cycle of the clock signal responsive to the estimate of the duty cycle from the duty cycle estimation circuitry. Other examples are described.

For methods and apparatus to drive LC circuitry with subharmonic injection, an example apparatus includes clock multiplier circuitry configured to multiply a frequency of a first clock signal to generate a second clock signal; and injection multiplication circuitry coupled to the clock multiplier circuitry, the injection multiplication circuitry configured to: generate an injection current responsive to amplitudes of the second clock signal; modify a resonant frequency of the injection multiplication circuitry by supplying the injection current; and generate a third clock signal having a frequency set by the resonant frequency. Other examples are described.

The drawings are not necessarily to scale. Generally, the same reference numbers in the drawing(s) and this description refer to the same or similar (functionally and/or structurally) features and/or parts. Although the drawings show regions with clean lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, the boundaries or lines may be unobservable, blended or irregular.

As electronics continue to become increasingly complex, circuitry has become capable of operating at high speeds with decreasing package sizes. Transmission speeds of communication systems continue to increase as electronics continue to advance. Thus, transmitter circuitry has to accurately generate transmission signals at high speeds using clock circuitry that generates accurate, high-frequency clock signals. Some clock circuitry generates a high-frequency clock signal by multiplying a relatively lower frequency clock signal. The high-frequency clock signal allows the transmitter circuitry to accurately generate transmissions at high frequencies.

In some systems, such as communication systems, phase errors of the clock signal from the clock circuitry may result in transmission errors. In other systems, such as radar systems, phase errors of the clock signal from the clock circuitry may result in detection errors. As transmission speeds continue to increase, some clock circuitry designs use increasingly complex circuitry to reduce phase errors.

One method of implementing clock circuitry is to use a phase locked loop (PLL) design. PLL clock circuitry includes phase frequency detection (PFD) circuitry, charge pump circuitry, low pass filter circuitry, a voltage-controlled oscillator (VCO), and divider circuitry. The PFD circuitry receives an input clock signal and a frequency divided output clock signal from the divider circuitry. The frequency divided clock signal is proportional to the output clock signal. The PFD circuitry compares phases of the input clock signal to the divided output clock signal and generates an output signal representing the comparison. The low pass filter circuitry uses the charge pump circuitry to generate a control voltage responsive to the output of the PFD circuitry. The VCO generates the output clock signal proportional to the control voltage. However, the low pass filter circuitry generates the control voltage with relatively high noise, which the VCO then multiplies to generate the output clock signal. Substantially increasing the size of the charge pump, which increases the system on chip (SoC) size and cost, reduces the noise of the low pass filter circuitry and the VCO.

Another method of implementing clock circuitry is using a harmonic multiplication design. In a first implementation, harmonic multiplication circuitry uses harmonic multiplication to multiply the frequency of an input clock signal. In such designs, the input clock signal drives transistors (also referred to as injection circuitry) to inject a current into inductor-capacitor (LC) circuitry. Such a method of current injection is referred to as an injection lock. The LC circuitry has a resonant frequency specific to the target frequency of the output clock signal. However, capacitances of the transistors, which inject the current, modify the resonant frequency of the LC circuitry every time current is injected into the LC circuitry. However, when using the injection circuitry and the LC circuitry to multiply the frequency of an input clock signal, the injection circuitry injects current at the frequency of the input clock signal resulting in cycles of the output clock signal with no current injection. Such a method of injecting current at a frequency of the input clock signal to generate an output clock signal having a frequency that is a multiple of the input clock signal is referred to as subharmonic injection. In designs that use subharmonic injection, amplitudes of the output clock signal have a varying amplitude responsive to the lack of current injection at every cycle of the output clock signal. The variations in the amplitudes of the clock signal increase the phase errors of the output clock signal.

In harmonic multiplication designs, harmonic filter circuitry may be used to multiply the input clock signal by a second multiple. The harmonic filter generates a clock signal that has a frequency that is approximately equal to the desired frequency of the output clock signal. The injection circuitry uses the multiplied input clock signal from the harmonic filter circuitry to inject current at each cycle of the output clock signal. In this implementation, the frequency of the output clock signal is approximately equal to the frequency of the multiplied input clock signal from the harmonic filter circuitry. However, the harmonic filter circuitry generates noise due to using harmonic multiplication to increase the frequency by the second multiple. The injection circuitry generates the output clock signal having phase errors due to the noise from the harmonic filter circuitry.

Examples described herein include methods and apparatus to drive LC circuitry with subharmonic injection. In some described examples, clock circuitry includes clock multiplier circuitry, injection multiplication circuitry, duty cycle correction circuitry, and duty cycle estimation circuitry. The clock multiplier circuitry multiplies a clock signal by a first multiple. The injection multiplication circuitry uses current source circuitry, current injection circuitry, and LC circuitry to multiply the multiplied clock signal from the clock multiplier circuitry. The current source circuitry reduces variations in amplitudes of a clock signal by supplying a current that compensates the LC circuitry for dampening. The current injection circuitry injects current into the LC circuitry responsive to pulses of the multiplied clock signal from the clock multiplier circuitry. Advantageously, the current injection circuitry reduces variations in the amplitude of an output clock signal from the injection multiplication circuitry.

The duty cycle correction circuitry and the duty cycle estimation circuitry further reduce phase errors between cycles of the output clock signal from the injection multiplication circuitry. The duty cycle correction circuitry adjusts rising and falling edges of cycles of the output clock signal to decrease variations between duty cycles of the output clock signal. The duty cycle estimation circuitry adjusts the timing of the rising and falling edges of the duty cycle correction circuitry responsive to a detection of variations in duty cycles. Advantageously, the duty cycle correction circuitry and the duty cycle estimation circuitry reduce variations between duty cycles of the output clock signal from the injection multiplication circuitry. Advantageously, reducing variations between the duty cycles of the output clock signal decreases phase errors.

is a block diagram of an example communication system. In the example of, the communication system includes an antenna, analog front end (AFE) circuitry, signal processing circuitry, and clock circuitry. The AFE circuitryoffurther includes example transmitter circuitryand example receiver circuitry. The clock circuitry offurther includes example oscillator circuitry, example clock multiplier circuitry, example injection multiplication circuitry, example duty cycle correction circuitry, and example duty cycle estimation circuitry. In some examples, the communication systemis communicatively coupled to another instance of the communication system. In such examples, the communication systemtransmits and receives data. In another example, the transmitter circuitryis communicatively coupled to the receiver circuitry. In such examples, the communication systemis a radar system.

The antennahas a terminal coupled to the AFE circuitry. The antennamay be communicatively coupled to another communication system, which exchanges electromagnetic signals with the communication systemusing the antenna. In some examples, a connector, such as a coaxal cable, couples the antennato the AFE circuitry. In such examples, the connector allows the antennaand the AFE circuitryto be located at separate locations.

The AFE circuitryhas a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the AFE circuitryis coupled to the antenna. The second and third terminals of the AFE circuitryare coupled to the signal processing circuitry. The fourth terminal of the AFE circuitryis coupled to the clock circuitry. In some examples, the communication systemmay be modified to include additional components in the AFE circuitry. For example, the AFE circuitrycan include one or both of the signal processing circuitryand the clock circuitry. The signal processing circuitryhas a first terminal and a second terminal coupled to the AFE circuitry. The signal processing circuitryis communicatively coupled to the AFE circuitry. The clock circuitryhas a terminal coupled to the AFE circuitry. In some examples, the clock circuitryhas an additional terminal coupled to a crystal component.

The transmitter circuitryhas a first terminal, a second terminal, and a third terminal. The first terminal of the transmitter circuitryis coupled to the antennaand the receiver circuitry. The second terminal of the transmitter circuitryis coupled to the signal processing circuitry. The third terminal of the transmitter circuitryis coupled to the clock circuitry. The receiver circuitryhas a first terminal and a second terminal. The first terminal of the receiver circuitryis coupled to the antennaand the transmitter circuitry. The second terminal of the receiver circuitryis coupled to the signal processing circuitry.

The oscillator circuitryhas a terminal coupled to the clock multiplier circuitry. In some examples, the oscillator circuitryis crystal oscillator circuitry. In such examples, the oscillator circuitryhas an additional terminal coupled to a crystal component. In other examples, the oscillator circuitry is resistor-capacitor (RC) oscillator circuitry. Alternatively, the oscillator circuitryis a different type of oscillator circuitry.

The clock multiplier circuitry(also referred to as frequency multiplier circuitry) has a first terminal and a second terminal. The first terminal of the clock multiplier circuitryis coupled to the oscillator circuitry. The second terminal of the clock multiplier circuitryis coupled to the injection multiplication circuitry. An example implementation of the clock multiplier circuitryis illustrated and described in connection with, below.

The injection multiplication circuitry(also referred to as frequency multiplier circuitry) has a first terminal, a second terminal, and a third terminal. The first terminal of the injection multiplication circuitryis coupled to the clock multiplier circuitry. The second and third terminals of the injection multiplication circuitryare coupled to the duty cycle correction circuitry. Alternatively, the injection multiplication circuitrymay be directly coupled to the AFE circuitry. An example implementation of the injection multiplication circuitryis illustrated and described in connection with, below.

The duty cycle correction circuitryhas a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first and second terminals of the duty cycle correction circuitryare coupled to the injection multiplication circuitry. The third terminal of the duty cycle correction circuitryis coupled to the AFE circuitryand the duty cycle estimation circuitry. The fourth and fifth terminals of the duty cycle correction circuitryare coupled to the duty cycle estimation circuitry. An example implementation of the duty cycle correction circuitryis illustrated and described in connection with.

The duty cycle estimation circuitryhas a first terminal, a second terminal, and a third terminal. The first terminal of the duty cycle estimation circuitryis coupled to the AFE circuitryand the duty cycle correction circuitry. The second and third terminals of the duty cycle estimation circuitryare coupled to the duty cycle correction circuitry. An example implementation of the duty cycle estimation circuitryis illustrated and described in connection with.

In example operation, the oscillator circuitrygenerates a first clock signal having a first frequency (F). The clock multiplier circuitryreceives the first clock signal from the oscillator circuitry. The clock multiplier circuitrygenerates a second clock signal having a second frequency (2F) by multiplying the first frequency of the first clock signal. In some examples, the clock multiplier circuitrygenerates the second clock signal by multiplying the first frequency of the first clock signal by two. Example operations of the clock multiplier circuitryare further described in connection with.

The injection multiplication circuitryreceives the second clock signal from the clock multiplier circuitry. The injection multiplication circuitrygenerates a third clock signal having a third frequency (6F) by multiplying the second frequency of the second clock signal. In some examples, the injection multiplication circuitrygenerates the third clock signal by multiplying the second frequency of the second clock signal by three. In the example of, the injection multiplication circuitryuses currents of the second clock signal to adjust a resonant frequency, which reduces phase errors. Example operations of the injection multiplication circuitryare further described in connection with, below.

In example operations, the duty cycle correction circuitryreceives the third clock signal from the injection multiplication circuitry. The duty cycle correction circuitrycorrects the third clock signal for duty cycle variations between multiples of the first frequency. For example, when the frequency of the third clock signal is six times the frequency of the first clock signal, the duty cycle correction circuitrycorrects six duty cycles to be approximately equal to each other. The duty cycle correction circuitrymay delay rising edges of the third clock signal to correct each multiple of the first frequency for duty cycle variations. The duty cycle correction circuitrymay delay falling edges and of the third clock signal to correct each multiple of the first frequency for duty cycle variations. Example operations of the duty cycle correction circuitryare further described in connection with, below. Advantageously, the duty cycle correction circuitryreduces phase errors of the third clock signal.

In example operations, the duty cycle estimation circuitryreceives the corrected third clock signal from the duty cycle correction circuitry. The duty cycle estimation circuitrydetermines a duty cycle for each multiple of the first frequency. For example, when the third frequency of the third clock signal is six times the first frequency of the first clock signal, the duty cycle estimation circuitrydetermines duty cycles for every six cycles of the third clock signal. The duty cycle estimation circuitrygenerates voltages proportional to the duration of each of the duty cycles. The duty cycle estimation circuitryadjusts the delays of the duty cycle correction circuitryto reduce differences between the voltages of each duty cycle. Example operations of the duty cycle estimation circuitryare further described in connection with, below. Advantageously, the duty cycle estimation circuitrydetermines the delays of the duty cycle correction circuitry.

In example operations, the transmitter circuitryreceives the corrected third clock signal from the duty cycle correction circuitry. The transmitter circuitrytransmits a signal using the corrected third clock signal and the antenna. In some examples, such as in radar systems, the transmitter circuitrytransmits the corrected clock signal. In such examples, the receiver circuitrydetects objects responsive to variations in the transmitted signal. Advantageously, reducing the phase errors and harmonics of the clock signal increases the accuracy of the transmitted signal.

is a schematic diagram of example clock multiplier circuitry, which is an example implementation of the clock multiplier circuitryof, and example injection multiplication circuitry, which is an example implementation of the injection multiplication circuitry. The clock multiplier circuitryofincludes a first example inverter, a second example inverter, a third example inverter, a fourth example inverter, and an example logic device. The injection multiplication circuitryofincludes example current injection circuitry, first example inductor-capacitor (LC) circuitry, second example LC circuitry, first example current source circuitry, a first example transistor, a second example transistor, and an example amplifier. The current injection circuitryofincludes second example current source circuitry, a third example transistor, and a fourth example transistor. The LC circuitryincludes a first example capacitorand a first example inductor. The LC circuitryincludes a second example capacitorand a second example inductor.

The clock multiplier circuitry(also referred to as frequency multiplier circuitry) has a first terminal, a second terminal, and a third terminal. The first terminal of the clock multiplier circuitrymay be coupled to oscillator circuitry (e.g., oscillator circuitryof), which supplies a clock signal (e.g., CLK(F)). The second and third terminals of the clock multiplier circuitryare coupled to the injection multiplication circuitry.

The injection multiplication circuitry(also referred to as frequency multiplier circuitry) has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first and second terminals of the injection multiplication circuitryare coupled to the clock multiplier circuitry. The third, fourth, and fifth terminals of the injection multiplication circuitrymay be coupled to the duty cycle correction circuitryof. In some examples, the third and fourth terminals of the injection multiplication circuitryare coupled to the AFE circuitryof. In some examples, the fifth terminal of the injection multiplication circuitryis coupled to register circuitry, which supply a first trim code (C) and a second trim code (C).

The inverterhas a first terminal and a second terminal. The first terminal of the inverteris coupled to the logic deviceand may be coupled to the oscillator circuitry. The second terminal of the inverteris coupled to the inverter. The inverterhas a first terminal and a second terminal. The first terminal of the inverteris coupled to the inverter. The second terminal of the inverteris coupled to the inverter. The inverterhas a first terminal and a second terminal. The first terminal of the inverteris coupled to the inverter. The second terminal of the inverteris coupled to the inverter. The inverterhas a first terminal and a second terminal. The first terminal of the inverteris coupled to the inverter. The second terminal of the inverteris coupled to the logic device.

In the example of, the inverters,,,have a propagation delay. The inverters,,,are structured as delay circuitry, which delays a clock signal from the oscillator circuitry. In some examples, the clock multiplier circuitrymay be modified to remove or replace the inverters,,,with alternative delay circuitry.

The logic devicehas a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the logic deviceis coupled to the inverterand may be coupled to the oscillator circuitry, which supplies the clock signal. The second terminal of the logic deviceis coupled to the inverter. The third and fourth terminals of the logic deviceare coupled to the injection multiplication circuitry. In the example of, the logic deviceis an exclusive OR (XOR) gate. In other examples, the clock multiplier circuitrymay be modified to implement another type of combinational logic. In the example of, the logic devicehas a differential output coupled to the injection multiplication circuitry. Alternatively, the clock multiplier circuitrymay be modified to have the logic devicehave a single ended output. In such examples, the clock multiplier circuitrymay further include single ended to differential converter circuitry.

The current injection circuitryhas a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the current injection circuitryare coupled to the clock multiplier circuitry. The third terminal of the current injection circuitryis coupled to the LC circuitry, the transistors,, and the amplifier. The fourth terminal of the current injection circuitryis coupled to the LC circuitry, the transistors,, and the amplifier.

The LC circuitry(e.g., also referred to as LC tank circuitry) has a first terminal and a second terminal. The first terminal of the LC circuitryis coupled to the current injection circuitry, the transistors,, and the amplifier. The second terminal of the LC circuitryis coupled to a common terminal, which supplies a common potential (e.g., ground).

The LC circuitryhas a first terminal and a second terminal. The first terminal of the LC circuitryis coupled to the current injection circuitry, the transistors,, and the amplifier. The second terminal of the LC circuitryis coupled to the common terminal, which supplies the common potential.

The current source circuitryhas a first terminal and a second terminal. The first terminal of the current source circuitryis coupled to a supply terminal, which supplies a supply voltage (V). The second terminal of the current source circuitryis coupled to the transistors,.

The transistorhas a first terminal, a second terminal, and a control terminal. The first terminal of the transistoris coupled to the current source circuitryand the transistor. The second terminal of the transistoris coupled to the current injection circuitry, the LC circuitry, the transistor, and the amplifier. The control terminal of the transistoris coupled to the current injection circuitry, the LC circuitry, the transistor, and the amplifier. In the example of, the transistoris an n-channel metal-oxide semiconductor field-effect transistor (MOSFET). Alternatively, with slight modifications the transistormay be an n-channel junction field effect transistor (JFET), an n-channel field-effect transistor (FET), an n-channel insulated-gate bipolar transistor (IGBT), an NPN bipolar junction transistor (BJT) or, with slight modifications, a p-type equivalent device.

The transistorhas a first terminal, a second terminal, and a control terminal. The first terminal of the transistoris coupled to the current source circuitryand the transistor. The second terminal of the transistoris coupled to the current injection circuitry, the LC circuitry, the transistor, and the amplifier. The control terminal of the transistoris coupled to the current injection circuitry, the LC circuitry, the transistor, and the amplifier. In the example of, the transistoris an n-channel MOSFET. Alternatively, with slight modifications the transistormay be an n-channel JFET, an n-channel FET, an n-channel IGBT, an NPN BJT or, with slight modifications, a p-type equivalent device.

The amplifierhas a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the amplifieris coupled to the current injection circuitry, the LC circuitry, and the transistors,. The second terminal of the amplifieris coupled to the current injection circuitry, the LC circuitry, and the transistors,. The third and fourth terminals of the amplifiermay be coupled to the duty cycle correction circuitry. Alternatively, the third and fourth terminals of the amplifiermay be directly coupled to the AFE circuitry.

The current source circuitryhas a first terminal and a second terminal. The first terminal of the current source circuitryis coupled to the supply terminal, which supplies the supply voltage. The second terminal of the current source circuitryis coupled to the transistors,.

The transistorhas a first terminal, a second terminal, and a control terminal. The first terminal of the transistoris coupled to the current source circuitryand the transistor. The second terminal of the transistoris coupled to the LC circuitry, the transistors,, and the amplifier. The control terminal of the transistoris coupled to the clock multiplier circuitry. In the example of, the transistoris an n-channel MOSFET. Alternatively, with slight modifications the transistormay be an n-channel JFET, an n-channel FET, an n-channel IGBT, an NPN BJT or, with slight modifications, a p-type equivalent device.

The transistorhas a first terminal, a second terminal, and a control terminal. The first terminal of the transistoris coupled to the current source circuitryand the transistor. The second terminal of the transistoris coupled to the LC circuitry, the transistors,, and the amplifier. The control terminal of the transistoris coupled to the clock multiplier circuitry. In the example of, the transistoris an n-channel MOSFET. Alternatively, with slight modifications the transistormay be an n-channel JFET, an n-channel FET, an n-channel IGBT, an NPN BJT or, with slight modifications, a p-type equivalent device.

The capacitorhas a first terminal and a second terminal. The first terminal of the capacitoris coupled to the current injection circuitry, the transistors,, the amplifier, and the inductor. The second terminal of the capacitoris coupled to the common terminal, which supplies the common potential. The capacitorhas a capacitance. In some examples, the capacitorhas trim terminals coupled to the duty cycle correction circuitry. In such examples, the capacitance of the capacitoris set by a first trim value (TRIM(C)) at the trim terminals. Also in some examples, the capacitorhas a bias terminal coupled to the duty cycle correction circuitry. In such examples, the capacitormay be referred to as a varactor, which has a capacitance that varies with a voltage across the capacitor. Also, when the capacitoris a varactor, the duty cycle correction circuitrysets the bias terminal of the capacitorto a first bias voltage (V) to tune a resonant frequency of the LC circuitry. Example operations to set the trim code and the bias voltage of the capacitorare further described below.

The inductorhas a first terminal and a second terminal. The first terminal of the inductoris coupled to the current injection circuitry, the transistors,, the amplifier, and the capacitor. The second terminal of the inductoris coupled to the common terminal, which supplies the common potential. The inductorhas an inductance.

In the example of, the capacitorand the inductorare structured as an LC oscillator (e.g., also referred to as an LC tank) having a resonant frequency (f). The resonant frequency defines a frequency of an oscillation of charge between the capacitorand the inductor. The resonant frequency is proportional to the capacitance of the capacitorand the inductance of the inductor. The resonant frequency of the LC oscillator of the capacitorand the inductormay be determined using Equation (1), below. Advantageously, adjusting the trim value of the capacitorallows the duty cycle correction circuitryto adjust the resonant frequency of the LC circuitry. Advantageously, adjusting the bias voltage of the capacitorallows the duty cycle correction circuitryto adjust the resonant frequency of the LC circuitry.

The capacitorhas a first terminal and a second terminal. The first terminal of the capacitoris coupled to the current injection circuitry, the transistors,, the amplifier, and the inductor. The second terminal of the capacitoris coupled to the common terminal, which supplies the common potential. In some examples, the capacitorhas trim terminals coupled to the duty cycle correction circuitry. In such examples, the capacitance of the capacitoris set by a second trim value (TRIM(C)) at the trim terminals. In some examples, the capacitorhas a bias terminal coupled to the duty cycle correction circuitry. In such examples, the capacitormay be referred to as a varactor, which has a capacitance that varies with a voltage across the capacitor. Also, when the capacitoris a varactor, the duty cycle correction circuitrysets the bias terminal of the capacitorto a second bias voltage (V) to tune the LC circuitry. Example operations to set the trim code and the bias voltage of the capacitorare further described below.

The inductorhas a first terminal and a second terminal. The first terminal of the inductoris coupled to the current injection circuitry, the transistors,, the amplifier, and the capacitor. The second terminal of the inductoris coupled to the common terminal, which supplies the common potential. The inductorhas an inductance.

In the example of, the capacitorand the inductorare structured as an LC oscillator having a resonant frequency (f). The resonant frequency defines a frequency of an oscillation of charge between the capacitorand the inductor. The resonant frequency is proportional to the capacitance of the capacitorand the inductance of the inductor. The resonant frequency of the LC oscillator of the capacitorand the inductormay be determined using Equation (1), above. Advantageously, adjusting the trim value of the capacitorallows the duty cycle correction circuitryto adjust the resonant frequency of the LC circuitry. Advantageously, adjusting the bias voltage of the capacitorallows the duty cycle correction circuitryto adjust the resonant frequency of the LC circuitry.