Front End Architecture with Converged 2g and 5G Broadband

This application claims priority under 35 U.S.C. § 119 (e) to U.S. Provisional Patent Application 63/653,269, titled FRONT END ARCHITECTURE WITH CONVERSED 2G AND 5G BROADBAND, filed on May 30, 2024, and hereby incorporated in its entirety for all purposes.

At least one example in accordance with the present disclosure relates generally to transmission modules for 2G and 5G compatible telecommunication systems.

Telecommunication standards are evolving over time. Existing standards for cellular data transmission include 2G, which is being phased out, and 5G, which is being phased in. Old devices may transmit using the 2Gstandard, and new devices may transmit using the 5G standard, amongst others (e.g., 3G, 4G, etc.).

According to at least one aspect of the present disclosure, a front end module (FEM) is presented, the front end module configured to provide first and second signals conforming to different standards in similar frequency bands, the front end module including a first input; a second input; a first balun coupled to the first input and the second input; a second balun coupled to the first balun and configured to convert a double ended signal into a single ended signal; a filter section coupled to the second balun and configured to selectively filter one or more components of the single ended signal; and an output coupled to the filter section and configured to receive the single ended signal.

In some examples, the filter section includes a first node coupled to the second balun, and a second node coupled to the output, and further includes a parallel combination of a first switchable capacitor and a first inductor coupled between the first node and the second node, wherein the first switchable capacitor is configured to selectively couple or decouple from at least one of the first node or second node based on whether the front end module is providing a 2G or 5G signal. In some examples, the filter section further includes a low impedance switch coupled between the first node and a reference node, and a second switchable capacitor coupled between the first node and the reference node, wherein the low impedance switch is configured to selectively be open or closed based on whether the front end module is providing a 2G or 5G signal, and the second switchable capacitor is configured to selectively be coupled to the first node based on whether the front end module is providing a 2G or 5G signal.

In some examples, the filter section further includes a series combination of a capacitor and an inductor coupled between the low impedance switch and the reference node. In some examples, the filter section further includes a second inductor coupled between the second switchable capacitor and the reference node, and a capacitor coupled in parallel with the second switchable capacitor between the first node and the second inductor. In some examples, the parallel combination further includes second switchable capacitor. In some examples, the parallel combination further includes a second inductor. In some examples, the filter section further includes a series combination of the second inductor and a second switchable capacitor coupled between the first node and a reference node, wherein the second switchable capacitor is configured to selectively couple or decouple to the reference node based on whether the front end module is providing a 2G or 5G signal. In some examples, the filter section further includes a switch and an inductor coupled in series between the first node and the second node. In some examples, the FEM further comprises a first amplifier coupled between the first input and a first winding of the first balun and configured to provide an output signal to the first balun; and a capacitor coupled between the second input and a reference node.

In some examples, the FEM further comprises a first amplifier coupled to a first end of a second winding of the first balun and configured to provide a first output signal to a first end of a first winding of the second balun; a second amplifier coupled to a second end of the second winding of the first balun and configured to provide a second output signal to a second end of the first winding of the second balun. In some examples, the FEM further comprises a first capacitor coupled between the first end of the first winding of the second balun and a reference node; and a second capacitor coupled between the second end of the first winding of the second balun and the reference node. In some examples, the FEM further comprises a series combination of an inductor and a capacitor coupled between an output of the first amplifier and an output of the second amplifier. In some examples, the second balun includes a first winding and a second winding, the first winding having a tap located between a first end of the first winding and a second end of the first winding. In some examples, the FEM further comprises a first capacitor coupled to the tap and to a first inductor; a resistor coupled to the first inductor and a reference node; a second inductor coupled to the first tap; a second capacitor coupled to the second inductor and to a reference node; and a voltage node coupled between the second capacitor and the second inductor and configured to provide a voltage.

In some examples, the FEM further comprises one or more capacitors coupled between a second end of the second winding and a reference node, wherein the filter section is coupled to a first end of the second winding. In some examples, the FEM further comprises a first switch coupled to the filter section; and a second switch coupled to the first switch and to the output, wherein the first switch has one input and a plurality of outputs, and the second switch has one output and a plurality of inputs, wherein each output of the plurality of outputs is coupled via respective path to a respective input of the plurality of inputs. In some examples, one or more of the respective paths between the plurality of inputs and the plurality of outputs include a respective filter. In some examples, at least one respective path between the plurality of outputs and the plurality of inputs includes a capacitor coupled to a reference node.

In some examples, at least one respective path between the plurality of outputs and the plurality of inputs includes a series combination of a first capacitor and a parallel combination of a second capacitor and an inductor. In some examples, the FEM further comprises an output filter coupled between the second switch and the output, wherein the output filter includes a first node coupled to the output of the second switch, and a second node coupled to the output, a parallel combination of a switchable capacitor and an inductor coupled between the first node and the second node, the switchable capacitor being configured to selectively couple or decouple from one of the first node or second node based on whether the front end module is providing a 2G or a 5G signal. In some examples, the output filter further includes a series combination of a capacitor and an inductor coupled between the second node and a reference node.

In some examples, the second balun includes four or more layers, including a first layer, a second layer, a third layer, and a fourth layer, wherein the first layer is coupled to the third layer via a first connection and a second connection, and the second layer is coupled to the fourth layer via a third connection, wherein a tap of the balun is coupled to the third layer. In some examples, the first layer of the second balun includes a first section and a second section, the first section having a first input and the first connection, and the second section having a second input and the second connection. In some examples, an inductor is coupled to the tap and routed around the first input and the second input with at least one of odd symmetry or even symmetry. In some examples, the second layer includes a first output and the third connection, and the fourth layer includes a second output and the third connection.

Telecommunications are steadily migrating toward the use of 5G (the fifth generation technology standard for cellular networks), and moving away from earlier generations such as 4G or 2G. However, a significant portion of the world still relies on 2G for their communications needs. In some estimations, even more than 80% of modern telecommunications rely on 2G. In some examples, the slowness of adopting 5G and moving away from 2G may be due to lack of 5G infrastructure, lack of cheap 5G devices, and so forth.

Aspects of the present disclosure relate to a front-end architecture (FEA) that supports both 2G and 5G efficiently using a power amplifier, or, additionally, any FEA that supports both an older standard (like 2G), and a newer standard (like 5G or 6G). Traditionally, FEAs and front-end modules (FEMs) have used separate systems for handling 2G and 5G signals. For example, a traditional system may have a chip dedicated to 5G signals and a chip dedicated to 2G signals, each chip having its own respective transmit (TX) and receive (RX) paths, its own voltage rails for supplying power, and even its own antenna for receiving and transmitting signals. This results in substantial excess materials being used in traditional designs (as the 2G and 5G architectures may both require their own power amplifiers, low noise amplifiers, filters, switches, and so forth). However, converged architectures (that support both 2G and 5G without using excess materials) face substantial implementation barriers. Among other things, 2G and 5G have significantly different power requirements, with 2G generally having higher power requirements than 5G. Furthermore, 2G and 5G have different linearity requirements as well, making designing output matching networks (OMNs) for 2G and 5G systems of all types difficult, especially if the OMNs must have wide frequency and power ranges. Additionally, power added efficiency (PAE) varies between 2G and 5G systems, and can make designing converged 2G and 5G architectures difficult as PAE may be poor for a converged system (or an unconverged system) in one mode (e.g., 5G mode), and good in the other mode (e.g., 2G mode). Poor PAE means the device housing the FEA may heat up substantially, posing a difficulty to handling and possibly damaging circuit components if the FEA overheats.

Aspects of this disclosure relate to a converged 2G and 5G FEA (and/or a converged FEA using any older and any newer standard) that addresses and mitigates the many problems identified above. In some examples, converged FEAs discussed herein use push-pull power amplifiers and OMNs to drive both 2G and 5G signals. In some examples, PAE is improved by 3-4% over traditional solutions, and the low-bandwidth modes for the FEA may have 32% fractional bandwidth (that is, the bandwidth of the FEA divided by its center frequency may correspond to 32%).

illustrates a first topologyfor an FEA. The first topologyincludes a first input, a second input, a first amplifier, a first capacitor, a first winding, a second winding, a second amplifier, a second capacitor, a third amplifier, a third capacitor, a third winding, a fourth winding, a fourth capacitor, a fifth capacitor, a filter section, a band switch, a first filter, a second filter, an antenna switching module(“ASM”), an antenna switching module filter(“ASM filter”), an output, and a reference node.

The inputis coupled to an input of the first amplifier. An output of the first amplifieris coupled to a first end of the first winding. A second end of the first windingis coupled to the second inputand to a first end of the first capacitor. A second end of the first capacitoris coupled to the reference node.

A first end of the second windingis coupled to an input of the second amplifier, and a second end of the second windingis coupled to an input of the third amplifier. An output of the first amplifieris coupled to a first end of the second capacitorand to a first end of the third winding. A second end of the second capacitoris coupled to the reference node. An output of the third amplifieris coupled to a second end of the third windingand to a first end of the third capacitor. A second end of the third capacitoris coupled to the reference node.

A first end of the fourth windingis coupled to the filter section. A second end of the fourth windingis coupled to a first end of the fourth capacitorand a first end of the fifth capacitor. Respective second ends of the fourth and fifth capacitors,are coupled to the reference node. The filter sectionis further coupled to an input terminal of the band switch. Output terminals of the band switchare coupled to respective conducting paths to respective input terminals of the ASM. In some examples, the conducting paths may have additional circuitry interposed between the output terminals of the band switchand the input terminals of the ASM. In some examples, the first filteris coupled between a first output terminal of the band switchand a first input terminal of the ASM. In some examples, the second filteris coupled between a second output terminal of the band switchand the second input terminal of the ASM. An output terminal of the ASMis coupled to the ASM filter. The ASM filteris coupled to the output.

The first inputmay be configured to receive an input signal, such as a voltage or current, and provide the input signal to the first amplifier. The input signal may vary with time. The first amplifiermay receive the input signal and amplify and/or attenuate the input signal or components (e.g., particular frequencies) of the input signal. The first amplifiermay provide the input signal to the first winding(e.g., after altering the input signal).

The first windingmay be electromagnetically coupled to the second winding. For example, a current through the first windingmay induce a current through the second windingaccording to the principals of magnetic induction. The input signal provided to the first windingmay therefore induce a second signal (e.g., a current) through the second winding. The first windingmay also provide the input signal, or another signal, to the first capacitorand the second input. The first windingmay be an inductor, and may have the same number of turns, fewer turns, or more turns that the second winding. In some examples, the first windingmay be part of a balun. In some examples, the first windingand second windingmay constitute a balun, for example, a single-to-double-ended balun.

The second inputmay be coupled to a voltage or other circuit element. For example, the second inputmay be configured to provide a low voltage or a high voltage. In some examples, the second inputprovides a constant voltage, and in other examples, the second inputprovides a time-varying voltage.

The first capacitormay be configured to provide a signal to the reference node. The reference nodemay be configured to provide a reference voltage (e.g., a voltage of zero or a voltage relative to which the other voltages in the first topologyare measured). In some examples, the reference nodemay be configured to provide a lowest voltage in the first topology. The first capacitormay be configured to route high frequency components of a given signal (such as the input signal or any signal induced on the first winding) to the reference node.

The second windingmay be an inductor and/or may be configured as a balun or part of a balun, for example, with the first winding. The second windingmay be configured to provide all and/or part of the second signal to the second amplifierand/or third amplifier.

The second amplifiermay be configured to amplify and/or attenuate some or all of the portions of the second signal the second amplifierreceives from the second winding. The second amplifiermay be configured to provide the second signal (as altered) to the second capacitorand/or the third winding.

The third amplifiermay be configured to amplify and/or attenuate some or all of the portions of the second signal the third amplifierreceives from the second winding. The third amplifiermay be configured to provide the second signal (as altered) to the third capacitorand/or the third winding.

The second amplifierand third amplifiermay be power amplifiers. The second and third amplifiers,may be configured to operate as push-pull amplifiers. In some examples, the second and third amplifier,may alternatively drive a signal. For example, the second amplifiermay provide an output based on the second signal to the second capacitorand/or third windingwhile the third amplifieris not providing an output. Then, when the second amplifieris no longer providing an output, the third amplifiermay provide an output to the third capacitorand/or third winding.

The second capacitormay be configured to block DC signals from the output node of the second amplifierto the reference node. The third capacitormay be configured to block DC signals from the output node of the third amplifierto the reference node.

The third windingmay be electromagnetically coupled to the fourth winding. In some examples, the third windingand fourth windingmay be configured to operate as a balun, for example, a double-to-single-ended balun. The third windingmay induce a third signal on the fourth winding.

The fourth windingmay provide the third signal to the fourth capacitor, fifth capacitor, and/or filter section.

The fourth capacitorand second capacitormay be configured to provide an improved Q-factor to the first topology, and may route portions of the third signal to the reference node. That is, the parallel combination of two smaller capacitors may provide a better Q factor than a single capacitor of equal capacitance.

The filter sectionmay filter the third signal in various ways. The function of the filter sectionwill be discussed in greater detail below. Once the filter sectionhas filtered the third signal, the filter sectionmay provide the third signal to the band switch.

The band switchmay have a single input terminal and numerous output terminals. The band switchmay be configured to couple the single input terminal to one or more of the numerous output terminals (but may, in some examples, couple the input terminal to only one output terminal at a time). The output terminal to which the input terminal is coupled may depend on the nature of the third signal and the desired qualities of the output signal.

The first filtermay be a filter, such as a bandpass, high pass, low pass, notch, or other type of filter. The first filtermay be a duplexer. The second filtermay be a filter, such as a bandpass, high pass, low pass, notch, or other type of filter. The second filtermay be a duplexer.

The ASMmay have numerous input terminals and a single output terminal. The ASMmay be configured to couple the single output terminal to one or more of the numerous input terminals (and may, in some examples, couple the output terminal to only one input terminal at a time). The input terminal to which the output terminal is coupled may depend on which respective output terminal of the band switchis coupled to the input terminal of the band switch. The ASMmay route the third signal to the ASM filter.

The ASM filtermay be a filter, such as a bandpass, high pass, low pass, notch, or other type of filter. The ASM filtermay filter the third signal and provide an output signal, based on the third signal, to the output. The ASM filterwill be discussed in greater detail, below.

The outputmay be coupled to an antenna and/or may be configured to provide a signal (such as a transmit signal) wirelessly or via a wired connection to other devices.

illustrates a second topologyof a FEA according to an example. The second topologyis identical to the first topologywith a handful of exceptions.illustrates one version of the filter sectionwhich may be used with examples of topologies disclosed herein, including the second topology.

The second topologyincludes the elements of the first topologyas well as a first tap capacitor, a first tap inductor, a first tap resistor, a second tap inductor, a second tap capacitor, a voltage node, and a conducting path capacitor.

The first tap capacitorand second tap inductorare coupled to a tap of the third winding. The tap of the third windingmay be located anywhere on the third winding, but, in some examples, may be a center tap located at or near the midpoint of the third inductor. The first tap inductoris coupled to the first tap capacitor. The first tap resistor is coupled to the first tap inductorand to the reference node. The second tap inductoris coupled to the second tap capacitorand to the voltage node. The second tap capacitoris coupled to the reference node.

The voltage nodemay be a low voltage node providing a voltage lower than the voltage of the reference node. The voltage nodemay provide a voltage equal to or different from the voltage of the second input.

The tap capacitors,, tap inductors,, and tap resistormay be used to tune the balun comprising the third windingand fourth windingand/or to provide harmonic impedance for said balun.

One of the conducting paths (for example, the nth and/or final conducting path) between the output terminals of the band switchand the input terminals of the ASMmay be coupled to the conducting path capacitor. The conducting path capacitormay be coupled to the reference node. The conducting path capacitormay be configured to shunt certain frequencies of signals on the nth conducting path to the reference node. In some examples, the nth conducting path and/or the conducting path to which the conducting path capacitoris coupled may be the conducting path corresponding to 2G transmissions.

illustrates a subsectionof the second topologyincluding the filter section, according to an example. The version of the filter sectionshown in the subsectionmay be appropriate for use in the second topologyor in any other topology disclosed herein.

The filter sectionincludes a first inductor, a first capacitor, a first switchable capacitor, a second switchable capacitor, a switch, a second capacitor, a second inductor, a third switchable capacitor, a third capacitor, and a third inductor. Also shown are a first nodeand a second node. The fourth windingand band switchare shown to contextualize the coupling of internal components of the filter sectionto the rest of the second topology(or any other topology herein).

A respective first end of the first inductor, first capacitor, first switchable capacitor, and second switchable capacitorare coupled to the first node. A respective second end of the first inductor, first capacitor, first switchable capacitor, and second switchable capacitorare coupled to the second node. The first nodeis coupled to the first end of the fourth winding. The second nodeis coupled to the input terminal of the band switch.

Respective first ends of the switch, third switchable capacitor, and third capacitorare coupled to the first node. A second end of the switchis coupled to the second capacitor. The second capacitoris coupled to the second inductor. The second inductoris coupled to the reference node. Respective second ends of the third capacitorand third switchable capacitorare coupled to the third inductor. The third inductoris coupled to the reference node.

The switchable capacitors,,may be switched on and/or off and may include a switch in series with the capacitor, for example. When on, the switchable capacitors,,are part of the conducting paths from the first nodeto the reference nodeand/or from the first nodeto the second node. When off, the switchable capacitors,,are not part of said conducting paths. For example, when the first and second switchable capacitors,are on, they may be coupled in parallel with the first capacitorand the first inductorbetween the first nodeand second node. When the first and second switchable capacitors,are off, they may be floating (e.g., not coupled to one or both of the first nodeand/or second node. Likewise, when the third switchable capacitoris on, it may be coupled in parallel with the third capacitorbetween the first nodeand the third inductor. When the third switchable capacitoris off, it may be floating (e.g., not coupled to one or both of the first nodeand/or third inductor).

The switchmay be a low impedance switch (e.g., a switch having a low resistance). The switchmay be configured to selectively couple and/or decouple the second capacitorfrom the first node

Referring now to a combination of, where the filter sectionof the second topologyhas the composition of the filter sectionof, said combination (which may be referred to as the second combination, for convenience, hereafter), may be configured to handle both 2G and 5G signals (e.g., transmitting 2G and 5G signals). However, depending on the band of the transmission (e.g., which band of frequencies incorporated into the 5G spectrum and/or 2G spectrum) or the mode of transmission (e.g., 2G or 5G), different switches may be closed (e.g., on) or open (e.g., off) and/or different switchable capacitors may be closed or open.

In some examples, the first switchable capacitormay be off when transmitting 2G signals, and/or on when transmitting 5G signals (e.g., in the B12, B28, and/or B71 channels). In some examples, the second switchable capacitormay be on when transmitting 2G signals and/or transmitting some 5G signals (e.g., on the B12 and/or B28 channels). In some examples, the third switchable capacitormay be on when transmitting 2G signals and/or when transmitting 5G signals (e.g., on the B12, B28, and/or B71 bands). In some examples, the switchmay be closed when transmitting 2G signals, and open when transmitting 5G signals.

illustrates a third topologyof an FEA according to an example. The third topologyis identical to the second topology, except as described below. The third topologymay incorporate the subsectionof(that is, may have a filter sectionidentical to the filter sectionof) or subsectionof(that is, may have a filter sectionidentical to the filter sectionof).