Dividing Superblocks in a Memory System

The present application for patent claims priority to U.S. Patent Application No. 63/659,230 by Smith et al., entitled “DIVIDING SUPERBLOCKS IN A MEMORY SYSTEM,” filed Jun. 12, 2024, which is assigned to the assignee hereof, and which is expressly incorporated by reference in its entirety herein.

The following relates to one or more systems for memory, including dividing superblocks in a memory system.

Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, the memory device may read (e.g., sense, detect, retrieve, determine) states from the memory cells. To store information, the memory device may write (e.g., program, set, assign) states to the memory cells.

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, not-or (NOR) and not-and (NAND) memory devices, and others. Memory cells may be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration may maintain stored logic states for extended periods of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose stored states when disconnected from an external power source.

A memory system may support the use of superblocks, which include blocks (e.g., a set of blocks) from a contiguous set of planes (e.g., each plane) of the memory system. In some cases, the memory system may perform access operations on the blocks of the superblock. In some instances, however, the memory system may be unable to perform one or more access operations on the superblock if one or more blocks of the set of blocks associated with the superblock are invalid (e.g., bad, corrupt, otherwise inaccessible). In some such cases, the memory system may refrain from using the superblock if one or more blocks of the set of blocks associated with the superblock are invalid. However, by not using such superblocks (e.g., residue superblocks) it may decrease overprovisioning associated with the memory device, decrease the overall performance of the memory system, and the like. Accordingly, a memory system configured to divide such superblocks (e.g., residue superblocks) into usable, runt superblocks may be desirable.

In accordance with examples as described herein, a memory system may be configured to generate and access usable, runt superblocks from incomplete superblocks and/or residue superblocks. For example, the memory system may determine whether a superblock includes a quantity of valid physical blocks below a threshold to use the superblock as an incomplete superblock and/or residue superblock.

A memory system may have bad physical blocks that may disrupt parallelism that can be gained by using a complete superblock. To improve performance, a memory system may be configured replace bad blocks to create as many complete superblocks as possible. The memory system may, in some examples, scan one or more physical blocks to determine which physical blocks are valid and/or invalid. The memory system may then swap an invalid block in a first superblock with a valid block from second superblock, thereby making the first superblock a complete superblock. With this swapping of blocks, some superblocks will be left with a residue of valid blocks and may be unusable as a complete superblock or an incomplete superblock. Techniques are described to repurpose these residue blocks and form smaller superblocks that are usable in some contexts.

The memory system may perform such operations to create complete superblocks having no invalid blocks. Such operations may also result in some superblocks being incomplete superblocks (e.g., with one invalid block) or a residue superblock (with two or more invalid blocks). Accordingly, the methods described herein to divide incomplete superblocks and/or residue superblocks into usable, runt superblocks (e.g., able to be accessed) may increase overprovisioning associated with the memory system, which may improve performance and reduce costs. Moreover, dividing incomplete superblocks and/or residue superblocks into usable, runt superblocks may increase or otherwise prolong the usable storage capacity of the memory system, improve a total bytes writable to the memory system, among other advantages.

In addition to applicability in memory systems as described herein, techniques for dividing incomplete superblocks and/or residue superblocks of the memory system may be generally implemented to improve the performance of various electronic devices and systems (including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and gaming). Some electronic device applications, including high-performance applications such as AI, AR, VR, and gaming, may be associated with relatively high processing requirements to satisfy user expectations. As such, increasing processing capabilities of the electronic devices by decreasing response times, improving power consumption, reducing complexity, increasing data throughput or access speeds, decreasing communication times, or increasing memory capacity or density, among other performance indicators, may improve user experience or appeal. Implementing the techniques described herein may improve the performance of electronic devices by dividing incomplete superblocks and/or residue superblocks of the memory system, which may decrease processing or latency times, improve response times, or otherwise improve user experience, among other benefits.

Features of the disclosure are illustrated and described in the context of systems, devices, and circuits. Features of the disclosure are further illustrated and described in the context of block diagrams, a process, and flowcharts.

shows an example of a systemthat supports dividing superblocks in a memory system in accordance with examples as disclosed herein. The systemincludes a host systemcoupled with a memory system. The systemmay be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle, an Internet of Things (IoT) enabled device, an embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and a processing device.

A memory systemmay be or include any device or collection of devices, where the device or collection of devices includes at least one memory array. For example, a memory systemmay be or include a Universal Flash Storage (UFS) device, an embedded Multi-Media Controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other devices.

The systemmay include a host system, which may be coupled with the memory system. In some examples, this coupling may include an interface with a host system controller, which may be an example of a controller or control component configured to cause the host systemto perform various operations in accordance with examples as described herein. The host systemmay include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host systemmay include an application configured for communicating with the memory systemor a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system), a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., peripheral component interconnect express (PCIe) controller, serial advanced technology attachment (SATA) controller). The host systemmay use the memory system, for example, to write data to the memory systemand read data from the memory system. Although one memory systemis shown in, the host systemmay be coupled with any quantity of memory systems.

The host systemmay be coupled with the memory systemvia at least one physical host interface. The host systemand the memory systemmay, in some cases, be configured to communicate via a physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory systemand the host system). Examples of a physical host interface may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fiber Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., DIMM socket interface that supports DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controllerof the host systemand a memory system controllerof the memory system. In some examples, the host systemmay be coupled with the memory system(e.g., the host system controllermay be coupled with the memory system controller) via a respective physical host interface for each memory deviceincluded in the memory system, or via a respective physical host interface for each type of memory deviceincluded in the memory system.

The memory systemmay include a memory system controllerand one or more memory devices. A memory devicemay include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although two memory devices-and-are shown in the example of, the memory systemmay include any quantity of memory devices. Further, if the memory systemincludes more than one memory device, different memory deviceswithin the memory systemmay include the same or different types of memory cells.

The memory system controllermay be coupled with and communicate with the host system(e.g., via the physical host interface) and may be an example of a controller or control component configured to cause the memory systemto perform various operations in accordance with examples as described herein. The memory system controllermay also be coupled with and communicate with memory devicesto perform operations such as reading data, writing data, erasing data, or refreshing data at a memory device—among other such operations-which may generically be referred to as access operations. In some cases, the memory system controllermay receive commands from the host systemand communicate with one or more memory devicesto execute such commands (e.g., at memory arrays within the one or more memory devices). For example, the memory system controllermay receive commands or operations from the host systemand may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory devices. In some cases, the memory system controllermay exchange data with the host systemand with one or more memory devices(e.g., in response to or otherwise in association with commands from the host system). For example, the memory system controllermay convert responses (e.g., data packets or other signals) associated with the memory devicesinto corresponding signals for the host system.

The memory system controllermay be configured for other operations associated with the memory devices. For example, the memory system controllermay execute or manage operations such as wear-leveling operations, garbage collection operations, error control operations such as error-detecting operations or error-correcting operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host systemand physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices.

The memory system controllermay include hardware such as one or more integrated circuits or discrete components, a buffer memory, or a combination thereof. The hardware may include circuitry with dedicated (e.g., hard-coded) logic to perform the operations ascribed herein to the memory system controller. The memory system controllermay be or include a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

The memory system controllermay also include a local memory. In some cases, the local memorymay include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) executable by the memory system controllerto perform functions ascribed herein to the memory system controller. In some cases, the local memorymay additionally, or alternatively, include static random access memory (SRAM) or other memory that may be used by the memory system controllerfor internal storage or calculations, for example, related to the functions ascribed herein to the memory system controller. Additionally, or alternatively, the local memorymay serve as a cache for the memory system controller. For example, data may be stored in the local memoryif read from or written to a memory device, and the data may be available within the local memoryfor subsequent retrieval for or manipulation (e.g., updating) by the host system(e.g., with reduced latency relative to a memory device) in accordance with a cache policy.

Although the example of the memory systeminhas been illustrated as including the memory system controller, in some cases, a memory systemmay not include a memory system controller. For example, the memory systemmay additionally, or alternatively, rely on an external controller (e.g., implemented by the host system) or one or more local controllers, which may be internal to memory devices, respectively, to perform the functions ascribed herein to the memory system controller. In general, one or more functions ascribed herein to the memory system controllermay, in some cases, be performed instead by the host system, a local controller, or any combination thereof. In some cases, a memory devicethat is managed at least in part by a memory system controllermay be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

A memory devicemay include one or more arrays of non-volatile memory cells. For example, a memory devicemay include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magneto RAM (MRAM), NOR (e.g., NOR flash) memory, Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally, or alternatively, a memory devicemay include one or more arrays of volatile memory cells. For example, a memory devicemay include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

In some examples, a memory devicemay include (e.g., on the same die, within the same package) a local controller, which may execute operations on one or more memory cells of the respective memory device. A local controllermay operate in conjunction with a memory system controlleror may perform one or more functions ascribed herein to the memory system controller. For example, as illustrated in, a memory device-may include a local controller-and a memory device-may include a local controller-

In some cases, a memory devicemay be or include a NAND device (e.g., NAND flash device). A memory devicemay be or include a die(e.g., a memory die). For example, in some cases, a memory devicemay be a package that includes one or more dies. A diemay, in some examples, be a piece of electronics-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each diemay include one or more planes, and each planemay include a respective set of blocks, where each blockmay include a respective set of pages, and each pagemay include a set of memory cells.

In some cases, a NAND memory devicemay include memory cells configured to each store one bit of information, which may be referred to as single level cells (SLCs). Additionally, or alternatively, a NAND memory devicemay include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLCs) if configured to each store two bits of information, as tri-level cells (TLCs) if configured to each store three bits of information, as quad-level cells (QLCs) if configured to each store four bits of information, or more generically as multiple-level memory cells. Multiple-level memory cells may provide greater density of storage relative to SLC memory cells but may, in some cases, involve narrower read or write margins or greater complexities for supporting circuitry.

In some cases, planesmay refer to groups of blocksand, in some cases, concurrent operations may be performed on different planes. For example, concurrent operations may be performed on memory cells within different blocksso long as the different blocksare in different planes. In some cases, an individual blockmay be referred to as a physical block, and a virtual blockmay refer to a group of blockswithin which concurrent operations may occur. For example, concurrent operations may be performed on blocks-,-,-, and-that are within planes-,-,-, and-, respectively, and blocks-,-,-, and-may be collectively referred to as a virtual block. In some cases, a virtual block may include blocksfrom different memory devices(e.g., including blocks in one or more planes of memory device-and memory device-). In some cases, the blockswithin a virtual block may have the same block address within their respective planes(e.g., block-may be “block” of plane-, block-may be “block” of plane-, and so on). In some cases, performing concurrent operations in different planesmay be subject to one or more restrictions, such as concurrent operations being performed on memory cells within different pagesthat have the same page address within their respective planes(e.g., related to command decoding, page address decoding circuitry, or other circuitry being shared across planes).

In some cases, a blockmay include memory cells organized into rows (pages) and columns (e.g., strings, not shown). For example, memory cells in the same pagemay share (e.g., be coupled with) a common word line, and memory cells in the same string may share (e.g., be coupled with) a common digit line (which may alternatively be referred to as a bit line).

For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first level of granularity (e.g., at a page level of granularity, or portion thereof) but may be erased at a second level of granularity (e.g., at a block level of granularity). That is, a pagemay be the smallest unit of memory (e.g., set of memory cells) that may be independently programmed or read (e.g., programed or read concurrently as part of a single program or read operation), and a blockmay be the smallest unit of memory (e.g., set of memory cells) that may be independently erased (e.g., erased concurrently as part of a single erase operation). Further, in some cases, NAND memory cells may be erased before they can be re-written with new data. Thus, for example, a used pagemay, in some cases, not be updated until the entire blockthat includes the pagehas been erased.

In some cases, to update some data within a blockwhile retaining other data within the block, the memory devicemay copy the data to be retained to a new blockand write the updated data to one or more remaining pages of the new block. The memory device(e.g., the local controller) or the memory system controllermay mark or otherwise designate the data that remains in the old blockas invalid or obsolete and may update a logical-to-physical (L2P) mapping table to associate the logical address (e.g., LBA) for the data with the new, valid blockrather than the old, invalid block. In some cases, such copying and remapping may be performed instead of erasing and rewriting the entire old blockdue to latency or wearout considerations, for example. In some cases, one or more copies of an L2P mapping table may be stored within the memory cells of the memory device(e.g., within one or more blocksor planes) for use (e.g., reference and updating) by the local controlleror memory system controller.

In some cases, L2P mapping tables may be maintained, and data may be marked as valid or invalid at the page level of granularity, and a pagemay contain valid data, invalid data, or no data. Invalid data may be data that is outdated, which may be due to a more recent or updated version of the data being stored in a different pageof the memory device. Invalid data may have been previously programmed to the invalid pagebut may no longer be associated with a valid logical address, such as a logical address referenced by the host system. Valid data may be the most recent version of such data being stored on the memory device. A pagethat includes no data may be a pagethat has never been written to or that has been erased.

In some cases, a memory system controlleror a local controllermay perform operations (e.g., as part of one or more media management algorithms) for a memory device, such as wear leveling, background refresh, garbage collection, scrub, block scans, health monitoring, or others, or any combination thereof. For example, within a memory device, a blockmay have some pagescontaining valid data and some pagescontaining invalid data. To avoid waiting for all of the pagesin the blockto have invalid data in order to erase and reuse the block, an algorithm referred to as “garbage collection” may be invoked to allow the blockto be erased and released as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting a blockthat contains valid and invalid data, selecting pagesin the block that contain valid data, copying the valid data from the selected pagesto new locations (e.g., free pagesin another block), marking the data in the previously selected pagesas invalid, and erasing the selected block. As a result, the quantity of blocksthat have been erased may be increased such that more blocksare available to store subsequent data (e.g., data subsequently received from the host system).

In some cases, a memory systemmay utilize a memory system controllerto provide a managed memory system that may include, for example, one or more memory arrays and related circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller). An example of a managed memory system is a managed NAND (MNAND) system.

The systemmay include any quantity of non-transitory computer readable media that support dividing superblocks in a memory system. For example, the host system(e.g., a host system controller), the memory system(e.g., a memory system controller), or a memory device(e.g., a local controller) may include or otherwise may access one or more non-transitory computer readable media storing instructions (e.g., firmware, logic, code) for performing the functions ascribed herein to the host system, the memory system, or a memory device. For example, such instructions, if executed by the host system(e.g., by a host system controller), by the memory system(e.g., by a memory system controller), or by a memory device(e.g., by a local controller), may cause the host system, the memory system, or the memory deviceto perform associated functions as described herein.

A complete superblock is a superblock that includes zero invalid block across a set of planes and/or dies. A runt superblock is a superblock that includes zero invalid blocks, but the size of the block is smaller than the complete superblock, and the runt superblock does not make use of the full set of planes. An incomplete superblock is a superblock that includes one or more invalid blocks, and a residue superblock is a superblock that includes two or more invalid blocks.

In accordance with examples as described herein, the memory systemmay be configured to generate and access runt superblocks that do not include invalid blocks from incomplete superblocks (e.g., superblocks that include at least a singular invalid block) and may be configured to access available residue superblocks (e.g., superblocks that include two or more invalid blocks). For example, the memory system controllermay scan the physical blocks (e.g., of the memory device) associated with one or more superblocks to determine which physical blocks are valid. The memory system controllermay determine whether a superblock includes a quantity of valid physical blocks below a threshold to use the superblock as an incomplete superblock and/or a residue superblock. The memory system controllermay then generate a second superblock (e.g., a runt superblock) using the one or more valid physical blocks of the incomplete superblock and/or residue superblock. The memory system controllermay access the generated runt superblock that would otherwise be unusable (e.g., unable to be accessed) due to the presence of invalid physical blocks.

The memory system controllermay perform such operations to generate usable, runt superblocks from incomplete superblocks and/or residue superblocks. The generated runt superblocks may be accessible (e.g., by a host system), despite the incomplete superblock and/or residue superblock having at least one bad block. Accordingly, the methods described herein to divide incomplete and/or residue superblocks of the memory system into usable, runt superblocks may increase the overall performance of the memory system, improve the total bytes written to the memory system, and the like.

The systemmay include any quantity of non-transitory computer readable media that support dividing superblocks in a memory system. For example, the host system(e.g., a host system controller), the memory system(e.g., a memory system controller), or a memory device(e.g., a local controller) may include or otherwise may access one or more non-transitory computer readable media storing instructions (e.g., firmware, logic, code) for performing the functions ascribed herein to the host system, the memory system, or a memory device. For example, such instructions, if executed by the host system(e.g., by a host system controller), by the memory system(e.g., by a memory system controller), or by a memory device(e.g., by a local controller), may cause the host system, the memory system, or the memory deviceto perform associated functions as described herein.

shows an example of a block diagramthat supports dividing superblocks in a memory system in accordance with examples as disclosed herein. The block diagrammay illustrate aspects or operations of a system, as described with reference to. For example, operations illustrated by the block diagrammay be performed by a memory system(e.g., a memory system controller) or a host system. The steps performed by the memory system may be implemented in instructions stored on memory of memory system(e.g., memory device) and executed by the memory system controller(and/or local controller). The steps performed by the host system may be implemented in instructions stored on memory of host systemand executed by the host system controller.

The block diagrammay depict dividing an incomplete superblockand/or residue superblockof the memory system into a usable, runt superblock. Such methods may increase the overall performance of the memory system. Moreover, accessing a runt superblockthat may otherwise be unused may increase or otherwise prolong the usable storage capacity of the memory system.

As described herein, each superblockmay include a set of blocks, which may be examples of a block, as described with reference to. Each superblockmay be associated with a set of physical blocks of the memory system from each plane of the memory system (e.g.,block from each plane) and may represent a logical (e.g., virtual) partitioning (e.g., grouping) of the set of physical blocks. Each superblockmay be an example of a virtual blockwith a quantity of blockscorresponding to a quantity of planes of the memory system, as described with reference to.

For example, each superblockmay include 8 blocks(e.g., corresponding to 8 planes of the memory system), where each blockis associated with a plane of a memory system. A superblock may be logical construct to describe a set of blocks that are accessible in parallel. As defined herein, a superblock may define blocks that are each in different planes of different memory dies. In some cases, the memory system may include multiple memory devices such that each superblockmay include blocksfrom each plane of the one or more memory devices. In some implementations, the blocksmay be ordered within a respective superblockbased on an order of the planes of the memory system, such that contiguous blocksmay be associated with continuous planes (e.g., a first block may correspond to a first plane, a second block may correspond to a second plane, etc.). Each superblockmay span more than one NAND die. For example, 4 blocksmay be included in a first NAND die-and 4 blocksmay be included in a second NAND die-. Eventually, superblocks may be categorized based on how many valid blocks the superblock includes (e.g., complete superblock, incomplete superblock, residue superblock, runt superblock).

A complete superblockis a superblock that includes zero invalid blocksacross a set of planes and/or dies. A runt superblockis a superblock that includes zero invalid blocks, but the size of the block is smaller than the complete superblock, and the runt superblockdoes not make use of the full set of planes. An incomplete superblockis a superblock that includes one or more invalid blocks, and a residue superblockis a superblock that includes two or more invalid blocks.

In such cases, the superblocksmay include valid blocks(e.g., a block including a quantity of valid data, a quantity of valid physical blocks, a quantity of operable access lines, or any combination thereof, that satisfies a threshold) and/or invalid blocks(e.g., a quantity of invalid physical cells, a quantity of inoperable access lines, or any combination thereof, that satisfies a second threshold). In some cases, the invalid blocksmay be inaccessible while performing an access operation (e.g., a read operation, a write operation, a refresh operation, a media management operation, a wear leveling operation) or may otherwise result in one or more errors due to being accessed. In some instances, each superblockmay include a quantity of valid blocks, a quantity of invalid blocks, or both.

In some systems, the quantity of blocks per plane is no longer sufficient to allow an arrangement as shown with reference to block diagram(e.g., two NAND diesand four planes per NAND dieto include 8 blocks per superblock). Rather, the memory system may allow for a quantity of blocks to be sufficient, and the quantity of blocks per plane to be at least large enough to skip one block per superblock. In such cases, the memory system may enable smart die matching (SDM). In order to maintain consistent performance for the memory system, it may be desired that every superblockis the same size (e.g., including a same quantity of blocks).

A memory system may have invalid blocksthat may disrupt parallelism that may be gained by using a complete superblock. The memory system may include one or more residue superblocksthat are not usable as incomplete superblocksdue to a quantity of valid blocks being below a threshold. With smaller quantities of valid blocks, the residue superblockshave reduced parallelism, which may result in lower performance of the overall memory system. In such cases, it may be desired to assign valid blocks of the residue superblocksto usable, runt superblocksthat enable the valid blocksof the residue superblock(e.g., incomplete superblock) to be accessed.

To improve performance, a memory system may be configured to swap invalid blockswith valid blocksto create as many complete superblocksas possible. The process of creating complete superblocksmay result in some superblocks including a higher quantity of invalid blocks. In effect, a valid blockis moved from a first superblock to a second superblock and an invalid blockis moved from the second superblock to the first superblock. The result of this swapping is that the second superblock is more complete than it was before (and may even become a complete superblock) and the first superblock includes more invalid blocks and will likely be a residue superblock. By concentrating invalid blocksin a few superblocks with this swapping scheme it may increase a percentage of superblocks that are complete superblocksor incomplete superblocks. The memory system may, in some examples, scan one or more blocksto determine which blocks are valid blocksand/or invalid blocks. The memory system may then swap an invalid blockin a first superblock with a valid blockfrom second superblock, thereby making the first superblock a complete superblockand making the second superblock an incomplete superblockand/or a residue superblock. With this swapping of blocks, some superblocksmay be left with a residue of valid blocksand may be unusable as a complete superblockor an incomplete superblock.

In response to scanning the superblocksand swapping the blocks, the memory system may determine that the residue superblockincludes a quantity of valid blocksthat is below a threshold. The threshold may be an example of a quantity of valid blocksthat is divisible by the quantity of planes. For example, the threshold may be 4 valid blocks. In some cases, the memory system may also identify the superblock (e.g., complete superblock, incomplete superblock, and/or residue superblock) in response to scanning the memory device. After identifying the superblockwith one or more invalid blocksin the identified planes, the memory system may replace the one or more invalid blockswith the one or more valid blocksto generate as many complete superblocksas possible.

For example, the memory system may determine that a first superblock includes an invalid blockin the third plane, and the memory system may replace the invalid blockin the first superblock with a valid blockfrom a third plane of a second superblock to generate the complete superblock. In such cases, the memory system may assign a physical block (e.g., the valid block) of the second superblock to the first superblock to generate the complete superblock, and assign a physical block (e.g., invalid block) of the first superblock to the second superblock to generate a residue superblock.

In some cases, adding the one or more invalid blocksto the residue superblockto make other superblockscomplete superblocksmay include updating a mapping of the complete superblockand residue superblock, such that the one or more invalid blocksare mapped to the residue superblockand the one or more valid blocksare mapped to the complete superblock. For example, the valid blockmay be mapped to the complete superblock, and the invalid blockmay be mapped to the residue superblock. In some implementations, updating the mapping may include updating a L2P table of the memory system (e.g., at non-volatile memory of the memory system), or a portion of the L2P table stored in volatile memory of the memory system. In some examples, access commands (e.g., read commands or write commands) may include one or more logical addresses that is mapped to one or more physical addresses using the L2P table. In some cases, the L2P table may associate physical blocks (whether valid or invalid) with various logical blocks (e.g., virtual blocks, superblocks).

In some cases, updating the mapping may include updating a bad block table to indicate that the invalid blockis assigned to the residue superblockand/or the incomplete superblockand to indicate that the invalid blockis further assigned to be the runt superblock. In some cases, updating the mapping may include updating a second data structure to indicate physical blocks assigned to superblocksthat include the quantity of valid blocksbelow the threshold.

Techniques are described to repurpose these residue superblocksand form smaller superblocks (e.g., runt superblocks) that are usable in some contexts. After identifying that the residue superblockincludes a quantity of valid blocksthat are below a threshold, the memory system may generate one or more runt superblocksfrom the residue superblock. In such cases, the memory system may utilize valid blocksto replace one or more invalid blocksin the superblocksto generate as many complete superblocksas possible while also generating residue superblockwith the swapped invalid blocks, thereby enabling runt superblocksto be generated from the residue superblocks.