Chip Package Structure and Method for Forming the Same

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements.

Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along scribe lines. The individual dies are then packaged separately. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, since feature sizes of dies continue to decrease, feature sizes of an interposer substrate for carrying the dies decrease as well. Therefore, it is a challenge to form reliable packages with the dies and the interposer substrate with small feature sizes.

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The term “substantially” in the description, such as in “substantially flat” or in “substantially coplanar”, etc., will be understood by the person skilled in the art. In some embodiments the adjective substantially may be removed. Where applicable, the term “substantially” may also include embodiments with “entirely”, “completely”, “all”, etc. The term “substantially” may be varied in different technologies and be in the deviation range understood by the skilled in the art. For example, the term “substantially” may also relate to 90% of what is specified or higher, such as 95% of what is specified or higher, especially 99% of what is specified or higher, including 100% of what is specified, though the present invention is not limited thereto. Furthermore, terms such as “substantially parallel” or “substantially perpendicular” may be interpreted as not to exclude insignificant deviation from the specified arrangement and may include for example deviations of up to 10°. The word “substantially” does not exclude “completely” e.g. a composition which is “substantially free” from Y may be completely free from Y.

The term “about” may be varied in different technologies and be in the deviation range understood by the skilled in the art. The term “about” in conjunction with a specific distance or size is to be interpreted so as not to exclude insignificant deviation from the specified distance or size. For example, the term “about” may include deviations of up to 10% of what is specified, though the present invention is not limited thereto. The term “about” in relation to a numerical value x may mean x±5 or 10% of what is specified, though the present invention is not limited thereto.

Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.

are cross-sectional views of various stages of a process for forming a chip package structure, in accordance with some embodiments. As shown in, a core substrateis provided, in accordance with some embodiments. The core substratehas surfacesand, in accordance with some embodiments. The surfacesandare opposite to each other, in accordance with some embodiments. The thickness Tof the core substrateranges from about 150 μm to about 250 μm, in accordance with some embodiments.

In some embodiments, the core substrateis made of organic materials such as epoxy, resin, glass fiber, molding compound, plastic (such as polyvinylchloride (PVC), acrylonitril, butadiene and styrene (ABS), polypropylene (PP), polyethylene (PE), polystyrene (PS), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonates (PC), polyphenylene sulfide (PPS)), the like, or a combination thereof. In some other embodiments, the core substrateis made of a conductive material (e.g., metal or alloy), a semiconductor material (e.g., silicon), glass, the like, a combination thereof, or another suitable material.

As shown in, portions of the core substrateare removed to form through holesin the core substrate, in accordance with some embodiments. The through holespass through the core substrate, in accordance with some embodiments. The through holesare formed using a drilling process, such as a laser drilling process, an etching process, or another suitable process.

As shown in, wiring layersandand conductive via structuresare formed, in accordance with some embodiments. The wiring layeris formed over the surface, in accordance with some embodiments. The wiring layeris formed over the surface, in accordance with some embodiments. The conductive via structuresare formed in the through holes, in accordance with some embodiments.

The wiring layersandand conductive via structuresare made of a conductive material, such as metal (e.g. copper, aluminum, or tungsten) or alloys thereof, in accordance with some embodiments.

The formation of the wiring layersandand conductive via structuresincludes forming a seed layer (not shown) over the surfacesandand in the through holes; forming a photoresist layer (not shown) over the seed layer, wherein the photoresist layer has openings exposing portions of the seed layer; performing an electroplating plating process to form a conductive layer in the openings; and removing the photoresist layer and the seed layer thereunder, in accordance with some embodiments. The conductive layer and the seed layer thereunder together form the wiring layersandand the conductive via structures, in accordance with some embodiments.

As shown in, dielectric layersandare formed over the surfacesandrespectively, in accordance with some embodiments. The dielectric layercovers the wiring layer, in accordance with some embodiments. The dielectric layercovers the wiring layer, in accordance with some embodiments.

The dielectric layersandinclude an Ajinomoto Build-up Film (ABF) or a prepreg sheet, in accordance with some embodiments. The dielectric layersandare made of an insulating material such as a polymer material (e.g., polybenzoxazole, polyimide, or a photosensitive material), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), silicon oxynitride, or the like, in accordance with some embodiments. In some embodiments, the dielectric layersandare made of the same material. In some other embodiments, the dielectric layersandare made of different materials.

As shown in, wiring structuresandare formed over opposite surfacesandof the core substrate, in accordance with some embodiments. The wiring structureincludes a wiring layerand conductive vias, in accordance with some embodiments.

The wiring layeris formed over the dielectric layer, in accordance with some embodiments. The conductive viasare formed in the dielectric layer, in accordance with some embodiments. The conductive viasare connected between the wiring layersand, in accordance with some embodiments.

The wiring structureincludes a wiring layerand conductive vias, in accordance with some embodiments. The wiring layeris formed under the dielectric layer, in accordance with some embodiments. The conductive viasare formed in the dielectric layer, in accordance with some embodiments. The conductive viasare connected between the wiring layersand, in accordance with some embodiments.

The wiring structureis made of a conductive material, such as metal (e.g. copper, aluminum, or tungsten) or alloys thereof, in accordance with some embodiments. The wiring structureis made of a conductive material, such as metal (e.g. copper, aluminum, or tungsten) or alloys thereof, in accordance with some embodiments.

The formation of the wiring structuresandincludes partially removing the dielectric layersandto form through holesandin the dielectric layersandrespectively; forming a first seed layer (not shown) and a second seed layer (not shown) over the dielectric layersandand in the through holesandrespectively; forming a first photoresist layer (not shown) and a second photoresist layer (not shown) over the first seed layer and the second seed layer respectively, wherein the first photoresist layer has first openings exposing portions of the first seed layer, and the second photoresist layer has second openings exposing portions of the second seed layer; performing an electroplating plating process to form a first conductive layer in the first openings and a second conductive layer in the second openings; and removing the first photoresist layer, the first seed layer thereunder, the second photoresist layer, and the second seed layer thereunder, in accordance with some embodiments.

The first conductive layer and the first seed layer thereunder together form the wiring structure, in accordance with some embodiments. The second conductive layer and the second seed layer thereunder together form the wiring structure, in accordance with some embodiments.

As shown in, a dielectric layeris formed over the dielectric layerand the wiring structure, in accordance with some embodiments. As shown in, a dielectric layeris formed over the dielectric layerand the wiring structure, in accordance with some embodiments.

The dielectric layerincludes an Ajinomoto Build-up Film (ABF) or a prepreg sheet, in accordance with some embodiments. The dielectric layeris made of an insulating material such as a polymer material (e.g., polybenzoxazole, polyimide, or a photosensitive material), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), silicon oxynitride, or the like, in accordance with some embodiments.

The dielectric layerincludes an Ajinomoto Build-up Film (ABF) or a prepreg sheet, in accordance with some embodiments. The dielectric layeris made of an insulating material such as a polymer material (e.g., polybenzoxazole, polyimide, or a photosensitive material), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), silicon oxynitride, or the like, in accordance with some embodiments.

In some embodiments, the dielectric layersandare made of the same material. In some other embodiments, the dielectric layersandare made of different materials.

As shown in, portions of the dielectric layerare removed to form through holesand trenchesin the dielectric layer, in accordance with some embodiments. The through holespass through the dielectric layerand expose portions of the wiring layer, in accordance with some embodiments.

The trenchesdo not pass through the dielectric layer, in accordance with some embodiments. The removal process includes a laser process such as an excimer laser process, in accordance with some embodiments.

As shown in, portions of the dielectric layerare removed to form through holes, in accordance with some embodiments. The through holespass through the dielectric layerand expose portions of the wiring layer, in accordance with some embodiments. The removal process includes a laser process, in accordance with some embodiments.

As shown in, a photoresist layer PRis formed under the dielectric layer, in accordance with some embodiments. The photoresist layer PRhas openings OP, in accordance with some embodiments. The opening OPis connected to the through hole, in accordance with some embodiments. The photoresist layer PRis made of a photoresist material such as a polymer material, in accordance with some embodiments.

As shown in, conductive linesand conductive via structuresare formed in the trenchesand the through holesrespectively, in accordance with some embodiments. The conductive via structuresare connected to the wiring layerthereunder, in accordance with some embodiments.

The line width Wof the conductive lineis less than the average width of the conductive via structure, in accordance with some embodiments. Since the trenchesare formed by an excimer laser process, the width Wof the trenchcan be reduced, in accordance with some embodiments. Therefore, the line width Wof the conductive linecan be reduced, in accordance with some embodiments. The line width Wranges from about 5 μm to about 10 μm, in accordance with some embodiments.

As a result, the density of the conductive linesis improved, which improves the signal transmission efficiency, in accordance with some embodiments. Furthermore, since the line width Wof the conductive lineis reduced, the thickness Tof the dielectric layeris reduced, in accordance with some embodiments. The thickness Tof the dielectric layerranges from about 5 μm to about 10 μm, in accordance with some embodiments.

The top surfaceof the conductive via structureis lower than the top surfaceof the dielectric layer, in accordance with some embodiments. The top surfaceof the conductive lineis lower than the top surfaceof the dielectric layer, in accordance with some embodiments.

The conductive linesand the conductive via structuresare made of a conductive material, such as metal (e.g. copper, aluminum, or tungsten) or alloys thereof, in accordance with some embodiments. The conductive linesand the conductive via structuresare formed using an electroplating process and an etching process, in accordance with some embodiments.

As shown in, a wiring layerand conductive via structuresare formed in the openings OPof the photoresist layer PRand the through holesof the dielectric layerrespectively, in accordance with some embodiments. The conductive via structuresare connected to the wiring layerthereover, in accordance with some embodiments.

The wiring layerand the conductive via structuresare made of a conductive material, such as metal (e.g. copper, aluminum, or tungsten) or alloys thereof, in accordance with some embodiments. As shown in, the photoresist layer PRis removed, in accordance with some embodiments.

is a perspective view of the chip package structure of, in accordance with some embodiments.is a cross-sectional view illustrating the chip package structure along a sectional line I-I′ in, in accordance with some embodiments.

As shown in, a dielectric layeris formed over the dielectric layer, the conductive lines, and the conductive via structure, in accordance with some embodiments. The dielectric layers,andtogether form a dielectric structure D, in accordance with some embodiments. The dielectric layerincludes an Ajinomoto Build-up Film (ABF) or a prepreg sheet, in accordance with some embodiments.

The dielectric layeris made of an insulating material such as a polymer material (e.g., polybenzoxazole, polyimide, or a photosensitive material), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), silicon oxynitride, or the like, in accordance with some embodiments.

As shown in, a dielectric layeris formed over the dielectric layerand the wiring layer, in accordance with some embodiments. The dielectric layers,andtogether form a dielectric structure D, in accordance with some embodiments. The dielectric layerincludes an Ajinomoto Build-up Film (ABF) or a prepreg sheet, in accordance with some embodiments.

The dielectric layeris made of an insulating material such as a polymer material (e.g., polybenzoxazole, polyimide, or a photosensitive material), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), silicon oxynitride, or the like, in accordance with some embodiments.

As shown in, the dielectric layeris partially removed to form trenchesandand through holesin the dielectric layer, in accordance with some embodiments. The through holespass through the dielectric layer, in accordance with some embodiments. The through holesexpose the conductive linesand the conductive via structures, in accordance with some embodiments.

The trenchesanddo not pass through the dielectric layer, in accordance with some embodiments. The trenchis connected to the corresponding through hole, in accordance with some embodiments. The trenchis spaced apart from the trench, in accordance with some embodiments.

The trenchis wider than the trench, in accordance with some embodiments. The trenchesandare shallower than the through hole, in accordance with some embodiments.

The removal process includes a laser process such as an excimer laser process, in accordance with some embodiments. In some embodiments, the trenchesandare formed using a first excimer laser process, and the through holesare formed using a second excimer laser process. In some other embodiments, the trenchesandand the through holesare formed using an excimer laser process.

As shown in, the dielectric layeris partially removed to form through holesin the dielectric layer, in accordance with some embodiments. The through holespass through the dielectric layer, in accordance with some embodiments. The through holesexpose the wiring layer, in accordance with some embodiments. The removal process includes a laser process, in accordance with some embodiments.

As shown in, a photoresist layer PRis formed under the dielectric layer, in accordance with some embodiments. The photoresist layer PRhas openings OP, in accordance with some embodiments. The opening OPis connected to the corresponding through hole, in accordance with some embodiments. The photoresist layer PRis made of a photoresist material such as a polymer material, in accordance with some embodiments.

is a perspective view of the chip package structure of, in accordance with some embodiments.is a cross-sectional view illustrating the chip package structure along a sectional line I-I′ in, in accordance with some embodiments.is a cross-sectional view illustrating the chip package structure along a sectional line II-II′ in, in accordance with some embodiments.

As shown in, conductive linesandand conductive via structuresare formed in the trenchesandand the through holesrespectively, in accordance with some embodiments. The conductive linesare connected to the conductive via structures, in accordance with some embodiments.

The top surfaceof the conductive via structureis lower than the top surfaceof the dielectric layer, in accordance with some embodiments. The conductive via structureis on the top surfaceof the corresponding conductive via structure, in accordance with some embodiments. The conductive via structureis in direct contact with the top surfaceof the corresponding conductive via structure, in accordance with some embodiments.