Integrated Circuit Device

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0079095, filed on Jun. 18, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

Inventive concepts relate to an integrated circuit (IC) device, and more particularly, to an IC device including a field-effect transistor (FET).

The downscaling of IC devices has rapidly progressed due to the development of electronic technology, and such highly downscaled IC devices expect having not only a high operating speed but also high operating accuracy. Accordingly, a technique of introducing a backside contact structure having a stable arrangement structure within a relatively small area has been proposed. It is desirable to develop an IC device including a backside contact structure, which is capable of improving the performance and reliability of a field-effect transistor (FET) by improving the reliability of an electrical contact between the backside contact structure and a source/drain region.

Inventive concepts provide an integrated circuit (IC) device, which may improve the performance and/or reliability of a field-effect transistor (FET) by improving the reliability of an electrical contact between a backside contact structure and a source/drain region.

According to some example embodiments, there is provided an IC device including a channel region, a gate line surrounding the channel region, a source/drain region adjacent to the gate line in a first lateral direction, the source/drain region contacting the channel region, and a backside via contact passing through a portion of the source/drain region in a vertical direction from a back side of the source/drain region, wherein the source/drain region includes a semiconductor layer including a dopant, and the source/drain region including a bottom epitaxial layer protruding from a bottom surface of the source/drain region toward a central portion of the source/drain region in the vertical direction, a blocking epitaxial layer contacting each of the channel region and the bottom epitaxial layer, and a main epitaxial layer filling a space defined by the blocking epitaxial layer on the bottom epitaxial layer, wherein a first dopant concentration of the bottom epitaxial layer is greater than a second dopant concentration of the blocking epitaxial layer and is greater than or equal to a third dopant concentration of the main epitaxial layer, and the backside via contact passes through at least a portion of the bottom epitaxial layer in the vertical direction.

Alternatively or additionally according to some example embodiments, there is provided an IC device including a plurality of channel regions apart from each other in a first lateral direction, a plurality of gate lines surrounding the plurality of channel regions, each gate line extending lengthwise in a second lateral direction, wherein the second lateral direction is perpendicular to the first lateral direction, a plurality of source/drain regions, each of which is between two adjacent ones of the plurality of gate lines, and a backside via contact passing through a portion of a first source/drain region in a vertical direction from a back side of a first source/drain region, wherein the first source/drain region is selected from the plurality of source/drain regions, wherein each of the plurality of source/drain regions includes a semiconductor layer including a dopant, and each of the plurality of source/drain regions including a bottom epitaxial layer protruding from a bottom surface of a corresponding one of the plurality of source/drain regions toward a central portion thereof in the vertical direction, a blocking epitaxial layer contacting a channel region adjacent thereto in the first lateral direction, from among the plurality of channel regions, and a main epitaxial layer filling a space defined by the blocking epitaxial layer on the bottom epitaxial layer, wherein, in each of the plurality of source/drain regions, a first dopant concentration of the bottom epitaxial layer is greater than a second dopant concentration of the blocking epitaxial layer and is greater than or equal to a third dopant concentration of the main epitaxial layer, and the backside via contact passes through at least a portion of the bottom epitaxial layer included in the first source/drain region in the vertical direction.

Alternatively or additionally according to some example embodiments, there is provided an IC device including a plurality of channel regions apart from each other in a first lateral direction, a plurality of gate lines respectively surrounding the plurality of channel regions, each gate line extending lengthwise in a second lateral direction, wherein the second lateral direction is perpendicular to the first lateral direction, a plurality of source/drain regions, each of which is between two adjacent ones of the plurality of gate lines, a frontside insulating structure covering a top surface of a front side of each of the plurality of source/drain regions, a backside via contact passing through a portion of a first source/drain region in a vertical direction from a back side of the first source/drain region, wherein the first source/drain region is selected from the plurality of source/drain regions, a backside metal silicide film between the first source/drain region and the backside via contact, a frontside source/drain contact passing through the frontside insulating structure in the vertical direction, the frontside source/drain contact passing through a portion of a second source/drain region in the vertical direction from a front side of the second source/drain region, wherein the second source/drain region is selected from the plurality of source/drain regions and apart from the first source/drain region, a frontside metal silicide film between the second source/drain region and the frontside source/drain contact, wherein each of the plurality of source/drain regions includes a semiconductor layer including a dopant, and each of the plurality of source/drain regions including a bottom epitaxial layer protruding from a bottom surface of a corresponding one of the source/drain regions toward a central portion thereof in the vertical direction, the bottom epitaxial layer having a first dopant concentration, a blocking epitaxial layer contacting each of the bottom epitaxial layer and a channel region adjacent to the blocking epitaxial layer in the first lateral direction, from among the plurality of channel regions, the blocking epitaxial layer having a second dopant concentration, wherein the second dopant concentration is lower than the first dopant concentration, and a main epitaxial layer filling a space defined by the blocking epitaxial layer on the bottom epitaxial layer, the main epitaxial layer having a third dopant concentration, wherein the third dopant concentration is lower than or equal to the first dopant concentration, wherein the backside via contact and the backside metal silicide film pass through at least a portion of the bottom epitaxial layer included in the first source/drain region in the vertical direction, and the frontside source/drain contact and the frontside metal silicide film are apart from the bottom epitaxial layer included in the second source/drain region in the vertical direction.

Hereinafter, some example embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used to denote the same elements in the drawings, and repeated descriptions thereof will be omitted.

is a plan layout diagram of some components of an integrated circuit (IC) deviceaccording to some example embodiments.

is a plan view of a cell blockof an integrated circuit (IC) deviceaccording to some example embodiments.

Referring to, the cell blockof the IC devicemay include a plurality of cells LC, which include circuit patterns configured to constitute various circuits. The plurality of cells LC may be arranged in a matrix form in a widthwise direction (X direction in) and a height direction (Y direction in) in the cell block.

Each of the plurality of cells LC may include a circuit pattern having a layout designed according to a place-and-route (PnR) technique to perform at least one logic function. The plurality of cells LC may perform various logic functions. In some example embodiments, the plurality of cells LC may include a plurality of standard cells or a plurality of IP blocks. In some example embodiments, at least some of the plurality of cells LC may perform the same logic function. Alternatively or additionally, in some example embodiments, at least some of the plurality of cells LC may perform different logic functions. Each of the plurality of logic cells LC may have the same size and/or shape, or, alternatively, at least one of the plurality of logic cells LC may have a different size and/or shape than others of the plurality of logic cells LC.

The plurality of cells LC may include various kinds of logic cells including a plurality of circuit elements. For example, each of the plurality of logic cells LC may include an AND gate, a NAND gate, an OR gate, a NOR gate, an exclusive OR (XOR) gate, an exclusive NOR (XNOR) gate, an inverter (INV), an adder (ADD), a buffer (BUF), a delay (DLY), a filter (FIL), a multiplexer (MXT/MXIT), an OR/AND/INVERTER (OAI) gate, an AND/OR (AO) gate, an AND/OR/INVERTER (AOI) gate, a D-flip-flop, a reset flip-flop, a master-slave flip-flop, a latch, or a combination thereof, without being limited thereto.

In the cell block, at least some of the plurality of cells LC that forms one row RW, RW, RW, RW, RW, or RWin the widthwise direction (X direction in) may have the same width as each other. Also, at least some of the plurality of cells LC that forms one row RW, RW, RW, RW, RW, or RWmay have the same height as each other. However, inventive concepts are not limited to those illustrated in, and at least some of the plurality of cells LC that forms one row RW, RW, RW, RW, RW, or RWmay have different widths and/or heights from each other.

An area of each of the plurality of cells LC included in the cell blockof the IC devicemay be defined by a cell boundary CBD. A cell boundary contact portion CBC where respective cell boundaries CBD of two cells LC that are adjacent to each other in the widthwise direction (X direction in) or the height direction (Y direction in), from among the plurality of cells LC, meet each other may be between the two adjacent cells LC.

In some example embodiments, from among the plurality of cells LC that form one row RW, RW, RW, RW, RW, or RW, two cells LC that are adjacent to each other in the widthwise direction may contact each other at the cell boundary contact portion CBC without a distance therebetween. Alternatively or additionally in some example embodiments, from among the plurality of cells LC that form one row RW, RW, RW, RW, RW, or RW, two cells LC that are adjacent to each other in the widthwise direction may be a distance (such as a predetermined distance) apart from each other.

In some example embodiments, from among the plurality of cells LC that form one row RW, RW, RW, RW, RW, or RW, two adjacent cells LC may perform the same function as each other. In this case, the two adjacent cells LC may have the same structure as each other. In some example embodiments, from among the plurality of cells LC that form one row RW, RW, RW, RW, RW, or RW, two adjacent cells may perform different functions from each other.

In some example embodiments, one cell LC, which is selected from the plurality of cells LC included in the cell blockof the IC device, may have a symmetrical structure to another cell LC, which is adjacent to the selected cell LC in the height direction (Y direction in), about the cell boundary contact portion CBC therebetween. For example, a reference logic cell LC_R in a third row RWmay have a symmetrical structure to a lower logic cell LC_L in a second row RWabout the cell boundary contact portion CBC therebetween. Also, the reference logic cell LC_R in the third row RWmay have a symmetrical structure to an upper logic cell LC_H in a fourth row RWabout the cell boundary contact portion CBC therebetween. Althoughillustrates an example in which the cell blockincluding six rows RW, RW, . . . , and RW, inventive concepts are not limited thereto. The cell blockmay include various numbers of rows, which are selected as needed, and one row may include various numbers of cells, which are selected as needed or desired.

A selected one of a plurality of ground lines VSS and a plurality of power lines VDD may be between a plurality of rows (e.g., RW, RW, RW, RW, RW, and RW), each of which includes a plurality of cells LC arranged in a line in the widthwise direction (X direction in). The plurality of ground lines VSS and the plurality of power lines VDD may each extend in a first lateral direction (X direction) and may be alternately arranged apart from each other in a second lateral direction (Y direction). The second lateral direction (Y direction) may be perpendicular to the first lateral direction (X direction). Accordingly, the plurality of ground lines VSS and the plurality of power lines VDD may each overlap the cell boundary CBD of the cell LC in the second lateral direction (Y direction).

is a plan layout diagram of an IC deviceaccording to some example embodiments.is a cross-sectional view taken along line X-X′ of.is a cross-sectional view taken along line Y-Y′ of.is a cross-sectional view taken along line Y-Y′ of.is an enlarged cross-sectional view of portion “EX” of.is an enlarged cross-sectional view of portion “EX” of.

With reference to, the IC deviceincluding a field-effect transistor (FET) having a gate-all-around structure including a channel region of a nanowire or nanosheet type and a gate surrounding the channel region is described. Of the IC device, components shown inmay constitute some of the plurality of cells LC shown in.

Referring to, the IC devicemay include a plurality of nanosheet stacks NSS, a plurality of gate linessurrounding the plurality of nanosheet stacks NSS, and a plurality of source/drain regions, each of which is between two adjacent ones of the plurality of gate lines. The plurality of gate lines, the plurality of nanosheet stacks NSS, and the plurality of source/drain regionsmay constitute or correspond to a plurality of nanosheet transistors TR.

The plurality of nanosheet stacks NSS may be arranged apart from each other in a first lateral direction (X direction) and a second lateral direction (Y direction), which intersect with each other at an angle such as at right angles. Each of the plurality of nanosheet stacks NSS may include a first nanosheet N, a second nanosheet N, a third nanosheet N, and a fourth nanosheet N, which are sequentially stacked in a vertical direction (Z direction) and apart from each other. The vertical direction (Z direction) may be a direction perpendicular to each of the first lateral direction (X direction) and the second lateral direction (Y direction). As used herein, each of the nanosheet stack NSS and the first to fourth nanosheets N, N, N, Nincluded in the nanosheet stack NSS may be referred to as a channel region.

The plurality of gate linesmay be apart from each other in the first lateral direction (X direction) and may extend lengthwise in the second lateral direction (Y direction). The plurality of gate linesmay be arranged at a constant pitch; however, example embodiments are not limited thereto. Each of the plurality of gate linesmay surround the first to fourth nanosheets N, N, N, and Nincluded in the nanosheet stack NSS. Each of the plurality of gate linesmay be surrounded by a gate dielectric film.

Each of the plurality of source/drain regionsmay be between two adjacent ones of the plurality of gate lines. A backside via contact BCA may be connected to some source/drain regions(referred to as first source/drain regions) selected from the plurality of source/drain regions. The backside via contact BCA may pass through a lower portion of the source/drain regionin the vertical direction (Z direction) from a back side of a corresponding one of the source/drain regions.

A frontside source/drain contact CA may be connected to some other source/drain regions(referred to as second source/drain regions) selected from the plurality of source/drain regions. The frontside source/drain contact CA may pass through an upper portion of the corresponding one of the source/drain regionsin the vertical direction (Z direction) from a front side of the source/drain region.

A top surface of a front side of each of the plurality of source/drain regionsmay be covered by an insulating linerand an inter-gate dielectric film. The insulating linerand the inter-gate dielectric filmmay constitute or be included in a frontside insulating structure. The top surface of the front side of each of the plurality of source/drain regionsmay be in contact with the insulating linerof the frontside insulating structure. The frontside source/drain contact CA may pass through the inter-gate dielectric filmand the insulating linerof the frontside insulating structure in the vertical direction (Z direction) and pass through the upper portion of the corresponding one of the source/drain regionsin the vertical direction (Z direction).

As used herein, a bottom surface of a back side of each of the plurality of source/drain regionsmay refer to a surface opposite to the top surface of the front side thereof in the vertical direction (Z direction). The bottom surface of the back side of the source/drain regionmay be apart from the frontside insulating structure in the vertical direction (Z direction).

A backside metal silicide filmmay be between the backside via contact BCA and the source/drain region(referred to as the first source/drain region) that is connected to the backside via contact BCA, from among the plurality of source/drain regions. The backside via contact BCA may be configured to be connected to the corresponding one of the source/drain regionsthrough the backside metal silicide film.

A frontside metal silicide filmmay be between the frontside source/drain contact CA and the source/drain region(referred to as the second source/drain region) that is connected to the frontside source/drain contact CA, from among the plurality of source/drain regions. The frontside source/drain contact CA may be configured to be connected to the corresponding one of the source/drain regionsthrough the frontside metal silicide film.

Each of the plurality of source/drain regionsmay include a bottom epitaxial layer, a blocking epitaxial layer, a main epitaxial layer, and a capping layer. In some example embodiments, the capping layermay be omitted in each of or at least some of the plurality of source/drain regions.

In each of the plurality of source/drain regions, the bottom epitaxial layermay have a shape protruding from a bottom surface of the corresponding one of the source/drain regionstoward a central portion thereof in the vertical direction (Z direction). As used herein, the bottom surface of the source/drain regionmay refer to the bottom surface of the back side of the source/drain regionand refer to a surface of the source/drain region, which is apart from the frontside insulating structure in the vertical direction (Z direction).

In each of the plurality of source/drain regions, the blocking epitaxial layermay be in contact with each of the first to fourth nanosheets N, N, N, and Nincluded in the nanosheet stack NSS, which is adjacent to the corresponding one of the source/drain regionsin the first lateral direction (X direction). In each of the plurality of source/drain regions, the main epitaxial layermay fill a space defined by the blocking epitaxial layeron the bottom epitaxial layer.

Each of the plurality of source/drain regionsmay include a semiconductor layer including a dopant such as one or more of a Group III-type dopant and/or one or more of a Group V-type dopant and/or one or more of a Group-IV type dopant. In each of the plurality of source/drain regions, a dopant concentration of the bottom epitaxial layermay be greater than a dopant concentration of each of the blocking epitaxial layerand the capping layerand be greater than or equal to a dopant concentration of the main epitaxial layer.

In some example embodiments, the IC devicemay include a nanosheet transistor (refer to TR in) including a PMOS transistor. Each of the plurality of source/drain regionsmay include a SiGelayer (here, x≠0) doped with a p-type dopant. In each of the plurality of source/drain regions, a germanium (Ge) content the bottom epitaxial layermay be greater than a Ge content of each of the blocking epitaxial layerand the capping layerand be greater than or equal to a Ge content of the main epitaxial layer. For example, each of the plurality of source/drain regionsmay include a SiGelayer (here, x≠0) doped with a p-type dopant. In each of the plurality of source/drain regions, a Ge content of the bottom epitaxial layermay be in a range of about 45 atomic percent (at %) to about 70 at %, and a Ge content of the blocking epitaxial layermay be in a range of about 3 at % to about 10 at %. A Ge content of the main epitaxial layermay be in a range of about 40 at % to about 65 at %, and a Ge content of the capping layermay be in a range of about 0 at % to about 10 at %.

When the IC deviceincludes a nanosheet transistor (refer to TR in) including a PMOS transistor and the plurality of source/drain regionsinclude a SiGelayer (here, x≠0) doped with a p-type dopant, in each of the plurality of source/drain regions, the concentration of the p-type dopants in the bottom epitaxial layermay be greater than the concentration of the p-type dopants in each of the blocking epitaxial layerand the capping layerand be greater than or equal to the concentration of the p-type dopants in the main epitaxial layer. The p-type dopant may include at least one selected from boron (B) and gallium (Ga), without being limited thereto. A dopant concentration of boron may be greater than, less than, or equal to a dopant concentration of gallium.

For instance, the plurality of source/drain regionsmay include boron (B) as the p-type dopant. In this case, in each of the plurality of source/drain regions, the dopant concentration of boron (B) in the bottom epitaxial layermay be in a range of about 8×10atoms/cmto about 3×10atoms/cm, and the dopant concentration of boron in the blocking epitaxial layermay be in a range of about 8×10atoms/cmto about 3×10atoms/cm. The dopant concentration of boron in the main epitaxial layermay be in a range of about 6×10atoms/cmto about 2×10atoms/cm, and the dopant concentration of boron in the capping layermay be in a range of about 0 atoms/cmto about 3×10atoms/cm.

In some example embodiments, the IC devicemay include a nanosheet transistor (refer to TR in) including an NMOS transistor, and each of the plurality of source/drain regionsmay include a silicon (Si) layer doped with an n-type dopant.

When the IC deviceincludes the nanosheet transistor (refer to TR in) including the NMOS transistor and each of the plurality of source/drain regionsincludes a Si layer doped with an n-type dopant, in each of the plurality of source/drain regions, the concentration of the n-type dopants in the bottom epitaxial layermay be greater than the concentration of the n-type dopants in each of the blocking epitaxial layerand the capping layerand be greater than the concentration of the n-type dopant in the main epitaxial layer. The n-type dopant may include at least one selected from phosphorus (P), arsenic (As), and antimony (Sb), without being limited thereto. A dopant concentration of each of phosphorus, arsenic, and antimony may be the same as each other, or a dopant concentration of at least one of phosphorus, arsenic, and antimony may be different from (greater than or less than) others of phosphorus, arsenic, and antimony.

For example, the plurality of source/drain regionsmay include phosphorus (P) as the n-type dopant. In this case, in each of the plurality of source/drain regions, the dopant concentration of phosphorus (P) in the bottom epitaxial layermay be in a range of about 8×10atoms/cmto about 6×10atoms/cm, and the dopant concentration of phosphorus in the blocking epitaxial layermay be in a range of about 1×10atoms/cmto about 1×10atoms/cm. The dopant concentration of phosphorus in the main epitaxial layermay be in a range of about 1×10atoms/cmto about 4×10atoms/cm, and the dopant concentration of phosphorus in the capping layermay be in a range of about 1×10to about 5×10atoms/cm.

As shown in, the backside via contact BCA and the backside metal silicide filmmay pass through a portion of the bottom epitaxial layerof the corresponding one of the source/drain regionsin the vertical direction (Z direction). The backside metal silicide filmmay be in contact with the bottom epitaxial layerof the corresponding one of the source/drain regions. Accordingly, the backside via contact BCA may be configured to be connected to the corresponding one of the source/drain regionsthrough the backside metal silicide film. As described above, the backside metal silicide filmlocated between the backside via contact BCA and the source/drain regionmay have a structure that contacts the bottom epitaxial layer, which has a highest dopant concentration in the source/drain region. As a result, a Schottky barrier height between the backside via contact BCA and the source/drain regionmay be reduced, and thus, resistance between the backside via contact BCA and the source/drain regionmay be reduced. Therefore, the electrical reliability of the IC devicemay be improved by suppressing or reducing an increase in contact resistance between the backside via contact BCA and the source/drain region.

As shown in, in each of the plurality of source/drain regions, the main epitaxial layermay be in contact with each of the bottom epitaxial layerand the blocking epitaxial layer. The bottom epitaxial layermay include an upper surface that is inclined in a direction close to the top surface of the front side of the corresponding one of the source/drain regionstoward the central portion thereof in the first lateral direction (X direction), and the top surface of the bottom epitaxial layermay include a first facetFhaving a {} plane orientation.

As shown in, the bottom epitaxial layermay further include a second facetFand a third facetF. The second facetFmay be inclined in a direction close to the top surface of the front side of the corresponding one of the source/drain regionstoward the central portion thereof in the second lateral direction (Y direction). The third facetFmay extend in the second lateral direction (Y direction). The second facetFof the bottom epitaxial layermay have a {} plane orientation, and the third facetFof the bottom epitaxial layermay have a {} plane orientation.

As shown in, a portion of the first facetFof the bottom epitaxial layermay be in contact with the blocking epitaxial layer, and another portion of the first facetFof the bottom epitaxial layermay be in contact with the main epitaxial layer. The upper surface of the bottom epitaxial layermay include a vertex portionP where two first facetsFhaving different inclination directions meet each other. The main epitaxial layermay include a portion that fills a corner space defined by the bottom epitaxial layerand the blocking epitaxial layerat a location adjacent to a portion where the bottom epitaxial layercontacts the blocking epitaxial layer. The main epitaxial layermay include a portion surrounding the vertex portionP of the bottom epitaxial layer.

As shown in, the frontside source/drain contact CA may pass through the frontside insulating structure including the insulating linerand the inter-gate dielectric filmin the vertical direction (Z direction), and the frontside source/drain contact CA and the frontside metal silicide filmmay pass through a portion of the corresponding one of the source/drain regionsin the vertical direction (Z direction) from the front side of the corresponding one of the source/drain regions.

The frontside source/drain contact CA and the frontside metal silicide filmmay be apart from the bottom epitaxial layerof the corresponding one of the source/drain regionsin the vertical direction (Z direction). The frontside metal silicide filmmay be in contact with the main epitaxial layerof the corresponding one of the source/drain regions, and the frontside source/drain contact CA may be configured to be connected to the main epitaxial layerof the corresponding one of the source/drain regionsthrough the frontside metal silicide film.

As shown in, in the plurality of source/drain regionsincluded in the IC device, the source/drain region(or the first source/drain region) connected to the backside via contact BCA may be different from the source/drain region(or the second source/drain region) connected to the frontside source/drain contact CA. That is, the source/drain region(or the first source/drain region) connected to the backside via contact BCA may be apart from the source/drain region(or the second source/drain region) connected to the frontside source/drain contact CA. However, inventive concepts are not limited thereto. For example, the frontside source/drain contact CA and the backside via contact BCA may be configured to be connected to one common source/drain region.

As shown in, the IC devicemay include a plurality of backside bulk insulating films BBI and a plurality of backside power rails MPR. The plurality of backside bulk insulating films BBI may be arranged in a line in the first lateral direction (X direction) and each extend lengthwise in the second lateral direction (Y direction). The plurality of backside power rails MPR may be separated from each other by the plurality of backside bulk insulating films BBI in the first lateral direction (X direction). As shown in, each of the plurality of backside power rails MPR may be between two adjacent ones of the plurality of backside bulk insulating films BBI in the first lateral direction (X direction). The backside via contact BCA may be integrally connected to a selected one of the plurality of backside power rails MPR.

In the IC device, the plurality of nanosheet stacks NSS may be apart from the plurality of backside bulk insulating films BBI in the vertical direction (Z direction). The blocking epitaxial layerof each of the plurality of source/drain regionsmay be in contact with the first to fourth nanosheets N, N, N, and Nincluded in the nanosheet stack NSS adjacent thereto, from among the plurality of nanosheet stacks NSS.

Each of the plurality of backside bulk insulating films BBI may be in contact with a pair of backside power rails MPR, which are adjacent to each other and selected from the plurality of backside power rails MPR. Each of the plurality of backside bulk insulating films BBI may extend lengthwise in the vertical direction (Z direction) from a space between the pair of backside power rails MPR, which are adjacent to each other, toward a selected one of the plurality of gate lines. In some example embodiments, each of the plurality of backside bulk insulating films BBI may include a nitrogen (N)-containing insulating film. For example, each of the plurality of backside bulk insulating films BBI may include one or more of a silicon nitride (SiN) film, a silicon carbonitride (SiCN) film, a silicon oxycarbonitride (SiOCN) film, without being limited thereto.