Semiconductor Device

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2024-098263, filed on Jun. 18, 2024, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a semiconductor device.

In order to reduce the size of a transistor or improve the performance of a transistor, a vertical transistor is used in which a gate electrode is buried in a trench. In the vertical transistor, there is a trade-off between the drain-source breakdown voltage (hereinafter, also simply referred to as “breakdown voltage”) and the on-resistance. That is, if the impurity concentration in the drift region is increased in order to reduce the on-resistance, the breakdown voltage decreases. Conversely, if the impurity concentration in the drift region is reduced in order to increase the breakdown voltage, the on-resistance increases.

As a structure to solve the trade-off between the breakdown voltage and the on-resistance, a field plate electrode is provided in the trench of a vertical transistor. By changing the electric field distribution in the drift region using the field plate electrode, it is possible to increase the impurity concentration in the drift region while maintaining the breakdown voltage, for example. Therefore, for example, it is possible to reduce the on-resistance while maintaining the breakdown voltage.

By providing the field plate electrode, a capacitance is added between the gate electrode and the field plate electrode, which may increase the gate capacitance. In order to realize high-speed transistors, it is desirable to reduce the gate capacitance.

A semiconductor device of embodiments includes: a first electrode; a second electrode; a semiconductor layer provided between the first electrode and the second electrode, having a first face facing the first electrode and a second face facing the second electrode, and including a first semiconductor region of a first conductive type electrically connected to the second electrode, a second semiconductor region of a second conductive type provided between the first semiconductor region and the first face, and a third semiconductor region of the first conductive type provided between the second semiconductor region and the first face and electrically connected to the first electrode; a gate electrode including a first portion provided in the semiconductor layer and extending in a first direction parallel to the first face and a second portion disposed in a second direction parallel to the first face and perpendicular to the first direction with respect to the first portion; a field plate electrode provided in the semiconductor layer, provided between the gate electrode and the second face, and electrically connected to the first electrode; a conductive layer provided in the semiconductor layer, provided between the first portion and the second portion, and electrically separated from the first electrode; a gate insulating layer provided between the gate electrode and the semiconductor layer; a field plate insulating layer provided between the field plate electrode and the semiconductor layer; a first insulating layer provided between the conductive layer and the field plate electrode; a second insulating layer provided between the first portion and the conductive layer; and a third insulating layer provided between the second portion and the conductive layer. A first distance in the first direction between an end of the field plate insulating layer in the first direction on the first face and the conductive layer is smaller than a second distance between the end and the gate electrode in the first direction.

Hereinafter, embodiments will be described with reference to the diagrams. In addition, in the following description, the same or similar members and the like are denoted by the same reference numerals, and the description of the members and the like once described will be omitted as appropriate.

In this specification, when there are notations of n-type, n-type, and n-type, this means that the n-type impurity concentration decreases in the order of n-type, n-type, and n-type. In addition, when there are notations of p-type, p-type, and p-type, this means that the p-type impurity concentration decreases in the order of p-type, p-type, and p-type.

The impurity concentration in a semiconductor device can be measured by, for example, secondary ion mass spectrometry (SIMS). In addition, the relative high and low of the impurity concentration in the semiconductor device can be determined from, for example, the high and low of the carrier concentration obtained by scanning capacitance microscopy (SCM). In addition, the distance such as the width or depth of an impurity region in the semiconductor device can be calculated by, for example, SIMS. In addition, the distance such as the width or depth of an impurity region in the semiconductor device can be calculated from, for example, an SCM image.

The qualitative analysis and quantitative analysis of the chemical composition of members forming the semiconductor device in this specification can be performed by, for example, SIMS, energy dispersive X-ray spectroscopy (EDX), and Rutherford back-scattering spectroscopy (RBS). In addition, when measuring the thickness of each member forming the semiconductor device, a distance between members, and the like, for example, a scanning electron microscope (SEM) or a transmission electron microscope (TEM) can be used.

A semiconductor device according to a first embodiment includes: a first electrode; a second electrode; a semiconductor layer provided between the first electrode and the second electrode, having a first face facing the first electrode and a second face facing the second electrode, and including a first semiconductor region of a first conductive type electrically connected to the second electrode, a second semiconductor region of a second conductive type provided between the first semiconductor region and the first face, and a third semiconductor region of the first conductive type provided between the second semiconductor region and the first face and electrically connected to the first electrode; a gate electrode including a first portion provided in the semiconductor layer and extending in a first direction parallel to the first face and a second portion disposed in a second direction parallel to the first face and perpendicular to the first direction with respect to the first portion; a field plate electrode provided in the semiconductor layer, provided between the gate electrode and the second face, and electrically connected to the first electrode; a conductive layer provided in the semiconductor layer, provided between the first portion and the second portion, and electrically separated from the first electrode; a gate insulating layer provided between the gate electrode and the semiconductor layer; a field plate insulating layer provided between the field plate electrode and the semiconductor layer; a first insulating layer provided between the conductive layer and the field plate electrode; a second insulating layer provided between the first portion and the conductive layer; and a third insulating layer provided between the second portion and the conductive layer. A first distance in the first direction between an end of the field plate insulating layer in the first direction on the first face and the conductive layer is smaller than a second distance between the end and the gate electrode in the first direction.

Hereinafter, a case where the first conductive type is n-type and the second conductive type is p-type will be described as an example. Hereinafter, a case where the semiconductor device is an n-channel metal oxide semiconductor field effect transistor (MOSFET) having electrons as carriers will be described as an example.

The semiconductor device according to the first embodiment is a MOSFET. The MOSFETis a vertical trench gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

The trench in this specification is a groove-shaped or concave structure that the semiconductor layer itself has. Therefore, components other than the semiconductor layer can be provided inside the trench. The trench is a part of the semiconductor layer.

are schematic diagrams of the semiconductor device according to the first embodiment.is the surface side of the MOSFET.is the back surface side of the MOSFET.

As shown in, a source electrode, a source electrode wiring, a gate electrode pad, and a gate electrode wiringare provided on the front surface side of the MOSFET.

The source electrode wiringis physically and electrically connected to the source electrode. The source electrode wiringextends in the second direction.

The gate electrode wiringis physically and electrically connected to the gate electrode pad. The gate electrode wiringextends in the second direction. The gate electrode wiringis provided between the source electrode wiringand the source electrodein the first direction.

As shown in, a drain electrodeis provided on the back surface side of the MOSFET.

A plurality of transistors are provided below the source electrode. The gate electrode padand the gate electrode wiringare electrically connected to the gate electrode of the transistor. A gate voltage for controlling the switching operation of the transistor is applied to the gate electrode pad.

is a schematic cross-sectional view of a part of the semiconductor device according to the first embodiment.is a cross-sectional view taken along the line AA′ of.is a cross-sectional view taken along the line AA′ of.

is a schematic top view of a part of the semiconductor device according to the first embodiment.is a top view of a portion indicated by the dotted line in.is a top view including a portion corresponding to.is a diagram of a position corresponding to a first face Fof a semiconductor layer.is a diagram excluding components above the first face F.

are schematic cross-sectional views of a part of the semiconductor device according to the first embodiment.is a cross-sectional view taken along the line BB′ of.is a cross-sectional view taken along the line CC′ of.is a cross-sectional view taken along the line DD′ of.is a cross-sectional view taken along the line EE′ of.is a cross-sectional view taken along the line FF′ of.

The MOSFETincludes the source electrode(first electrode), the drain electrode(second electrode), the semiconductor layer, a gate electrode, a gate insulating layer, a field plate electrode, a field plate insulating layer, a conductive layer, a first interelectrode insulating layer(first insulating layer), a second interelectrode insulating layer(second insulating layer), a third interelectrode insulating layer(third insulating layer), and an interlayer insulating layer.

The source electrodeincludes a source contact plug. The source electrode wiringincludes a field plate contact plug. The gate electrode wiringincludes a gate contact plug

The semiconductor layerincludes a trench, an n-type drain region, an n-type drift region(first semiconductor region), a p-type body region(second semiconductor region), and an n-type source region(third semiconductor region).

The gate electrodeincludes a first portion, a second portion, and a third portion

The semiconductor layeris provided between the source electrodeand the drain electrode. The semiconductor layerincludes a first face (“F” in) and a second face (“F” in). The second face Fis opposite to the first face F.

The first face Ffaces source electrode. The second face Ffaces the drain electrode.

The first direction and the second direction are directions parallel to the first face F. The second direction is a direction perpendicular to the first direction. In addition, the third direction is a direction perpendicular to the first face F. The third direction is a direction perpendicular to the first direction and the second direction.

Hereinafter, “depth” means a depth with respect to the first face F. That is, “depth” means a distance in the third direction with respect to the first face F.

The semiconductor layeris, for example, single crystal silicon (Si). When the semiconductor layeris formed of single crystal silicon, the surface of the semiconductor layeris a face inclined at an angle equal to or more than 0° and equal to or less than 8° with respect to the (100)-face, for example.

The n-type drain regionis provided in the semiconductor layer. The drain regionis in contact with the second face F. The drain regionis in contact with the drain electrode. The drain regionis electrically connected to the drain electrode.

The drain regioncontains n-type impurities. The n-type impurity is, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration is equal to or more than 1×10cmand equal to or less than 1×10cm, for example.

The n-type drift regionis provided in the semiconductor layer. The drift regionis provided between the drain regionand the first face F. The drift regionis provided on the drain region. The drift regionfunctions as a current path when the MOSFETis turned on.

The drift regioncontains n-type impurities. The n-type impurity is, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration is, for example, equal to or more than 1×10cmand equal to or less than 1×10cm.

The thickness of the drift regionin the third direction is, for example, equal to or more than 5 μm and equal to or less than 15 μm.

The p-type body regionis provided in the semiconductor layer. The body regionis provided between the drift regionand the first face F.

The body regionis provided between two adjacent trenches.

The body regionis in contact with, for example, the source electrode. The body regionis electrically connected to, for example, the source electrode. For example, as shown in, the body regionis electrically connected to the source electrodeusing the source contact plug. The source contact plugis in contact with the body region.

When the MOSFETis turned on, a channel of an inversion layer is formed in the body regionfacing the gate electrode.

The body regioncontains p-type impurities. The p-type impurity is, for example, boron (B). The p-type impurity concentration is, for example, equal to or more than 1×10cmand equal to or less than 1×10cm.

The n-type source regionis provided in the semiconductor layer. The source regionis provided between the body regionand the first face F.

The source regionis in contact with the first face F. The source regionis in contact with the source electrode. The source regionis electrically connected to the source electrode. For example, as shown in, the source regionis electrically connected to the source electrodeusing the source contact plug. The source contact plugis in contact with the source electrode.

The source regionis provided between two adjacent trenches.

The source regioncontains n-type impurities. The n-type impurity is, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration is, for example, equal to or more than 1×10cmand equal to or less than 1×10cm.

The trenchis provided in the semiconductor layer. The trenchis disposed on the first face Fside of the semiconductor layer. The trenchis a groove formed in the semiconductor layer.

As shown in, the trenchextends in the first direction. A plurality of trenchesare repeatedly arranged in the second direction. For example, a plurality of trenchesare repeatedly arranged at predetermined pitches in the second direction.

The trenchpenetrates the body regionand reaches the drift region. The depth of the trenchis, for example, equal to or more than 1 μm and equal to or less than 5 μm. The width of the trenchin the second direction is, for example, equal to or more than 0.3 μm and equal to or less than 1 μm.

The gate electrodeis provided in the semiconductor layer. The gate electrodeis provided between a part of the semiconductor layerand another part of the semiconductor layer. The gate electrodeis provided in the trench. The gate electrodeincludes the first portion, the second portion, and the third portion