Magnetoresistive Random Access Memory Device and Manufacturing Method Thereof

The present invention relates to a memory device and a manufacturing method thereof, and more particularly, to a magnetoresistive random access memory device and a manufacturing method thereof.

There are essentially two types of data memory devices used in electronic products, non-volatile and volatile memory devices. Magnetic random access memory is a kind of non-volatile memory technology. Unlike current industry-standard memory devices, the magnetic random access memory uses magnetism instead of electrical charges to store data. In general, magnetic random access memory cells include a data layer and a reference layer. The data layer is composed of a magnetic material and the magnetization of the data layer can be switched between two opposing states by an applied magnetic field for storing binary information. The reference layer can be composed of a magnetic material in which the magnetization is pinned so that the strength of the magnetic field applied to the data layer and partially penetrating the reference layer is insufficient for switching the magnetization in the reference layer. During the read operation, the resistance of the magnetic random access memory cell is different when the magnetization alignments of the data layer and the reference layer are the same or not, and the magnetization polarity of the data layer can be identified accordingly. The structure of magnetic random access memory devices will vary depending on the technology used to magnetize the data layer. Currently, spin-transfer torque (STT) magnetic random access memory and spin-orbit torque (SOT) magnetic random access memory are relatively common technology. In addition, the manufacturing process of the magnetic random access memory may be integrated with the back end of line (BEOL) process of the semiconductor manufacturing process, and the integration with the BEOL process is influenced by the design variations of the magnetic random access memory. Therefore, how to improve the manufacturing process integration of the magnetic random access memory device through structures and/or process design is an ongoing research direction for people in related fields.

A magnetoresistive random access memory (MRAM) device and a manufacturing method thereof are provided in the present invention. A connection structure located corresponding to a magnetic tunneling junction (MTJ) structure penetrates through a second cap layer, an oxide layer, and a first cap layer vertically for improving the manufacturing process integration of the MRAM device.

According to an embodiment of the present invention, a magnetoresistive random access memory (MRAM) device is provided. The MRAM device includes a magnetic tunneling junction (MTJ) structure, a spin-orbit torque (SOT) layer, a first cap layer, an oxide layer, a second cap layer, and a connection structure. The MTJ structure and the SOT layer are disposed above a substrate, and the MTJ structure is located on the SOT layer. The first cap layer is disposed adjacent to the MTJ structure, the oxide layer is disposed on the first cap layer, and the second cap layer is disposed on the oxide layer. The first cap layer, the oxide layer, and the second cap layer are partly disposed above the MTJ structure in a vertical direction. The connection structure is disposed above the MTJ structure and penetrates through the second cap layer, the oxide layer, and the first cap layer vertically.

According to another embodiment of the present invention, a manufacturing method of a magnetoresistive random access memory (MRAM) device is provided. The manufacturing method includes the following steps. A magnetic tunneling junction (MTJ) structure is formed above a substrate. A spin-orbit torque (SOT) layer is formed above the substrate, and the MTJ structure is located on the SOT layer. A first cap layer is formed adjacent to the MTJ structure, an oxide layer is formed on the first cap layer, and a second cap layer is formed on the oxide layer. The first cap layer, the oxide layer, and the second cap layer are partly located above the MTJ structure in a vertical direction. A connection structure is formed above the MTJ structure, and the connection structure penetrates through the second cap layer, the oxide layer, and the first cap layer vertically.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

The present invention has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth herein below are to be taken as illustrative rather than limiting. It should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the present invention.

Before the further description of the preferred embodiment, the specific terms used throughout the text will be described below.

The terms “on,” “above,” and “over” used herein should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something).

The term “etch” is used herein to describe the process of patterning a material layer so that at least a portion of the material layer after etching is retained. When “etching” a material layer, at least a portion of the material layer is retained after the end of the treatment. In contrast, when the material layer is “removed”, substantially all the material layer is removed in the process. However, in some embodiments, “removal” is considered to be a broad term and may include etching.

The term “forming” or the term “disposing” are used hereinafter to describe the behavior of applying a layer of material to the substrate. Such terms are intended to describe any possible layer forming techniques including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

Please refer to.is a schematic drawing illustrating a magnetoresistive random access memory (MRAM) deviceaccording to an embodiment of the present invention. As shown in, the MRAM deviceincludes a magnetic tunneling junction (MTJ) structure (such as a MTJ structure), a spin-orbit torque (SOT) layer (such as a SOT layer), a first cap layer, an oxide layer, a second cap layer, and a connection structure. The MTJ structureand the SOT layerare disposed above a substrate, and the MTJ structureis located on the SOT layer. The first cap layeris disposed adjacent to the MTJ structure, the oxide layeris disposed on the first cap layer, and the second cap layeris disposed on the oxide layer. The first cap layer, the oxide layer, and the second cap layerare partly disposed above the MTJ structurein a vertical direction D. The connection structureis disposed above the MTJ structureand penetrates through the second cap layer, the oxide layer, and the first cap layervertically. The first cap layer, the oxide layer, and the second cap layerare formed above the MTJ structure, and the connection structurepenetrates through the second cap layer, the oxide layer, and the first cap layervertically for improving manufacturing process integration between the connection structureand structures on other regions. The related manufacturing yield may be enhanced accordingly.

In some embodiments, the vertical direction Dmay be regarded as a thickness direction of the substrate. The substratemay have a top surfaceTS and a bottom surfaceBS opposite to the top surfaceTS in the vertical direction D, and the MTJ structures, the SOT layer, the first cap layer, the oxide layer, the second cap layer, and the connection structuredescribed above may be disposed at the side of the top surfaceTS. A horizontal direction substantially orthogonal to the vertical direction D(such as a horizontal direction D) may be substantially parallel with the top surfaceTS and/or the bottom surfaceBS of the substrate, but not limited thereto. In this description, a distance between the bottom surfaceBS of the substrateand a relatively higher location and/or a relatively higher part in the vertical direction Dmay be greater than a distance between the bottom surfaceBS of the substrateand a relatively lower location and/or a relatively lower part in the vertical direction D. The bottom or a lower portion of each component may be closer to the bottom surfaceBS of the substratein the vertical direction Dthan the top or upper portion of this component. Another component disposed above a specific component may be regarded as being relatively far from the bottom surfaceBS of the substratein the vertical direction D, and another component disposed under a specific component may be regarded as being relatively close to the bottom surfaceBS of the substratein the vertical direction D. It is worth noting that, in this description, a top surface of a specific component may include the topmost surface of this component in the vertical direction D, and a bottom surface of a specific component may include the bottommost surface of this component in the vertical direction D, but not limited thereto. Additionally, in this description, the condition that a certain component is disposed between two other components in a specific direction may include but is not limited to a condition that the certain component is sandwiched between the two other components in the specific direction.

In some embodiments, the substratemay include a memory region Rand a logic region R. The MTJ structure, the SOT layer, and the connection structuredescribed above may be disposed above the memory region R, and the memory region Rmay be regarded as a MRAM cell region, but not limited thereto. In some embodiments, the MRAM devicemay further include a bottom electrode, a cap layer, and a top electrode. The bottom electrodemay be disposed between the SOT layerand the substratein the vertical direction D, the top electrodeis disposed on the MTJ structurein the vertical direction D, and the cap layermay be disposed between the top electrodeand the MTJ structurein the vertical direction D. The first cap layer, the oxide layer, and the second cap layermay be partly located above the top electrodein the vertical direction D, and the connection structuremay penetrate through the second cap layer, the oxide layer, and the first cap layervertically for contacting and being electrically connected with the top electrode.

In some embodiments, the MRAM devicemay further include a dielectric layer, a dielectric layer, a plurality of connection structures, a stop layer, a dielectric layer, and a plurality of connection structures. The dielectric layerand the dielectric layermay be disposed above the memory region Rand the logic region R, the dielectric layeris disposed on the dielectric layer, and the connection structuresare disposed in the dielectric layer. The stop layermay cover the connection structuresand the dielectric layerlocated on the memory region Rand the logic region R, and the dielectric layeris disposed on the stop layerand located on the memory region Rand the logic region R. The connection structuresmay be disposed in the dielectric layerand the stop layerlocated on the memory region R, and the bottom electrodemay be disposed on the dielectric layerand electrically connected with two of the connection structures, but not limited thereto. In some embodiments, the connection structureand the connection structuremay be regarded as a trench conductor and a via conductor, respectively, but not limited thereto.

In some embodiments, the substratemay include a semiconductor substrate or a non-semiconductor substrate. The semiconductor substrate may include a silicon substrate, a silicon germanium semiconductor substrate or a silicon-on-insulator (SOI) substrate, and the non-semiconductor substrate may include a glass substrate, a plastic substrate, or a ceramic substrate, but not limited thereto. For example, when the substrateincludes a semiconductor substrate, a plurality of field effect transistors (not shown), a dielectric layer covering the field effect transistors (such as the dielectric layerand the dielectric layer), and the connection structureselectrically connected with the field effect transistors may be disposed on the semiconductor substrate according to some considerations, and the connection structureelectrically connected with the bottom electrodemay be electrically connected with specific transistor via the corresponding connection structure, but not limited thereto. In some embodiments, electrical current may be formed in the bottom electrodevia the two connection structuresconnected with the bottom electrode, and the magnetic moment and the magnetization effect influencing the MTJ structuremay be formed by the electrical current passing through the SOT layer. In addition, the MTJ structuresmay include a free layer, a barrier layer, and a reference layerstacked sequentially from bottom to top, but not limited thereto. The top electrodemay be directly above the MTJ structureand the cap layerin the vertical direction D, and a top surfaceTS of the top electrodemay include a curved surface because of the influence of the manufacturing process characteristics, but not limited thereto. In some embodiments, the first cap layermay cover and contact a top surface of the SOT layer, a sidewall of the MTJ structure, and a surface of the top electrode, and a bottom surface of the first cap layer(such as a bottom surfaceBS of the first cap layerlocated on the SOT layerin the vertical direction Dand directly contacting the SOT layer) may be lower than the top surfaceTS of the top electrodein the vertical direction D, but not limited thereto. In some embodiments, a protection layer (not illustrated) may be disposed between the sidewall of the MTJ structureand the first cap layer, and the protection layer may be formed in the process of forming the MTJ structureconcurrently, but not limited thereto.

In some embodiments, because of the influence of related processes, a top surface of the SOT layerwithout being covered by the MTJ structurein the vertical direction Dmay be slightly lower than a top surface of the SOT layerlocated under the MTJ structurein the vertical direction D, but not limited thereto. Additionally, because of the influence of the top surfaceTS of the top electrode, the top surfaces of the first cap layer, the oxide layer, and the second cap layermay include curved surfaces also. The oxide layermay directly contact the first cap layer, and a sidewallSW of the oxide layer, a sidewallSW of the first cap layer, a sidewallSW of the SOT layer, and a sidewallSW of the bottom electrodemay be substantially aligned with one another (such as being aligned with one another in the horizontal direction D) and/or flush with one another, but not limited thereto. In addition, because of the influence of related processes, a top surface of the dielectric layerwithout being covered by the bottom electrodein the vertical direction Dmay be lower than a top surface of the dielectric layerlocated under the bottom electrodein the vertical direction D, and the second cap layermay be disposed conformally on and directly contact the top surface and the sidewallSW of the oxide layer, the sidewallSW of the first cap layer, the sidewallSW of the SOT layer, the sidewallSW of the bottom electrode, and the dielectric layer. Therefore, a bottom surface of the second cap layer(such as a bottom surfaceBS of the second cap layerlocated on the dielectric layerin the vertical direction Dand directly contacting the dielectric layer) may be lower than the bottom surfaceBS of the first cap layerin the vertical direction D. The bottom surfaceBS of the first cap layer, a bottom surfaceBS of the oxide layer, and the bottom surfaceBS of the second cap layermay be lower than the top surfaceTS of the top electrodein the vertical direction D.

In some embodiments, a material composition of the oxide layermay be different from a material composition of the first cap layerand a material composition of the second cap layer, and the material composition of the first cap layermay be identical to the material composition of the second cap layer, but not limited thereto. For example, the oxide layermay include silicon oxide, such as tetraethoxysilane (TEOS) or other suitable oxide dielectric materials, and the first cap layerand the second cap layermay include silicon nitride or other suitable cap materials. In addition, the oxide layerlocated above the MTJ structureis sandwiched between the first cap layerand the second cap layerin the vertical direction D, and the top surface of the first cap layer, the top surface of the oxide layer, and a top surface of the second cap layermay be higher than the top surfaceTS of the top electrodein the vertical direction Daccordingly. In addition, the first cap layer, the oxide layer, and the second cap layermay surround the sidewall of the MTJ structure, the sidewall of the cap layer, and the sidewall of the top electrodein the horizontal direction (such as the horizontal direction D, but not limited thereto), and a part of the oxide layermay be sandwiched between the first cap layerand the second cap layerin the horizontal direction. In some embodiments, the MRAM devicemay further include an interlayer dielectric layer, an interconnection structure, and a stop layer. The interlayer dielectric layeris disposed above the memory region Rand the logic region R. The interlayer dielectric layerlocated above the memory region Rmay be disposed on the second cap layer, and the interlayer dielectric layerlocated above the logic region Rmay be disposed on and directly contacting the dielectric layer. In some embodiments, because of the influence of the related processes, the top surface of the dielectric layerlocated above the logic region Rmay be lower than the top surface of the dielectric layerlocated above the memory region R. The thickness of the interlayer dielectric layerlocated above the logic region Rmay be greater than the thickness of the interlayer dielectric layerlocated above the memory region R, and the top surface of the interlayer dielectric layerlocated above the memory region Rand the top surface of the interlayer dielectric layerlocated above the logic region Rmay be substantially coplanar. The interconnection structuremay include a dual damascene structure or other suitable structures, and the interconnection structuremay be disposed above the logic region Rand penetrate through the interlayer dielectric layer, the dielectric layer, and the stop layerin the vertical direction Dfor contacting and being electrically connected with the connection structurelocated corresponding to the interconnection structure. In some embodiments, the top surface of the connection structure, the top surface of the interconnection structure, and the top surface of the interlayer dielectric layermay be substantially coplanar, and the stop layermay be disposed on and contact the top surfaces of the connection structure, the interconnection structure, and the interlayer dielectric layer.

In some embodiments, the dielectric layer, the dielectric layer, and the dielectric layermay include an oxide dielectric material, a low dielectric constant dielectric material (such as a dielectric material with dielectric constant lower than 2.9, but not limited thereto), or other suitable dielectric materials. The interlayer dielectric layermay include a low dielectric constant dielectric material or an ultra-low dielectric constant (ULK) dielectric material (such as a dielectric material with dielectric constant lower than 2.7, but not limited thereto), and a dielectric constant of the interlayer dielectric layermay be lower than a dielectric constant of the oxide layer, but not limited thereto. In some embodiments, the connection structure, the connection structure, the connection structure, and the interconnection structuremay respectively include a barrier layer and an electrically conductive material disposed on the barrier layer. The barrier layer may include titanium (Ti), titanium nitride, tantalum (Ta), tantalum nitride, or other suitable electrically conductive battier materials, and the electrically conductive material may include tungsten (W), copper (Cu), aluminum (Al), titanium aluminide, cobalt tungsten phosphide, or other suitable electrically conductive materials with relatively low electrical resistivity. For example, the connection structuremay include a barrier layerand an electrically conductive materialdisposed on the barrier layer, and the connection structuremay include a barrier layerand an electrically conductive materialdisposed on the barrier layer, but not limited thereto. The stop layerand the stop layermay include nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or other suitable materials. The bottom electrodemay include tantalum, tantalum nitride, platinum (Pt), copper, gold (Au), aluminum, or other suitable electrically conductive materials. The top electrodemay include tantalum, tantalum nitride, titanium, titanium nitride, platinum, copper, gold, aluminum, or other suitable electrically conductive materials. The cap layermay include ruthenium (Ru), or other suitable electrically conductive materials.

The SOT layermay include a SOT material, and the SOT material may be defined as a material capable of generating the spin Hall effect and/or a material with greater spin-orbit coupling strength, so as to generate spin-orbit torque on the free layerand change the direction of the magnetic torque of the free layer. For example, the SOT material may include hafnium (Hf), rhenium (Re), ruthenium, gold, platinum, tantalum, tungsten, iridium (Ir), palladium (Pd), an alloy of the materials described above (such as IrPt, PtAu, PtPd, BiSb, and so forth), a compound of the materials described above (such as PrS, WTe, and so forth), or other suitable materials (such as BiSb and BiSe). The free layerand the reference layermay include ferromagnetic materials, such as iron, cobalt, nickel, cobalt-iron (CoFe), cobalt-iron-boron (CoFeB), or other suitable ferromagnetic materials. In some embodiments, the reference layerand an antiferromagnetic layer (not illustrated) may constitute a pinned layer with fixed direction of magnetic torque. The antiferromagnetic layer may include antiferromagnetic materials, such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), a cobalt/platinum (Co/Pt) multilayer, or other suitable antiferromagnetic materials. The barrier layermay include insulation materials, such as magnesium oxide (MgO), aluminum oxide, or other suitable insulation materials.

Please refer to.are schematic drawings illustrating a manufacturing method of a magnetoresistive random access memory device according to an embodiment of the present invention, whereinis a schematic drawing in a step subsequent to,is a schematic drawing in a step subsequent to,is a schematic drawing in a step subsequent to,is a schematic drawing in a step subsequent to,is a schematic drawing in a step subsequent to,is a schematic drawing in a step subsequent to,is a schematic drawing in a step subsequent to,is a schematic drawing in a step subsequent to, andis a schematic drawing in a step subsequent to. In some embodiments,may be regarded as a schematic drawing in a step subsequent to, but not limited thereto. As shown in, the manufacturing method in this embodiment includes the following steps. The magnetic tunneling junction (MTJ) structure (such as the MTJ structure) and the spin-orbit torque (SOT) layer (such as the SOT layer) are formed above the substrate, and the MTJ structureis located on the SOT layer. The first cap layeris formed adjacent to the MTJ structure, the oxide layeris formed on the first cap layer, and the second cap layeris formed on the oxide layer. The first cap layer, the oxide layer, and the second cap layerare partly located above the MTJ structurein the vertical direction D. The connection structureis formed above the MTJ structure, and the connection structurepenetrates through the second cap layer, the oxide layer, and the first cap layervertically.

Specifically, the manufacturing method in this embodiment may include but is not limited to the following steps. As shown in, active components (such as the transistors described above), passive components, or other required circuit structures may be formed on the substrate, and the dielectric layer, the dielectric layer, the connection structures, the stop layer, the dielectric layer, and the connection structuresdescribed above may then be formed. Subsequently, an electrically conductive materialM, a SOT materialM, a ferromagnetic materialM, a barrier materialM, a ferromagnetic materialM, and a cap materialM may be sequentially formed above the memory region Rand the logic region Rof the substrate. Afterwards, a patterned electrically conductive materialP may be formed on the cap materialM located above the memory region R. In some embodiments, an electrically conductive material may be formed on the cap materialM, a mask layermay be formed on this electrically conductive material, and a patterning process using a patterned mask layer (such as a patterned photoresist layer, not illustrated) as a mask (such as a reactive ion etching (RIE) process, but not limited thereto) may then be performed to the mask layerand the electrically conductive material for forming the patterned electrically conductive materialP. The mask layermay be removed after this patterning process or remain on the patterned electrically conductive materialP after this patterning process. The mask layermay include an oxide mask material (such as silicon oxide) or other suitable mask materials. As shown inand, an etching processusing the patterned electrically conductive materialP and/or the mask layeras a mask may then be performed for removing a part of the cap materialM, a part of the ferromagnetic materialM, a part of the barrier materialM, and a part of the ferromagnetic materialM and forming the MTJ structureincluding the reference layer, the barrier layer, and the free layerand the cap layeron the SOT materialM. In some embodiments, the etching processmay include an ion beam etching (IBE) process or other suitable etching approaches, and the patterned electrically conductive materialP may be partially etched by the etching processto be the top electrodelocated above the MTJ structure. Additionally, in some embodiments, the top electrodemay have a curved top surface protruding upwards by adjusting the process parameters of the etching processfor enhancing the sidewall etching efficiency in the IBE process, but not limited thereto. In some embodiments, the SOT materialM may be partly etching by the etching process, and a top surface of the SOT materialM without being covered by the MTJ structurein the vertical direction Dmay be slightly lower than a top surface of the SOT materialM located under the MTJ structurein the vertical direction D, but not limited thereto.

As shown in, after the MTJ structureand the top electrodeare formed, a cap materialM may be formed and an oxide materialM may be formed on the cap materialM. The cap materialM and the oxide materialM may be formed above the memory region Rand the logic region R. In some embodiments, after the etching process, a protection layer (not illustrated) may be formed by oxidizing the sidewall of the MTJ structurein-situ, and the cap materialM may be formed in-situ also after the protection layer is formed, but not limited thereto. The cap materialM may be formed on the top electrode, the MTJ structure, and the SOT materialM and cover the SOT materialM, the sidewall of the MTJ structure, and the top electrode. The cap materialM and the oxide materialM may have curved top surfaces protruding upwards because of the influence of the top electrode. Subsequently, as shown inand, an anti-reflection layer(such as a bottom anti-reflection layer, but not limited thereto) and a patterned mask layer(such as a patterned photoresist layer, but not limited thereto) may be formed on the oxide materialM, and an etching process(such as a RIE process, but not limited thereto) using the patterned mask layeras a mask may be performed. At least a part of the oxide materialM may be etched by the etching processto be a patterned oxide materialP formed on the cap materialM, and the oxide materialM located above the logic region Rand the anti-reflection layerlocated above the logic region Rmay be completely removed by the etching process. Additionally, the patterned mask layerand the remaining anti-reflection layermay be removed after the etching process. Because of the process characteristics of the etching process(such as loading effect, but not limited thereto), the cap materialM located above the logic region Rmay be partially etched by the etching process, and the top surface of the cap materialM located above the logic region Rmay be lower than the top surface of the cap materialM located above the memory region Rafter the etching processaccordingly, but not limited thereto.

Subsequently, as shown inand, an etching process(such as a small angle IBE process, but not limited thereto) using the patterned oxide materialP as a mask may be performed, and a part of the patterned oxide materialP may be located above the MTJ structureand the cap materialM in the vertical direction Dafter the etching process. In other words, the top surface of the cap materialM is not exposed by the etching process. In addition, the cap materialM may be etched to be the first cap layerby the etching process, the SOT materialM may be etched to be the SOT layerby the etching process, the electrically conductive materialM may be etched to be the bottom electrodeby the etching process, and the patterned oxide materialP may be partially etched to be the oxide layerby the etching process. In some embodiments, the electrically conductive materialM, the SOT materialM, and the cap materialM may be partly formed above the memory region Rand partly formed above the logic region R. The cap materialM, the SOT materialM, and the electrically conductive materialM located above the logic region Rmay be completely removed by the etching process, but not limited thereto. Additionally, in some embodiments, the dielectric layermay be partially etched by the etching process, and because of the influence of the process characteristics of the etching processand/or the difference in the material layers on the dielectric layer, the top surface of the dielectric layerlocated above the logic region Rmay be lower than the top surface of the dielectric layerlocated above the memory region Rafter the etching process, and the top surface of the dielectric layerlocated above the memory region Rwithout being covered by the bottom electrodemay be lower than the top surface of the dielectric layerunder the bottom electrodein the vertical direction D. In addition, the oxide layer, the first cap layer, the SOT layer, and the bottom electrodemay be formed concurrently by the etching process, and the sidewallSW of the oxide layer, the sidewallSW of the first cap layer, the sidewallSW of the SOT layer, and the sidewallSW of the bottom electrodemay be substantially aligned with one another (such as being aligned with one another in the horizontal direction D) and/or flush with one another accordingly, but not limited. It is worth noting that the method of forming the SOT layerin this invention may include but is not limited to the steps shown indescribed above, and the SOT layerillustrated in theandmay also be formed by other suitable approaches according to some design considerations.

Subsequently, as shown in, after the etching process, a cap materialM may be formed above the memory region Rand the logic region R. The cap materialM located above the logic region Rmay be formed on the dielectric layer, and the cap materialM located above the memory region Rmay cover the top surface and the sidewallSW of the oxide layer, the sidewallSW of the first cap layer, the sidewallSW of the SOT layer, the sidewallSW of the bottom electrode, and a part of the dielectric layer. In some embodiments, the cap materialM may be formed in-situ after the etching process, but not limited thereto. Subsequently, as shown inand, a patterned mask layer(such as a patterned photoresist layer, but not limited thereto) may be formed on the cap materialM located above the memory region R, and an etching processusing the patterned mask layeras a mask may be performed for removing a part of the cap materialM (such as the cap materialM located above the logic region R) and forming the second cap layer. At least a part of the cap materialM located above the memory region Rmay be etched to be the second cap layerby the etching process, and the patterned mask layermay be removed after the etching process. As shown inand, after the step of forming the second cap layer, an interlayer dielectric layermay be formed above the memory region Rand the logic region R. The interlayer dielectric layerlocated above the logic region Rmay be formed on the dielectric layer, and the interlayer dielectric layerlocated above the memory region Rmay be formed on the second cap layer. Subsequently, a planarization processmay be performed to the interlayer dielectric layer, and the planarization processmay include a chemical mechanical polishing (CMP) process or other suitable planarization approaches. In some embodiments, the planarization processmay stop on the second cap layer, at least a part of the top surface of the second cap layermay be exposed by the planarization process, and a bottom surface of the interlayer dielectric layer(such as a bottom surfaceBS of the interlayer dielectric layerwithout being located above the SOT layerin the vertical direction D) may be lower than the MTJ structurein the vertical direction D, but not limited thereto.

Subsequently, as shown in, the connection structure, the interconnection structure, and the stop layermay be formed for forming the MRAM device. In some embodiments, an opening corresponding to the connection structureand an opening corresponding to the interconnection structuremay be formed, these openings may be filled with an electrically conductive material, and another planarization process may be performed to remove the electrically conductive material located outside the openings for forming the connection structureand the interconnection structure. Therefore, the top surface of the connection structure, the top surface of the interconnection structure, and the top surface of the interlayer dielectric layermay be substantially coplanar, but not limited thereto. The opening corresponding to the connection structuremay penetrate through the interlayer dielectric layer, the second cap layer, the oxide layer, and the first cap layerlocated above the top electrode, and the opening corresponding to the interconnection structure(such as a trench and a via hole corresponding to the dual damascene structure) may penetrate through the interlayer dielectric layer, the dielectric layer, and the stop layerlocated above the logic region R. By the design that the opening corresponding to the connection structurehas to penetrate through the second cap layer, the oxide layer, and the first cap layervertically, the negative influence of the step of forming the opening corresponding to the connection structureon the top electrodemay be reduced, especially when the opening corresponding to the connection structureand at least a part of the opening corresponding to the interconnection structureare formed concurrently by the same process. The manufacturing yield may be enhanced and/or the process integration between the memory region Rand the logic region Rmay be improved accordingly.

To summarize the above descriptions, in the MRAM device and the manufacturing method thereof according to the present invention, the oxide layer used to define the SOT layer and the second cap layer may be partly disposed above the MTJ structure, and the connection structure corresponding to the MTJ structure vertically penetrates through the second cap layer, the oxide layer, and the first cap layer for improving the process integration of the MRAM device and/or enhancing related manufacturing yield.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.