Semiconductor Device and Failure Analysis Method Therefor

The present application claims priority from Japanese Patent Application No. 2024-100205 filed on Jun. 21, 2024, the content of which is hereby incorporated by reference to this application.

The present disclosure relates to a semiconductor device and a method thereof, for example, a semiconductor device making analysis of failures possible and a method thereof.

There is disclosed a technique listed below.

Patent Document 1 discloses a microcomputer failure analysis system that compares input and output signal levels at the number of clocks of each of a defective product and a non-defective product to estimate the number of clocks at a time of failure and makes a search by an In Circuit Emulator (ICE) to estimate cause of the failure.

In a semiconductor device without limiting to the system disclosed in Patent Document 1, it is required that the analysis of occurring failure is made possible.

The other problems and novel features will be apparent from the present specification and the accompanying drawing.

A semiconductor device according one embodiment of the present disclosure includes a central processing unit (CPU), an external terminal receiving a signal from outside, a first memory storing an external input signal supplied via the external terminal, and a switching circuit for switching an input signal necessary for a processing of the CPU to the external input signal, which is stored in the first memory, from the external input signal obtained via the external terminal.

In a method according to one embodiment of the present disclosure includes, a semiconductor device: causes a first memory to store an external input signal via an external terminal of a semiconductor device determined as malfunction; switches an input signal given to the semiconductor device to the external input signal, which is stored in the first memory, from the external input signal passing through the external terminal based on an instruction; operating the semiconductor device by using the signal, which is stored in the first memory, as the input signa; and specifying a failure position in the semiconductor device.

The present disclosure can provide a semiconductor device, which makes the analysis of the failures possible, and a method thereof.

Hereinafter, embodiments will be explained with reference to the drawings. Note that the drawings are simply illustrated, so that a technical scope of the embodiments should not be narrowly interpreted by using description of those drawings as a basis. In addition, the same reference numerals are denoted by the same components, and duplicate explanation will be omitted. In a block diagram showing a configuration example of a semiconductor device, an arrow connecting the components to one another shows a flow of characteristic data shown below. However, data transmitted and received between the components is not limited to data shown below.

In the embodiments described below, the invention will be described in a plurality of sections or embodiments when required as a matter of convenience. However, these sections or embodiments are not irrelevant to each other unless otherwise stated, and the one relates to the entire or a part of the other as a modification example, details, or a supplementary explanation thereof. Similarly, in the embodiments described below, when referring to the number of elements (including number of pieces, values, amount, range, and the like), the number of the elements is not limited to a specific number unless otherwise stated or except the case where the number is apparently limited to a specific number in principle, and the number larger or smaller than the specified number is also applicable.

Further, in the embodiments described below, it goes without saying that the components (including element steps) are not always indispensable unless otherwise stated or except the case where the components are apparently indispensable in principle. Similarly, in the embodiments described below, when the shape of the components, positional relation thereof, like mentioned, the and the are substantially approximate and similar shapes and the like are included therein unless otherwise stated or except the case where it is conceivable that they are apparently excluded in principle. The same goes for the numerical value and the range described above.

In addition, the configuration or processing shown by each embodiment can be appropriately combined with the configuration or processing shown by another embodiment.

Before explanation about a semiconductor device according to the present embodiment, a failure analysis method previously considered by the present inventors will be explained.

If being based on the disclosure of Patent Document, the following failure analysis method is considered as a related technique. Firstly, a customer checks the occurrence of malfunction on a board mounting the semiconductor device, for example, a microcontroller (hereinafter, called an MCU). Next, the customer removes the MCU from the board, and mounts the MCU on another board, thereby checking whether the malfunction is reproduced also on the another board. When the malfunction occurs on both boards, it is determined that the failures exist in the MCU, so that the customer provides a maker(s) with the board mounting the MCU in which the malfunction occurs or with the removed MCU alone and the board from which the MCU is removed.

The maker uses dedicated jigs and tools (for example, a base board, a utility board, a Personal Computer (PC), and the like), thereby operating the defective MCU and the good MCU. The maker compares output signal data of each of the defective MCU and the good MCU, and investigates the number of clocks, a program counter value, and the like which cause a difference between both operations. Then, the maker analyzes an execution command based on an investigation result and estimates a failure cause(s).

The failure analysis of the maker needs to specify a failure position(s) in order to elucidate the failure cause. For specifying the failure position, a failure position specifying tester is used. For reproducing the malfunction on this tester, a failure position specifying program is required.

However, in the above related technique, the following problem arises. Recently, by increasing the number of pins provided on the board, a Ball Grid Array (BGA) package becomes a mainstream as a package of the semiconductor device. However, generally, the customer has no reball device, so that there is a case in which the removal and the remounting of the above MCU cannot be performed. In addition, although the failure cause may be estimated from the analysis of the execution command similarly to the related technique, it is difficult to specify the failure position. In order to specify the failure position, the failure position specifying tester is used. In order to reproduce the malfunction on the tester, a maker side needs the dedicated failure position specifying program.

The semiconductor device shown by embodiments described below can solve the above problems.

is a block diagram showing a configuration example of a semiconductor device Haccording to a first embodiment. The semiconductor device His mounted on a printed board H, and an input signal Eis inputted in it. The input signal Eis a signal supplied to the semiconductor device Hvia an external terminal Hfrom a part Hthat is provided outside the semiconductor device Hmounted on the printed board H. The semiconductor device

His, for example, a microcontroller (MCU), and includes a central processing unit (CPU) Hand a memory H. Further, the semiconductor device Hincludes a selector H, a switching circuit H, and the external terminal H. The part His, for example, a part having a communication I/F. Note that, hereinafter, the printed board H on which the semiconductor device Hand the part Hare mounted is simply called a board H, too.

The selector His connected to the CPU Hand the memory Hvia a bus B. The selector Hswitches, from the input signal Eto a signal Mstored in the memory H, an input signal (that is, external input signal) supplied from outside the semiconductor device Haccording to control of the switching circuit H. Namely, the selector Hswitches a path of the external input signal used by the CPU Haccording to the control of the switching circuit H.

The CPU Huses, as the external input signal, the input signal Ell or the input signal Minputted via the selector Hto execute a program stored in the memory H.

When the CPU Huses, as the external input signal, the input signal Esupplied from the part Hvia the selector Hto perform the processing, the memory Hsimultaneously stores this input signal E. As the memory H, any type of memory can be applied. However, in order to store the input signal Eeven after power of the semiconductor device His turned off, it is preferable to use a non-volatile memory as the memory H. In addition, the program executed by the CPU His also stored in the memory H.

The switching circuit Hcontrols the selector Hbased on an instruction. The switching circuit Hswitches the external input signal, which is used for the processing of the CPU H, to the signal Mstored in the memory Hor the input signal Esupplied from the part Haccording to the instruction of an operation mode. The instruction to the switching circuit Hmay be given based on an instruction signal from outside or may be given based on information stored in the semiconductor device H. Those details will be described after a second embodiment.

Note that when the signal stored in the memory His inputted as the external input signal to the CPU H, a signal outputted from the memory Hmay be the input signal Einitially stored in the memory Hor may be a signal different from the input signal E. For example, an input signal stored in a memory of another semiconductor device having the same configuration as that of the semiconductor device Hmay be a signal that is newly stored in the memory Hand is outputted from the memory H. The signal Moutputted from the memory Hdoes not pass an outside of the semiconductor device H(for example, without passing the part Hmounted on the board H), and is inputted as the external input signal in the CPU H.

In addition, the memory Hmay be included in the semiconductor device H, or may be mounted, as a part different from the semiconductor device H, on the printed board H.

is a flowchart showing one example of a typical processing of the semiconductor device H, and a processing outline of the semiconductor device Hwill be explained with reference to this flowchart. Note that a part already explained about each processing will be omitted appropriately.

Firstly, the memory Hstores the input signal Efrom the part Hmounted on the board H (step S). At this time, the CPU Hcan operate according to the input signal E. By detecting an operation situation of the semiconductor device H, a user can judge whether the operation of the semiconductor device Hhas abnormality or not.

Here, also about a semiconductor device mounted on another printed board having the same configuration as that of the board H, a processing of step Sdescribed above is performed. That is, the semiconductor device mounted on the another printed board receives an input signal from a part mounted on the another printed board (hereinafter, called an input signal E), and stores this input signal. Consequently, the input signal Esupplied to the semiconductor device mounted on the another printed board is stored in the memory provided in the semiconductor device mounted on the another printed board.

After the input signal Eis stored in the memory H, the user causes the memory Hto store the input signal Estored in the memory of the semiconductor device mounted on the another printed board. Here, the user may cause the memory of the semiconductor device mounted on the another printed board to store the input signal Estored in the memory H.

Thereafter, the switching circuit Hcontrols the selector Hbased on the instruction, and switches the external input signal, which is used for the processing of the CPU H, to the signal Mstored in the memory Hfrom the input signal Esupplied from the part H(step S). The CPU Huses, as the external input signal, the signal Mstored in the memory H. Here, the signal Mstored in the memory His the input signal Esupplied to the semiconductor device, which is mounted on the another printed board, from its opposite part. Accordingly, the CPU Huses the input signal Eto perform the processing. At this time, a sensor provided inside or outside the semiconductor device Hdetects the operation situation of the semiconductor device H, so that the user can judge whether the operation of the semiconductor device Hhas the abnormality or not.

is a diagram showing one example of a failure specifying method. This example shows a situation in which operation abnormality occurs about a function realized by the part mounted on the printed board A (that is, a failure occurs) and, meanwhile, shows a situation in which operation abnormality does not occur about a function realized by the part mounted on the printed board B. Hereinafter, the printed board A is called a board A, and the printed board B is called a board B. Each of the board A and the board B includes the same configuration as the board H having the semiconductor device Has shown in. Specifically, each of the board A and the board B includes components corresponding to the part Hand the semiconductor device Has shown in. Hereinafter, explanation will be made on the premise that the board A has a part Aand a semiconductor device Aand the board B has a part Band a semiconductor device B. In addition, each of the semiconductor device Aand the semiconductor device Bis explained as a component corresponding to the semiconductor device Hshown in. That is, the semiconductor device Ahas a selector A, a CPU A, a memory A, and a switching circuit A. Further, the semiconductor device Bhas a selector B, a CPU B, a memory B, and a switching circuit B. The user of the board A and the board B performs the following failure specifying method.

However, the user cannot determine, at this point in time, whether the failure cause is present in the semiconductor device Aor in the board A (for example, part A) other than the semiconductor device A. Accordingly, the user performs the following processing in order to determine the failure cause.

is a diagram showing one example of a failure specifying result. Before replacing input data (that is, data of stored input signals), it is judged that the operation of the board A has the abnormality and that the operation of the board B has no abnormality as described in (1) and (2).

After replacing the input data, an operation situation of the board A and an operation situation of the board B are considered to become any of the following states:

In the case of (i), the user sends the semiconductor device A, whose failure occurs, to the maker, thereby being capable of asking the maker to repair or exchange the semiconductor device A. The maker uses the input signal and a user program stored in the memory Aof the semiconductor device Ato cause them to operate the semiconductor Aby using a dedicated device for specifying the failure position. Consequently, the maker can determine which position of the semiconductor device the failure occurs at.

When the abnormality occurs at the operation of the semiconductor device H, the user performs the above processing, thereby being capable of making analysis about where the failure cause is. Further, by using the semiconductor device H, the following effects also occur.

In making the analysis, the user does not need to remove the semiconductor device Hor the part Hfrom the board H. As described above, the user replaces the input signal stored in the memory H, thereby making it possible to determine whether the failure cause is present on the board or in the semiconductor device.

Further, when using the failure position specifying tester to perform the failure analysis for specifying the failure position, the maker can use the user program and the input signal that are stored in the memory H. The maker does not need to make a dedicated program for specifying the failure position, the dedicated program using the failure position specifying tester. Particularly, in the following case, it may be difficult to make the program for reproducing symptoms of the failure of the semiconductor device:

The following embodiment discloses a specific example of the semiconductor device Hexplained in the first embodiment. However, the specific example of the semiconductor device Hshown in the first embodiment is not limited to the followings. In addition, the following configuration and processings that are explained below are illustrations, and are not limited to this.

is a block diagram showing a configuration example of a semiconductor device Haccording to a second embodiment. The semiconductor device His a MCU mounted on the printed board. In addition, a partA is provided outside the semiconductor device Hon the printed board. Hereinafter, respective components and a connection relationship between the components shown inwill be explained. Note that hereinafter, the printed board H on which the semiconductor device Hand the partA are mounted is simply called a board H.

The semiconductor device Hincludes selectors, I/O buffers, an error detector, a reset controller, a CPU, a Flash memory, and a Random Access Memory (RAM). Those components in the semiconductor device Hare connected to one another via an internal bus B. In addition, each of those components is connected to a record/reproduction control circuitvia the internal bus B. Further, the semiconductor device Hincludes digital I/O terminals.

The selector, the I/O buffer, the digital I/O terminal, and the partA are connected in this order. A digital input signal inputted from outside the board H (hereinafter, simply described as an input signal) is supplied to the record/reproduction control unitthrough the partA, the digital I/O terminal, the selectorand the internal bus B. The input signal is a digital signal indicating a H/L state of the signal.

The selectoris configured as a multiplexer, and is inputted as the input signal from the I/O bufferand a signal from a below-described data conversion circuitincluded in the record/reproduction control circuit. In addition, a signal from a below-described signal path switching circuitincluded in the record/reproduction control circuitis inputted as a selection signal in the selector. The selectorselects any one of the input signal from the I/O bufferand the signal from the date conversion circuitaccording to the selection signal. The selectoroutputs the selected signal via the internal bus Bto the CPUand the RAM. Specifically, the signal path switching circuitoutputs the selection signal so that the selectoroutputs the input signal from the I/O bufferat a time of a record mode and outputs the signal from the data conversion circuitat a time of a reproduction mode.

Note that the CPUcorresponds to the CPU Hof the first embodiment. The Flash memorycorresponds to the memory Hof the first embodiment.

The error detectoris one function included in the semiconductor device H. The error detectordetects abnormalities (for example, Error-Correcting Code (ECC) errors of the RAM, parity errors of a data bus, and the like) during an operation of the semiconductor device H. The error detectoroutputs an error detection signal ED to the below-described multiplexerincluded in the record/reproduction control, when detecting abnormality contents. Note that in a case of being set so that the recording is ended when the errors are detected at a time of recording the input signal, the error detectoroutputs the error detection signal, so that the recording of the input signal is ended.

The reset controlleris one function included in the semiconductor device H. The reset controllerresets each circuit in the semiconductor device Haccording to the reset signal to the semiconductor device Hinputted via the reset I/FB from outside the semiconductor device Hand the reset signal generated in the semiconductor device H. In addition, when resetting each circuit in the semiconductor device H, the reset controlleroutputs the reset signal RST to the multiplexer.

The CPUperforms the processing according to the user program based on the signal inputted in the semiconductor device H. The user program is stored in the Flash memory. Note that the semiconductor device Hmay include a not-shown peripheral circuit. The peripheral circuit includes, for example, an interruption control circuit and a communication control circuit.

The Flash memorystores the input signal data inputted via the record/reproduction control circuitand the RAMand, additionally thereto, stores the user program for operating the CPU. The Flash memoryis a non-volatile memory, and can continue to retain the stored data without deleting the stored data even when the power of the semiconductor device His turned off.