Generating and Analyzing a Layout of a Semiconductor Device

This application claims priority to U.S. Provisional Patent Application No. 63/663,685 entitled “GENERATING AND ANALYZING A LAYOUT OF A SEMICONDUCTOR DEVICE,” filed Jun. 24, 2024, which is incorporated herein by reference in its entirety.

The present disclosure generally relates to electronic design automation (EDA) for semiconductor devices and, for example, the design and simulation of semiconductor devices.

A semiconductor device may include a power device, such as a power metal oxide semiconductor field effect transistor (MOSFET). A layout of the semiconductor device may be designed before the semiconductor device is manufactured. In some situations, the layout of the semiconductor device may cause unintended consequences on a performance of the semiconductor device due to various factors, such as parasitic metal routing resistance.

A method comprising: generating a layout of a semiconductor device based on one or more parameters regarding the layout of the semiconductor device; analyzing the layout of the semiconductor device; performing iterations of generating the layout and analyzing the layout, wherein one or more values, of the one or more parameters, are a first value during a first iteration of the iterations, and wherein the one or more values, of the one or more parameters, are a second value during a second iteration of the iterations; generating a model of the semiconductor device based on performing the iterations; and providing the model of the semiconductor device to a semiconductor manufacturing facility to cause the semiconductor manufacturing facility to manufacture the semiconductor device based on the model.

A system comprising: one or more processing units adapted to: generate a layout of a power semiconductor device based on one or more parameters regarding the layout of the power semiconductor device; analyze the layout of the semiconductor device to determine a characteristic of the power semiconductor device; perform iterations of generating the layout and analyzing the layout, wherein one or more values, of the one or more parameters, are a first value during a first iteration of the iterations, and wherein the one or more values, of the one or more parameters, are a second value during a second iteration of the iterations; generate a model of the power semiconductor device based on performing the iterations; and provide the model of the power semiconductor device to cause the power semiconductor device to be manufactured based on attributes of the model.

A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising: one or more instructions that, when executed by one or more processors of a computing device, cause the computing device to: generate a layout of a semiconductor device based on one or more parameters regarding the layout of the semiconductor device; analyze the layout of the semiconductor device; perform iterations of generating the layout and analyzing the layout, wherein one or more values, of the one or more parameters, are a first value during a first iteration of the iterations, and wherein the one or more values, of the one or more parameters, are a second value during a second iteration of the iterations; generate a model of the semiconductor device based on performing the iterations; and provide the model to cause the semiconductor device to be manufactured based on the model.

The following detailed description of example implementations refers to the accompanying drawings. The same reference numbers in different drawings may identify the same or similar elements.

A layout of a semiconductor device may be designed before the semiconductor device is manufactured. Designing the layout of the semiconductor device may include determining the device area and aspect ratio, a number of pads, determining locations of the pad on the semiconductor device, and metal routing topology, among other examples. Performance and reliability of the semiconductor device and, accordingly, the design of the layout of such semiconductor device may vary with device and package layout implementation choices and constraints due to effects on the semiconductor device. Measures of resistance in the semiconductor device, such as parasitic metal routing resistance, resistance between source and drain pads (also referred to as “on-resistance” or “Ron”), or the like may vary with different potential designs of a given semiconductor device. Excessive resistance within the semiconductor device may degrade performance and/or reliability of the semiconductor device.

Manual procedures to generate a layout of the semiconductor device may involve relatively laborious efforts from engineers or other individuals, and may further yield sub-optimal layouts that exhibit more resistance than optimal layouts. Manually generated layouts may, for example, lead to larger chip area, increased cost, increased resistance, and/or higher power dissipation than optimal layouts that may be generated in accordance with some implementations described herein.

Implementations described herein are directed to optimizing the design of a semiconductor device, where such device specifies a particular set of components (e.g., Field Effect Transistors (FETs), Metal Oxide Semiconductor FETs (MOSFETs), electro-static discharge (ESD) protection devices, diodes, capacitors, or the like), but is variable in terms of factors such as aspect ratio, quantity and location of source and/or drain pads, and metal or wire topology (e.g., where such metals or wires facilitate signals to be sent between components of the semiconductor device), among other potential factors. While examples are described herein in the context of semiconductor devices that include components such as MOSFETs, capacitors, and/or other components, similar concepts are applicable to semiconductor devices that include other types of components.

Implementations described herein may utilize electronic design automation (EDA) tools to utilize artificial intelligence/machine learning (AI/ML) techniques or other automated techniques to generate one or more models that indicate optimal layouts for semiconductor devices, in view of specifications of such semiconductor devices (e.g., specified sets of components of respective semiconductor devices). The layouts may be used as part of a design process (e.g., may be used to guide or inform design teams of an optimal layout), and/or may be used to directly manufacture semiconductor devices in accordance with the optimal layout. For example, the layouts may be provided to a semiconductor manufacturing facility to cause (or instruct) the semiconductor manufacturing facility to manufacture or fabricate one or more semiconductor devices based on the model.

illustrates, for example, example layouts,, andof a semiconductor device that includes a particular set of components, such as a specified quantity and/or arrangement of MOSFETs, ESDs, capacitors, or the like. For the sake of clarity, the set of components are not shown in the figure for each example layout.

As shown, each layout may also include a respective set of pads, which may include source and/or drain pads that serve to provide electrical power to various components of the semiconductor device. For example, layoutmay include one arrangement of pads, layoutmay include another arrangement of pads, and layoutmay include yet another arrangement of pads. As further illustrated by the figure, different layouts may include different quantities of pads. For example, layoutsandinclude six pads, while layoutincludes four pads. Further, the locations of padsmay be different for each of the different layouts. While each configuration of padsmay be sufficient to power the components of the semiconductor device (in each layout,, or), the different pad configurations (e.g., quantity and/or location of pads) may, in concert with other factors such as an aspect ratio of each layout, lead to differing amounts of resistance of the semiconductor device.

As further shown, each layout may include a different aspect ratio (e.g., a function of length in two dimensions, such as a length and width of the semiconductor device in accordance with each layout). For example, layoutmay exhibit a “narrowest” or “longest” aspect ratio, and layoutmay exhibit a “widest” or “shortest” aspect ratio. That is, the cumulative area of the components (other than pads) of the semiconductor device may be approximately the same among the layouts, even though the aspect ratios of such layouts differ. The aspect ratio, in concert with or without other factors (e.g., quantity and/or location of padsand/or metal routing topology) may lead to differing amounts of resistance of the semiconductor device.

As noted above, each layout may be associated with a different metal or conductor routing topology. The metal or conductor routing topology may refer to paths, or otherwise to an arrangement, of metal and/or conductors that connect different components of the semiconductor device to each other, thus facilitating electrical signals to be sent between such different components. The metal or conductor routing topology, in concert with or without other factors (e.g., quantity and/or location of padsand/or aspect ratio) may lead to differing amounts of resistance of the semiconductor device.

illustrates an example procedure for generating a set of semiconductor devices, with a specified set of components, that are in accordance with an optimal layout. In the examples described herein, layouts may be “optimal” in terms of resistance (e.g., Ron) of the semiconductor device. An “optimal” resistance may be a lowest possible resistance, may be a resistance that is within a particular range, or may be defined in some other suitable manner.

As shown, component specificationmay be provided to Automated Layout Design System (ALDS). ALDSmay, for example, implement EDA tools and utilize AI/ML techniques to generate optimal layoutbased on component specification. In some examples, ALDSmay use a scripting language to generate optimal layout. In some examples, the scripting language may include a silicon compiler interface language (SCIL) script. The SCIL script (also referred to as SKILL script) may be used in conjunction with a parameterized cells (PCell) description language. In some examples, the scripting language maybe loaded into the EDA tool using another scripting language, such as a Perl script. As noted above, component specificationmay specify particular components, such as MOSFETs, ESDs, capacitors, diodes, or other types of components to be included in a semiconductor device. In some implementations, the component specificationmay specify particular “blocks” or sets of components that are to be placed in a particular arrangement, such as proximate to each other, and/or in particular locations with respect to each other.

As discussed below, ALDSmay identify optimal layout, given component specification. In some implementations, optimal layoutmay be represented by a particular model, such as a model generated using AI/ML techniques or other suitable automated techniques. Optimal layoutmay include parameters, such as aspect ratio parameter, pad configuration parameter, routing topology parameter, and resistance parameter. As noted above, aspect ratio parametermay refer to a length and/or width of a semiconductor device that implements optimal layout. Pad configuration parametermay refer to a quantity and/or location of pads, such as source pads and/or drain pads, on the semiconductor device that implements optimal layout. Routing topology parametermay indicate locations of particular components on the semiconductor device, as well as paths or locations of metal and/or conductors that connect such components. Resistance parametermay specify an actual or predicted measure of resistance (e.g., Ron) exhibited by a semiconductor device that implements optimal layout.

As discussed below, some or all of parametersmay be identified by ALDSusing AI/ML techniques, which may include iteratively generating and running simulations of potential semiconductor device layouts to identify and implement optimal layout. A layout model (that indicates optimal layouts for semiconductor devices) may be generated during the iterative process of generating and running simulations. A meta-model (that indicates a mathematical model of dependence of semiconductor device performance on its input variables) may be generated during the iterative process. As explained herein, the AI/ML techniques may be used as part of controlling the iteration process, for identifying optimal layout, and for generating the meta-model. For example, the AI/ML techniques may be used as part of smart sampling of input variables for various iterations. The AI/ML techniques may include polynomial regression (also referred to as polynomials), kriging, genetic aggregation of response surface (GARS), and support vector regression (SVR), without limitation. In some examples, the model may be generated using one or more of the AI/ML techniques that best fit data (e.g., parameters). Optimal layoutmay be provided to semiconductor manufacturing facility, which may include machinery and/or systems that manufacture or fabricate one or more semiconductor devicesbased on optimal layout. In other words, ALDSmay provide optimal layoutto semiconductor manufacturing facilityto cause (or instruct) semiconductor manufacturing facilityto manufacture or fabricate one or more semiconductor devicesbased on optimal layout. In some examples, semiconductor manufacturing facilitymanufacture or fabricate one or more semiconductor devicesbased on the attributes of optimal layout. In some instances, the optimal layoutand/or the generated meta-model of the semiconductor device may be used as part of a design process (e.g., may be used to guide or inform design teams) so that an optimal layout is included as a sub-part of a larger semiconductor design layout along with other semiconductor component design layouts. The larger semiconductor design layout may be provided to semiconductor manufacturing facilityto cause (or instruct) one or more larger semiconductor devices including optimal layoutto be manufactured or fabricated.

illustrates an example of operations that may be performed by ALDSin order to generate optimal layout. As shown, Layout Model Generation component(e.g., which may be a component of ALDS) may receive a set of input constraintsand a set of input variables.

Input constraintsmay include attributes or parameters that are not able to be changed or modified by Layout Model Generation component. On the other hand, input variablesmay include an identification of attributes or parameters that may be modified or refined by Layout Model Generation componentusing AI/ML techniques or other suitable techniques. In accordance with some implementations, input constraintsmay include, for example, one or more component specification, and input variablesmay indicate that parameters such as aspect ratio, pad configuration, and routing topology are able to be varied or changed by Layout Model Generation component.

Layout model generation componentmay generate one or more layout models(e.g., using AI/ML modeling techniques or other suitable techniques). In some examples, Layout Model Generation componentmay implement an EDA tool that generates one or more layout modelsand/or optimal layout. For example, the EDA tool may generate layout models (e.g., layout models) for a given set of input variables (e.g., input variablessuch as area, length, among other examples). As explained herein, the AI/ML techniques may include polynomial regression, kriging, GARS, and SVR, without limitation. In some examples, layout model generation componentmay generate the one or more layout modelsusing a scripting language (also referred to as “layout generating script”), as explained herein. As similarly discussed with respect to optimal layout, each layout modelmay be associated with a respective set of parameters, which may include different values for some or all of the input variables, such as aspect ratio, pad configuration, a routing topology. Each layout modelmay also be associated with a respective measure of resistance (e.g., Ron). In some examples, the set of parameters of a layout modelmay be referred to as an input of the layout modelwhile the measure of resistance for the layout modelmaybe referred to as an output of the layout model.

In some examples, each layout modelmay be analyzed. For example, as part of analyzing a layout model, the layout modelmay be scored and ranked. As an example, Model Scoring Component(e.g., which may be a component of ALDS) may score each layout modelbased on one or more optimization factors. In some examples, resistance (e.g., Ron) may be a factor to be optimized, which may include minimizing resistance, identifying a particular layout modelthat exhibits a particular amount or range of resistance, and/or otherwise optimizing the resistance of a semiconductor device that implements a given layout model. Model Scoring Componentmay, for example, simulate the operation of a semiconductor device that implements each given layout modelin order to identify the measure of resistance (e.g., Ron) for each layout model. In other examples, one or more other optimization factors, or combinations of optimization factors, may be used to score layout models. Such optimization factorsmay include temperature of a semiconductor device that implements a given layout model, power consumption of a semiconductor device that implements a given layout model, and/or other factors which may be sought to be optimized.

Model Scoring Componentmay, for example, generate one ranked set-of layout modelsbased on one optimization factor(or set of optimization factors), may generate another ranked set-of layout modelsbased on another optimization factor(or set of optimization factors), may generate yet another ranked set-N of layout modelsbased on one optimization factor(or set of optimization factors), and so on. In this example, assume that ranked set-has been optimized based on resistance (e.g., Ron). In some implementations, the same layout modelmay be associated with multiple different scores with respect to different optimization factors. For example, a given layout modelmay be associated with one score that has been generated based on one optimization factor(or set of optimization factors), another score that has been generated based on another optimization factor(or set of optimization factors), and so on.

A highest scoring layout model, in ranked set-, may be, for example, a particular layout modelthat exhibits a lowest measure of resistance (e.g., Ron) out of the generated layout models. In some implementations, the highest scoring layout modelof a given ranked setmay be selected as an optimal layout, at least with respect to the optimization factor (or factors)used to score, rank, or evaluate layout modelsfor the given ranked set. In some examples, Model Scoring Componentmay implement an EDA tool that analyzes (e.g., scores, ranks, or evaluates) layout models. The EDA tool may take a layout modelas input and may simulate and analyze the layout modelto extract outputs or performance optimization factors (e.g. Ron). For example, layout modelsmay be analyzed as described herein. In some examples, Model Scoring Componentmay analyze (e.g., score, rank, or evaluate) layout modelsusing a scripting language. In some examples, the scripting language may include a Perl script. In some implementations, the scripting language may be used to generate configuration files for the EDA tools that generate and analyze layout models. In some examples, an output of the EDA tool (that generates optimal layoutand/or layout models) may be provided as an input to the EDA tool that analyzes layout models. For example, a layout model(e.g., the output of the EDA tool that generates layout models) may be provided as the input to the EDA tool that analyzes layout models. In some implementations, ALDSmay accordingly select the highest scoring layout model, from a given ranked setthat is associated with a particular optimization factoror set of optimization factors(e.g., resistance in some examples), as the optimal layoutwhen given input constraints(e.g., component specification) and input variables.

In some implementations, Layout Model Generation componentand Model Scoring Component () may be run one after another multiple times in an iterative manner. In some implementations these iterations may be controlled by AI/ML algorithms which sample or determine input variables () for subsequent iterations based on results of prior iterations. For example, Layout Model Generation componentmay continue to refine attributes of layout modelsin order to generate additional layout models. For example, Layout Model Generation componentmay identify a relatively high scoring layout model(e.g., with respect to one or more optimization factors), and may iteratively generate a new layout modelthat is based on the identified high scoring layout model. Iteratively generating the new layout modelmay include adjusting (e.g., marginally or slightly adjusting) one or more parameters of the high scoring layout modelin order to attempt to generate an even higher scoring layout model, which would be considered even more optimal. In some instances, the AI/ML algorithms are also able to generate a meta-model of the semiconductor device. The meta-models represent a simplified relationship of one or more optimization factorson one or more input variables. For example, a meta-model can be a mathematical relation or algorithm representing input and output relations (e.g., Ron=Function(length)).

is a diagram of example components of a device, which may be used to generate a layout of a semiconductor device in accordance with some implements described herein. In some implementations, ALDS, semiconductor manufacturing facility, Layout Model Generation component, and/or Model Scoring Componentmay include one or more devicesand one or more components of device. As shown in, devicemay include bus, processor, memory, storage component, input component, output component, and communication component.

Busincludes a component that enables wired or wireless communication among the components of device. Processorincludes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, or another type of processing component. Processoris implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processorincludes one or more processors capable of being programmed to perform a function. Memoryincludes a random access memory, a read only memory, or another type of memory (e.g., a flash memory, a magnetic memory, or an optical memory).

Storage componentstores information or software related to the operation of device. For example, storage componentmay include a hard disk drive, a magnetic disk drive, an optical disk drive, a solid state disk drive, a compact disc, a digital versatile disc, or another type of non-transitory computer-readable medium. Input componentenables deviceto receive input, such as user input or sensed inputs. For example, input componentmay include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system component, an accelerometer, a gyroscope, or an actuator. Output componentenables deviceto provide output, such as via a display, a speaker, or one or more light-emitting diodes. Communication componentenables deviceto communicate with other devices, such as via a wired connection or a wireless connection. For example, communication componentmay include a receiver, a transmitter, a transceiver, a modem, a network interface card, or an antenna.

Devicemay perform one or more processes described herein. For example, a non-transitory computer-readable medium (e.g., memoryor storage component) may store a set of instructions (e.g., one or more instructions, code, software code, or program code) for execution by processor. Processormay execute the set of instructions to perform one or more processes described herein. In some implementations, execution of the set of instructions, by one or more processors, causes the one or more processorsor the deviceto perform one or more processes described herein. In some implementations, hardwired circuitry may be used instead of or in combination with the instructions to perform one or more processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.

The number and arrangement of components shown inare provided as an example. Devicemay include additional components, fewer components, different components, or differently arranged components than those shown in. Additionally, or alternatively, a set of components (e.g., one or more components) of devicemay perform one or more functions described as being performed by another set of components of device.

is a flowchart of an example processassociated with generating and analyzing a layout of a semiconductor device as described herein. In some implementations, one or more process blocks ofmay be performed by a device, such as ALDS. Additionally, or alternatively, one or more process blocks ofmay be performed by one or more components of device, such as processor, memory, storage component, input component, output component, and/or communication component.

As shown in, processmay include generating a layout of the semiconductor device based on one or more parameters regarding the layout of the semiconductor device (block). For example, the device may generate a layout of the semiconductor device based on one or more parameters regarding the layout of the semiconductor device, as described above in connection with(e.g., layout models).

As further shown in, processmay include providing the layout of the semiconductor device for analysis (block). For example, the device may provide the layout of the semiconductor device for analysis, as described above in connection with(e.g., Model Scoring Component).

As further shown in, processmay include analyzing the layout of the semiconductor device (block). For example, the device may analyze the layout of the semiconductor device, as described above in connection with(e.g., Model Scoring Component).

As further shown in, processmay include performing iterations of generating the layout and analyzing the layout (block). For example, the device may perform iterations of generating the layout and analyzing the layout, as described above in connection with. In some implementations, the one or more parameters are a first value during a first iteration of the iterations. In some implementations, the one or more parameters are a second value during a second iteration of the iterations.

As further shown in, processmay include generating a model of the semiconductor device based on performing the iterations (block). For example, the device may generate a model of the semiconductor device based on performing the iterations, as described above in connection with(e.g., optimal layout).

As further shown in, processmay include providing the model of the semiconductor device to a semiconductor manufacturing facility to cause the semiconductor manufacturing facility to manufacture the semiconductor device based on the model (block). For example, the device may provide the model of the semiconductor device to the semiconductor manufacturing facility to cause the semiconductor manufacturing facility to manufacture the semiconductor device based on the model, as described above in connection with(e.g., semiconductor manufacturing facility). In some examples, the semiconductor manufacturing facility may manufacture the semiconductor device based on attributes of the model. The attributes of the model may include an aspect ratio attribute, a pad configuration attribute, a routing topology attribute, and/or a resistance attribute, among other examples.

In some implementations, the semiconductor device includes a power semiconductor device.

In some implementations, the one or more parameters include a dimension of the semiconductor device, wherein the input of the model includes the dimension of the semiconductor device, and wherein the output of the model includes a resistance of the semiconductor device.

In some implementations, the one or more parameters include a dimension of the semiconductor device, and wherein analyzing the layout of the semiconductor device comprise performing a simulation of an operation of the semiconductor device to determine a resistance of the semiconductor device based on the dimension of the semiconductor device.

In some implementations, generating the layout of the semiconductor device comprises generating the layout of the semiconductor device using a first script.

In some implementations, analyzing the layout of the semiconductor device comprises analyzing the layout of the semiconductor device using a second script.

In some implementations, generating the layout of the semiconductor device comprises generating the layout of the semiconductor device using a first tool.

In some implementations, analyzing the layout of the semiconductor device comprises analyzing the layout of the semiconductor device using a second tool.

In some implementations, processincludes providing an output of the first tool as an input of the second tool.

In some implementations, the model includes a meta-model.

Althoughshows example blocks of process, in some implementations, processmay include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in. Additionally, or alternatively, two or more of the blocks of processmay be performed in parallel.

As used herein, the term “component” is intended to be broadly construed as hardware, firmware, or a combination of hardware and software. It will be apparent that systems or methods described herein may be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual control hardware or software code used to implement these systems or methods is not limiting of the implementations. Thus, the operation and behavior of the systems or methods are described herein without reference to specific software code—it being understood that software and hardware can be used to implement the systems or methods based on the description herein.

As used herein, satisfying a threshold may, depending on the context, refer to a value being greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, or the like.