Pixel, Display Device, and Electronic Device

The present application claims priority to, and the benefit of, Korean Patent Application No. 10-2024-0079277, filed on Jun. 19, 2024, in the Korean Intellectual Office, and Korean Patent Application No. 10-2024-0159430, filed on Nov. 11, 2024, in the Korean Intellectual Property Office, the entire disclosures of which are incorporated herein by reference.

The disclosure generally relates to a pixel, a display device, and an electronic device.

With the development of information technologies, the importance of a display device which is a connection medium between a user and information increases. Accordingly, display devices, such as a liquid crystal display device and an organic light-emitting display device, are increasingly used.

A display device includes a plurality of pixels for displaying an image. Also, the display device may include a scan driver, an emission driver, and the like, which are used to control the pixels. Clock signals are suitable to control the scan driver and the emission driver, and suitable power consumption may increase as the number of clock signals becomes larger.

Embodiments provide a pixel, a display device, and an electronic device, in which the number of suitable clock signals can be reduced or minimized.

In accordance with an aspect of the disclosure, there is provided a display device including pixels including a light-emitting element configured to emit light based on a driving current, a first transistor configured to control an amount of the driving current, based on a data voltage, a second transistor configured to receive the data voltage from a data line, and to receive a first scan signal having a turn-on level, a first emission transistor connected between a first power line and the first transistor, and including a gate electrode for receiving a first emission signal, and a second emission transistor connected between the first transistor and the light-emitting element, and including a gate electrode for receiving a second emission signal, wherein the first emission transistor and the second emission transistor are configured to be turned off once or more, and the second transistor is configured to receive the first scan signal having a turn-on level, during an address scan period, and wherein the first scan signal having a turn-off level is maintained, one of the first emission transistor or the second emission transistor is configured to be turned off once or more, and another of the first emission transistor or the second emission transistor is configured to maintain a turn-on state, during a self-scan period.

A waveform of the first emission signal during the address scan period, and a waveform of the first emission signal during the self-scan period, may be different, wherein a waveform of the second emission signal during the address scan period, and a waveform of the second emission signal during the self-scan period, may be different.

A time length for which supply of the driving current to the light-emitting element is suspended during the address scan period may be equal to a time length for which supply of the driving current to the light-emitting element is suspended during the self-scan period.

The pixels may further include an initialization transistor connected between an initialization voltage line and an anode electrode of the light-emitting element, and including a gate electrode for receiving a second scan signal.

A waveform of the second scan signal during the address scan period, and a waveform of the second scan signal during the self-scan period, may be the same.

The pixels may further include a reference transistor connected between a reference voltage line and a gate electrode of the first transistor, and including a gate electrode for receiving a third scan signal.

A waveform of the third scan signal during the address scan period, and a waveform of the third scan signal during the self-scan period, may be different.

A turn-on level of the first emission signal may be maintained, and the second emission signal may include a pulse of a turn-off level, during the self-scan period.

The display device may further include a first emission driver configured to provide the first emission signal, a second emission driver configured to provide the second emission signal, a first scan driver configured to provide the first scan signal, a second scan driver configured to provide the second scan signal, and a third scan driver configured to provide the third scan signal, wherein the first emission driver and the third scan driver share same clock signals of a first group.

The second emission driver and the second scan driver may share same clock signals of a second group.

The clock signals of the first group and the clock signals of the second group may be different.

The first emission signal may include a pulse of a turn-off level, and a turn-on level of the second emission signal is maintained, during the self-scan period.

The display device may further include a first emission driver configured to provide the first emission signal, a second emission driver configured to provide the second emission signal, a first scan driver configured to provide the first scan signal, a second scan driver configured to provide the second scan signal, and a third scan driver configured to provide the third scan signal, wherein the first emission driver and the second scan driver share same clock signals of a first group.

The second emission driver and the third scan driver may share same clock signals of a second group.

The clock signals of the first group and the clock signals of the second group may be different.

In accordance with another aspect of the disclosure, there is provided an electronic device including a processor configured to provide an input frame, a data driver configured to generate data voltages using grayscales for the input frame, and pixels configured to display an image using the data voltages, the pixels including a light-emitting element configured to emit light based on a driving current, a first transistor configured to control an amount of the driving current, based on a data voltage, a second transistor configured to receive the data voltage from a data line, and to receive a first scan signal having a turn-on level, a first emission transistor connected between a first power line and the first transistor, and including a gate electrode for receiving a first emission signal, and a second emission transistor connected between the first transistor and the light-emitting element, and including a gate electrode for receiving a second emission signal, wherein the first emission transistor and the second emission transistor are configured to be turned off once or more during an address scan period in which the first scan signal having a turn-on level is received, and wherein one of the first emission transistor or the second emission transistor is configured to be turned off once or more, and another of the first emission transistor or the second emission transistor is configured to maintain a turn-on state, during a self-scan period in which the first scan signal having a turn-off level is maintained.

A waveform of the first emission signal during the address scan period, and a waveform of the first emission signal during the self-scan period, may be different, wherein a waveform of the second emission signal during the address scan period, and a waveform of the second emission signal during the self-scan period, are different.

A time length for which supply of the driving current to the light-emitting element is suspended during the address scan period may be equal to a time length for which supply of the driving current to the light-emitting element is suspended during the self-scan period.

The pixels may further include an initialization transistor connected between an initialization voltage line and an anode electrode of the light-emitting element, and including a gate electrode for receiving a second scan signal, wherein a waveform of the second scan signal during the address scan period, and a waveform of the second scan signal during the self-scan period, may be the same.

The pixels may further include a reference transistor connected between a reference voltage line and a gate electrode of the first transistor, and including a gate electrode for receiving a third scan signal, wherein a waveform of the third scan signal during the address scan period, and a waveform of the third scan signal during the self-scan period, are different.

Aspects of some embodiments of the present disclosure and methods of accomplishing the same may be understood more readily by reference to the detailed description of embodiments and the accompanying drawings. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are redundant, that are unrelated or irrelevant to the description of the embodiments, or that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects of the present disclosure may be omitted. Unless otherwise noted, like reference numerals, characters, or combinations thereof denote like elements throughout the attached drawings and the written description, and thus, repeated descriptions thereof may be omitted.

The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to only the illustrated embodiments herein. The use of “can,” “may,” or “may not” in describing one or more embodiments corresponds to one or more embodiments of the present disclosure.

A person of ordinary skill in the art would appreciate, in view of the present disclosure in its entirety, that each suitable feature of the various embodiments of the present disclosure may be combined or combined with each other, partially or entirely, and may be technically interlocked and operated in various suitable ways, and each embodiment may be implemented independently of each other or in conjunction with each other in any suitable manner unless otherwise stated or implied.

In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and/or descriptive purposes. In other words, because the sizes and thicknesses of elements in the drawings are arbitrarily illustrated for convenience of description, the disclosure is not limited thereto.

It will be understood that when an element, layer, region, or component (e.g., an apparatus, a device, a circuit, a wire, an electrode, a terminal, a conductive film, etc.) is referred to as being “formed on,” “on,” “connected to,” or “(operatively, functionally, or communicatively) coupled to” another element, layer, region, or component, it can be directly formed on, on, connected to, or coupled to the other element, layer, region, or component, or indirectly formed on, on, connected to, or coupled to the other element, layer, region, or component such that one or more intervening elements, layers, regions, or components may be present. In addition, this may collectively mean a direct or indirect coupling or connection and an integral or non-integral coupling or connection.

For example, when a layer, region, or component is referred to as being “electrically connected” or “electrically coupled” to another layer, region, or component, it can be directly electrically connected or coupled to the other layer, region, and/or component or one or more intervening layers, regions, or components may be present. The one or more intervening components may include a switch, a transistor, a resistor, an inductor, a capacitor, a diode and/or the like. Accordingly, a connection is not limited to the connections illustrated in the drawings or the detailed description and may also include other types of connections. In describing embodiments, an expression of connection indicates electrical connection unless explicitly described to be direct connection, and “directly connected/directly coupled,” or “directly on,” refers to one component directly connecting or coupling another component, or being on another component, without an intermediate component.

Meanwhile, other expressions describing relationships between components, such as “between,” “immediately between” or “adjacent to” and “directly adjacent to,” may be construed similarly. It will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

For the purposes of this disclosure, expressions such as “at least one of,” or “any one of,” or “one or more of” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of X, Y, and Z,” “at least one of X, Y, or Z,” “at least one selected from the group consisting of X, Y, and Z,” and “at least one selected from the group consisting of X, Y, or Z” may be construed as X only, Y only, Z only, any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, the expressions “at least one of A and B” and “at least one of A or B” may include A, B, or A and B. As used herein, “or” generally means “and/or,” and the term “and/or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and/or B” may include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases, when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. When “C to D” is stated, it means C or more and D or less, unless otherwise specified.

It will be understood that, although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms do not correspond to a particular order, position, or superiority, and are only used to distinguish one element, member, component, region, area, layer, section, or portion from another element, member, component, region, area, layer, section, or portion. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present disclosure. The description of an element as a “first” element may not require or imply the presence of a second element or other elements. The terms “first,” “second,” etc. may also be used herein to differentiate different categories or sets of elements. For conciseness, the terms “first,” “second,” etc. may represent “first-category (or first-set),” “second-category (or second-set),” etc., respectively.

The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, while the plural forms are also intended to include the singular forms, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “have,” “having,” “includes,” and “including,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

When one or more embodiments may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order.

As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. For example, “substantially” may include a range of +/−5% of a corresponding value. “About” or “approximately,” as used herein, is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Further, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.” Furthermore, the expression “being the same” may mean “being substantially the same”. In other words, the expression “being the same” may include a range that can be tolerated by those of ordinary skill in the art. The other expressions may also be expressions from which “substantially” has been omitted.

In some embodiments well-known structures and devices may be described in the accompanying drawings in relation to one or more functional blocks (e.g., block diagrams), units, and/or modules to avoid unnecessarily obscuring various embodiments. Those skilled in the art will understand that such block, unit, and/or module are/is physically implemented by a logic circuit, an individual component, a microprocessor, a hard wire circuit, a memory element, a line connection, and other electronic circuits. This may be formed using a semiconductor-based manufacturing technique or other manufacturing techniques. The block, unit, and/or module implemented by a microprocessor or other similar hardware may be programmed and controlled using software to perform various functions discussed herein, optionally may be driven by firmware and/or software. In addition, each block, unit, and/or module may be implemented by dedicated hardware, or a combination of dedicated hardware that performs some functions and a processor (for example, one or more programmed microprocessors and related circuits) that performs a function different from those of the dedicated hardware. In addition, in some embodiments, the block, unit, and/or module may be physically separated into two or more interact individual blocks, units, and/or modules without departing from the scope of the present disclosure. Inaddition, in some embodiments, the block, unit and/or module may be physically combined into more complex blocks, units, and/or modules without departing from the scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

is a diagram illustrating a display device in accordance with one or more embodiments of the disclosure.

Referring to, a display devicein accordance with one or more embodiments of the disclosure may include a timing controller, a data driver, a scan driver, a pixel unit, and an emission driver.

The timing controllermay receive grayscales for an input image (or an input frame). The grayscales may include a first color grayscale, a second color grayscale, and a third color grayscale. The first color grayscale may be a grayscale for expressing a first color, the second color grayscale may be a grayscale for expressing a second color, and the third color grayscale may be a grayscale for expressing a third color.

Also, the timing controllermay receive a control signal for an image. The control signal may include a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal. The vertical synchronization signal may include a plurality of pulses, and indicate that a previous frame period is ended and a current frame period is started with respect to a time point at which each of the pulses is generated. An interval between adjacent pulses of the vertical synchronization signal may correspond to a frame period. The horizontalsynchronization signal may include a plurality of pulses, and indicate that a previous horizontal period is ended and a new horizontal period is started with respect to a time point at which each of the pulses is generated. An interval between adjacent pulses of the horizontal synchronization signal may correspond to a horizontal period. The data enable signal may have an enable level with respect to corresponding horizontal periods and have a disable level in remaining periods. If the data enable signal is at the enable level, color grayscales may be supplied in corresponding periods.

The timing controllermay provide the data driverwith grayscales rendered or corrected to be suitable for specifications of the display device, using the grayscales for the input frame. In some embodiments, the timing controllermay provide the data driverwith grayscales which are not particularly corrected. Also, the timing controllermay provide the scan driverwith clock signals CLKs, CLKs, and CLKs, scan start signals GSP, GSP, and GSP, and the like. The timing controllermay provide the emission driverwith clock signals CLKeand CLKe, emission stop signals ESPand ESP, and the like.

The data drivermay generate data voltages to be provided to data lines DL, . . . , DLj, . . . , and DLq, using grayscales and control signals, which are received from the timing controller. For example, the data drivermay sample grayscales, using a clock signal, and apply data voltages corresponding to the grayscales to the data lines DLto DLq in units of pixel rows. Here, q may be an integer greater than 1, and j may be an integer greater than 0 and less than q.

The scan drivermay include first to third scan driversGW,GI, andGR. The first scan driverGW may provide first scan signals to first scan lines GW, . . . , GWi, . . . , and GWp. Here, p may be an integer greater than 1, and i may be an integer greater than 0 and less than p. The second scan driverGI may provide second scan signals to second scan lines Gl, . . . , Gli, . . . , and Glp. The third scan driverGR may provide third scan signals to third scan lines GR, . . . , GRi, . . . , GRp.

For example, the first scan driverGW may generate the first scan signals to be supplied to the first scan lines GWto GWp by receiving at least one clock signal CLKsand a first scan start signal GSPfrom the timing controller. The first scan driverGW may sequentially provide the first scan signals having a pulse of a turn-on level to the first scan lines GWto GWp. For example, the first scan driverGW may be configured in the form of shift registers, and generate the first scan signals in a manner that sequentially transfers the first scan start signal GSPin the form of a pulse of a turn-on level to a next scan stage under the control of the clock signal CLKs.

The second scan driverGI may generate the second scan signals to be supplied to the second scan lines Glto Glp by receiving at least one clock signal CLKsand a second scan start signal GSPfrom the timing controller. The third scan driverGR may generate the third scan signals to be supplied to the third scan lines GRto GRp by receiving at least one clock signal CLKsand a third scan start signal GSPfrom the timing controller. The second scan driverGI and the third scan driverGR may be configured substantially identically to the first scan driverGW, and therefore, overlapping descriptions will be omitted.

The emission drivermay include a first emission driverEM and a second emission driverEMB. The first emission driverEM may provide first emission signals to first emission lines EM, . . . , EMi, . . . , and EMp. The second emission driverEMB may provide second emission signals to second emission lines EMB, . . . , EMBi . . . , and EMBp.

For example, the first emission driverEM may generate the first emission signals to be supplied to the first emission lines EMto EMp by receiving at least one clock signal CLKeand a first emission stop signal ESPfrom the timing controller. The first emission driverEM may sequentially provide the first emission signals having a pulse of a turn-on level to the first emission lines EMto EMp. For example, the first emission driverEM may be configured in the form of shift registers, and may generate the first emission signals in a manner that sequentially transfers the first emission stop signal ESPin the form of a pulse of a turn-on level to a next (e.g., subsequent) scan stage under the control of the clock signal CLKe.