Method for Preparing Tem Sample

This application claims priority to Chinese patent application No. CN202410816298.7, filed on Jun. 21, 2024, the disclosure of which is incorporated herein by reference in its entirety.

The present disclosure relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for preparing a TEM sample.

As the integrated circuit (IC) process shrinks, improvements to the process may cause various problems in a chip. An effective means for failure analysis is cutting the chip using a focused ion beam (FIB) to prepare a sample with a thickness less than 100 nm and then observing the sample using a transmission electron microscope (TEM). Due to different process stations, it is sometimes required to perform fixed-point failure analysis of the front end of line on a chip of the back end of line.

In an existing positioning method, auxiliary localization of a target position on a lower layer is performed according to a layout of an upper layer structure, and then the target position on the lower layer is located by observing a change in a pattern of the upper layer structure during a TEM sample preparation process. However, the presence of different materials above a target result in different etch rates on the surface of the sample, affecting the flatness of a cross section, which is directly represented by ion beam pull marks in the shape of vertical strips generated on the cross section, i.e., a “curtain effect”. The “curtain effect” affects the thickness of the sample, making it difficult to expose some minor failure points, thereby affecting the failure analysis of the chip.

In addition, for some samples at the back end of metal, analysis for information of a metal gate is required. Since there are numerous metal lines with repeated structures above the metal gate, and sometimes one metal line contains multiple sets of metal gates, it is difficult to accurately locate the target position according to the layout of the upper layer structure alone, making it difficult to prepare a TEM sample. Therefore, there is an urgent need for a TEM sample preparation method, with which the target position in a lower layer structure can be accurately located.

According to some embodiments in this application, a method for preparing a TEM sample is disclosed in the following steps:

In some cases, the semiconductor substrate includes a silicon substrate.

In some cases, the target pattern layer includes a gate layer.

In some cases, the top pattern layer includes a metal interconnection layer.

In some cases, a gate structure in the gate layer includes a metal gate.

In some cases, a metal grid is provided on the sample stage, and the chip sample is fixed to the metal grid by means pf soldering.

In some cases, one of the third side and the fourth side of the chip sample is fixed to the metal grid.

In some cases, the width of the chip sample serves as a thickness, and the thickness of the chip sample is greater than 500 nm.

In some cases, the thickness of the TEM sample is less than 100 nm.

In some cases, the FIB system is a dual-beam system provided with a FIB and an electron beam, and there is a 52-degree angle between the FIB and the electron beam.

In some cases, the first protective layer is formed by means of an electron beam assisted deposition process.

In some cases, the second protective layer is formed by means of an electron beam assisted deposition process.

In some cases, the material of the second protective layer includes carbon.

In some cases, the sample stage has translation and rotation functions.

In some cases, the FIB mark pattern is composed of a plurality of trench strips and includes at least a first trench strip and a second trench strip parallel to each other, the first trench strip and the second trench strip respectively define two length edges of the TEM sample, and a distance between the first trench strip and the second trench strip defines the thickness of the TEM sample.

For the preparation of the TEM sample of the target pattern layer having the top pattern layer, in the present disclosure, the first-time FIB cutting is first performed to remove the top pattern layer and expose the target pattern layer, and then the FIB mark pattern is formed directly on the surface of the target pattern layer using a FIB for marking, where the FIB mark pattern is arranged according to the target position of the TEM sample, so that the FIB mark pattern may define the target position of the TEM sample. After that, the second-time cutting may be performed on the chip sample based on the localization of the FIB mark pattern, so as to implement accurate localization of the TEM sample.

In addition, since the first-time FIB cutting involves only the top pattern layer and does not involve a region below the target pattern layer, and the top pattern layer has been removed before the second-time cutting, no curtain effect is generated in the present disclosure.

Accordingly, with the present disclosure, the TEM sample of the target pattern layer having the top pattern layer can be accurately located without generating a curtain effect.

is a flowchart of a method for preparing a TEM sample according to an embodiment of the present disclosure.are schematic diagrams of structures of a chip samplein steps of the method for preparing a TEM sample according to an embodiment of the present disclosure. The method for preparing a TEM sample according to an embodiment of the present disclosure includes the following steps.

Step S: Referring to, the chip sampleis fixed on a sample stageof a FIB system.

The chip sampleincludes a semiconductor substrate, a target pattern layerformed above a top surface of the semiconductor substrate, and a top pattern layerlocated above the target pattern layer.

shows a three-dimensional structure of the chip sample. Referring to, the chip samplehas a cuboid structure, a bottom surfaceof the chip sampleis a bottom surface of the semiconductor substrate, a top surfaceof the chip sampleis a top surface of the top pattern layer, and the chip sampleincludes a first sideand a second sideopposite each other and composed of a length and a height and a third sideand a fourth sideopposite each other and composed of a width and a height. In, the first sideis a front side, the second sideis a back side, the third sideis a left side, and the fourth sideis a right side.

In the embodiment of the present disclosure, the semiconductor substrateincludes a silicon substrate.

The target pattern layerincludes a gate layer. A gate structure in the gate layer includes a metal gate.

The top pattern layerincludes a metal interconnection layer. In an existing method, the position of TEM sample is usually located subsequently using a pattern of the metal interconnection layer. However, one metal line in the metal interconnection layer often includes multiple sets of the metal gates, and therefore accurate localization cannot be achieved. Moreover, in the existing method, during thinning of the TEM sample, i.e., the FIB cutting, the TEM sample is cut in a direction from the metal interconnection layer to the metal gate, thereby generating a curtain effect.

In the embodiment of the present disclosure, a metal grid is provided on the sample stage, and the chip sampleis fixed to the metal grid by means pf soldering.

One of the third sideand the fourth sideof the chip sampleis fixed to the metal grid.

The width of the chip sampleserves as a thickness, and the thickness of the chip sampleis greater than 500 nm. Typically, the chip sampleis obtained by performing cutting and thinning processes on a wafer composed of the semiconductor substrate.

The FIB system is a dual-beam system provided with a FIB and an electron beam, and there is a 52-degree angle between the FIB and the electron beam.

The sample stagehas translation and rotation functions. A focusing height may be adjusted using a motion function of the sample stage, e.g., adjusting an eucentric height. The direction of cutting the chip samplewith the FIB and a corresponding deposition surface for electron beam deposition may be adjusted using the rotation function of the sample stage. The sample stageis usually arranged on a quick flip stage to implement a quick flip of the sample stage, e.g., a 90° flip, a 180° flip, etc. The sample stageis also capable of a rotation of an angle of 52°, so as to facilitate a switch between FIB processing and electron beam processing.

shows that the third sideof the chip sampleis fixed to the metal grid. The third sideof the chip samplebeing fixed to the metal grid is illustrated as an example below. A front side observed in a direction toward the paper inis the first side. In, the metal grid is in a vertical state.

Step S: Referring to, a first protective layeris formed on one of the first sideand the second side. In, the first protective layeris formed on the first side. Since the first sideand the second sideare symmetrical, in other embodiments, the first protective layermay also be formed on the second side.

The metal grid inis subjected to a flip of 90 degrees relative to that in, which can be achieved by means of the quick flip stage. A front side observed in the direction toward the paper inis the fourth side. The first sideis at the top, and the second sideis the bottom.

In the embodiment of the present disclosure, the first protective layeris formed by means of an electron beam assisted deposition process. The material of the first protective layerincludes metal, such as platinum or tungsten.

Step S: Referring to, first-time FIB cutting is performed on the chip sampleusing a FIB, to remove the top pattern layerand to expose a top surface of the target pattern layer, where a direction of the first-time FIB cutting points from a side on which the first protective layeris located to another side opposite the side.

A front side observed in the direction toward the paper inis also the fourth side. The first sideis at the top, and the second sideis the bottom. However, compared with, in step S, it is required to adjust the eucentric height and rotate the sample stageby 52 degrees.

A region indicated by a dashed lineinis a region removed by the first-time FIB cutting. A front side observed in the direction toward the paper inis also the fourth side. The top surfaceof the chip sampleis transferred downward to the top surfaceof the target pattern layer.

Step S: Referring to, the top surface of the target pattern layeris etched using a FIB, to form a FIB mark patternthat defines a target position of the TEM sample.

The front side observed in the direction toward the paper inis the top surfaceof the target pattern layer.

In the embodiment of the present disclosure, the FIB mark patternis composed of a plurality of trench strips and includes at least a first trench strip and a second trench strip parallel to each other, the first trench strip and the second trench strip respectively define two length edges of the TEM sample, and a distance between the first trench strip and the second trench strip defines the thickness of the TEM sample. In, the FIB mark patternfurther includes a third trench strip perpendicularly intersecting the first trench strip and the second trench strip.

In the embodiment of the present disclosure, the FIB mark patternis close to the fourth side. In other embodiments, the FIB mark patternmay also be located at another suitable position between the third sideand the fourth side, as long as the position of the TEM sample can be accurately defined.

Step S: Referring to, a second protective layeris formed on the top surfaceof the target pattern layer.

In the embodiment of the present disclosure, the second protective layeris formed by means of an electron beam assisted deposition process.

The material of the second protective layerincludes carbon.

The front side observed in the direction toward the paper inis a top surface of the first protective layer. A bottom surface of the first protective layeris the first side.