Integrated Circuit Providing Various Channel Lengths

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0080590, filed on Jun. 20, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

The disclosure relates to an integrated circuit, and more particularly, to an integrated circuit including various channel lengths.

Along with the development of a semiconductor process, the sizes of devices included in an integrated circuit may decrease, and the degree of integration of the integrated circuit may increase. The integrated circuit may include a digital circuit (such as a logic gate, configured to process a digital signal), an analog circuit (such as an amplifier, configured to process an analog signal), and a mixed circuit (such as an analog-digital converter, configured to process an analog signal and a digital signal). The analog circuit and the mixed circuit configured to process an analog signal may require devices having various characteristics, for example, transistors having various channel lengths. Accordingly, it may be essential to efficiently integrate devices having various characteristics in an integrated circuit through a semiconductor process.

Provided is an integrated circuit including various channel lengths.

According to an aspect of the disclosure, an integrated circuit includes: a first device region and a second device region extending parallel to each other on a substrate in a first direction; a first gate electrode extending in a second direction and intersecting with the first device region and the second device region; a first transistor including the first gate electrode and a first channel having a first conductive-type in the first device region; and a second transistor including the first gate electrode and a second channel having the first conductive-type in the second device region, wherein a first source/drain region of the first transistor is electrically connected to a first source/drain region of the second transistor, and wherein a second source/drain region of the first transistor is electrically disconnected from a second source/drain region of the second transistor.

The integrated circuit further includes: a second gate electrode extending in the second direction and intersecting with the first device region and the second device region; a third transistor comprising the second gate electrode and a third channel having the first conductive-type in the first device region; and a fourth transistor comprising the second gate electrode and a fourth channel having the first conductive-type in the second device region.

he integrated circuit further includes: a third transistor comprising the second gate electrode and a third channel having the first conductive-type in the first device region, and a fourth transistor comprising the second gate electrode and the fourth channel having the first conductive-type in the second device region.

The integrated circuit further includes: a third transistor comprising the second gate electrode and a third channel having a second conductive-type in the first device region, and a fourth transistor comprising the second gate electrode and a fourth channel having the second conductive-type in the second device region.

According to an aspect of the disclosure, an integrated circuit includes: a first device region extending on a substrate in a first direction; a first gate electrode and a second gate electrode extending in a second direction, being parallel to each other, and intersecting with the first device region; a first transistor including the first gate electrode and a first channel having a first conductive-type in the first device region; and a second transistor including the second gate electrode and a second channel having the first conductive-type in the first device region, wherein the first transistor and the second transistor are configured to share a first source/drain region between the first gate electrode and the second gate electrode, and wherein the first gate electrode is electrically connected to the second gate electrode.

The integrated circuit may further includes: a third gate electrode extending in the second direction and intersecting with the first device region; a third transistor comprising the third gate electrode and a third channel having the first conductive-type channel in the first device region, wherein the second transistor and the third transistor are configured to share a source/drain region between the second gate electrode and the third gate electrode, and wherein the third gate electrode is electrically connected to the second gate electrode.

The integrated circuit may further includes: a third transistor comprising the third gate electrode and a third channel having the first conductive-type in the first device region.

The integrated circuit may further includes: a third transistor comprising the third gate electrode and a third channel having a second conductive-type in the first device region.

According to an aspect of the disclosure, an integrated circuit includes: a first transistor and a second transistor having a first conductive-type channel and connected in series to each other; and a third transistor and a fourth transistor having a second conductive-type channel and connected in series to each other, wherein a first gate of the first transistor and a second gate of the second transistor are electrically connected to a first node, and wherein a third gate of the third transistor and a fourth gate of the fourth transistor are electrically connected to a second node.

The terms as used in the disclosure are provided to merely describe specific embodiments, not intended to limit the scope of other embodiments. Singular forms include plural referents unless the context clearly dictates otherwise. The terms and words as used herein, including technical or scientific terms, may have the same meanings as generally understood by those skilled in the art. The terms as generally defined in dictionaries may be interpreted as having the same or similar meanings as or to contextual meanings of the relevant art. Unless otherwise defined, the terms should not be interpreted as ideally or excessively formal meanings. Even though a term is defined in the disclosure, the term should not be interpreted as excluding embodiments of the disclosure under circumstances.

The terms “include” and “comprise”, and the derivatives thereof refer to inclusion without limitation. The term “or” is an inclusive term meaning “and/or”. The phrase “associated with,” as well as derivatives thereof, refer to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, have a relationship to or with, or the like. The term “controller” refers to any device, system, or part thereof that controls at least one operation. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. The phrase “at least one of,” when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one item in the list may be needed. For example, “at least one of A, B, and C” includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A and B and C, and any variations thereof. As an additional example, the expression “at least one of a, b, or c” may indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. Similarly, the term “set” means one or more. Accordingly, the set of items may be a single item or a collection of two or more items.

In the disclosure, in order to determine whether a specific condition is satisfied or fulfilled, an expression of more than or less than may be used, but this is only a description for expressing an example, and does not exclude description of more than or equal to or less than or equal to. A condition described as ‘more than or equal to’ may be replaced with ‘more than’, a condition described as ‘less than or equal to’ may be replaced with ‘less than’, and a condition described as ‘more than or equal to and less than’ may be replaced with ‘more than and less than or equal to’.

are circuit diagrams illustrating integrated circuitsandaccording to embodiments. For example, the circuit diagram ofshows some of devices included in the integrated circuit. The circuit diagram ofshows some of devices included in the integrated circuit

Referring to, the integrated circuitmay include a first circuit, a second circuit, and a third circuit. In some embodiments, the first circuit, the second circuit, and the third circuitmay respectively include devices which process an analog signal and have different characteristics. For example, the first circuit, the second circuit, and the third circuitmay respectively include transistors having different channel lengths. A channel length may indicate the channel length of a transistor and, for example, may correspond to the distance between a source and a drain in a field effect transistor (FET) and may be proportional to a gate length. An analog circuit may require transistors having various channel lengths in accordance with circumstances, and the integrated circuitmay include transistors having various channel lengths. Examples of the transistor are described below with reference to.

As shown in, the first circuitmay include a first n-channel field effect transistor (NFET) Nand a first p-channel field effect transistor (PFET) P. The second circuitmay include a second NFET Nand a second PFET P. The third circuitmay include a third NFET Nand a third PFET P. The first NFET Nmay have a shorter channel length than the second NFET Nand the third NFET N. The first PFET Pmay have a shorter channel length than the second PFET Pand the third PFET P. The second NFET Nmay have a shorter channel length than the third NFET N. The second PFET Pmay have a shorter channel length than the third PFET P. Herein, an NFET may be referred to as a transistor having a first conductive-type (or second conductive-type) channel, and a PFET may be referred to as a transistor having the second conductive-type (or first conductive-type) channel.

Due to a semiconductor process (for example, a local layout effect (LLE) or the like), a space between transistors having different channel lengths may be required. For example, when the first NFET Nis adjacent to the second NFET Nin the layout of the integrated circuit, the first NFET Nand/or the second NFET Nmay not be normally formed due to limitations of the semiconductor process. Or, the first NFET Nand the second NFET Nmay not provide designed performance due to the LLE. Accordingly, in the layout of the integrated circuit, a space may be required between the first NFET Nand the second NFET N, i.e., between the first circuitand the second circuit. As a result, in the related art, the layout of the integrated circuitincluding the first circuit, the second circuit, and the third circuitmay have low efficiency.

Referring to, the integrated circuitmay include a first circuit, a second circuit, and a third circuit, which may respectively correspond to the first circuit, the second circuit, and the third circuitof. Unlike the integrated circuitof, which includes transistors having different channel lengths, the integrated circuitofmay include transistors having a uniform channel length.

As shown in, the first circuitmay include the first NFET Nand the first PFET P. The second circuitmay include second NFETs Nand Nand second PFETs Pand P. The third circuitmay include third NFETs Nto Nand third PFETs Pto P. The first NFET N, the second NFETs Nand N, and the third NFETs Nto Nmay have the same channel length.

In an embodiment, the first PFET P, the second PFETs Pand P, and the third PFETs Pto Pmay have the same channel length. Accordingly, in the layout of the integrated circuitof, a space among the first circuit, the second circuit, and the third circuitmay be removed or minimized. In some embodiments, the channel length of each of the first NFET N, the second NFETs Nand N, and the third NFETs Nto Nmay correspond to the minimum channel length of NFETs in the integrated circuit, and the channel length of each of the first PFET P, the second PFETs Pand P, and the third PFETs Pto Pmay correspond to the minimum channel length of PFETs in the integrated circuit

In the second circuit, the second NFETs Nand Nmay be connected in series to each other and respectively have gates connected to a node N. Accordingly, the second NFETs Nand Nmay provide an effective channel length corresponding to the channel length of the second NFET Nof. In an embodiment, in the second circuit, the second PFETs Pand Pmay be connected in series to each other and respectively have gates connected to a node N. Accordingly, the second PFETs Pand Pmay provide an effective channel length corresponding to the channel length of the second PFET Pof.

In an embodiment, in the third circuit, the third NFETs Nto Nmay be connected in series to each other and respectively have gates connected to a node N. Accordingly, the third NFETs Nto Nmay provide an effective channel length corresponding to the channel length of the third NFET Nof.

In an embodiment, in the third circuit, the third PFETs Pto Pmay be connected in series to each other and respectively have gates connected to a node N. Accordingly, the third PFETs Pto Pmay provide an effective channel length corresponding to the channel length of the third PFET Pof.

As described above, the integrated circuitmay provide transistors having various channel lengths through uniform transistors. Accordingly, due to the various channel lengths, the integrated circuitmay provide an analog circuit having improved performance. In an embodiment, overhead for integrating transistors having various channel lengths may be reduced, and the area of the integrated circuitmay be reduced or the degree of integration of the integrated circuitmay be improved. In an embodiment, the layout of the integrated circuitmay have a uniform structure, and because variation is reduced, the integrated circuitmay provide improved reliability. Hereinafter, with reference to drawings, structures in which transistors having various channel lengths are provided by uniform transistors are described. Hereinafter, PFETs are mainly described, but it would be understood that embodiments are also applicable to NFETs.

are perspective views illustrating transistors according to embodiments. For example,shows a fin-shaped field effect transistor (FinFET).shows a gate-all-around field effect transistor (GAAFET).shows a multi-bridge channel field effect transistor (MBCFET).shows a vertical field effect transistor (VFET).show that one of two source/drain regions is removed.shows a cross-section of the VFETas a plane that is parallel to a plane formed by the Y axis and the Z axis and passes through a channel CH of the VFET

Referring to, the FinFETmay be formed by a fin-shaped active pattern extending in the X-axis direction between shallow trench isolations (STIs) and a gate G extending in the Y-axis direction. A “source/drain SD” may be formed at (or included in) both sides of the gate G, and accordingly, a source and a drain may be spaced apart from each other in the X-axis direction. Throughout the disclosure, the term ‘source/drain SD’ indicates that an area of the source area S and another area of the drain area D can be interchangeable in the embodiments of the disclosure.

An insulating layer may be formed between a channel CH and the gate G. In some embodiments, the FinFETmay be formed by a plurality of active patterns spaced apart from each other in the X-axis direction and the gate G.

Referring to, the GAAFETmay be formed by active patterns, i.e., nanowires, spaced apart from each other in the Z-axis direction and extending in the X-axis direction and the gate G extending in the Y-axis direction. The source/drain SD may be formed at both sides of the gate G, and accordingly, a source and a drain may be spaced apart from each other in the X-axis direction. An insulating layer may be formed between the channel CH and the gate G. The three rectangles shown in(one rectangle indicated by ‘CH’) are the nanowires. The number of nanowires included in the GAAFETofis not limited to that shown in.

Referring to, the MBCFETmay be formed by active patterns, i.e., nanosheets, spaced apart from each other in the Z-axis direction and extending in the X-axis direction and the gate G extending in the Y-axis direction. The source/drain SD may be formed at both sides of the gate G, and accordingly, a source and a drain may be spaced apart from each other in the X-axis direction. An insulating layer may be formed between the channel CH and the gate G. The three rectangles shown in(one rectangle indicated by ‘CH’) are the nanosheets. The number of nanosheets included in the MBCFETofis not limited to that shown in.

Referring to, the VFETmay include a top source/drain T_SD and a bottom source/drain B_SD spaced apart from each other in the Z-axis direction with the channel CH therebetween. The VFETmay include the gate G surrounding the perimeter of the channel CH between the top source/drain T_SD and the bottom source/drain B_SD. An insulating layer may be formed between the channel CH and the gate G.

Hereinafter, an integrated circuit including the FinFETor the MBCFETis mainly described, but devices included in the integrated circuit are not limited to the examples of. For example, the integrated circuit may include a ForkFET having a structure in which an N-type transistor is relatively close to a P-type transistor because nanosheets for the P-type transistor and nanosheets for the N-type transistor are separated by a dielectric wall. In an embodiment, the integrated circuit may include an FET (such as a complementary field effect transistor (CFET), a negative capacitance field effect transistor (NCFET), or a carbon nanotube (CNT) FET) and a bipolar junction transistor.

is a top view illustrating a layoutof an integrated circuit according to an embodiment. For example, the top view ofshows the layoutincluding the first PFET Pof. Hereinafter, the layoutofincludes the first PFET Pof, andis described with reference to.

Herein, the X-axis direction and the Y-axis direction may be referred to as a first direction and a second direction, respectively, and the Z-axis direction may be referred to as the vertical direction or a third direction. The Z-axis direction may be perpendicular to (or substantially perpendicular to) the X-axis direction and the Y-axis direction.

A plane formed by the X axis and the Y axis may be referred to as a ‘horizontal plane.’ A component disposed relatively in the +Z direction than another component may be considered to be ‘above’ the other component, and a component disposed relatively in the −Z direction than another component may be considered to be ‘below’ the other component. In an embodiment, the ‘area’ of a component may indicate a ‘size’ occupied by the component on a plane parallel to the horizontal plane, and the ‘width’ of a component may indicate a ‘length’ of the component in a direction perpendicular to the direction in which the component extends.

A surface exposed in the +Z direction may indicate a ‘top’ surface, a surface exposed in the −Z direction may indicate a ‘bottom’ surface, and a surface exposed in the +X direction or the +Y direction may indicate a ‘side’ surface. In the drawings, only some layers may be shown, and a via connecting a higher pattern to a lower pattern may be shown even though the via is beneath the higher pattern. In an embodiment, a pattern, such as a pattern of a wiring layer, formed of a conductive material may be referred to as a ‘conductive pattern’ or simply as a ‘pattern.’

Referring to, the layoutmay include a first device region RXextending in the X-axis direction. A first gate electrode Gmay extend in the Y-axis direction and intersect with the first device region RX. The first gate electrode Gmay form (or include) the first PFET Pin the first device region RX. For example, as shown in, in the first device region RX, a first active pattern ACmay extend in the X-axis direction and intersect with the first gate electrode G. A first source/drain SDand a second source/drain SDmay be respectively at both sides of the first gate electrode G. Accordingly, the first PFET Pmay have a ‘channel length’ corresponding to the width (i.e., the length in the X-axis direction) of the first gate electrode G. In some embodiments, as described above with reference to, the channel length of the first PFET Pmay correspond to the minimum channel length in the integrated circuit. In some embodiments, an analog signal may be applied to the first gate electrode G.

A first contact CAand a second contact CAmay be connected to the first source/drain SDand the second source/drain SD, respectively, and extend in the Y-axis direction. A first pattern Mof a first wiring layer Mmay be connected to the first contact CAthrough a via of a first via layer Vand extend in the X-axis direction. In an embodiment, a second pattern Mof the first wiring layer Mmay be connected to the second contact CAthrough a via of the first via layer Vand extend in the X-axis direction. Vias may be on the first pattern Mand the second pattern M. The first pattern Mand the second pattern Mmay be connected to patterns of a higher wiring layer through the vias. In some embodiments, the first wiring layer Mmay be a wiring layer closest to a gate electrode.

A first diffusion break DBand a second diffusion break DBmay extend in the Y-axis direction and intersect with the first device region RX. As shown in, the first gate electrode Gmay extend in the Y-axis direction between the first diffusion break DBand the second diffusion break DB. As shown in, the first gate electrode G, the first diffusion break DB, and the second diffusion break DBmay extend in the Y-axis direction at the same pitch CPP therebetween. The first diffusion break DBand the second diffusion break DBmay include an insulating material and isolate the first PFET Pfrom the other PFETs formed in the first device region RX. Like the first diffusion break DBand the second diffusion break DB, a diffusion break substituting for a gate electrode may be referred to as a single diffusion break (SDB).

illustrate a layoutof an integrated circuit according to an embodiment. For example,is a top view illustrating the layoutincluding the third PFETs Pto Pof.are examples of cross-sectional view cut along line X-X′ of the layoutof.is a cross-sectional view cut along line Y-Y′of the layoutof. Hereinafter, the layoutofincludes the third PFETs Pto Pof.are described with reference to, and the description made above with reference to the drawings is omitted herein.

Referring to, the layoutmay include the first device region RXand a second device region RXextending in the X-axis direction, which are parallel to each other. The first gate electrode Gand a second gate electrode Gmay extend in the Y-axis direction, may be parallel to each other, and may intersect with the first device region RXand the second device region RX.

The first gate electrode Gmay form two PFETs (e.g., the third PFETs Pand Pof) in the first device region RXand the second device region RX, respectively, and the second gate electrode Gmay form two PFETs (e.g., the third PFETs Pand Pof) in the first device region RXand the second device region RX, respectively. As shown in, the first active pattern ACmay extend in the X-axis direction in the first device region RXand intersect with the first gate electrode Gand the second gate electrode G. In an embodiment, a second active pattern ACmay extend in the X-axis direction in the second device region RXand intersect with the first gate electrode Gand the second gate electrode G.

As shown in, the two PFETs formed by the first gate electrode Gand the second gate electrode Gin the first device region RXmay share one source/drain (i.e., the second source/drain SDof), and the two PFETs formed by the first gate electrode Gand the second gate electrode Gin the second device region RXmay share one source/drain. The first gate electrode Gmay be electrically connected to the second gate electrode Gthrough a fourth pattern Mof the first wiring layer M, and the fourth pattern Mmay be included in the node Nof. The first gate electrode Gand the second gate electrode Gmay have the same width (i.e., a length in the X-axis direction), and the four transistors, i.e., the third PFETs Pto P, formed by the first gate electrode Gand the second gate electrode Gmay have the same channel length. In some embodiments, as described below with reference to, a source/drain of a PFET in the first device region RXmay be electrically connected to a source/drain of a PFET in the second device region RXvia a pattern (not shown) extending in the Y-axis direction. As shown in, the patterns of the first wiring layer Mmay extend in the X-axis direction.

The first diffusion break DBand the second diffusion break DBmay extend in the Y-axis direction and intersect with the first device region RXand the second device region RX. As shown in, the first gate electrode Gand the second gate electrode Gmay extend in the Y-axis direction between the first diffusion break DBand the second diffusion break DB.

Referring to, on a substrate SUB, the first gate electrode Gand the second gate electrode Gmay extend in the Y-axis direction and the first active pattern ACmay extend in the X-axis direction. The first source/drain SDmay be between the first diffusion break DBand the first gate electrode G, the second source/drain SDmay be between the first gate electrode Gand the second gate electrode G, and a third source/drain SDmay be between the second gate electrode Gand the second diffusion break DB. The first contact CA, the second contact CA, and a third contact CAmay be on the first source/drain SD, the second source/drain SD, and the third source/drain SD, respectively. A first via Vmay be on the first contact CA, and the first pattern Mof the first wiring layer Mmay be electrically connected to the first source/drain SDthrough the first via Vand the first contact CA. A second via Vmay be on the third contact CA, and the second pattern Mof the first wiring layer Mmay be electrically connected to the third source/drain SDthrough the second via Vand the third contact CA.

In some embodiments, the layoutmay include a pattern extending on the backside of the substrate SUB. For example, as shown in, in the layout, beneath the substrate SUB, a first backside pattern BMand a second backside pattern BMmay extend in a first backside wiring layer BMand a backside interlayer dielectric (BILD) may be disposed between the first backside pattern BMand the second backside pattern BM. A first backside contact BCmay extend in the Z-axis direction by penetrating the substrate SUB between the first source/drain SDand the first backside pattern BM, and the first backside pattern BMmay be electrically connected to the first source/drain SDthrough the first backside contact BC. A second backside contact BCmay extend in the Z-axis direction by penetrating the substrate SUB between the third source/drain SDand the second backside pattern BM, and the second backside pattern BMmay be electrically connected to the third source/drain SDthrough the second backside contact BC. Backside contacts and backside patterns may be disposed under a certain rule due to uniform transistors, and problems due to non-uniformity of the backside contacts and the backside patterns in the layoutmay be resolved.

Referring to, the first source/drain SDand a fourth source/drain SDmay be on the substrate SUB. As shown in, the first source/drain SDmay be included in the first device region RX, and the fourth source/drain SDmay be included in the second device region RX. The first contact CAand a fourth contact CAmay be on the first source/drain SDand the fourth source/drain SD, respectively. The first via Vmay be on the first contact CA, and the first pattern Mof the first wiring layer Mmay be electrically connected to the first source/drain SDthrough the first via Vand the first contact CA. A third via Vmay be on the fourth contact CA, and a third pattern Mof the first wiring layer Mmay be electrically connected to the fourth source/drain SDthrough the third via Vand the fourth contact CA.

illustrate a layoutof an integrated circuit according to an embodiment. For example,is a top view illustrating the layoutincluding the third PFETs Pto Pof,is a cross-sectional view cut along line X-X′ of the layoutof, andis a cross-sectional view cut along line Y-Y′ of the layoutof. Hereinafter, the layoutofincludes the third PFETs Pto Pof.are described with reference to, and the description made above with reference to the drawings is omitted herein.