Electro-Optical Device and Electronic Apparatus

The present application is based on, and claims priority from JP Application Serial Number 2024-104904, filed Jun. 28, 2024, the disclosure of which is hereby incorporated by reference herein in its entirety.

The present disclosure relates to an electro-optical device and an electronic apparatus.

In an electro-optical device by a demultiplexer system, data lines are grouped in sets of a plurality of lines. A data signal is supplied to a data signal line provided corresponding to each group. The data signal is distributed to each of the data lines by a switching element in an on state or an off state that is determined by a selection signal (see, for example, JP-A-2007-240830).

In such an electro-optical device, the selection signal is supplied via a selection signal line that extends in a direction intersecting with the data line. Further, in order to shield the selection signal line and the data signal line, a constant potential wiring line may be provided so as to overlap with the selection signal line, the data signal line, and the like in plan view.

However, noise caused by the potential fluctuation in the selection signal may be superimposed onto the constant potential wiring line. The constant potential wiring line is often shared with a constant potential line used in another element. Thus, the potential fluctuation caused by noise superimposed onto the constant potential wiring line may lead to a problem of, for example, degradation in display quality.

In order to solve the above-mentioned problem an electro-optical device according to an aspect of the present disclosure includes a plurality of data lines including k data lines being grouped, k being an integer equal to or greater than 2, a data signal line to which a data signal according to gradation of a pixel is supplied, in a time-division manner, corresponding to the k data lines, k selection signal lines to each of which a selection signal is supplied, k inversion selection signals to each of which an inversion selection signal of the selection signal is supplied, the k inversion selection signal lines forming pairs with the k selection signal lines, a first switching element being provided corresponding to the plurality of data lines in an one-on-one manner, being in an on state or an off state between the data signal line and one data line, according to a selection signal supplied to one selection signal line among the k selection signal lines, and a constant potential wiring line overlapping with the k selection signal lines and the k inversion selection signal lines in plan view and being maintained at a predetermined potential.

Hereinafter, a projection display device according to an embodiment is described with reference to the drawings. In each drawing, dimensions and scales of respective portions are appropriately different from actual ones. Further, since embodiments to be described below are preferred specific examples, various technically preferable limitations are applied, but the scope of the present disclosure is not limited to these embodiments unless it is otherwise stated in the following description that the present disclosure is limited.

1 FIG. 1 100 is a perspective view illustrating a configuration of a moduleincluding an electro-optical deviceaccording to a first embodiment.

100 100 72 10 74 100 76 74 The electro-optical deviceis a transmissive liquid crystal panel used as a light bulb of a projection-type display apparatus, for example. The electro-optical deviceis accommodated in a frame-shaped casethat opens in a display regionhaving a rectangular shape. One end of an FPC substrateis coupled to the electro-optical device. Note that FPC is an abbreviation for flexible printed circuits. A plurality of terminalsare provided on the other end of the FPC substrate, and are coupled to an upper circuit, which is omitted in illustration.

30 74 74 76 A display control circuitof a semiconductor chip is mounted on the FPC substrateby face-down bonding. Video data is synchronized with a synchronization signal, and is supplied from the upper circuit to the FPC substratevia the plurality of terminalsare supplied. The video data defines gradation of the pixel in the image to be displayed, for example, in 8 bits.

10 10 Note that, in the drawing, an X direction is a longitudinal direction of the display region, and is an extension direction of a scanning line. A Y direction is a short direction of the display region, and is an extension direction of a data line.

100 100 When the electro-optical deviceis used as a light bulb of a projection-type display apparatus, transmitted images by three electro-optical devicescorresponding to the primary colors R (red), G (green), and B (blue) are synthesized, and thus a color image is expressed as described later.

Therefore, a pixel which is a minimum unit of a color image can be divided into a red sub-pixel by an electro-optical device corresponding to R, a green sub-pixel by an electro-optical device corresponding to G, and a blue sub-pixel by an electro-optical device corresponding to B. However, when there is no need to specify the colors of the red, green and blue sub-pixels, or, for example, when only brightness is of concern, there is no need to intentionally use the term sub-pixel. In view of this, in the present description, the red, green, and blue sub-pixels are simply described as “pixels”.

10 30 100 100 The synchronization signal includes a vertical synchronization signal for instructing the start of vertical scanning with respect to the pixels arrayed in the display region, a horizontal synchronization signal for instructing the start of horizontal scanning with respect to the pixels, and a clock signal indicating a timing for one pixel of the video data. The display control circuitprocesses the video data and the synchronization signal, and outputs a data signal and a control signal that are required for driving the electro-optical device. The data signal is a signal obtained by converting the video data into an analog signal, and the control signal is a signal for controlling vertical scanning and horizontal scanning in the electro-optical device.

30 74 30 76 Note that, instead of a configuration in which the display control circuitis mounted on the FPC substrate, there may be provided a configuration in which the display control circuitis mounted on the upper circuit to supply the video signal and the control signal via the terminal.

2 FIG. 1 1 100 30 10 100 130 150 is a block diagram illustrating an electrical configuration of the module. The moduleincludes the electro-optical deviceand the display control circuitdescribed above. In the peripheral edge of the display regionof the electro-optical device, a scanning line driving circuitand a peripheral circuitare provided.

100 130 150 The electro-optical deviceincludes a configuration in which a liquid crystal is sealed between an element substrate at which a thin film transistor or the like is formed and a counter substrate at which a common electrode is formed, and the scanning line driving circuitare the peripheral circuitformed at the element substrate.

10 100 110 10 12 14 12 110 12 14 110 In the display regionof the electro-optical device, pixel circuitscorresponding to pixels of an image to be displayed are arrayed in the matrix. In detail, in the display region, m scanning linesare provided to extend in a horizontal direction in the drawing, and (3n) data linesin total that are grouped in every three lines are provided to extend in a vertical direction in the drawing and to be electrically insulated from the scanning lines. Further, the pixel circuitsare provided corresponding to intersections between the M scanning linesand the (3n) data lines. Therefore, in the embodiment, the pixel circuitsare arranged in a matrix with m vertical rows×(3n) horizontal columns.

Herein, m is an integer equal to or greater than 2. n is an integer equal to or greater than 2. Note that, in the embodiment, it is assumed that m<(3n).

12 110 12 To generalize and describe the rows of the scanning linesand the rows in the pixel circuitsin a matrix array, an integer i equal to or greater than 1 and equal to or less than m is used. For example, the scanning linesmay be referred to as first, second, third, . . . , (i−1)-th, i-th, . . . (m−1)-th, and m-th rows in order from the top in the drawing.

14 110 14 Similarly, to generalize and describe the columns of the data linesand the columns in the pixel circuitsin a matrix array, an integer j equal to or greater than 1 and equal to or less than n is used. For example, to distinguish the data lines, the columns may be referred to as first, second, third, . . . , (3j−2)-th, (3j−1)-th, (3j)-th, . . . , (3n-2)-th, (3n-1)-th, and (3n)-th columns from the left in the drawing.

110 3 FIG. For the sake of convenience of the description, a configuration of the pixel circuitis described with reference to.

3 FIG. 110 12 14 is a diagram illustrating an equivalent circuit of a total of four of the pixel circuits, in two rows and two columns, corresponding to the intersections between two of the adjacent scanning linesand two of the adjacent data lines.

110 116 120 116 110 116 12 14 118 109 As illustrated in the drawing, the pixel circuitincludes a transistorand a liquid crystal element. The transistoris, for example, an N-channel thin film transistor. In the pixel circuit, the transistorhas a gate node coupled to the scanning line, a source node coupled to the data line, and a drain node coupled to the pixel electrodeand one end of a storage capacitor.

In the present description, the term “couple” means direct or indirect coupling or coupling between two or more elements, and includes, for example, coupling between two or more elements via different wiring layers and contact holes even when the two or more elements are not directly coupled in a semiconductor substrate.

108 110 118 108 105 118 108 110 120 118 108 105 The common electrodeis provided in common to all of the pixel circuitsat the counter substrate to face the pixel electrode. The common electrodeis maintained at a substantially constant potential Ccom over time. Then, a liquid crystalis interposed between the pixel electrodesand the common electrode. Therefore, for each of the pixel circuits, the liquid crystal elementis configured by the pixel electrode, the common electrode, and the liquid crystal.

109 120 140 140 108 The storage capacitoris electrically parallel to the liquid crystal element, and includes the other end coupled to a capacitance wiring line. The capacitance wiring lineis maintained at a constant potential over time, for example, at the potential Ccom that is the same as the common electrode.

2 FIG. 14 14 Referring back to the description in, in the embodiment, the (3n) data linesare grouped in every three lines. In a j-th group counted from the left, three data linescorrespond to the (3j−2)-th, the (3j−1)-th, and the (3j)-th columns.

14 14 14 14 Further, with regard to the data linesor columns, the (3j−2)-th column in the j-th group may be referred to as a first series, the (3j−1)-th column as a second series, and the (3j)-th column as a third series. In other words, in the j-th group, the data linein the first series corresponds to the (3j−2)-th column, the data linein the second series corresponds to the (3j−1)-th column, the data linein the third series corresponds to the (3j)-th column.

30 130 The display control circuitprocesses the video data and the synchronization signal that are supplied from the upper circuit, and outputs the control signal to the scanning line driving circuitand also outputs data signals Vid(1), Vid(2), Vid(3), . . . , Vid(n) and selection signals Sel(1) to Sel(3).

100 13 14 12 The data signals Vid(1), Vid(2), Vid(3), . . . , Vid(n) are supplied to the electro-optical devicevia the n data signal lines. The data signals Vid(1), Vid(2), Vid(3), . . . , Vid(n) are generalized and described. The data signal Vid(j) is a signal at a potential according to gradation of the three pixels corresponding to the intersections between the three data linesbelonging to the j-th group and the scanning linessubjected to horizontal scanning. In detail, the potential of the data signal Vid(j) changes in a time-division manner according to the gradation of the three pixels during the horizontal scanning period.

14 14 14 11 The selection signal Sel(1) is a signal for selecting the data linein the first series. Similarly, the selection signal Sel(2) is a signal for selecting the data linein the second series, and the selection signal Sel(3) is a signal for selecting the data linein the third series. Each of the logic levels of the selection signals Sel(1) to Sel(3) is inverted by a NOT circuit Iv, and the selection signals Sel(1) to Sel(3) are output sequentially as inversion selection signals/Sel(1) to/Sel(3), respectively.

Note that the selection signals Sel(1) to Sel(3) are supplied individually to the selection signal lines extending in the X direction, and the inversion signals being the inversion selection signals/Sel(1) to/Sel(3) are similarly supplied individually to inversion selection signal lines extending in the X direction.

Inversion refers to a relationship in which logic levels of logic signals that form a pair are reversed. The inversion selection signal is a signal whose logic level is the inverse of that of the selection signal. When the inversion selection signal is generated by inverting the selection signal by the NOT circuit, the inversion selection signal involves a time delay with respect to the selection signal. However, as described later, when noise caused by the selection signal can be canceled out by noise caused by the inversion selection signal, the time delay is not an issue.

30 130 12 12 12 Under control of the display control circuit, the scanning line driving circuitsupplies scanning signals individually to the scanning linesin the m rows. Here, the scanning signal supplied to the scanning linein the first row is denoted with Gwr(1). Similarly, the scanning signals supplied to the scanning linein the second, third, . . . , (i−1)-th, i-th, . . . , (m-i)-th, and m-th rows are denoted with Gwr(2), Gwr(3), . . . , Gwr(i−1), Gwr(i), . . . , Gwr(m−1), and Gwr(m), respectively.

30 130 130 The display control circuitoutputs various control signals for controlling the scanning line driving circuit. However, the control signals supplied to the scanning line driving circuitare not important in this application. Thus, only the signal paths are illustrated, and description for details of the above-mentioned controls signals is omitted.

150 13 14 150 1 1 14 The peripheral circuitis a circuit (demultiplexer) that distributes the data signals, which are supplied to the data signal line, to the respective data linesaccording to the selection signals Sel(1) to Sel(3). In detail, the peripheral circuitincludes a transistor Nand a NOT circuit Ivfor the data linein one column.

1 116 110 1 1 The transistor Nis an N-channel thin transistor similar to the transistorin the pixel circuit. The transistor Nand the NOT circuit Ivare described while focusing on the j-th group.

13 13 13 1 13 2 13 3 The data signal Vid(j) is supplied to the data signal linecorresponding to the j-th group. The data signal lineis split sequentially into three lines, specifically, data signal lines_,_, and_.

1 13 1 14 In the j-th group, the transistor Nin the first series includes an input end coupled to the data signal line_and an output end coupled to the j-th data linein the first series.

1 1 In the j-th group, the NOT circuit Ivin the first series re-inverts the logic level of the inversion selection signal/Sel(1), and outputs the resultant signal. The selection signal Sel(1) and the inversion signal of the inversion selection signal/Sel(1) are merged and supplied to the gate node of the j-th transistor Nin the first series.

1 13 2 14 In the j-th group, the transistor Nin the second series includes an input end coupled to the data signal line_and an output end coupled to the j-th data linein the second series.

1 1 In the j-th group, the NOT circuit Ivin the second series re-inverts the logic level of the inversion selection signal/Sel(2), and outputs the resultant signal. The selection signal Sel(2) and the inversion signal of the inversion selection signal/Sel(2) are merged and supplied to the gate node of the j-th transistor Nin the second series.

1 13 3 14 Similarly, in the j-th group, the transistor Nin the third series includes an input end coupled to the data signal line_and an output end coupled to the j-th data linein the third series.

1 1 In the j-th group, the NOT circuit Ivin the third series re-inverts the logic level of the inversion selection signal/Sel(3), and outputs the resultant signal. The selection signal Sel(3) and the inversion signal of the inversion selection signal/Sel(3) are merged and supplied to the gate node of the j-th transistor Nin the third series.

2 FIG. 100 100 Note thatis a diagram for describing an electrical configuration of the electro-optical devicefor better understanding. Next, in view of this, an actual arrangement of the respective elements in the electro-optical deviceis described.

4 FIG. 100 is a plan view illustrating an arrangement of the respective elements, in particular, an arrangement at the element substrate in the electro-optical device.

74 100 74 10 150 The one end of the FPC substrateis coupled to the one side of the electro-optical devicein the longitudinal direction as described above. Between the one end of the FPC substrateand the display region, the peripheral circuitis provided.

130 10 130 12 The scanning line driving circuitis provided outside of each of two sides of the display regionin the Y direction. There is adopted a configuration in which the two scanning line drive circuitsare provided and the scanning signal is supplied from both the ends of the scanning line. The reason for this configuration is to suppress an influence of a delay of the scanning signal on display as compared to a case in which the scanning signal is supplied from only one end.

30 130 11 2 FIG. 4 FIG. Note that the same control signal is supplied from the display control circuitto the two scanning line driving circuits. Further, the selection signals Sel(1) to Sel(3) are supplied from the left end in. However, as illustrated in, the selection signals Sel(1) to Sel(3) are supplied from both the right and left ends similarly to the scanning signal so as to suppress an influence of a delay. Similarly, the NOT circuit Ivis also provided to each of the right and left ends. Thus, the inversion selection signals/Sel (1) to/Sel(3) are also supplied from both the right and left ends.

5 FIG. 160 100 is a plan view illustrating an arrangement of a light shielding filmin the electro-optical device.

160 10 160 10 130 150 10 The light shielding filmdefines the display region. The light shielding filmis provided to surround the display regionin plan view so that entry of light into the scanning line driving circuit, the peripheral circuit, and the like is prevented. The expression “surround in plan view” refers to covering the outer region of the display region, which is a target to be surrounded, in a frame-like manner in plan view.

160 13 13 1 13 2 13 3 Further, a constant potential is applied to the light shielding filmso as to shield the data signal linebefore splitting and the data signal lines_,_, and_after splitting.

160 13 13 1 13 2 13 3 In other words, the light shielding filmoverlaps with the data signal lines,_,_, and_in plan view so as to shield those signal lines.

Note that, in the present description, the term “plan view” is to view one of the element substrate and the counter substrate from the other one.

160 140 109 140 10 160 10 160 In the embodiment, the light shielding filmis electrically coupled to the capacitance wiring linethat commonly couples the other ends of the storage capacitors, and is maintained at a potential Com. Note that the wiring layer forming the capacitance wiring linein the display regionand the wiring layer forming the light shielding filmoutside the display regionmay be different from each other, or may be the same. In any case, the light shielding filmmay be a wiring layer that is non-transparent to light and electrically conductive, specifically, using a material such as aluminum and titanium nitride.

6 FIG. 100 is a timing chart illustrating an operation of the electro-optical device.

100 12 130 In the electro-optical device, the m rows of scanning linesare scanned row by row in an order of first, second, third, . . . , m-th row in a period of a frame (V). In detail, as illustrated in the drawing, the scanning signals Gwr(1), Gwr(2), . . . , Gwr(i−1), Gwr(i), . . . , Gwr(m−1), and Gwr(m) are sequentially and exclusively set to an H level by the scanning line driving circuitfor each horizontal scanning period (H).

Note that, in the preset embodiment, periods in which the adjacent scanning signals among the scanning signals Gwr(1) to Gwr(m) are at the H level are separated in time. Specifically, after the scanning signal Gwr(i−1) changes from an L level to the H level, the next scanning signal Gwr(i) is at the H level after a period. This period corresponds to a horizontal blanking period.

In the present description, the period of the one frame (V) refers to a period required to display one frame of the image designated by the video data supplied from the upper circuit. When a length of the period of the one frame (V) is the same as a vertical synchronization period, for example, when a frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, the length is 16.7 milliseconds corresponding to one cycle of the vertical synchronization signal. Further, the horizontal scanning period (H) is a time interval at which the scanning signals Gwr(1) to Gwr(m) are sequentially at the H level, but for convenience in the drawing, a start timing of the horizontal scanning period (H) is approximately at a center of the horizontal blanking period.

121 110 110 120 109 14 110 120 109 110 14 When a certain scanning signal among the scanning signals Gwr(1) to Gwr(m), for example, the scanning signal Gwr(i) in the i-th row is at the H level, the transistorof the pixel circuitlocated in the i-th row is in an on state. Thus, in the pixel circuit, one end of the liquid crystal elementand the one end of the storage capacitorare in a state of electrically coupled to the corresponding data line. In a case of the pixel circuitin the i-th row and the (3j−2)-th column, the one end of the liquid crystal elementand the one end of the storage capacitorin the pixel circuitis in a state of electrically coupled to the data linein the (3j−2)-th column.

Note that, in the present description, an “ON state” of the transistor means that the source node and drain node of the transistor are electrically closed and enters a low impedance state. Moreover, an “off state” of the transistor means that the source node and drain node are electrically open and enters a high impedance state.

During the period in which the scanning signal Gwr(i) is at the H level, the selection signals Sel(1), Sel(2), and Sel(3) are sequentially and exclusively at the H level.

1 1 When the selection signal Sel(1) is at the H level, the inversion selection signal/Sel(1) is at the L level, an output of the NOT circuit Ivin the first series is at the H level. Thus, the transistor Nin the first series is in an on state.

30 The display control circuitsequentially outputs the potentials of the data signals Vid(1), Vid(2), Vid(2), . . . , Vid(j), . . . , Vid(n) at potentials corresponding to gradation of the pixels in the i-th row and the first, fourth, . . . , (3j−2)-th, . . . , and (3n-2)-th columns and also potentials according to the write polarity.

120 109 110 14 1 120 120 109 Thus, the data signal Vid(j) is applied to the one end of the liquid crystal elementand the one end of the storage capacitorin the pixel circuitin the i-th row and the (3j−2)-th column via the data linein the (3j−2)-th column. Even when the transistor Nin the (3j−2) column is at an off state, moreover, even when the horizontal scanning period for the i-th row is terminated and the scanning signal Gwr(i) is at the L level, the potential of the data signal Vid(j) applied to the one end of the liquid crystal elementis maintained by the capacitive property of the liquid crystal elementand the storage capacitor.

120 118 108 120 As is well known, in the liquid crystal element, the orientation of liquid crystal molecules changes according to an electric field generated by the pixel electrodeand the common electrode. Therefore, the liquid crystal elementhas a transmittance according to an effective value of an applied voltage.

120 120 Note that, in the embodiment, it is assumed that the normally black mode is employed in which the transmittance is lowest when the voltage applied to the liquid crystal elementis zero and the transmittance is higher as the voltage applied to the liquid crystal elementis increased.

120 105 118 108 The data signal Vid (j) is a potential according to gradation of the pixel in the i-th row and the (3j−2)-th column, and is a potential according to the write polarity. When the liquid crystal elementis driven, it is required to perform AC driving so as to prevent degradation of the liquid crystal. Thus, a high-level positive potential and a low-level negative potential with respect to a potential Vcen at the center of the amplitude is applied to the pixel electrodein an alternating switching manner for each period corresponding to one frame (V), for example. Note that the potential Vcen may be regarded as substantially the same potential as a potential LCcom applied to the common electrode.

A range within which the positive potential may fall is indicated with Rng(+). For example, the range Rng(+) is from a potential Vwt(+) when the gradation is at the highest value to a potential Vbk(+) when the gradation is at the lowest value. A range within which the negative potential may fall is indicated with Rng(−). For example, the range Rng(−) is from a potential Vwt(−) when the gradation is at the highest value to a potential Vbk(−) when the gradation is at the lowest value. Herein, description is made on the (3j−2) column in the horizontal scanning in the i-th row. A similar operation is executed similarly in the first, fourth, seventh, . . . , and (3n-2)-th columns in the first series.

The selection signal Sel(1) is at the L level, and then the selection signal Sel(2) is at the H level.

1 30 120 110 14 When the selection signal Sel(2) is at the H level, the transistor Nin the second series is in an on state. The display control circuitsequentially outputs the potentials of the data signals Vid(1), Vid(2), Vid(2), . . . , Vid(j), . . . . Vid(n) at potentials corresponding to gradation of the pixels in the i-th row and the second, fifth, . . . , (3j−1)-th, . . . , and (3n−1)-th columns and also potentials according to the write polarity. With this, the liquid crystal elementof the pixel circuitcorresponding to the intersection between the scanning line in the i-th row and the data linein the second series achieves the transmittance according to gradation.

The selection signal Sel(2) is at the L level, and then the selection signal Sel(3) is at the H level.

1 30 120 110 14 When the selection signal Sel(3) is at the H level, the transistor Nin the third series is in an on state. The display control circuitsequentially outputs the potentials of the data signals Vid(1), Vid(2), Vid(2), . . . , Vid(j), . . . . Vid(n) at potentials corresponding to gradation of the pixels in the i-th row and the third, sixth, . . . , (3j)-th, . . . , and (3n)-th columns and also potentials according to the write polarity. With this, the liquid crystal elementof the pixel circuitcorresponding to the intersection between the scanning line in the i-th row and the data linein the third series achieves the transmittance according to gradation. After that, the selection signal Sel(3) is at the L level, and the horizontal scanning of the i-th row is terminated.

Herein, description is made on the horizontal scanning in the i-th row. A similar operation is sequentially executed in the horizontal scanning in the first, second, third, . . . , and the m-th rows.

30 When the horizontal scanning in the m-th row is terminated, the processing proceeds to the subsequent frame period, and the horizontal scanning is started again from the first row. Note that, during the next frame period, the display control circuitinverts the potential polarity of the data signal.

100 Before describing the advantages of the electro-optical deviceaccording to the first embodiment, an electro-optical device according to a comparative example is described.

7 FIG. 150 180 1 14 160 180 160 1 1 is a diagram illustrating a configuration in the j-th group in the peripheral circuitin the electro-optical device according to the comparative example. As illustrated in the drawing, in the comparative example, the selection signals Sel(1) to Sel(3) are supplied respectively via the selection signal lines, but the inversion selection signals/Sel(1) to/Sel(3) are not supplied. Further, the NOT circuit Ivfor each of the data linesis not provided. In the comparative example, in plan view, the light shielding filmoverlaps with the three selection signal linesto which the selection signals Sel(1) to Sel(3) are supplied respectively, as indicated with hatching. Note that, in reality, the light shielding filmalso overlaps with the transistor N. However, to avoid obscuring the symbols and making the drawing difficult to understand, hatching is not applied over the transistor N.

160 180 The light shielding filmand the selection signal lineare electrically insulated from each other via an insulating layer, but a parasitic capacitance is generated due to the insulating layer as a dielectric.

8 FIG. 160 is a diagram for describing noise superimposed onto the light shielding filmin the comparative example. The selection signals Sel(1), Sel(2), and Sel(3) are exclusively at the H level in the stated order in the horizontal scanning period (H).

160 160 When the logic level of the selection signal Sel(1) changes, noise Nsla according to the change of the logic level is superimposed onto the light shielding filmvia parasitic capacitance. Similarly, when the logic levels of the selection signals Sel(2) and Sel(3) change, noise according to the changes of the logic levels are superimposed onto the light shielding filmvia parasitic capacitance.

2 160 3 160 a a In detail, noise Nsaccording to the change of the logic level of the selection signal Sel(2) is superimposed onto the light shielding filmvia parasitic capacitance, and noise Nsaccording to the change of the logic level of the selection signal Sel(3) is superimposed onto the light shielding filmvia parasitic capacitance.

160 140 160 160 160 140 The light shielding filmis electrically coupled to the capacitance wiring linemaintained at the potential Com. However, when noise is superimposed onto the light shielding film, the light shielding filmfluctuates from the potential Com, which causes an unstable state. The fluctuation of the potentials of the light shielding filmand the capacitance wiring linecauses degradation of display quality such as display unevenness.

9 FIG. 150 100 is a diagram illustrating a configuration in the j-th group in the peripheral circuitin the electro-optical deviceaccording to the first embodiment.

180 181 As described above, in the embodiment, the selection signals Sel(1) to Sel(3) are individually supplied via the selection signal lines. Moreover, the inversion selection signals/Sel(1) to/Sel(3) are also individually supplied via the inversion selection signal lines.

160 180 181 160 181 180 Further, in the first embodiment, the light shielding filmoverlaps not only with the three selection signal linesbut also with the three inversion selection signal linesin plan view. The light shielding filmand the inversion selection signal lineare electrically insulated from each other via an insulating layer. However, similarly to the selection signal line, a parasitic capacitance is generated due to the insulating layer as a dielectric.

The inversion selection signals/Sel(1) to/Sel(3) are signals obtained by inverting the logical levels of the selection signals Sel(1) to Sel(3). Thus, the change of the logic level of the selection signal Sel(1) and the change of the logic level of the inversion selection signal/Sel(1) are in opposite directions, and have approximately the same magnitude. Similarly, the change of the logic level of the selection signal Sel(2) and the change of the logic level of the inversion selection signal/Sel(2) are also in opposite directions, and have approximately the same magnitude, and the change of the logic level of the selection signal Sel(3) and the change of the logic level of the inversion selection signal/Sel(3) are also in opposite directions, and have approximately the same magnitude.

10 FIG. 160 is a diagram for describing cancellation of noise superimposed onto the light shielding filmin the first embodiment.

1 160 1 1 1 160 a b a b When the logic level of the selection signal Sel(1) changes, the noise Nsaccording to the change of the logic level is superimposed onto the light shielding filmvia parasitic capacitance. However, at the same time, noise Nsthat is opposite to the noise Nsand has substantially the same magnitude, specifically, noise Nsaccording to the change of the logic level of the inversion selection signal/Sel(1) is superimposed onto the light shielding filmvia parasitic capacitance.

1 160 1 a b Therefore, the noise Nsthat is superimposed onto the light shielding filmas the logic level of the selection signal Sel(1) changes is canceled out by the noise Nsthat is superimposed as the logic level of the inversion selection signal/Sel(1) changes.

2 160 2 a b Similarly, the noise Nsthat is superimposed onto the light shielding filmas the logic level of the selection signal Sel(2) changes is canceled out by noise Nsthat is superimposed as the logic level of the inversion selection signal/Sel(2) changes.

3 160 3 a b The noise Nsthat is superimposed onto the light shielding filmas the logic level of the selection signal Sel(3) changes is canceled out by noise Nsthat is superimposed as the logic level of the inversion selection signal/Sel(3) changes.

Here, the phrase that certain “noise” is canceled by different “noise” refers to a situation where opposing noise propagates through, for example, parasitic capacitance and reduces the original noise by offsetting the original noise.

1 3 1 3 160 140 160 a a b b In this manner, in the first embodiment, the noise Nsto the noise Nscaused by the changes of the logic levels of the selection signals Sel(1) to Sel(3) are canceled out by the noise Nsto the noise Nscaused by the changes of the logic levels of the inversion selection signals/Sel(1) to/Sel(3). Therefore, in the first embodiment, fluctuation of the potential of the light shielding filmis suppressed. Thus, degradation of display quality such as display unevenness caused by the potential fluctuation of the capacitance wiring linecoupled to the light shielding filmcan be avoided.

160 180 160 181 160 180 181 Note that, in the first embodiment, parasitic capacitance generated between the light shielding filmand the selection signal linemay include the same or a similar configuration as parasitic capacitance generated between the light shielding filmand the inversion selection signal line. To achieve this, it is conceivable that the wiring layer forming the light shielding film, the wiring layer forming the selection signal line, and the wiring layer forming the inversion selection signal linebe configured as follows.

11 FIG. 1 180 181 2 160 For example, as illustrated in the cross-sectional view in, there may be adopted a configuration in which a first wiring layer Mtis subjected to patterning to form the selection signal lineand the inversion selection signal lineand a second wiring layer Mtis subjected to patterning to form the light shielding film.

1 118 2 Note that, in reality, a gate electrode, a semiconductor layer, and the like are provided beneath the first wiring layer Mtwhereas the wiring layers such as the pixel electrodeare provided above the second wiring layer Mt. Further, an inter-layer insulating film is provided between the wiring layers.

180 181 160 180 160 181 160 With this configuration, the commonly shared insulating film is sandwiched between the selection signal lineor the inversion selection signal line, and the light shielding film. Thus, parasitic capacitance between the selection signal lineand the light shielding filmand parasitic capacitance between the inversion selection signal lineand the light shielding filmcan easily match with each other.

1 160 2 180 181 Note that there may be adopted a configuration in which the first wiring layer Mtis subjected to patterning to form the light shielding film, and the second wiring layer Mtis subjected to patterning to form the selection signal lineand the inversion selection signal line.

12 FIG. 1 180 2 160 3 181 160 180 181 Further, for example, as illustrated in the cross-sectional view in, there may be adopted a configuration in which the first wiring layer Mtis subjected to patterning to form the selection signal line, the second wiring layer Mtis subjected to patterning to form the light shielding film, and a third wiring layer Mtis subjected to patterning to form the inversion selection signal line. In other words, there may be adopted a configuration in which the light shielding filmis sandwiched between the selection signal lineand the inversion selection signal line.

180 181 With this configuration, the selection signal lineand the inversion selection signal lineoverlap with each other in plan view. Thus, the region in plan view can be reduced.

1 181 3 180 Note that there may be adopted a configuration in which the first wiring layer Mtis subjected to patterning to form the inversion selection signal line, and the third wiring layer Mtis subjected to patterning to form the selection signal line.

13 14 1 In the first embodiment, the switching element that distributes the data signal, which is supplied to the data signal line, to each of the data lines, is configured by the N-channel transistor N. Alternatively, a P-channel transistor may be used.

13 14 However, when only one of the channel types is used as the transistor, a resistance value in an on state is relatively increased. Thus, as resolution is increased, and the period during which the transistor is in an ON state is reduced, there is a possibility that the data signal supplied to the data signal linecannot be sufficiently written (propagate) to each of the data lines.

100 Therefore, a second embodiment that reduces such a possibility is described. Note that the electro-optical deviceaccording to the second embodiment is different from the first embodiment only in the demultiplexer and the periphery thereof, and the other matters are the same as those in the first embodiment. Thus, the second embodiment is described while mainly focusing on the differences.

13 FIG. 150 100 is a diagram illustrating a configuration in the j-th group in the peripheral circuitin the electro-optical deviceaccording to the second embodiment.

14 In the second embodiment, a transmission gate Trs is provided for each of the data lines.

1 1 1 1 116 110 The transmission gate Trs is an analog switch in which a P-channel transistor Pand the N-channel transistor Nare coupled in series. Both the transistors Pand Nare thin film transistors similar to the transistorin the pixel circuit.

1 14 Further, in the second embodiment, the NOT circuit Ivis not provided for each of the data lines.

181 180 181 11 In the second embodiment, similarly to the first embodiment, the three inversion selection signal linesextend in the X direction similarly to the selection signal lines. The inversion selection signals/Sel(1) to/Sel(3) are sequentially supplied to the three inversion selection signal linesby the respective NOT circuits Ivprovided corresponding thereto.

13 1 14 In the j-th group, the transmission gate Trs in the first series includes an input end coupled to the data signal line_that is split corresponding to the first series in the j-th group, and an output end coupled to the data linein the first series in the j-th group.

1 1 1 1 In the j-th group, the selection signal Sel(1) is supplied to the gate node of the transistor Nof the transistors Pand Nforming the transmission gate Trs in the first series. The inversion selection signal/Sel(1) is supplied to the gate node of the transistor Pforming the transmission gate Trs.

In the j-th group, the transmission gate Trs in the second series is similar to that in the first series.

13 2 14 1 1 In other words, in the j-th group, the transmission gate Trs in the second series includes an input end coupled to the data signal line_that is split corresponding to the second series in the j-th group, and an output end coupled to the data linein the second series in the j-th group. In the j-th group, the selection signal Sel(2) is supplied to the gate node of the transistor Nforming the transmission gate Trs in the second series, and the inversion selection signal/Sel(2) is supplied to the gate node of the transistor P.

In the j-th group, the transmission gate Trs in the third series is similar to that in the first series.

13 3 14 1 1 In other words, in the j-th group, the transmission gate Trs in the third series includes an input end coupled to the data signal line_that is split corresponding to the third series in the j-th group, and an output end coupled to the data linein the third series in the j-th group. In the j-th group, the selection signal Sel(3) is supplied to the gate node of the transistor Nforming the transmission gate Trs in the third series, and the inversion selection signal/Sel(3) is supplied to the gate node of the transistor P.

1 3 1 3 160 140 160 a a b b In the second embodiment, the noise Nsto the noise Nscaused by the changes of the logic levels of the selection signals Sel(1) to Sel(3) are also canceled out by the noise Nsto the noise Nscaused by the changes of the logic levels of the inversion selection signals/Sel(1) to/Sel(3). Therefore, in the second embodiment, fluctuation of the potential of the light shielding filmis suppressed. Thus, degradation of display quality such as display unevenness caused by the potential fluctuation of the capacitance wiring linecoupled to the light shielding filmcan also be avoided.

1 1 In the second embodiment, an on state of the transmission gate Trs refers to a situation where the transistor Nand the transistor Pare simultaneously in an on state in parallel. Thus, the resistance value is reduced to approximately a half of that when only one type of channel transistor is in an on state.

Further, when the potential of the data signal is high in positive-polarity writing, the P-channel transistor compensates for the insufficient writing due to the N-channel transistor. In contrast, when the potential of the data signal is low in negative-polarity writing, the N-channel transistor compensates for the insufficient writing due to the P-channel transistor.

13 14 Therefore, according to the second embodiment, even when resolution is increased, the data signal supplied to the data signal linecan be sufficiently written to each of the data lines, and display unevenness due to the difference in the write polarity can be suppressed.

180 181 1 1 Next, description is made on an example of a split wiring line from the selection signal lineand the inversion selection signal lineto the gate node of the transistor Pand the gate node of the transistor Nthat form the transmission gate Trs in the second embodiment.

14 FIG. 14 FIG. 15 FIG. 14 FIG. 100 180 181 is a plan view illustrating main parts of the electro-optical deviceaccording to the second embodiment. Specifically, the main parts include the selection signal lineand the inversion selection signal line, and the split wiring line toward the gate node of the transistor forming the transmission gate Trs. Note that, in, the respective wiring lines are shifted from each other for better understanding of the layer structure. In reality, the respective wiring lines overlap with each other in plan view. Further,is a cross-sectional view taken along the line A-a in, illustrating a configuration of the wiring layer in a simplified manner.

15 FIG. 14 FIG. 1 180 2 160 3 181 4 13 1 160 In the second embodiment, as illustrated in the cross-sectional view in, the first wiring layer Mtis subjected to patterning to form the selection signal lineand the like, the second wiring layer Mtis subjected to patterning to form the light shielding film, the third wiring layer Mtis subjected to patterning to form the inversion selection signal lineand the like, and a fourth wiring layer Mtis subjected to patterning to form the data signal line_and the like. Note that, in, the light shielding filmis omitted to avoid complexity.

14 FIG. 180 181 180 181 180 181 180 181 As illustrated in, both the selection signal linesand the inversion selection signal linesextend in the X direction, and are arrayed in the following order, for example. In detail, in the order toward the Y direction, the selection signal lineto which the selection signal Sel(1) is supplied, the inversion selection signal lineto which the inversion selection signal/Sel(1) is supplied, the selection signal lineto which the selection signal Sel(2) is supplied, the inversion selection signal lineto which the inversion selection signal/Sel(2) is supplied, the selection signal lineto which the selection signal Sel(3) is supplied, and the inversion selection signal lineto which the inversion selection signal/Sel(3) is supplied are arrayed.

11 12 180 13 1 11 180 1 12 181 14 FIG. In the first series, wiring lines Mwand Mware split from a point at which the selection signal lineto which the selection signal Sel(1) is supplied and the data signal line_intersect with each other in plan view. In detail, the wiring line Mwis split in a direction opposite to the Y direction from the selection signal lineto which the selection signal Sel(1) is supplied, and extends to reach the gate node of the transistor Nforming the transmission gate Trs in the first series, which is omitted in. Further, the wiring line Mwextends in the Y direction to reach an intersection with the inversion selection signal lineto which the inversion selection signal/Sel(1) is supplied, in plan view.

13 181 13 1 13 181 1 14 FIG. In plan view, the wiring line Mwis split from a point at which the inversion selection signal lineto which the inversion selection signal/Sel(1) is supplied and the data signal line_intersect with each other. In detail, the wiring line Mwis split in a direction opposite to the Y direction from the inversion selection signal lineto which the inversion selection signal/Sel(1) is supplied, and extends to reach the gate node of the transistor Pforming the transmission gate Trs in the first series, which is omitted in.

160 2 11 12 1 13 3 Therefore, in the first series, the light shielding filmformed of the second wiring layer Mtis interposed between the wiring lines Mwand Mwof the first wiring layer Mtand the wiring line Mwof the third wiring layer Mtfor substantially the same distance in the Y direction.

21 22 180 13 2 21 180 181 180 21 180 1 21 180 24 23 23 3 1 2 21 24 In the second series, wiring lines Mwand Mware split from a point at which the selection signal lineto which the selection signal Sel(2) is supplied and the data signal line_intersect with each other in plan view. In detail, the wiring line Mwis split in a direction opposite to the Y direction from the selection signal lineto which the selection signal Sel(2) is supplied, passes through the inversion selection signal lineto which the inversion selection signal/Sel(1) is supplied, and is bent in a direction opposite to the X direction right before the selection signal lineto which the selection signal Sel(1) is supplied. The wiring line Mwand the selection signal lineare obtained by subjecting the same first wiring layer Mtto patterning, and hence cannot intersect with each other in plan view. Thus, the wiring line Mwcrosses over the selection signal lineto which the selection signal Sel(1) is supplied, and is coupled to a wiring line Mwvia a relay wiring line Mw. Note that the wiring line Mwis obtained by, for example, subjecting the third wiring layer Mtother than the first wiring layer Mtand the second wiring layer Mtto patterning, and is coupled to the wiring lines Mwand Mwvia contact holes indicated with x marks in the drawing.

180 24 21 23 24 13 2 1 14 FIG. In this manner, the selection signal lineto which the selection signal Sel(2) is supplied is coupled to the wiring line Mwvia the wiring lines Mwand Mwsequentially. The wiring line Mwis in a state of overlapping with the data signal line_in plan view, and extends in a direction opposite to the Y direction to reach the gate node of the transistor Nforming the transmission gate Trs in the second series, which is omitted in.

22 181 Further, the wiring line Mwextends in the Y direction to reach an intersection with the inversion selection signal lineto which the inversion selection signal/Sel(2) is supplied in plan view.

25 181 13 2 25 181 180 22 181 A wiring line Mwis split from a point at which the inversion selection signal lineto which the inversion selection signal/Sel(2) is supplied and the data signal line_intersect with each other in plan view. In detail, the wiring line Mwis split in a direction opposite to the Y direction from the inversion selection signal lineto which the inversion selection signal/Sel(2) is supplied, crosses over the selection signal lineto which the selection signal Sel(1) is supplied and the wiring line Mw, and is bent right before the inversion selection signal lineto which the inversion selection signal/Sel(1) is supplied.

25 181 3 25 181 27 26 26 1 2 3 25 27 The wiring line Mwand the inversion selection signal lineare obtained by subjecting the same third wiring layer Mtto patterning, and hence cannot intersect with each other in plan view. Thus, the wiring line Mwpasses through the inversion selection signal lineto which the inversion selection signal/Sel(1) is supplied, and is coupled to the wiring line Mwvia a relay wiring line Mw. Note that the wiring line Mwis obtained by, for example, subjecting the first wiring layer Mtother than the second wiring layer Mtand the third wiring layer Mtto patterning, and is coupled to the wiring lines Mwand Mwvia contact holes indicated with x marks in the drawing.

181 27 25 26 27 13 2 1 14 FIG. In this manner, the inversion selection signal lineto which the inversion selection signal/Sel(2) is supplied is coupled to the wiring line Mwvia the wiring lines Mwand Mwsubsequently. The wiring line Mwis in a state of overlapping with the data signal line_in plan view, and extends in a direction opposite to the Y direction to reach the gate node of the transistor Pforming the transmission gate Trs in the second series, which is omitted in.

160 2 21 22 24 1 25 27 3 Therefore, in the second series, the light shielding filmformed of the second wiring layer Mtis interposed between the wiring lines Mw, Mw, and Mwof the first wiring layer Mtand the wiring lines Mwand Mwof the third wiring layer Mtfor substantially the same distance in the Y direction.

160 2 160 Note that the light shielding filmformed of the second wiring layer Mtis obtained through patterning so that the light shielding filmdoes not contact with metal or the like filling the contact holes.

180 36 31 33 34 35 36 13 3 1 14 FIG. Details of the third series are omitted in the description since they overlap with those of the second series. The selection signal lineto which the selection signal Sel(3) is coupled to a wiring line Mwvia wiring lines Mw, Mw, Mw, and Mwsequentially. The wiring line Mwis in a state of overlapping with the data signal line_in plan view, and extends in a direction opposite to the Y direction to reach the gate node of the transistor Nfor ming the transmission gate Trs in the third series, which is omitted in.

32 181 Further, the wiring line Mwextends in the Y direction to reach an intersection with the inversion selection signal lineto which the inversion selection signal/Sel(3) is supplied, in plan view.

180 41 37 38 39 40 41 13 3 1 14 FIG. The selection signal lineto which the inversion selection signal/Sel(3) is supplied is coupled to a wiring line Mwvia wiring lines Mw, Mw, Mw, and Mwsequentially. The wiring line Mwis in a state of overlapping with the data signal line_in plan view, and extends in a direction opposite to the Y direction to reach the gate node of the transistor Pforming the transmission gate Trs in the third series, which is omitted in.

160 2 31 32 34 36 1 37 39 41 3 Therefore, in the third series, the light shielding filmformed of the second wiring layer Mtis interposed between the wiring lines Mw, Mw, Mw, and Mwof the first wiring layer Mtand the wiring lines Mw, Mw, and Mwof the third wiring layer Mtfor substantially the same distance in the Y direction.

160 180 181 160 180 181 160 In this manner, in the second embodiment, the light shielding filmis sandwiched between the selection signal lineand the inversion selection signal linein each series. Moreover, the light shielding filmis sandwiched between the wiring line split from the selection signal lineand the wiring line split from the inversion selection signal linefor substantially the same distance. Thus, in the second embodiment, an effect is exerted by using the transmission gate Trs, and the noise generated in the light shielding filmdue to the level changes of the selection signals Sel(1) to Sel(3) can be canceled out accurately by the noise due to the level changes of the inversion selection signals/Sel(1) to/Sel(3).

180 181 1 1 14 FIG. 15 FIG. In the second embodiment, the structures of the selection signal lineand the inversion selection signal line, and the split wiring line from those signal lines toward the gate node of the transistor Pand the gate node of the transistor Nthat form the transmission gate Trs are not limited to those illustrated inand.

16 FIG. 17 FIG. 16 FIG. 100 is a plan view illustrating another example of the main parts in the electro-optical deviceaccording to the second embodiment.is a cross-sectional view taken along the line B-b in, illustrating a configuration of the wiring layer in a simplified manner.

1 181 180 2 51 56 3 180 181 4 160 the selection signal linesin the even-numbered series, the second wiring layer Mtis subjected to patterning to form wiring lines Mwto Mw, the third wiring layer Mtis subjected to patterning to form the selection signal linesin the odd-numbered series and the inversion selection signal linesin the even-numbered series, and the fourth wiring layer Mtis subjected to patterning to form the light shielding film. In this embodiment, for example, the first wiring layer Mtis subjected to patterning to form the inversion selection signal linesin the odd-numbered series and

16 FIG. 160 13 1 13 3 Note that, in, the light shielding filmand the data signal lines_to_are omitted to avoid complexity.

16 FIG. 14 FIG. 180 181 As illustrated in, the selection signal linesand the inversion selection signal linesare arrayed in the order similar to that in.

51 56 51 180 51 181 51 1 16 FIG. In contrast, the wiring lines Mwto Mwextend in the Y direction, and are arrayed at a substantially equal interval. Among those, the wiring line Mwis coupled to the selection signal lineto which the selection signal Sel(1) is supplied, via a contact hole. Further, on the side in the Y direction, the wiring line Mwextends to reach the intersection with the inversion selection signal lineto which the inversion selection signal/Sel(3) is supplied. On the side opposite to the Y direction, the wiring line Mwextends to reach the intersection with the gate node of the transistor Nforming the transmission gate Trs in the first series, which is omitted in.

52 181 52 181 52 1 16 FIG. Similarly, the wiring line Mwis coupled to the inversion selection signal lineto which the inversion selection signal/Sel(1) is supplied, via a contact hole. Further, on the side in the Y direction, the wiring line Mwextends to reach the intersection with the inversion selection signal lineto which the inversion selection signal/Sel(3) is supplied. On the side opposite to the Y direction, the wiring line Mwextends to reach the intersection with the gate node of the transistor Pforming the transmission gate Trs in the first series, which is omitted in.

53 54 180 181 53 54 181 53 54 1 1 both the wiring lines Mwand Mwextend to reach the intersection with the inversion selection signal lineto which the inversion selection signal/Sel(3) is supplied. On the side opposite to the Y direction, the wiring lines Mwand Mwextend to sequentially reach the gate nodes of the transistors Nand Pforming the transmission gate Trs in the second series. The wiring lines Mwand Mware respectively coupled to the selection signal lineto which the selection signal Sel(2) is supplied and the inversion selection signal lineto which the inversion selection signal/Sel(2) is supplied, via contact holes subsequently. On the side in the Y direction,

55 56 180 181 55 56 181 55 56 1 1 both the wiring lines Mwand Mwextend to reach the intersection with the inversion selection signal lineto which the inversion selection signal/Sel(3) is supplied. On the side opposite to the Y direction, the wiring lines Mwand Mwextend to sequentially reach the gate nodes of the transistors Nand Pforming the transmission gate Trs in the third series. The wiring lines Mwand Mware respectively coupled to the selection signal lineto which the selection signal Sel(3) is supplied and the inversion selection signal lineto which the inversion selection signal/Sel(3) is supplied, via contact holes subsequently. On the side in the Y direction,

180 181 160 160 In this manner, according to the other example of the second embodiment, the selection signal lineand the inversion selection signal linein each series face each other with the light shielding filmtherebetween. Thus, the noise generated in the light shielding filmdue to the level changes of the selection signals Sel(1) to Sel(3) can be canceled out by the noise due to the level changes of the inversion selection signals/Sel(1) to/Sel(3).

51 56 180 181 Further, the wiring lines Mwto Mweach have the same area intersecting with the selection signal lineand the inversion selection signal line, and hence the parasitic capacitance can be equalized.

18 FIG. 150 100 is a diagram illustrating a configuration of main parts of the peripheral circuitin the electro-optical deviceaccording to a third embodiment.

5 14 In the third embodiment, the transmission gate Trs and a NOT circuit Ivare provided for each of the data lines.

1 1 Similarly to the second embodiment, the transmission gate Trs is an analog switch in which a P-channel transistor Pand the N-channel transistor Nare coupled in series.

13 1 13 2 13 3 14 In the j-th group, the transmission gates Trs in the first series, the second series, and the third series include input ends that are sequentially coupled to the data signal lines_,_, and_corresponding to the series, and output ends that are coupled to the data linescorresponding to the series.

1 180 In the j-th group, the selection signal Sel(1) is supplied to the gate node of the transistor Nforming the transmission gate Trs in the first series, via the wiring line split from the selection signal line.

180 5 1 The signal obtained by inverting the logic level of the selection signal Sel(1), which is supplied via the wiring line split from the selection signal line, by the NOT circuit Ivis supplied to the gate node of the transistor Pforming the transmission gate Trs in the first series.

181 180 5 181 In the third embodiment, the three inversion selection signal linesare provided to extend in the X direction similarly to the selection signal linesand to be segmented by group. The signal inverted by the NOT circuit Ivin the first series is coupled to one of the three inversion selection signal linesvia the signal line extending in the Y direction.

5 In the j-th group, the transmission gate Trs and the NOT circuit Ivin the second series are similar to those in the first series.

1 180 In other words, in the j-th group, the selection signal Sel(2) is supplied to the gate node of the transistor Nforming the transmission gate Trs in the second series, via the wiring line split from the selection signal line.

180 5 1 The signal obtained by inverting the logic level of the selection signal Sel(2), which is supplied via the wiring line split from the selection signal line, by the NOT circuit Ivis supplied to the gate node of the transistor Pforming the transmission gate Trs in the second series.

5 181 The signal inverted by the NOT circuit Ivin the second series is coupled to another of the three inversion selection signal linesvia the signal line extending in the Y direction.

5 In the j-th group, the transmission gate Trs in the third series and the NOT circuit Ivare also the same as those in the first series and the second series.

1 180 In other words, in the j-th group, the selection signal Sel(3) is supplied to the gate node of the transistor Nforming the transmission gate Trs in the third series, via the wiring line split from the selection signal line.

180 5 1 The signal obtained by inverting the logic level of the selection signal Sel(3), which is supplied via the wiring line split from the selection signal line, by the NOT circuit Ivis supplied to the gate node of the transistor Pforming the transmission gate Trs in the third series.

5 181 The signal inverted by the NOT circuit Ivin the third series is coupled to the other of the three inversion selection signal linesvia the signal line extending in the Y direction.

181 The inversion selection signals/Sel(1) to/Sel(3) in the first embodiment are supplied individually to the three inversion selection signal lines.

160 180 181 Thus, similarly to the first embodiment and the second embodiment, the light shielding filmintersects with the three selection signal linesto which the selection signals Sel(1) to Sel(3) are supplied and the three inversion selection signal linesto which the inversion selection signals/Sel (1) to/Sel(3) are supplied.

160 180 160 181 160 180 160 181 Note that, in the third embodiment, in plan view, there may be adopted such a layout that an area in which the light shielding filmand the selection signal linein each series overlap with each other and an area in which the light shielding filmand the inversion selection signal lineoverlap with each other are substantially the same. The reason for this is that parasitic capacitance generated between the light shielding filmand the selection signal lineand parasitic capacitance generated between the light shielding filmand the inversion selection signal lineare substantially the same, allowing the noise to be accurately canceled out.

160 140 In the third embodiment, the noise caused by the changes of the logic levels of the selection signals Sel(1) to Sel(3) is also canceled out by the noise caused by the changes of the logic levels of the inversion selection signals/Sel(1) to/Sel(3). Therefore, in the third embodiment, degradation of display quality such as display unevenness caused by the potential fluctuation of the light shielding filmand the capacitance wiring linecan also be avoided.

18 FIG. 5 180 1 181 Note that, in the third embodiment illustrated in, there is adopted a configuration in which the NOT circuit Ivinverts the selection signal supplied to the selection signal line, and supplies the inverted signal to the gate node of the transistor Pin the transmission gate Trs and the inversion selection signal line. However, the configuration is not limited thereto.

5 181 1 180 Although not particularly illustrated, there may be adopted a configuration in which the NOT circuit Ivinverts the inversion selection signal supplied to the inversion selection signal line, and supplied the inverted signal to the gate node of the transistor Nin the transmission gate Trs and the selection signal line.

14 In the first embodiment, the second embodiment, and the third embodiment (hereinafter, referred to as “the embodiment and the like”), the number of data linesforming one group is “three” in the description. The number may be “two” or an integer equal to or greater than “four”.

100 Next, a projection-type display apparatus is described as an example of an electronic apparatus to which the electro-optical deviceaccording to the embodiment and the like is applied.

19 FIG. 200 200 100 100 100 is a diagram illustrating an optical configuration of a projection-type display apparatus. As illustrated in the drawing, the projection-type display apparatusincludes electro-optical devicesR,G, andB.

200 2102 2102 2106 2108 100 100 100 Inside the projection-type display apparatus, a lamp unitincluding a white light source such as a halogen lamp and an LED is provided. Light emitted from the lamp unitis separated into three primary colors of red (R), green (G), and blue (B) by three mirrorsand two dichroic mirrorsdisposed inside. Of the light of the primary colors, light of R is incident on the electro-optical deviceR, light of G is incident on the electro-optical deviceG, and light of B is incident on the electro-optical deviceB, respectively.

2121 2122 2123 2124 Note that, since an optical path of B is longer than optical paths of R and G, it is necessary to prevent a loss in the optical path of B. For this reason, a relay lens systemincluding an incident lens, a relay lens, and an emission lensis provided in the optical path of B.

100 100 100 100 The electro-optical devicesR,G, andB are of the same type as the electro-optical deviceaccording to the embodiment and the like, but they are different in the color of incident light and are distinguished by reference numerals for convenience.

100 100 The liquid crystal element of the electro-optical deviceR is driven based on a data signal corresponding to R supplied from the upper circuit, and has a transmittance corresponding to the voltage of the data signal. Thus, in the electro-optical deviceR, a transmitted image of R is generated by controlling the transmittance of the liquid crystal element individually.

100 100 Similarly, in the electro-optical deviceG, a transmitted image of G is generated based on a data signal corresponding to G. In the electro-optical deviceB, a transmitted image of B is generated based on a data signal corresponding to B.

100 100 100 2112 2112 2112 2112 2114 2114 The transmitted images of the respective colors generated by the electro-optical devicesR,G, andB are incident on a dichroic prismfrom three directions. In the dichroic prism, the R light and the B light are refracted at 90 degrees, while the G light travels straight. The dichroic prismtherefore combines the images of the respective colors. The image combined by the dichroic prismis incident on a projection lens. The projection lensenlarges and projects the combined image onto a screen Scr.

100 100 2112 100 100 100 100 Note that the transmitted images formed by the electro-optical devicesR andB are projected after being reflected by the dichroic prism, whereas the transmitted image formed by the electro-optical deviceG travels straight and is projected. Therefore, the transmitted images by the electro-optical devicesR andB are in a relationship of being laterally inverted with respect to the transmitted image of the electro-optical deviceG.

200 Further, the projection-type display apparatusis exemplified here as the electronic apparatus. However, the present disclosure is not limited thereto. For example, the present disclosure can also be applied to a display panel of a head mounted display, an electronic viewfinder in a video camera, a lens-interchangeable digital camera, or the like, a display unit of a portable information terminal, a wristwatch, or the like.

The following aspects, for example, can be ascertained from the above-described embodiments.

In order to solve the above-mentioned problem an electro-optical device according to an aspect of the present disclosure includes a plurality of data lines including k data lines being grouped, k being an integer equal to or greater than 2, a data signal line to which a data signal according to gradation of a pixel is supplied, in a time-division manner, corresponding to the k data lines, k selection signal lines to each of which a selection signal is supplied, k inversion selection signals to each of which an inversion selection signal of the selection signal is supplied, the k inversion selection signal lines forming pairs with the k selection signal lines, a first switching element being provided corresponding to the plurality of data lines in an one-on-one manner, being in an on state or an off state between the data signal line and one data line, according to a selection signal supplied to one selection signal line among the k selection signal lines, and a constant potential wiring line overlapping with the k selection signal lines and the k inversion selection signal lines in plan view and being maintained at a predetermined potential.

According to the electro-optical device according to the first aspect, the noise superimposed onto the constant potential wiring line due to the potential fluctuation of the selection signal line is canceled out by the noise caused by the potential fluctuation of the inversion selection signal line. Thus, the potential fluctuation of the constant potential wiring line can be suppressed. Note that cancellation of original noise by different noise refers to a situation where noise in a direction opposite to the original noise is generated to offset the original noise.

160 1 Note that the light shielding filmis an example of the “constant potential wiring line”, and the transistor Nis an example of the “first switching element”.

In the electro-optical device according to a second aspect being a specific aspect of the first aspect, the constant potential wiring line has a light shielding property, and the constant potential wiring line surrounds a display region in which a plurality of pixel circuits are arrayed, in plan view. According to the electro-optical device according to the second aspect, entry of stray light into the display region can be prevented.

The electro-optical device according to a third aspect being a specific aspect of the second aspect further includes a scanning line, wherein the pixel circuit includes a second switching element, an electro-optical element, and a storage capacitor, the second switching element is in an on state or an off state between the data line and one end of the electro-optical element, according to a potential of the scanning line, the electro-optical element has an optical property according to a voltage at the one end and the other end, the storage capacitor retains a voltage at the one end of the electro-optical element, and the constant potential wiring line and the other end of the storage capacitor are electrically coupled to each other.

According to the electro-optical device according to the third aspect, the potential applied to the constant potential wiring line can be shared as the potential applied to the other end of the storage capacitor, and the potential fluctuations at the constant potential wiring line and the other end of the storage capacitor can be suppressed. Thus, degradation of display quality due to the potential fluctuations can be suppressed.

120 116 140 Note that the liquid crystal elementis an example of the “electro-optical element”, the transistoris an example of the “second switching element”, and the capacitance wiring lineis an example of the “other end of the storage capacitor”.

In the electro-optical device according to a fourth aspect being another specific aspect of the first aspect, the first switching element is a P-channel transistor or an N-channel transistor. According to the electro-optical device according to the fourth aspect, the configuration can be simplified.

The electro-optical device according to a fifth aspect being a specific aspect of the fourth aspect further includes an NOT circuit provided corresponding to the plurality of data lines in one-one-one manner, wherein the first switching element is the N-channel transistor, the NOT circuit corresponding to one data line among the plurality of data lines inverts a logic level of an inversion selection signal supplied to one inversion selection signal line among the k inversion selection signal lines, and a merged signal is supplied to a gate node of the N-channel transistor, the merged signal being a combination of an inversion signal supplied to one selection signal line forming a pair with the one inversion selection signal line and an output signal of the NOT circuit corresponding to the one data line.

Note that the first switching element may be a P-channel transistor. Specifically, the electro-optical device includes an NOT circuit provided corresponding to the plurality of data lines in one-one-one manner, wherein the first switching element is the P-channel transistor, the NOT circuit corresponding to one data line among the plurality of data lines inverts a logic level of a selection signal supplied to one selection signal line among the k selection signal lines, and a merged signal is supplied to a gate node of the P-channel transistor, the merged signal being a combination of an signal supplied to one inversion selection signal line forming a pair with the one selection signal line and an output signal of the NOT circuit corresponding to the one data line.

In the electro-optical device according to a sixth aspect being another specific aspect of the first aspect, the first switching element is a transmission gate obtained by combining a P-channel transistor and an N-channel transistor. According to the electro-optical device according to the sixth aspect, the data signal supplied to the data signal line can be sufficiently written to the data line, and display unevenness due to the difference in the write polarity can be suppressed.

The electro-optical device according to a seventh aspect being a specific aspect of the sixth aspect further includes an NOT circuit provided corresponding to the plurality of data lines in one-on-one manner, wherein a selection signal supplied to one selection signal line among the k selection signal lines is supplied to a gate node of an N-channel transistor in the first switching element corresponding to one data line among the plurality of data lines, and the NOT circuit corresponding to the one data line inverts a logic level of a selection signal supplied to the one selection signal line, and supplies the selection signal to a gate node of a P-channel transistor in the first switching element corresponding to the one data line and an inversion selection signal line forming a pair with the one selection signal line.

An electronic apparatus according to an eighth aspect includes the electro-optical device according to any one of the first to seventh aspects.