Storage Device, Storage System, and Operation Method of Storage Device

This application claims the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2021-0178425 filed on Dec. 14, 2021, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

The present disclosure relates to a storage device, a storage system, and a method of operating a storage device.

A storage device, particularly a storage device including a flash memory device, a non-volatile memory, includes a buffer memory and a memory controller to store or read data from or to a memory cell through a write operation and a read operation. The memory controller receives data and/or control commands from a host and applies commands for implementing the write operation and/or the read operation of the flash memory device to the flash memory device implemented as a separate chip. As an integration of memory cells approaches the limit, the storage device may have a three-dimensional structure in which components thereof are stacked.

The present disclosure provides a storage device with a reduced size and improved operating speed by forming a non-volatile memory, a buffer memory, and a memory controller included in a storage device in the form of a single stacked chip.

According to an aspect of the present disclosure, a storage device may include a first semiconductor structure including a first cell area, including a plurality of memory cells disposed on a first semiconductor substrate, and a first metal pad disposed above the first cell area. The first cell area includes gate electrodes stacked on the first semiconductor substrate, spaced apart from each other, and channel structures penetrating through the gate electrodes and connected to the first semiconductor substrate. A second semiconductor structure includes a peripheral circuit area, disposed on a second semiconductor substrate and in which peripheral circuits for controlling the plurality of first memory cells are disposed, a second cell area including a plurality of second memory cells disposed adjacently to the peripheral circuit area, and a second metal pad bonded to the first metal pad. A third semiconductor structure includes a memory controller, disposed on a third semiconductor substrate and connected to a third metal pad through a connection via penetrating through the third semiconductor substrate, and a connection structure penetrating through the second semiconductor substrate and connecting the memory controller to the second semiconductor structure. The memory controller controls the first cell area and the second cell area based on a signal applied from a host through the third metal pad.

According to another aspect of the present disclosure, a storage device may include a non-volatile memory including a first cell area, including a plurality of first memory cells disposed on a first semiconductor substrate, and a peripheral circuit area disposed on a second semiconductor substrate and including a peripheral circuit for controlling the plurality of first memory cells. A buffer memory includes a second cell area disposed on the second semiconductor substrate, the second cell area including a plurality of second memory cells temporarily storing data to be stored in the plurality of first memory cells and data stored in the plurality of first memory cells. A memory controller is disposed on a third semiconductor substrate and controls an operation on the plurality of second memory cells using a selection circuit disposed on the second semiconductor substrate, in which a first metal pad disposed above the first cell area and a second metal pad disposed above the peripheral circuit are bonded to each other in a direction perpendicular to an upper surface of the first semiconductor substrate. A connection structure penetrates through the second semiconductor substrate and is electrically connected to the third semiconductor substrate.

According to still another aspect of the present disclosure, a storage system may include a plurality of storage devices each configured in a single chip including a first semiconductor structure including a first cell area, a second semiconductor structure bonded to the first semiconductor structure by a wafer bonding method and including a peripheral circuit area and a second cell area, and a third semiconductor structure on which a memory controller is disposed. The memory controller is connected to the second semiconductor structure through a connection structure penetrating through the semiconductor substrate included in the second semiconductor structure. A network switch is configured to distribute data to the plurality of storage devices. A connector is configured to receive the data from a host and transmits the data to the network switch.

According to yet another aspect of the present disclosure, a method of operating a storage device may include: (1) receiving, by a memory controller, data and a write command from a host, (2) converting, by the memory controller, the write command into a control signal, (3) determining, by the memory controller, a characteristic of the data and whether to store the data in a second cell area, and (4) applying, by the memory controller, the control signal to a non-volatile memory and inputting the data to the non-volatile memory using the control signal. A first semiconductor substrate on which a first cell area included in the non-volatile memory is disposed and a second semiconductor substrate on which a peripheral circuit area and the second cell area are disposed are electrically bonded by a wafer bonding method. The second semiconductor substrate and a third semiconductor substrate on which the memory controller is disposed are bonded through a connection structure penetrating through the second semiconductor substrate.

Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings.

1 FIG. is a cross-sectional view schematically illustrating a storage device according to an exemplary embodiment in the present disclosure.

The storage device may include storage media for storing data according to a request from a host, such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game machine, a TV, and a tablet PC. As an example, the storage device may include at least one of a solid state drive (SSD), an embedded memory, and a removable external memory. Hereinafter, the storage device according to the exemplary embodiment in the present disclosure described in the present specification may be an SSD. Accordingly, the storage device may be a device conforming to the non-volatile memory express (NVMe) standard.

In the conventional storage device, when a non-volatile memory, a buffer memory, and a memory controller are disposed on the same plane of a printed circuit board, the non-volatile memory, the buffer memory, and the memory controller may occupy a relatively large area on the printed circuit board, so the integration efficiency may be reduced, and the size of the storage device may be increased and the production cost may be increased. In addition, even when a structure in which only a portion of the configuration of the storage device is stacked is used, a step of interpreting a command signal applied to the non-volatile memory during a write and/or read operation is essentially required, thereby reducing the operating speed.

100 The size of the storage deviceaccording to the exemplary embodiment in the present disclosure may be reduced by forming the non-volatile memory, the buffer memory, and the memory controller as a single chip having a stacked structure. In addition, the storage device according to the exemplary embodiment in the present disclosure may minimize a connection length between the non-volatile memory and the memory controller and may omit a step of interpreting a command signal by directly applying the control signal to the non-volatile memory, thereby improving the operating speed of the storage device.

1 FIG. 100 110 120 130 Referring to, the storage deviceaccording to the exemplary embodiment in the present disclosure may include a first semiconductor structure, a second semiconductor structure, and a third semiconductor structurethat have a structure stacked in a first direction (e.g., a Z direction).

110 111 112 110 112 140 113 140 The first semiconductor structuremay include a first semiconductor substrateand an upper areaof the first semiconductor substrate (the first semiconductor structureis illustrated in an inverted aspect). The upper areaof the first semiconductor substrate may include a first cell areaand a first metal paddisposed above the first cell area.

111 111 121 131 110 120 130 100 The first semiconductor substratemay include silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or other suitable materials. The semiconductor substrates,, andthat are included in the semiconductor structures,, andincluded in the storage devicemay include the same material. However, this is only an example and may not be limited.

140 141 111 142 141 111 The first cell areamay include a plurality of first memory cells for storing data. For example, the plurality of first memory cells may include gate electrodesstacked on a first semiconductor substratespaced apart from each other and channel structurespenetrating through the gate electrodesand connected to the first semiconductor substrate. That is, the plurality of first memory cells may be memory cells constituting a vertical NAND flash memory (VNAND).

100 Meanwhile, the storage deviceaccording to the exemplary embodiment in the present disclosure may be applied to a charge trap flash (CFT) in which a charge storage layer is formed of an insulating layer as well as a flash memory device in which the charge storage layer is formed of a conductive floating gate.

120 121 122 122 150 160 123 150 160 The second semiconductor structuremay include a second semiconductor substrateand an upper areaof the second semiconductor substrate. The upper areaof the second semiconductor substrate may include a peripheral circuit areaincluding peripheral circuits of the non-volatile memory, a second cell area, and a second metal paddisposed above the peripheral circuit areaand/or the second cell area.

150 140 121 The peripheral circuit areamay include peripheral circuits for controlling the first cell area, in particular, the plurality of first memory cells. For example, the peripheral circuits may include a page buffer, a decoder, a sense amplifier, a write driver, a charge pump, and the like and the peripheral circuits may include arbitrary devices (e.g., diode, resistor, or capacitor), including a plurality of transistors disposed on the second semiconductor substrate, and wirings.

160 150 160 160 10 1 FIG. The second cell areamay include a plurality of second memory cells disposed adjacently to the peripheral circuit area. Referring to, the second cell areaaccording to the exemplary embodiment in the present disclosure may include a dynamic random access memory (DRAM). The second cell areamay be a buffer memory that adjusts a data transfer rate between the non-volatile memory and a hostby temporarily storing data stored in or read from the non-volatile memory.

160 160 For example, the plurality of second memory cells included in the second cell areaincluding the DRAM may be DRAM cells and each of the DRAM cells may be implemented by a select transistor and a capacitor. However, this is only an exemplary embodiment and is not limited thereto and the second cell areamay include, in addition to the DRAM, a buffer memory operating on a different principle, such as a static random access memory (SRAM), a magnetoresistive random access memory (MRAM), and a phase-change random access memory (PRAM).

160 150 160 Accordingly, elements included in the second cell areaand structures thereof may vary. For example, at least some of the peripheral circuits included in the peripheral circuit areamay be disposed above or below the second cell area.

123 150 160 113 113 123 110 120 The second metal paddisposed above the peripheral circuit areaand/or the second cell areamay be bonded to the first metal padin a first direction. The first metal padand the second metal padmay connect the first semiconductor structureand the second semiconductor structureby a wafer bonding method.

110 120 The wafer bonding method may form a direct connection path having a short connection length between the first semiconductor structureand the second semiconductor structure. Accordingly, the wafer bonding method may improve an input/output speed of data and control signals while eliminating delay due to a chip interface and reducing power consumption.

113 123 113 123 Meanwhile, the first metal padand the second metal padmay include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or the like. Each of the first metal padand the second metal padmay be electrically separated by adjacent layers in the second direction (e.g., X direction) and/or third direction (e.g., Y direction). As one example, the layer may include silicon oxide, silicon nitride, a low-k dielectric, or the like.

1 FIG. 100 190 121 190 Referring to, the storage deviceaccording to the exemplary embodiment in the present disclosure may further include a pad-out layerdisposed on a lower surface of the second semiconductor substrate. As an example, the pad-out layermay include a dielectric material such as silicon oxide, silicon nitride, and a low-k dielectric.

190 195 150 160 110 120 195 140 110 195 The pad-out layermay include one or more contact padsfor electrically connecting peripheral circuits included in the peripheral circuit areaand the second cell areato an external circuit. Since the first semiconductor structureand the second semiconductor structureare electrically connected to each other by the wafer bonding method, an electrical signal of an external circuit applied to the contact padmay be transmitted to the first cell areaincluded in the first semiconductor structure. That is, the contact padmay transmit an electrical signal between the non-volatile memory and the external circuit for pad-out.

130 131 132 132 170 125 The third semiconductor structuremay include a third semiconductor substrateand an upper areaof the third semiconductor substrate. The upper areaof the third semiconductor substrate may include a memory controllerand a connection structure.

125 120 130 121 125 121 190 120 130 125 1 FIG. The connection structuremay electrically connect the second semiconductor structureand the third semiconductor structureby penetrating through the second semiconductor substrate.illustrates that the connection structurecompletely penetrates through the second semiconductor substrateand the pad-out layerand is directly connected between a contact extending from an upper interconnection layer of the second semiconductor structureand an upper interconnection layer of the third semiconductor structure. However, this is only an exemplary embodiment and may not be limited. For example, the connection structuremay be formed in various structures according to process methods and exemplary embodiments.

170 125 170 The memory controllermay transmit and receive signals to and from the non-volatile memory electrically connected through the connection structure. The memory controllermay control the overall operation of the non-volatile memory based on signals transmitted and received to and from the non-volatile memory.

100 180 131 180 170 131 In the storage deviceaccording to the exemplary embodiment in the present disclosure, a third metal padmay be disposed on a lower surface of the third semiconductor substrate. The third metal padmay be electrically connected to the memory controllerthrough a connection via penetrating through the third semiconductor substrate.

170 10 180 170 140 160 10 The memory controllermay receive a control command from the hostthrough the third metal padand transmit and receive data. The memory controllermay generate control signals for the first cell areaand the second cell areabased on the control command applied from the hostand may control the operation of the non-volatile memory based on the control signals.

125 120 130 125 Similar to the wafer bonding method, the connection structuremay form a direct connection path having a short connection length between the second semiconductor structureand the third semiconductor structure. Accordingly, the connection structuremay improve an input/output speed of data and control signals while eliminating delay due to a chip interface and reducing power consumption.

100 140 150 160 170 The storage deviceaccording to the exemplary embodiment in the present disclosure may reduce the chip size by vertically stacking the non-volatile memory including the first cell areaand the peripheral circuit area, the second cell area, and the memory controllerand may directly connect each component.

2 FIG. is a block diagram schematically illustrating a host-storage system illustrating the storage device according to the exemplary embodiment in the present disclosure.

2 FIG. 1 FIG. 1 FIG. 1 10 100 100 170 170 170 140 150 Referring to, a host-storage systemmay include a hostand the storage deviceaccording to the exemplary embodiment in the present disclosure. In addition, the storage devicemay include the memory controllerand the non-volatile memory (NVM). For example, the memory controllermay correspond to the memory controllerillustrated inand the non-volatile memory (NVM) may correspond to the first cell areaand the peripheral circuit areaillustrated in.

10 11 12 12 100 100 Also, according to the exemplary embodiment in the present disclosure, the hostmay include a host controllerand a host memory. The host memorymay function as a buffer memory for temporarily storing data to be transmitted to the storage deviceor data transmitted from the storage device.

100 10 100 10 100 The storage devicemay include a solid state drive (SSD) as a storage medium for storing data according to a request from the host. In this case, the storage devicemay be a device conforming to the NVMe standard. The hostand the storage devicemay generate a packet according to an adopted standard protocol and transmit the generated packet.

100 However, this is only an example and may not be limited. For example, the storage devicemay be implemented in various interface schemes such as advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCIe), NVM express (NVMe), IEEE 1394, universal serial bus (USB), secure digital (SD) card, multi-media card (MMC), eMMC, UFS, embedded universal flash storage (eUFS), and compact flash (CF).

100 100 100 When the non-volatile memory (NVM) of the storage deviceincludes a flash memory, the flash memory may include a 3D (or vertical) NAND (VNAND) memory cell array. As another example, the storage devicemay include other various types of non-volatile memories. For example, the storage devicemay include a NOR flash memory, a resistive random access memory (RRAM), a phase-change RAM (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), and other various types of memory devices.

11 12 11 12 11 12 According to an exemplary embodiment, the host controllerand the host memorymay be implemented as separate semiconductor chips. Alternatively, in some exemplary embodiments, the host controllerand the host memorymay be integrated on the same semiconductor chip. As an example, the host controllermay be any one of a plurality of modules included in an application processor and the application processor may be implemented as a system on chip (SoC). In addition, the host memorymay be an embedded memory provided in the application processor or a non-volatile memory or a memory module disposed outside the application processor.

11 12 The host controllermay manage an operation of storing data (e.g., write data) of the buffer area of the host memoryin the non-volatile memory (NVM) or data (e.g., read data) of the non-volatile memory (NVM) in the buffer area.

170 100 171 172 170 173 174 175 176 177 170 173 172 173 The memory controllerincluded in the storage deviceaccording to the exemplary embodiment in the present disclosure may include a host interfaceand a central processing unit (CPU). In addition, the memory controllermay further include a flash translation layer (FTL), a packet manager, a buffer memory, an error correction code (ECC) engine, and an advanced encryption standard (AES) engine. The memory controllermay further include a working memory into which the flash translation layeris loaded, and the CPUmay execute the flash translation layerto control a write operation and a read operation to the non-volatile memory (NVM).

171 10 10 171 171 10 The host interfacemay transmit and receive packets to and from the host. A packet transmitted from the hostto the host interfacemay include a command, data to be written to the non-volatile memory (NVM) or the like, and a packet transmitted from the host interfaceto the hostmay include a response to the command, data read from the non-volatile memory (NVM), or the like.

170 100 170 10 100 The memory controllerof the storage deviceaccording to the exemplary embodiment in the present disclosure may transmit data to be written to the non-volatile memory (NVM) to the non-volatile memory (NVM) or receive data read from the non-volatile memory (NVM). Meanwhile, the memory controllermay convert a command received from the hostinto a control signal. Since the storage deviceis implemented as a single chip, it is possible to directly control the non-volatile memory (NVM) in the form of the control signal without a separate chip interface.

173 10 The flash translation layermay perform various functions such as address mapping, wear-leveling, and garbage collection. The address mapping operation is an operation of changing a logical address received from the hostinto a physical address used to store data in the non-volatile memory (NVM). The wear-leveling is a technique for preventing excessive deterioration in a specific block by allowing blocks in the non-volatile memory (NVM) to be uniformly used and may be implemented by, for example, a firmware technique for balancing erase counts of physical blocks. The garbage collection is a technique for securing usable capacity in the non-volatile memory (NVM) by copying valid data of a block to a new block and then erasing an existing block.

174 10 10 175 The packet managermay generate a packet according to the protocol of the interface negotiated with the hostor parse various types of information from the packet received from the host. In addition, the buffer memorymay temporarily store data to be written to the non-volatile memory (NVM) or data to be read from the non-volatile memory (NVM).

175 170 170 175 160 100 120 175 130 120 1 FIG. The buffer memorymay be provided in the memory controllerbut may be disposed outside the memory controller. That is, the buffer memorymay be distinguished from the buffer memory implemented by the second cell areaillustrated in. However, this is only an exemplary embodiment and is not limited thereto and the storage deviceincludes both the buffer memory included in the second semiconductor structureand the buffer memoryincluded in the third semiconductor structureor includes only the buffer memory included in the second semiconductor structure.

176 176 176 The ECC enginemay perform an error detection and correction function on data read from the non-volatile memory (NVM). More specifically, the ECC enginemay generate parity bits for write data to be written into the non-volatile memory (NVM) and the generated parity bits may be stored in the non-volatile memory (NVM) together with the write data. During the data read operation in the non-volatile memory (NVM), the ECC enginemay correct the error in the read data using the parity bits read together with the data read from the non-volatile memory (NVM) and output the error-corrected read data.

177 170 The AES enginemay perform at least one of an encryption operation and a decryption operation on data input to the memory controllerusing a symmetric-key algorithm.

3 FIG. is a block diagram schematically illustrating a non-volatile memory included in the storage device according to the exemplary embodiment in the present disclosure.

3 FIG. 100 140 150 Referring to, the non-volatile memory included in the storage deviceaccording to the exemplary embodiment in the present disclosure may include a first cell area including a memory cell arrayA and a peripheral circuit areaincluding peripheral circuits.

150 151 152 153 154 155 3 FIG. The peripheral circuit areaof the non-volatile memory may include a row decoder, a page buffer, an input/output buffer, a voltage generator, and a control logic circuit. Although not illustrated in, the non-volatile memory may further include column logic, a pre-decoder, a temperature sensor, and the like.

155 155 The control logic circuitmay generally control various operations in a non-volatile memory. For example, the control logic circuitmay output a voltage control signal CTRL_VOL, a row address X-ADDR, and a column address Y-ADDR.

140 140 152 151 The memory cell arrayA may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of first memory cells. The memory cell arrayA may be connected to the bufferthrough bit lines BL and connected to a row decoderthrough word lines WL, string selection lines SSL, and ground selection lines GSL.

100 140 140 In the storage deviceaccording to the exemplary embodiment in the present disclosure, the memory cell arrayA may include a 3D memory cell array and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include the plurality of first memory cells respectively connected to word lines WL stacked vertically on a substrate. U.S. Pat. Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 are incorporated herein by reference in their entirety. As an exemplary embodiment, the memory cell arrayA may include a 2-dimensional (2D) memory cell array and the 2D memory cell array may include a plurality of NAND strings disposed along a row direction and a column direction.

152 152 152 152 152 The page buffermay include a plurality of page buffers, and the plurality of page buffers may be respectively connected to the plurality of first memory cells through a plurality of bit lines BL. The page buffermay select at least one of the bit lines BL in response to a column address Y-ADDR. The page buffermay operate as a write driver or a sense amplifier according to an operation mode. For example, during the write operation, the page buffermay apply a bit line voltage corresponding to data to be written to the selected bit line. During the read operation, the page buffermay sense data stored in the first memory cell by sensing a current or voltage of the selected bit line.

154 154 The voltage generatormay generate various types of voltages for performing write, read, write verify, and erase operations based on the voltage control signal CTRL_VOL. For example, the voltage generatormay generate a write voltage, a read voltage, a write verify voltage, an erase voltage, etc., as a word line voltage VWL.

151 151 The row decodermay select one of the plurality of word lines WL in response to the row address X-ADDR and select one of the plurality of string selection lines SSL. For example, the row decodermay apply the write voltage and the write verify voltage to the selected word line during the write operation and apply the read voltage to the selected word line during the read operation.

4 FIG. is an equivalent circuit diagram of a memory block included in the non-volatile memory included in the storage device according to the exemplary embodiment in the present disclosure.

4 FIG. A memory block BLKi illustrated inrepresents a three-dimensional memory block formed on a semiconductor substrate in a three-dimensional structure. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the semiconductor substrate.

4 FIG. 4 FIG. 11 33 1 2 3 11 33 1 2 8 11 33 1 2 8 Referring to, the memory block BLKi may include a plurality of memory NAND strings NSto NSconnected between bit lines BL, BL, and BLand a common source line CSL. Each of the plurality of memory NAND strings NSto NSmay include a string select transistor SST, a plurality of memory cells MC, MC, . . . , MC, and a ground select transistor GST.illustrates that each of the plurality of memory NAND strings NSto NSincludes eight memory cells MC, MC, . . . , MC, but is not necessarily limited thereto.

1 2 3 1 2 8 1 2 8 1 2 8 1 2 8 1 2 3 1 2 3 The string select transistor SST may be connected to the corresponding string selection lines SSL, SSL, and SSL. The plurality of memory cells MC, MC, . . . , MCmay be connected to corresponding gate lines GTL, GTL, . . . , GTL, respectively. The gate lines GTL, GTL, . . . , GTLmay correspond to word lines, and some of the gate lines GTL, GTL, . . . , GTLmay correspond to dummy word lines. The ground select transistor GST may be connected to the corresponding ground select lines GSL, GSL, and GSL. The string select transistor SST may be connected to the corresponding bit lines BL, BL, and BL, and the ground select transistor GST may be connected to the common source line CSL.

1 1 2 3 1 2 3 1 2 8 1 2 3 4 FIG. Word lines (e.g., WL) having the same height are commonly connected, and the ground selection lines GSL, GSL, and GSLand the string selection lines SSL, SSL, and SSLmay each be separated from each other.illustrates that the memory block BLK is connected to eight gate lines GTL, GTL, . . . , GTLand three bit lines BL, BL, BL, but is not necessarily limited thereto.

5 FIG. is a diagram illustrating a wafer bonding method in the storage device according to the exemplary embodiment in the present disclosure.

5 FIG. 1000 Referring to, a non-volatile memorymay have a chip to chip (C2C) structure. The C2C structure may mean that an upper chip including a cell area CELL is manufactured on a first wafer and a lower chip including a peripheral circuit area PERI is manufactured on a second wafer different from the first wafer, and then the upper chip and the lower chip are connected to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip and a bonding metal formed on an uppermost metal layer of the lower chip. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-to-Cu bonding method, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

1 5 FIGS.and 1000 140 150 113 123 Referring totogether, a cell area CELL included on a first wafer of the non-volatile memorymay correspond to the first cell areaand a peripheral circuit area PERI included on a second wafer may correspond to the peripheral circuit area. In addition, the bonding metal may correspond to the first metal padand the second metal pad.

1000 Each of the peripheral circuit area PERI and the cell area CELL of the non-volatile memorymay include an outer pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

1710 1715 1720 1720 1720 1710 1730 1730 1730 1720 1720 1720 1740 1740 1740 1730 1730 1730 1730 1730 1730 1740 1740 1740 a b c a b c a b c a b c a b c a b c a b c The peripheral circuit area PERI may include the second semiconductor substrate, an interlayer insulating layer, a plurality of circuit elements,, andformed on the second semiconductor substrate, first metal layers,, andconnected to the plurality of circuit elements,, and, respectively, and second metal layers,, andformed on the first metal layers,, and. In an exemplary embodiment, the first metal layers,, andmay be formed of tungsten having a relatively high electrical specific resistance and the second metal layers,, andmay be formed of copper having a relatively low electrical specific resistance.

1730 1730 1730 1740 1740 1740 1740 1740 1740 1740 1740 1740 1740 1740 1740 a b c a b c a b c a b c a b c. In the present specification, only the first metal layers,, andand the second metal layers,, andare illustrated and described, but not limited thereto, and at least one metal layer may be further formed on the second metal layers,, and. At least some of the one or more metal layers formed above the second metal layers,, andmay be formed of aluminum having a different electrical specific resistance, etc., than that of copper forming the second metal layers,, and

1715 1710 1720 1720 1720 1730 1730 1730 1740 1740 1740 a b c a b c a b c The interlayer insulating layermay be disposed on the second semiconductor substrateto cover the plurality of circuit elements,, and, the first metal layers,, and, and the second metal layers,, andand may include an insulating material such as silicon oxide or silicon nitride.

1771 1772 1740 1771 1772 1871 1872 1771 1772 1871 1872 b b b b b b b b b b b Lower bonding metalsandmay be formed on the second metal layerof the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metalsandof the peripheral circuit area PERI may be electrically connected to upper bonding metalsandof the cell area CELL by the bonding method, and the lower bonding metalsandand the upper bonding metalsandmay be formed of aluminum, copper, tungsten, or the like.

1810 1820 1831 1838 1830 1810 1810 1830 1830 The cell area CELL may provide at least one memory block. The cell area CELL may include a first semiconductor substrateand a common source line. A plurality of word linesto() may be stacked on the first semiconductor substratealong a direction (Z-axis direction) perpendicular to an upper surface of the first semiconductor substrate. String selection lines and a ground selection line may be disposed above and below the word lines, respectively, and the plurality of word linesmay be disposed between the string selection lines and the ground selection line.

1810 1830 1850 1860 1850 1860 1860 1810 c c c c c In the bit line bonding area BLBA, the channel structure CH may extend in a direction (Z-axis direction) perpendicular to the upper surface of the first semiconductor substrateto penetrate through the word lines, the string selection lines, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, a buried insulation layer, and the like, and the channel layer may be electrically connected to a first metal layerand a second metal layer. For example, the first metal layermay be a bit line contact and the second metal layermay be a bit line. In an exemplary embodiment, the bit linemay extend in a third direction (e.g., Y direction) parallel to an upper surface of the first semiconductor substrate.

5 FIG. 1860 1860 1720 1893 1860 1871 1872 1871 1872 1771 1772 1720 1893 c c c c c c c c c c c In an exemplary embodiment illustrated in, an area in which the channel structure CH, the bit line, and the like are disposed may be defined as a bit line bonding area BLBA. The bit linemay be electrically connected to the circuit elementsproviding a page bufferin the peripheral circuit area PERI in the bit line bonding area BLBA. For example, the bit linemay be connected to the upper bonding metalsandin the peripheral circuit area PERI and the upper bonding metalsandmay be connected to the lower bonding metalsandthat are connected to the circuit elementsof the page buffer.

1830 1810 1841 1847 1840 1830 1840 1830 1850 1860 1840 1830 1840 1871 1872 1771 1772 b b b b b b In the word line bonding area WLBA, the word linesmay extend along the second direction (X-axis direction) parallel to the upper surface of the first semiconductor substratewhile being perpendicular to the third direction and may be connected to a plurality of cell contact plugsto(). The word linesand the cell contact plugsmay be connected to each other through pads provided by at least some of the word linesextending in different lengths along the second direction. A first metal layerand a second metal layermay be sequentially connected to the cell contact plugsconnected to the word lines. The cell contact plugsmay be connected to the peripheral circuit area PERI through the upper bonding metalsandof the cell area CELL in the word line bonding area WLBA and the lower bonding metalandof the peripheral circuit area PERI.

1840 1720 1894 1720 1894 1720 1893 1720 1893 1720 1894 b b c c b The cell contact plugsmay be electrically connected to the circuit elementsforming the row decoderin the peripheral circuit area PERI. The operating voltage of the circuit elementsproviding the row decodermay be different from that of the circuit elementsforming the page buffer. For example, the operating voltage of the circuit elementsforming the page buffermay be greater than that of the circuit elementsforming the row decoder.

1880 1880 1820 1850 1860 1880 1880 1850 1860 a a a a A common source line contact plugmay be disposed in the outer pad bonding area PA. The common source line contact plugmay be formed of a metal, a metal compound, or a conductive material such as polysilicon and may be electrically connected to the common source line. Afirst metal layerand a second metal layermay be sequentially stacked above the common source line contact plug(as seen from an inverted aspect). For example, an area in which the common source line contact plug, the first metal layer, and the second metal layerare disposed may be defined as the outer pad bonding area PA.

1705 1805 1701 1710 1710 1705 1701 1705 1720 1720 1720 1703 1710 1701 1703 1710 1703 1710 5 FIG. a b c Meanwhile, input/output padsandmay be disposed in the outer pad bonding area PA. Referring to, a lower insulating filmcovering a lower surface of the second semiconductor substratemay be formed under the second semiconductor substrateand the second input/output padmay be formed on the lower insulating film. The second input/output padmay be connected to at least one of the plurality of circuit elements,, anddisposed in the peripheral circuit area PERI through the second input/output contact plugand may be separated from the second semiconductor substrateby the lower insulating film. In addition, since a side insulating film may be disposed between the second input/output contact plugand the second semiconductor substrate, the second input/output contact plugand the second semiconductor substratemay be electrically separated from each other.

5 FIG. 1810 1810 1801 1805 1801 1805 1720 1720 1720 1803 1805 1720 a b c a. Referring to, an upper insulating filmcovering an upper surface of the first semiconductor substratemay be formed above the first semiconductor substrateand the first input/output padmay be disposed on the upper insulating film. The first input/output padmay be connected to at least one of the plurality of circuit elements,, anddisposed in the peripheral circuit area PERI through a first input/output contact pad. In an exemplary embodiment, the first input/output padmay be electrically connected to the circuit element

1801 1820 1803 1805 1830 1803 1810 1810 1805 1715 5 FIG. According to an exemplary embodiment, the first semiconductor substrate, the common source line, and the like may not be disposed in the area where the first input/output contact plugis disposed. In addition, the first input/output padmay not overlap with the word linesin the first direction (e.g., Z direction). Referring to, the first input/output contact plugmay be separated from the first semiconductor substratein a direction parallel to the upper surface of the first semiconductor substrateand may be connected to the first input/output padby penetrating through the interlayer insulating layerof the cell area CELL.

1705 1805 1000 1705 1701 1805 1801 1000 1705 1805 According to exemplary embodiments, the second input/output padand the first input/output padmay be selectively formed. For example, the non-volatile memorymay include only the second input/output paddisposed above the lower insulating film, or only the first input/output paddisposed above the upper insulating film. Alternatively, the non-volatile memorymay include both the second input/output padand the first input/output pad.

The metal pattern of the uppermost metal layer may exist as a dummy pattern in each of the outer pad bonding area PA and the bit line bonding area BLBA included in each of the cell area CELL and the peripheral circuit area PERI, or the uppermost metal layer may be empty.

1000 1773 1872 1872 1773 1872 1773 1773 a a a a a a a In the non-volatile memory, a lower metal patternhaving the same shape as the upper metal patternof the cell area CELL may be formed on the uppermost metal layer of the peripheral circuit area PERI to correspond to the upper metal patternformed on the uppermost metal layer of the cell area CELL in the outer pad bonding area PA. The lower metal patternformed on the uppermost metal layer of the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. Similarly, the upper metal patternhaving the same shape as the lower metal patternof the peripheral circuit area PERI may be formed on the upper metal layer of the cell area CELL to correspond to the lower metal patternformed on the uppermost metal layer of the peripheral circuit area PERI in the outer pad bonding area PA.

1771 1772 1740 1771 1772 1871 1872 b b b b b b b Lower bonding metalsandmay be formed on the second metal layerof the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metalsandof the peripheral circuit area PERI may be electrically interconnected to upper bonding metalsandof the cell area CELL by the bonding method.

1892 1752 1752 1892 In addition, in the bit line bonding area BLBA, an upper metal patternhaving the same shape as the lower metal patternof the peripheral circuit area PERI may be formed on the uppermost metal layer of the cell area CELL, corresponding to the lower metal patternformed on an uppermost metal layer of the peripheral circuit area PERI. A contact may not be formed on the upper metal patternformed on the uppermost metal layer of the cell area CELL.

1000 1000 5 FIG. 5 FIG. However, the non-volatile memoryillustrated inis only an example illustrating the wafer bonding method, and the structure of the non-volatile memoryaccording to the wafer bonding method may not be limited to that illustrated in.

6 8 FIGS.to are simple diagrams illustrating a shape of a connection structure in the storage device according to the exemplary embodiment in the present disclosure.

1 FIG. 100 125 120 130 Referring to, in the storage deviceaccording to the exemplary embodiment in the present disclosure, the connection structureconnecting the second semiconductor structureand the third semiconductor structuremay be formed in various structures according to exemplary embodiments.

6 FIG. 125 120 130 Referring to, the connection structureA may have a structure that directly connects a lower interconnection layer MLL of the second semiconductor structureand an upper interconnection layer MLH of the third semiconductor structure.

121 122 120 132 130 For example, a first via VIA in the form of a through hole via THV may penetrate through the second semiconductor substrateand extend to the upper areaof the second semiconductor substrate to be connected to the lower interconnection layer MLL of the second semiconductor structure. Also, the first via VIA may extend to the upper areaof the third semiconductor substrate to be connected to the upper interconnection layer MLH of the third semiconductor structure.

7 FIG. 125 120 130 1 2 121 Referring to, the connection structureB may have a structure in which the lower interconnection layer MLL of the second semiconductor structureand the upper interconnection layer MLH of the third semiconductor structureare connected through power rails BPRand BPRmounted between device isolation layers STI of the second semiconductor substrate.

1 130 2 1 120 For example, the second via VIA may connect between the mounted first power rail BPRand the upper interconnection layer MLH of the third semiconductor structureand the mounted second power rail BPRelectrically connected to the mounted first power rail BPRand the lower interconnection layer MLL of the second semiconductor structuremay be connected by a contact CNT.

8 FIG. 125 121 121 120 121 130 Referring to, the connection structureC may be connected to pads disposed on the upper and lower surfaces of the second semiconductor substrate, respectively, the pad disposed on the upper surface of the second semiconductor substratemay be connected to the lower interconnection layer MLL of the second semiconductor structure, and the pad disposed on the lower surface of the second semiconductor substratemay be connected to the third semiconductor structurethrough the bump BMP.

121 121 120 121 For example, the third via VIA in the form of the through hole via THV may penetrate through the second semiconductor substrateto be connected to the pads disposed on the upper and lower surfaces of the second semiconductor substrate, respectively. The lower interconnection layer MLL of the second semiconductor structuremay be connected to the pad disposed on the upper surface of the second semiconductor substratethrough the contact CNT.

125 125 125 100 125 120 130 6 8 FIGS.to However, the structures of the connection structuresA,B, andC illustrated inare merely exemplary embodiments and may not be limited. In the storage deviceaccording to the exemplary embodiment in the present disclosure, the connection structureelectrically connecting the second semiconductor structureand the third semiconductor structuremay be formed in various structures according to the process.

9 FIG. is a cross-sectional view schematically illustrating a storage device according to another exemplary embodiment in the present disclosure.

9 FIG. 1 FIG. 200 100 200 210 220 230 210 220 213 223 220 230 225 Referring to, a storage deviceaccording to another exemplary embodiment in the present disclosure may correspond to the storage deviceillustrated in. For example, the storage devicemay include a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure. In addition, the first semiconductor structureand the second semiconductor structuremay be bonded by the wafer bonding method by the first metal padand the second metal padand the second semiconductor structureand the third semiconductor structuremay be electrically connected through the connection structure.

210 211 212 212 240 241 242 The first semiconductor structuremay include a first semiconductor substrateand an upper areaof the first semiconductor substrate, and the upper areaof the first semiconductor substrate may include a first cell areaimplemented as a VNAND memory by gate electrodesand channel structures.

220 221 222 222 250 260 The second semiconductor structuremay include a second semiconductor substrateand an upper areaof the second semiconductor substrate, and the upper areaof the second semiconductor substrate may include a peripheral circuit areaand a second cell areaoperating as a buffer memory.

230 231 232 270 270 280 231 231 The third semiconductor structuremay include a third semiconductor substrateand an upper areaof the third semiconductor substrate including a memory controller. The memory controllermay be connected to a third metal paddisposed on a lower surface of the third semiconductor substratethrough a connection via penetrating through the third semiconductor substrate.

200 290 211 290 291 240 210 220 291 250 260 220 291 9 FIG. Meanwhile, the storage deviceillustrated inmay further include a pad-out layerdisposed on the lower surface of the first semiconductor substrate(as seen from an inverted aspect). The pad-out layermay include one or more contact padsfor electrically connecting the first cell areato an external circuit. Since the first semiconductor structureand the second semiconductor structureare electrically connected to each other by the wafer bonding method, an electrical signal of the external circuit applied to the contact padmay be transmitted to the peripheral circuit areaand the second cell areaincluded in the second semiconductor structure. That is, the contact padmay transmit an electrical signal between the non-volatile memory and the external circuit for pad-out.

10 FIG. is a cross-sectional view schematically illustrating a storage device according to another exemplary embodiment in the present disclosure.

10 FIG. 1 FIG. 300 100 300 310 320 330 310 320 313 323 320 330 325 Referring to, a storage deviceaccording to another exemplary embodiment may correspond to the storage deviceillustrated in. For example, the storage devicemay include a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure. In addition, the first semiconductor structureand the second semiconductor structuremay be bonded by the wafer bonding method by the first metal padand the second metal padand the second semiconductor structureand the third semiconductor structuremay be electrically connected through the connection structure.

310 311 312 312 340 341 341 342 342 a b a b. The first semiconductor structuremay include a first semiconductor substrateand an upper areaof the first semiconductor substrate, and the upper areaof the first semiconductor substrate may include a first cell areaimplemented as a VNAND memory by gate electrodesandand channel structuresand

300 342 342 340 341 341 342 342 342 342 340 300 342 342 a b a b a b a b a b In the storage deviceaccording to the exemplary embodiment in the present disclosure, the channel structuresandincluded in the first cell areamay be formed in a multi-stage structure. Accordingly, the gate electrodesandthrough which the channel structuresandpenetrate may also be additionally stacked along the channel structuresand. The capacity of the non-volatile memory may be increased in the first cell areaof the storage deviceby using the channel structuresandformed in a multi-level structure.

320 321 322 322 350 360 390 395 321 The second semiconductor structuremay include a second semiconductor substrateand an upper areaof the second semiconductor substrate, and the upper areaof the second semiconductor substrate may include a peripheral circuit areaand a second cell areaoperating as a buffer memory. Meanwhile, a pad-out layerincluding a contact padmay be disposed on a lower surface of the second semiconductor substrate.

330 331 332 370 370 380 331 331 The third semiconductor structuremay include a third semiconductor substrateand an upper areaof the third semiconductor substrate including a memory controller. The memory controllermay be connected to a third metal paddisposed on a lower surface of the third semiconductor substratethrough a connection via penetrating through the third semiconductor substrate.

11 FIG. is a schematic perspective view illustrating the storage device according to the exemplary embodiment in the present disclosure.

11 FIG. 1 FIG. 400 100 400 410 420 430 410 420 420 430 400 100 Referring to, a storage deviceaccording to an exemplary embodiment in the present disclosure may illustrate the storage deviceillustrated inas a structural unit in terms of operation. For example, the storage devicemay include a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure. The first semiconductor structuremay be bonded to the second semiconductor structureby the wafer bonding method, and the second semiconductor structureand the third semiconductor structuremay be electrically connected through a connection structure. The stacked structure of the storage devicemay be the same as that of the storage device.

410 440 411 420 460 421 430 431 10 The first semiconductor structuremay include a memory cell arrayA including a plurality of first memory cells disposed on a first semiconductor substrate. The second semiconductor structuremay include peripheral circuits and a buffer memorydisposed on the second semiconductor substrate. The third semiconductor structuremay include a memory controller that is disposed on the third semiconductor substrateand transmits data transmitted from the hostto the non-volatile memory.

471 472 473 474 476 477 431 170 2 FIG. A host interface, a CPU, a flash translation layer, a packet manager, the ECC engine, and an AES enginedisposed on the third semiconductor substratemay correspond to each of the components included in the memory controllerillustrated in.

451 451 452 452 454 455 150 a b a b 3 FIG. The peripheral circuits may control the plurality of first memory cells and may include row decodersand, page buffersand, a voltage generator, and a control logic circuit. The peripheral circuits may correspond to each of the components included in the peripheral circuit areaillustrated in.

460 Meanwhile, the buffer memoryincluding data to be stored in the plurality of first memory cells and a plurality of second memory cells temporarily storing data stored in the plurality of first memory cells may be a DRAM memory device. However, this is only an example and may not be limited.

421 460 421 On the second semiconductor substrate, peripheral circuits may be disposed outside the buffer memory, for example, the second cell area. For example, the peripheral circuits may be disposed closer to an edge of the second semiconductor substratethan the second cell area. However, this is only an example and may not be limited.

429 421 429 429 A selection circuitfor controlling to selectively perform operations on the plurality of first memory cells or the plurality of second memory cells may be disposed on the second semiconductor substrate. In one example, the selection circuitmay be a multiplexer and/or a demultiplexer. The selection circuitmay determine whether to perform an operation on the plurality of second memory cells.

429 429 That is, the memory controller may set a data processing path using the selection circuit. Hereinafter, the operation of the memory controller is described in terms of the write operation, but the present disclosure is not limited thereto, and the memory controller may control the selection circuitin a similar manner in the read operation.

10 For example, when the write operation of writing data transmitted from the hostto the plurality of first memory cells is performed, the memory controller may determine whether to write data to the plurality of first memory cells via the plurality of second memory cells or whether to write data to the plurality of first memory cells without passing through the plurality of second memory cells.

10 10 10 On the other hand, when the read operation of transmitting the data stored in the first memory cell to the hostis performed, the memory controller may determine whether to transmit data to the hostwithout passing through the plurality of second memory cells or whether to transmit data to the hostvia the second memory cells.

10 The memory controller may determine whether to process the data via the plurality of second memory cells based on characteristics of data transmitted from the hostor data stored in the first memory cell on which the read operation is performed.

10 429 For example, when the data transmitted from the hostis sequence data or data requiring long-term storage, for example, cold data, the memory controller may control the selection circuitto directly write data to the plurality of first memory cells without passing through the plurality of second memory cells.

10 429 On the other hand, when the data transmitted from the hostis periodically modified data, for example, hot data, the memory controller may control the selection circuitto write data to the plurality of first memory cells via the plurality of second memory cells. For example, data may be temporarily stored in the plurality of second memory cells and then stored in the first memory cells.

For example, the cold data that is periodically modified or not frequently accessed, such as moving picture data, may be directly stored in the plurality of first memory cells without passing through the plurality of second memory cells. On the other hand, the hot data frequently accessed or frequently modified, such as logical to physical map data, may be stored in the plurality of second memory cells and then stored in the plurality of first memory cells. However, even the cold data may be handled as hot data when frequently accessed.

10 10 10 10 The memory controller may periodically process data in the plurality of second memory cells based on a difference between a speed at which data is transmitted and received to and from the hostand a speed at which data is processed in the plurality of first memory cells. In the case where a bottleneck occurs when data is transmitted and received to and from the host, data may be transmitted through the plurality of second memory cells. In this case, the memory controller may periodically store data in the plurality of second memory cells and read the data. For example, the bottleneck may occur when a speed at which data is read from the plurality of first memory cells to the memory controller is faster than a speed at which data is transmitted from the memory controller to the host, when a speed at which data is transmitted from the hostto the memory controller is slower than a speed at which the memory controller writes data to the plurality of first memory cells, or the like.

10 When data is stored in all of the plurality of second memory cells, the memory controller may store the data transmitted from the hostin the plurality of first memory cells without passing through the plurality of second memory cells.

12 FIG. is a schematic perspective view illustrating a storage device according to another exemplary embodiment in the present disclosure.

12 FIG. 11 FIG. 1 FIG. 500 400 500 510 520 530 510 520 520 530 500 100 Referring to, a storage deviceaccording to another exemplary embodiment may correspond to the storage deviceillustrated in. For example, the storage devicemay include a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure. The first semiconductor structuremay be bonded to the second semiconductor structureby the wafer bonding method, and the second semiconductor structureand the third semiconductor structuremay be electrically connected through a connection structure. The stacked structure of the storage devicemay be the same as that of the storage deviceillustrated in.

510 540 511 520 560 521 530 531 10 In addition, the first semiconductor structuremay include a memory cell arrayA including a plurality of first memory cells arranged on a first semiconductor substrate. The second semiconductor structuremay include peripheral circuits and a buffer memorydisposed on the second semiconductor substrate. The third semiconductor structuremay include a memory controller that is disposed on the third semiconductor substrateand transmits data transmitted from the hostto the non-volatile memory.

531 575 529 575 531 Meanwhile, the memory controller disposed on the third semiconductor substratemay further include a static RAM (SRAM)for specifying locations of data to be stored in the plurality of first memory cells and data stored in the plurality of first memory cells. A selection circuitfor controlling to selectively perform an operation on the static RAMmay be further disposed on the third semiconductor substrate.

13 FIG. 14 FIG. is a diagram illustrating a write operation of the storage device according to the exemplary embodiment in the present disclosure.is a flowchart illustrating the write operation of the storage device according to the exemplary embodiment in the present disclosure.

13 14 FIGS.and 100 10 110 10 170 100 100 Referring to, the storage deviceaccording to the exemplary embodiment in the present disclosure may start a write operation by receiving data and a write command from the host(S). In this case, the hostmay transmit the data and write command to the memory controllerincluded in the storage device. The storage devicemay translate the received write command into the form of a control signal.

170 120 170 170 140 130 The memory controllermay determine the characteristics of the received data (S). The memory controllermay set a data write path based on the characteristics of the received data. In other words, the memory controllermay determine whether to directly store data in the first cell area, for example, a VNAND memory cell, based on the characteristics of the received data (S).

170 160 140 140 For example, when the received data is sequence data, the memory controllermay bypass the buffer memoryand directly transmit the data to the first cell area(S).

140 170 145 100 170 140 10 140 160 The first cell areamay receive a command for storing data received from the memory controller(S). In this case, since the storage deviceaccording to the exemplary embodiment in the present disclosure has a stacked single-chip structure, the memory controllermay directly apply a control signal to the first cell area. The data transmitted from the hostmay be input to the first cell areabased on the applied control signal (S).

170 160 150 150 160 152 Meanwhile, when the received data is random data, the memory controllermay apply a control signal to the buffer memoryand the peripheral circuit area(S) to store the received data in the buffer memory(S).

170 160 154 140 156 10 140 160 Thereafter, the memory controllermay read data stored in the buffer memory(S) and transmit the read data to the first cell area(S). Accordingly, the data transmitted from the hostmay be input to the first cell area(S).

15 FIG. 16 FIG. is a diagram illustrating the read operation of the storage device according to the exemplary embodiment in the present disclosure.is a flowchart illustrating a read operation of the storage device according to the exemplary embodiment in the present disclosure.

15 16 FIGS.and 100 10 210 10 170 100 100 Referring to, the storage deviceaccording to the exemplary embodiment in the present disclosure may start a read operation by receiving a read command from the host(S). In this case, the hostmay transmit the read command to the memory controllerincluded in the storage device. The storage devicemay translate the received read command into the form of a control signal.

170 140 220 170 230 160 240 The memory controllermay perform a read operation on data stored in the first cell area, for example, a VNAND memory cell, based on the control signal (S). Similar to the write operation, the memory controllermay determine the characteristics of the read data (S) and determine whether to store the data in the buffer memorybased on the characteristics of the read data (S).

170 140 250 160 10 170 255 270 For example, when the received data is sequence data, the memory controllermay apply a control signal to the first cell area(S) and bypasses the buffer memoryand directly transmit the read data to the hostvia the memory controller(S) (S).

170 160 150 260 160 262 Meanwhile, when the received data is random data, the memory controllermay apply a control signal to the buffer memoryand the peripheral circuit area(S) to store the read data in the buffer memory(S).

170 160 264 10 170 266 270 Thereafter, the memory controllermay read data stored in the buffer memory(S) and transmit the data to the hostvia the memory controller(S) (S).

17 FIG. is a diagram illustrating a form of disposing the storage device, according to the exemplary embodiment in the present disclosure, on a printed circuit board.

17 FIG. 1 FIG. 17 FIG. 600 100 600 680 20 685 600 Referring to, a storage deviceaccording to an exemplary embodiment in the present disclosure may correspond to the storage deviceillustrated in. However, in the storage deviceillustrated in, a third metal padand a printed circuit boardmay be connected through a bump. The storage devicemay be packaged in the form of a ball grid array (BGA).

600 600 600 20 670 640 660 600 The storage deviceaccording to the exemplary embodiment in the present disclosure may reduce the overall size of the storage devicein the form of a single chip compared to the conventional product by combining the storage devicewith the printed circuit board. In addition, since a separate interface according to the inter-chip connection is not required, the memory controllermay directly control the first cell areaand the second cell area. Accordingly, steps such as command interpretation and data signal translation may be omitted during the operation of the storage device, and thus the operating speed may be improved.

18 FIG. is a diagram schematically illustrating a storage system according to an exemplary embodiment in the present disclosure.

18 FIG. 2 100 1 100 2 100 30 40 2 n Referring to, a storage systemaccording to an exemplary embodiment in the present disclosure may include a plurality of storage devices-,-, . . . ,-each of which is formed in a single chip, a network switch, and a connector. As an example, the storage systemmay be implemented on one printed circuit board.

100 1 100 2 100 100 200 300 400 500 600 17 100 1 100 2 100 n n 1 FIGS. Each of the plurality of storage devices-,-, . . . ,-may correspond to the storage devices,,,,, andillustrated into. For example, each of the plurality of storage devices-,-, . . . ,-may include a first semiconductor structure including a first cell area, a second semiconductor structure including a peripheral circuit area and a second cell area, and a third semiconductor structure including a memory controller. The first semiconductor structure may be bonded to the second semiconductor structure by a wafer bonding method, and the second semiconductor structure and the third semiconductor structure may be electrically connected to each other through the connection structure.

2 40 30 30 40 100 1 100 2 100 n. In the storage systemaccording to the exemplary embodiment in the present disclosure, the connectormay receive data from the host and transmit the data to the network switch. Meanwhile, the network switchmay distribute data received through the connectorto the plurality of storage devices-,-, . . . ,-

2 100 1 100 2 100 100 1 100 2 100 100 1 100 2 100 n n n The storage systemmay be reduced in size by coupling the plurality of storage devices-,-, . . . ,-to one printed circuit board and improve the operating speed of the plurality of storage devices-,-, . . . ,-. In addition, data may be exchanged between the plurality of storage devices-,-, . . . ,-without the involvement of the host and the capacity of the server may be easily increased by further coupling the storage device to the printed circuit board.

19 19 FIGS.A toE are diagrams illustrating a process of manufacturing a storage device according to an exemplary embodiment in the present disclosure.

19 19 FIGS.A toE 1 FIG. 19 19 FIGS.A toE 100 200 300 400 500 600 110 120 130 100 may be diagrams schematically illustrating a process of manufacturing the storage deviceillustrated in. The manufacturing process ofmay be similarly applied to the storage devices,,,, andaccording to other exemplary embodiments. However, this is only an example and may not be limited. For example, the first semiconductor structure, the second semiconductor structure, and the third semiconductor structureincluded in the storage devicemay be independently manufactured regardless of an order.

19 FIG.A 110 140 141 142 111 113 110 140 Referring to, in the first semiconductor structure, the first cell areaincluding gate electrodesand channel structuresmay be formed on the first semiconductor substrate. In this case, a first metal padfor bonding the first semiconductor structureto other structures may be formed above the memory cell area.

19 FIG.B 120 150 160 121 123 120 150 160 123 113 Referring to, in the second semiconductor structure, the peripheral circuit areaand the second cell areamay be formed on the second semiconductor substrate. In this case, a second metal padfor bonding the second semiconductor structureto other structures may be formed above the peripheral circuit areaand/or the second cell area. For example, the position of the second metal padmay correspond to the position of the first metal pad.

19 FIG.C 125 121 120 125 150 160 120 a a Referring to, a connection structurepenetrating through the second semiconductor substratemay be formed in the second semiconductor structure. For example, the connection structuremay be electrically connected to the peripheral circuit areaand the second cell areaof the second semiconductor structure.

19 FIG.D 130 170 180 131 131 125 130 170 125 130 125 120 b b a Referring to, in the third semiconductor structure, the memory controllerconnected to the third metal padthrough the connection via penetrating through the third semiconductor substratemay be formed on the third semiconductor substrate. In this case, the connection structurefor bonding the third semiconductor structureto other structures may be formed above the memory controller. For example, the position of the connection structureincluded in the third semiconductor structuremay correspond to the position of the connection structureincluded in the second semiconductor structure.

19 FIG.E 19 19 FIGS.A toD 110 120 130 110 120 113 123 120 130 125 125 a b. Referring to, the first semiconductor structure, the second semiconductor structure, and the third semiconductor structuremanufactured throughmay be bonded to be stacked in the first direction (e.g., Z direction). For example, the first semiconductor structuremay be bonded to the second semiconductor structurethrough the bonding of the first metal padand the second metal pad. Also, the second semiconductor structuremay be bonded to the third semiconductor structurethrough the bonding of the connection structuresand

Since a storage device according to an exemplary embodiment in the present disclosure is manufactured as a single chip, it is possible to reduce a size of the storage device and improve an operating speed of the storage device.

A storage system according to an exemplary embodiment in the present disclosure may dispose a plurality of storage devices each manufactured as a single chip on one printed circuit board.

As is traditional in the field, embodiments may be described and illustrated in terms of blocks which carry out a described function or functions. These blocks, which may be referred to herein as units or modules or the like, are physically implemented by analog and/or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits and the like, and may optionally be driven by firmware and/or software. The circuits may, for example, be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards and the like. The circuits constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block. Each block of the embodiments may be physically separated into two or more interacting and discrete blocks without departing from the scope of the disclosure. Likewise, the blocks of the embodiments may be physically combined into more complex blocks without departing from the scope of the disclosure. An aspect of an embodiment may be achieved through instructions stored within a non-transitory storage medium and executed by a processor.

Various and beneficial advantages and effects of the present disclosure are not limited to the contents described above and may be more easily understood in a process of describing exemplary embodiments of the present disclosure.

While the present disclosure has been shown and described in connection with the exemplary embodiments, it will be apparent to those in the art that modifications and variations can be made without departing from the spirit and scope of the disclosure as defined by the appended claims. Accordingly, various types of substitutions, modifications and changes will be possible by those of ordinary skill in the art without departing from the present disclosure described in the claims and belong to the scope of the present disclosure.