Sige Nanoribbons for High Performance Transistors

While strain on a transistor channel can increase the mobility of charge carriers through the channel, the delivery of strain on channels is difficult or diminished in some transistor structures, e.g., in certain types of transistors. For example, in gate-all-around (GAA) field-effect transistors (FETs) (e.g., with nanowire channels), uniaxial stress is not exerted (or at least not to the same extent, relative to FinFETs) by source and drain epitaxial bodies grown from the ends of channels. With multiple nanowires between epi bodies in GAA FETs, source and drain bodies may be merged, polycrystalline bodies with multiple faults or dislocations that preclude the provision of satisfactory strain by source and drain bodies, which may limit carrier mobilities in some transistor structures.

In some integrated circuit (IC) devices, different groups of transistors may benefit from the use of different materials. For example, p-type FETs may benefit from silicon germanium channel materials, while pure silicon channels may work better in n-type FETs. However, the fabrication of adjacent transistors having different channel materials may be excessively complex and/or costly.

New techniques, structures, and materials are needed to improve the manufacture and operation of GAA FETs in IC devices.

In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. The various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter.

References within this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase “one embodiment” or “in an embodiment” does not necessarily refer to the same embodiment. In addition, the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled.

The terms “over,” “to,” “between,” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over” or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.

The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe structural relationships between components. These terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may be used to indicate that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause-and-effect relationship, an electrical relationship, a functional relationship, etc.).

The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

The vertical orientation is in the z-direction and recitations of “top,” “bottom,” “above,” and “below” refer to relative positions in the z-dimension with the usual meaning. However, embodiments are not necessarily limited to the orientations or configurations illustrated in the figure.

The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value (unless specifically specified). Unless otherwise specified in the specific context of use, the term “predominantly” means more than 50%, or more than half. For example, a composition that is predominantly a first constituent means more than half of the composition is the first constituent. The term “primarily” means the most, or greatest, part. For example, a composition that is primarily a first constituent means the composition has more of the first constituent than any other constituent. A composition that is primarily first and second constituents means the composition has more of the first and second constituents than any other constituent.

Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects to which are being referred and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

Views labeled “cross-sectional,” “profile,” and “plan” correspond to orthogonal planes within a cartesian coordinate system. Thus, cross-sectional and profile views are taken in the x-z and y-z planes, and plan views are taken in the x-y plane. Typically, profile views in the x-z plane are cross-sectional views. Where appropriate, drawings are labeled with axes to indicate the orientation of the figure.

Materials, structures, and techniques are disclosed for forming, and producing strain in, transistor channels of compound semiconductor materials, including nanoribbons having uniform compositions throughout the nanoribbon volumes.

One or more additive elements may be deposited on and around a transistor channel, for example, a nanoribbon in a gate-all-around (GAA) field-effect transistor (FET). Atoms of the additive element(s) may be introduced into, and thoroughly interspersed in, the crystal lattice of the channel by vacancy-assisted diffusion, e.g., to improve one or more characteristics of the channel. Oxygen (and/or nitrogen, etc.) vacancies may be introduced by a capping layer (for example, a dielectric capping layer) that encases the channel (including the additive element(s)) and retains the vacancy element(s) during diffusion. The capping layer can be removed after the channel elements are completely intermixed into a consistent composition throughout the channel. A thorough diffusion ensures a homogenous composition and precludes adverse effects of an interface between unmatched lattices, such as non-uniform strain, reduced carrier mobilities, and increased leakage current. Even if the initial channel composition is purely elemental (e.g., pure silicon), the final composition of the channel can be tuned by adjusting any of the initial channel thickness and the thickness and/or composition of the deposited layer(s). In some embodiments, the initial channel thickness is reduced before depositing the additive element(s) on the channel.

In some embodiments, the channel is fabricated using conventional materials and/or existing processes, and the channel lattice is then modified by the addition of a new element. For example, germanium atoms may be added to a nanoribbon channel of silicon. The resulting structure may have superior channel qualities due to the general electrical qualities of silicon germanium, as well as the compressive strain caused by the larger lattice constant relative to the preexisting silicon nanoribbon. The alteration of the channel lattice may be especially advantageous given the difficulty in otherwise effecting strain in GAA FET channels between merged source and drain bodies.

T In the example of germanium added to silicon, the current disclosure allows the use of existing processes (which may conserve known benefits, such as proven reliabilities and reduced costs, relative to other, more disruptive process-flow changes) to produce the silicon nanoribbon. The example also enables the use of one material (e.g., silicon) for one channel type (e.g., nFET) and another material (e.g., silicon germanium) for another channel type (e.g., pFET), which clearly has benefits in CMOS (complementary MOS (metal-oxide-semiconductor)) integrated circuit (IC) devices. The channels of differing materials, with and without the added element(s), may be positioned as channels would be in the established process, for example, parallel and at identical heights in stacks with identical pitches. Besides the compressive effect, silicon germanium otherwise improves pFET performance (e.g., by increasing mobility and reducing threshold voltage V) and reliability (e.g., having reduced negative-bias temperature instability (NBTI)). Although the example of adding germanium into a lattice of silicon is repeatedly referenced, other materials may be employed (e.g., as an added, diffused element or as an initial lattice) to introduce or alter other characteristics and/or to exert another type or magnitude of strain.

In some embodiments, for example, having nanoribbons with larger atoms diffused into a lattice of smaller atoms, nanoribbons exhibit a tell-tale bulge or thickening near a midpoint of the nanoribbon. The larger atoms inserted into a compact lattice may cause the bulge by expanding the lattice evenly along a length of a nanoribbon, but with the nanoribbon lattice pinned to the previous, smaller lattice constant to source and drain bodies at the nanoribbon ends.

1 1 1 1 1 FIGS.A,B,C,D, andE 1 FIG.A 1 1 FIGS.B andC 1 1 FIGS.B andC 1 FIG.A 1 FIG.C 1 1 FIGS.D andE 100 101 120 122 102 illustrate cross-sectional profile views of an IC devicehaving transistor structureswith channel regions in nanoribbons,of different materials, in accordance with some embodiments.shows the orientation of cross-sectional views B-B′ and C-C′ of.illustrate the orientation of cross-sectional view A-A′ of. Viewinis shown in greater detail infor multiple possible embodiments.

120 122 120 120 120 122 120 122 120 120 120 120 122 120 122 120 122 122 122 120 120 122 1 2 A B 1 A 3 1 A 2 B 2 B 2 3 1 2 3 1 Nanoribbonmay include an element not present in nanoribbon, e.g., an element that may be added to the lattice of nanoribbonto enhance a characteristic of nanoribbon. Nanoribbons,have thicknesses T, Tat the respective midpoints M, Mof nanoribbons,. Each of enhanced nanoribbonsmay include a bulge, for example, with a thickness Tat or near midpoint Mof nanoribbongreater than a thickness Tat or near an end of nanoribbon. Thickness Tat or near midpoint Mof nanoribbonmay be greater than a thickness Tat or near midpoint Mof nanoribbon. The bulge may be due to the expanded lattice of nanoribbon. Nanoribbon(lacking an element present in the lattice of nanoribbon) may have a uniform thickness Talong a length of nanoribbon(e.g., at or near midpoint Mand both ends of nanoribbons). The uniform thickness Tof nanoribbonmay be approximately equal to thickness Tat or near an end of nanoribbon. Nanoribbons,may be parallel, at the same heights H, H, H, and separated by the same pitches P, which may simplify processing (and so reduce manufacturing costs, e.g., of both time and money).

1 FIG.A 1 FIG.A 1 FIG.A 1 FIG.A 1 FIG.A 121 120 122 101 120 122 125 120 122 120 122 101 120 122 101 121 120 125 101 121 122 125 125 125 125 s shows stacksof nanoribbons,in transistor structures. Nanoribbons,extend in the y-directions through gate electrode() and the x-z view A-A′ of, which shows a transverse cross-section of nanoribbons,. As noted, the figures and their elements are not necessarily illustrated to scale. In other embodiments, nanoribbons,may be very narrow or wide (e.g., in the x-direction), e.g., nanowires, nanosheets, etc. Transistor structuresinclude (and nanoribbons,couple) source and drain bodies (not shown in) in front of and behind the x-z viewing plane of. Transistor structureA includes stackA of nanoribbonsthrough gate electrodeA. Transistor structureB includes stackB of nanoribbonsthrough gate electrodeB. In the example of, gate electrodesA,B are portions of an integrated electrode.

120 122 121 121 120 122 120 122 120 122 120 122 120 122 121 121 120 122 120 122 1 3 2 1 1 2 2 3 1A 1B 1 2A 2B 2 3A 3B 3 1A 2A 3A A 1B 2B 3B B 1 FIG.C 1 FIG.A 1 FIG.B 1 FIG.A Corresponding nanoribbons,in stacksA,B are at same heights, for example, upper nanoribbons,at height H, lower nanoribbons,at height H, and nanoribbons,at height Hbetween upper and lower nanoribbons,. Nanoribbons,in stacksA,B are separated by the same pitches P, e.g., between heights H, Hand between heights H, H. Nanoribbons,are all parallel, with centerlines CL extending in the y-directions (e.g., coplanar centerlines CL, CLat height H, coplanar centerlines CL, CLat height H, and coplanar centerlines CL, CLat height H). Coplanar centerlines CL, CL, CLare in the y-z plane of view C-C′ ofand intersect the x-z plane of view A-A′ ofat midpoints Mof nanoribbons. Coplanar centerlines CL, CL, CLare in the y-z plane of view B-B′ ofand intersect the x-z plane of view A-A′ ofat midpoints Mof nanoribbons.

120 122 120 122 101 101 101 101 101 101 101 122 101 120 101 1 1 FIGS.A-E Nanoribbons,include different channel materials. In many embodiments, nanoribbons,include complementary channel materials. The channel materials are referred to herein as “complementary” because one channel material is advantageous for an NMOS transistor structurewhile the other channel material is advantageous for a PMOS transistor structure. In exemplary embodiments, channel material within an NMOS transistor structureoffers higher electron mobility than the channel material within a PMOS structure. In exemplary embodiments, channel material within a PMOS transistor structurelikewise offers higher hole mobility than the channel material within a NMOS transistor structure. The high complementary carrier mobilities may therefore enable high drive currents independently for both NMOS and PMOS structures. For clarity of discussion, in the example of, nanoribbonsare referred to as being within a channel of NMOS transistor structureB while nanoribbonsare within a channel of PMOS transistor structureA.

120 122 120 122 120 122 120 122 122 1-X X In accordance with some embodiments, PMOS and NMOS nanoribbons,have complementary chemical compositions where one composition is advantageous for a p-type transistor (e.g., having higher hole mobility) and the other composition is advantageous for an n-type transistor (e.g., having higher electron mobility). For example, nanoribbonsmay each be a first Group IV, Group III-V, etc., semiconductor material while nanoribbonsare each a second Group IV, Group III-V, etc., semiconductor material. In many embodiments, nanoribbonsinclude a semiconductor element absent from nanoribbons. In some notable Group IV embodiments, nanoribbonsinclude germanium (e.g., SiGe) while nanoribbonsinclude primarily silicon and may consist essentially of silicon (e.g., substantially pure silicon with germanium absent in nanoribbons).

120 120 120 120 120 120 120 1-X X 1-X X T In embodiments having nanoribbonsof silicon germanium (e.g., SiGe), nanoribbonsmay have any suitable concentration of germanium. In many embodiments, nanoribbonshave a germanium concentration of at least 20% and no more than 40%. Advantageously, nanoribbonshave an optimized concentration of germanium (e.g., 0.2≤x≤0.4 in SiGe) to provide performance and reliability improvements as previously described (e.g., reduced threshold voltage Vand reduced NBTI). Advantageously, nanoribbonshave a sufficient concentration of germanium (e.g., ≥20%) to provide, e.g., increased compressive strain and hole mobility. Advantageously, nanoribbonsdo not have overly high concentrations of germanium (e.g., ≤40%), which might cause dislocations or other lattice defects. An optimal concentration of germanium may vary with nanoribbongeometry.

120 120 120 120 123 120 1 A 1A 2A 3A A 1A A A Advantageously, nanoribbonshave a homogenous composition, for example, throughout a length or thickness of nanoribbons. In many embodiments, nanoribbonshave a same composition (e.g., germanium concentration) along thickness Tat midpoint M(e.g., at the intersection of views A-A′ and C-C′), whether on one of centerlines CL, CL, CLor on a surface over midpoint M(e.g., at an interface of nanoribbonand gate layer). For the purposes of this disclosure, two compositions are considered the same or approximately equal if the various concentrations (e.g., germanium concentrations) are within 5% of each other. For example, in many embodiments, nanoribbonshave a same germanium concentration on centerline CLat midpoint M(e.g., of 25% germanium) and on a surface over midpoint M(e.g., of 30% germanium).

120 122 120 122 120 120 120 120 120 122 1 2 1 A 2 B 1 1A 2A 3A 1 2 3 1B 2B 3B 1 Nanoribbons,may have any suitable thicknesses T, T, for example, about 3 nm, 5 nm, 7 nm, etc. In many embodiments, nanoribbonhas a thickness Tat midpoint Mmore than 5% greater than (e.g., greater than 105% of) thickness Tat midpoint Mof nanoribbon, for example, due to an additional element in, and the expanded lattice of, nanoribbon. A lattice of nanoribbonmay expand or strain in multiple directions. For example, although an increase of thickness Tis shown in the z-direction, a thickness variation in the x- and z-directions may be increased by strain in the y-directions. A thickness variation in the x-directions may be limited by geometries of nanoribbons, e.g., by the comparative widths and heights of nanoribbons. Nanoribbons,are parallel (e.g., with centerlines CL, CL, CLat the same heights H, H, Has centerlines CL, CL, CL, respectively) and separated by the same pitches P.

125 120 125 123 120 122 126 127 101 101 125 125 101 101 125 125 122 125 123 126 127 101 125 120 125 123 126 127 101 127 127 127 127 125 101 101 125 101 101 One or more gate electrodesare between individual ones of nanoribbons. Gate electrodemay include one or more insulator materials in a gate layer, which provides isolation between nanoribbons,and associated gate metals,. In some embodiments, transistor structuresA,B have distinct gate electrodesA,B. In some embodiments, transistor structuresA,B share a common gate electrode. In some embodiments, one gate electrodeB is between individual ones of nanoribbons. Gate electrodeB may include one or more gate insulator materials (e.g., in gate layer) and one or more gate electrode materials (e.g., workfunction metalsB,B) advantageous for NMOS structureB. Another gate electrodeA is between individual ones of nanoribbons. Gate electrodeA may include one or more gate insulator materials (e.g., in gate layer) and one or more gate electrode materials (e.g., workfunction metalsA,A) advantageous for PMOS structureA. In some embodiments, gate metalsA,B are workfunction metalsA,B. In some embodiments, gate electrodeB includes a first high-K (“high-permittivity”) insulator material advantageous for n-type transistor structuresB and a first workfunction metal advantageous for n-type transistor structuresB while gate electrodeA includes a second high-K insulator material advantageous for p-type transistor structuresA and a second workfunction metal advantageous for p-type transistor structuresA.

123 125 Exemplary high-K dielectrics (e.g., in gate layer) include metal oxides (e.g., including one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate), or metal silicates (e.g., including one or more of above metals, oxygen and silicon). Examples of work function metals (e.g., in gate electrode) include ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide), hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.

145 125 145 125 101 199 145 145 145 145 145 145 125 132 145 Gate isolationis over gate electrode. Isolationmay include a low-permittivity (“low-K”) dielectric material that separates gate electrodefrom interconnect metallization layers, e.g., in one or more interconnect networks over and/or under structures, on a front- and/or back-side of substrate. In many embodiments, isolationincludes an oxide, nitride, and/or oxynitride. In some such embodiments, isolationincludes an oxide and/or nitride doped with carbon. Different materials in isolationmay perform different functions, such as providing etch selectivities. In many embodiments, isolationincludes an oxide and/or nitride, etc., of silicon (such as, but not limited to, SiN, SiO, SiON, SiOC, SiCN). In some embodiments, isolationincludes an oxide and/or nitride, as well as hydrogen (e.g., SiOCH), which may correspond to a reduced permittivity. In some embodiments, isolationincludes pores (e.g., nanopores) in an oxide and/or nitride, which may correspond to a reduced permittivity. Gate electrodemay be coupled to interconnect metallization layers by contact or viathrough gate isolation.

199 199 199 199 199 199 101 149 199 199 2 3 Substratemay include any suitable material or materials. Any suitable semiconductor or other material, for example, an insulator material, can be used. Substratemay be any suitable substrate, such as a wafer, die, etc. Substratemay include a semiconductor material that transistors can be formed out of and on, including a crystalline material, such as monocrystalline or polycrystalline silicon (Si), germanium (Ge), silicon germanium (SiGe), a III-V alloy material (e.g., gallium arsenide (GaAs)), a silicon carbide (SiC), a sapphire (AlO), or any combination thereof. In some embodiments, substrateincludes crystalline silicon and subsequent components are also silicon. In some embodiments, a crystalline material of substrateis removed (e.g., by grinding) from a back-side of transistor structuresand replaced with an isolation material, such as that of isolation. Substratemay be a silicon-on-insulator (SOI) substrate. Substratemay also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in IC substrates.

149 199 121 199 149 145 125 123 149 199 101 149 101 Shallow-trench isolation (STI)is over substrateand between stacks, for example, between subfins of substrate. Isolationmay include a low-K dielectric material, e.g., as described of isolation. Gate electrode(for example, gate layer) may be on STI. In some embodiments, crystalline material (e.g., silicon) of substrate, such as in subfins, is removed beneath transistor structures, and material of STIis on a back-side of structures.

1 FIG.B 1 FIG.B 1 FIG.A 121 122 101 122 125 122 122 122 122 120 122 122 122 122 110 122 122 122 122 122 110 122 122 122 120 1B 2B 3B B 2 B 2 2 2 2 2 2 2 2 2 3 illustrates stackB of nanoribbonsin transistor structureB. Nanoribbonsextend in the y-directions through gate electrodeB in the y-z plane of view B-B′ of, which shows a longitudinal cross-section of nanoribbons. Centerlines CL, CL, CLof nanoribbonsextend in the y-directions in the y-z plane of view B-B′ and intersect the x-z plane of view A-A′ ofat midpoints Mof nanoribbons. Nanoribbon(lacking an element present in the lattice of nanoribbon) may have a uniform thickness Talong a length of nanoribbon(e.g., at or near midpoint Mand at both ends of nanoribbons). In many embodiments, nanoribbonhas a perfectly (or very nearly perfectly) uniform thickness Talong the length of nanoribbonbetween source and drain bodiesB, and thickness Tis a maximum thickness Tof nanoribbonsand a minimum thickness Tof nanoribbons(e.g., with 0.0% variation between minimum and maximum). For example, thickness Tof nanoribbonsmay follow a uniform crystal lattice (e.g., of silicon under very little strain). In some embodiments, nanoribbonis not perfectly uniform, but a thickness variation of thickness Talong the length of nanoribbonbetween source and drain bodiesB is less than 1% (e.g., a maximum thickness Tof a nanoribbonis less than 1% more than a minimum thickness Tof the same nanoribbon). In many embodiments, the uniform thickness Tof nanoribbonis approximately equal to (e.g., within 1% of) thickness Tat or near an end of nanoribbon.

1 FIG.C 121 120 101 shows stackA of nanoribbonsin transistor structuresA.

120 125 120 120 120 102 1 FIG.C 1 FIG.A 1 1 FIGS.D andE 1 FIG.C 1A 2A 3A A Nanoribbonsextend in the y-directions through gate electrodeA and the y-z plane of view C-C′ of, which shows a longitudinal cross-section of nanoribbons. Centerlines CL, CL, CLof nanoribbonsextend in the y-directions in the y-z plane of view C-C′ and intersect the x-z plane of view A-A′ ofat midpoints Mof nanoribbons. Multiple embodiments are shown in greater detail in, which magnify viewof.

120 122 120 120 120 120 120 120 110 120 110 120 110 110 120 110 110 1 A 3 1 3 1 A 3 A 3 3 1 A Nanoribbonmay include an element not present in nanoribbon(e.g., an element that may be added to the lattice of nanoribbonto enhance a characteristic of nanoribbon), and each of enhanced nanoribbonsmay include a bulge (e.g., with a thickness Tat or near midpoint Mof nanoribbongreater than a thickness Tat or near an end of nanoribbon). Nanoribbonsare symmetric between bodiesA with symmetric bulges (and thicknesses T, T). Nanoribbonshave thickness Tat midpoint Mbetween source and drain bodiesA, and nanoribbonshave thickness Tat an intervening point between midpoint Mand one of source and drain bodiesA (e.g., adjacent one of source and drain bodiesA). Nanoribbonsmay have a minimum thickness Tat or adjacent one of source and drain bodiesA, and the thickness may monotonically increase from minimum thickness Tto maximum thickness Tat midpoint Mbetween source and drain bodiesA.

1 3 1 3 1 3 1 3 1 3 1 3 120 122 120 120 120 122 120 In many embodiments, thickness Tis at least 5% greater than thickness T. The bulge (e.g., thickness Tbeing greater than thickness T) may be caused by the enlarged lattice constant of nanoribbon(e.g., with an additional element relative to nanoribbons), and the bulge (e.g., the difference between thicknesses T, T) may be larger for larger concentrations of the additional element in nanoribbon. For example, in many embodiments, a silicon germanium nanoribbonwith a germanium concentration greater than 20% has a thickness variation (e.g., bulge of thickness Tgreater than thickness T) of at least 3% between thicknesses T, T. In many embodiments, nanoribbonhas a concentration of the additional element (e.g., not in nanoribbons) greater than 25% (e.g., 30% or 35% or 40%). In many embodiments, nanoribbonhas a thickness variation of more than 5% between thicknesses T, T.

120 120 120 122 120 120 120 125 120 125 122 122 120 1 3 1 3 1 3 1 2 3 In many embodiments, nanoribbonhas a larger thickness variation between thicknesses T, T(e.g., of more than 5%) due to a thicker deposition of the added element on nanoribbon. In many embodiments, the thickness variation of nanoribbonis ten times or more than more than the thickness variation of nanoribbons(e.g., which may be <1%, for example, 0.1% or 0.2%). The thickness variation (e.g., bulge) of nanoribbonmay advantageously improve current control through nanoribbons. The greater thickness T(relative to thickness Tand to other, smaller thicknesses T) may enable lower channel resistances (and larger “on” currents) where nanoribbonis covered by gate electrodeA. The lower thickness T(where nanoribbonis not covered by gate electrodeA) may ensure lower leakage currents (e.g., lower “off” currents for a same thickness T). Nanoribbonmay have virtually no within-ribbon thickness variation (e.g., no bulge). Thickness Tof nanoribbonmay be approximately equal to (e.g., within 1% of) thickness Tat or near an end of nanoribbon.

1 A 2 B 1 A 2 B 1 1 2 2 B 1 A 1 2 1 2 2 1 120 122 120 122 101 101 120 120 122 121 121 122 120 120 122 120 122 121 121 120 122 122 120 Thickness Tat or near midpoint Mof nanoribbonmay be greater than a thickness Tat or near midpoint Mof nanoribbon. In some embodiments, nanoribbonhas a thickness Tat or near midpoint M5% or more greater than thickness Tat or near midpoint Mof nanoribbon, which may provide advantageous proportions of currents in transistor structuresA,B. Thickness Tof nanoribbonmay be increased, e.g., by the deposition of the additive element. Thicknesses T, Tof nanoribbons,may be controlled by independent processing of stacksA,B. Thickness Tat or near midpoint Mof nanoribbonmay be greater than thickness Tat or near midpoint Mof nanoribbon. Thickness T(or T) of nanoribbon(or) may be reduced, e.g., by a trimming of nanoribbons(or) in stackA (orB). Either of nanoribbons,may be 2%, 5%, 10%, 50% thicker (e.g., either of thicknesses T, Tmay be greater) than the other of nanoribbons,(and thicknesses T, T).

120 120 110 122 120 120 120 120 120 120 110 110 110 120 110 A 1A 2A 3A A A 2 3 A 3 1A 2A 3A A 2 3 A Bulges in nanoribbonsmay be evidence of an element added to the now-expanded lattice between ends of nanoribbonspinned to a smaller lattice constant (e.g., before expansion) at source and drain bodiesA. The additional element (e.g., not in nanoribbons), even if deposited as a cladding on and around nanoribbons, may be evenly spread (e.g., homogenously mixed by a thorough diffusion) throughout nanoribbons, and the smoothness of the bulge may be due to surface tension acting to reduce surface area of the bulge and the enlarged nanoribbon. For example, nanoribbonsmay have a homogenous composition along a length of nanoribbons(e.g., an axis or centerline CL). In many embodiments, nanoribbonshave approximately equal first and second atomic compositions on each of centerlines CL, CL, CLwith a first atomic composition at midpoint Mand a second atomic composition at an intervening point between midpoint Mand one of source and drain bodiesA (e.g., either of midpoint M, M, equidistant between midpoint Mand one of source and drain bodiesA, or the intervening point indicated as having thickness T, adjacent one of source and drain bodiesA). In some embodiments, nanoribbonshave approximately equal first, second, and third germanium concentrations on each of centerlines CL, CL, CLwith a first germanium concentration at midpoint Mand second and third germanium concentrations at midpoints M, M, equidistant between midpoint Mand each of source and drain bodiesA.

122 120 120 120 120 120 123 1 3 1 A 1A 2A 3A A An additional element (e.g., not in nanoribbons) may be evenly spread (e.g., homogenously mixed) throughout nanoribbons, including vertically along a thickness Tor Tin the z-dimension. For example, nanoribbonsmay have a homogenous composition along thickness Tof nanoribbons, e.g., with first germanium concentrations on each of midpoints Mon centerlines CL, CL, CLequal to (e.g., within 5% of) second germanium concentrations on surfaces of nanoribbonsover midpoints M(e.g., at interfaces of nanoribbonsand gate layer).

1 1 FIGS.B andC 1 FIG.B 120 122 110 122 110 110 110 110 110 As illustrated in, nanoribbons,couple source and drain bodies. In the example of, NMOS nanoribbonsare coupled to, and in contact with, n-type source and drain bodiesB. Source and drain bodiesB may have any chemical composition and microstructure suitable for an NMOS transistor. N-type source and drain bodiesB may include monocrystalline or polycrystalline semiconductor material. In many embodiments, n-type source and drain bodiesB include a Group IV or III-V semiconductor material doped with any impurity dopants known to be suitable for the desired conductivity type, and to any concentration known to be suitable for transistors. In some embodiments, bodiesB include silicon and an n-type dopant, such as phosphorous, arsenic, or another donor impurity.

1 FIG.C 120 110 110 110 110 110 110 110 In the example of, PMOS nanoribbonsare coupled to, and in contact with, p-type source and drain bodiesA. P-type source and drain bodiesA may have any chemical composition and microstructure suitable for a PMOS transistor. Source and drain bodiesA may include monocrystalline or polycrystalline semiconductor material. In many embodiments, source and drain bodiesA include a Group IV or III-V semiconductor material doped with any impurity dopants known to be suitable for the desired conductivity type, and to any concentration known to be suitable for transistors. In some embodiments, bodiesA include silicon, germanium, and a p-type dopant, such as boron, aluminum, gallium or any other acceptor impurity. In some exemplary embodiments, source and drain bodiesB are predominantly silicon doped with any suitable concentration of donor impurities while source and drain bodiesA are predominantly silicon germanium doped with any suitable concentration of acceptor impurities.

110 112 112 120 122 120 122 112 112 120 112 110 112 110 110 110 112 112 112 110 120 112 110 110 112 112 110 112 120 112 112 110 112 112 122 110 112 112 112 120 122 112 112 Source and drain bodiesmay include (or contact) interface layers. Buffer layerscontact ends of nanoribbons,(e.g., covering an entire x-z end of nanoribbons,). Layersmay be thin layers, for example, epitaxially grown on nanoribbonsonly as thick as necessary to serve as a growth template (e.g., nucleation layer) for the growth of source and drain bodies. Interface layersin or on bodiesA,B may have a lower dopant concentration than the bodieslayersare in or on (including a dopant concentration of zero in layer). Interface layersin or on bodiesA may have a concentration of the additional (enhancing) element less than the concentration of the additional element in nanoribbons. In some embodiments, interface layersin or on bodiesA has a concentration of the additional element less than the concentration of the additional element in portions of bodiesA contacting layers. For example, in some such embodiments, layerhas a concentration of germanium (e.g., <20%) less than a concentration of germanium in silicon germanium source or drain bodyA contacting (e.g., epitaxially grown from) layerand less than a concentration of germanium in silicon germanium nanoribbonscontacting layer. In some such embodiments, layerhas a dopant concentration (e.g., of boron) less than a dopant concentration of the source or drain bodyA contacting (e.g., epitaxially grown from) layer. In some embodiments, layerson nanoribbonshave a dopant concentration (e.g., of phosphorous) less than a dopant concentration of the source or drain bodyB contacting (e.g., epitaxially grown from) layer. Interface layermay be a high-quality (e.g., epitaxially grown) layerthat inhibits diffusion (e.g., of dopants) into nanoribbons,. Layermay inhibit diffusion during processing (e.g., a high-temperature anneal) due to the composition of layer(e.g., a concentration as described above).

100 142 143 110 125 110 125 131 125 142 143 142 120 122 143 120 122 120 122 142 143 142 143 142 143 145 142 143 1 FIG.A Deviceincludes spacers,between source and drain bodies, between gate electrodeand source and drain bodies, and between gate electrodeand metallization structures, e.g., as electrical insulation. Gate electrodeis between spacers,. Cavity spacersare between nanoribbons,. Spacersare over an uppermost of nanoribbons,. Nanoribbons,extend through spacers,. Spacers,may have any suitable composition, for example, any suitably insulative (e.g., electrically insulative) composition. Advantageously, spacers,include one or more low-K materials, e.g., as described of isolationat. For example, each of spacers,may include an oxide, nitride, and/or oxynitride (such as of silicon), with or without carbon doping or hydrogen, and with or without nanopores.

141 110 141 110 101 141 145 149 142 143 Trench isolationis over and/or under source and drain bodies. Isolationmay include a low-K dielectric material that separates bodiesfrom interconnect metallization layers (e.g., in one or more interconnect networks), over and/or under structures. Isolation,,(and spacers,) may have the same or differing compositions.

101 131 110 100 101 131 131 131 Transistor structuresmay be coupled to interconnect metallization layers by metallization structures, which are contact structures on source and drain bodies. In some embodiments, IC deviceincludes front- and back-side interconnect networks, and structuresare coupled to metallization layers by in one or more interconnect networks by front- or back-side metallization structures. Structuresmay be coupled to interconnect layers by vias contacting structures.

1 FIG.D 1 FIG.C 102 120 110 120 123 112 120 110 112 110 120 1 A 2A 2 3 2A A 1 2 A illustrates viewfromin greater detail. Thickness Tof nanoribbonis through midpoint Mon centerline CL. Midpoints M, Mare on centerline CL, each equidistant between midpoint Mand one of source and drain bodiesA. Surfaces S, Sare interfaces of nanoribbonand gate layer, over and under, respectively, midpoint M. Interface layersare on ends of nanoribbon, in or on bodiesA (e.g., as nucleation layersfor growth of source and drain bodiesA off of ends of nanoribbon).

120 120 122 120 110 120 110 1 3 3 3 1 A Nanoribbonmay have a bulge (e.g., thickness Tbeing greater than thickness T) caused by an enlarged lattice constant of nanoribbon(e.g., with an additional element relative to nanoribbons). Nanoribbonsmay have a minimum thickness Tat or adjacent one of source and drain bodiesA, and the thickness of nanoribbonmay monotonically increase from minimum thickness Tto maximum thickness Tat midpoint Mbetween source and drain bodiesA.

120 120 120 120 120 120 120 110 1 A 2A 1 A A 2A 2 A 1 A 2A 1 2 A 2A A 2 3 A Nanoribbonmay have a homogenous composition along thickness Tof nanoribbons, e.g., with a first atomic composition (and, e.g., first germanium concentration) on midpoint Mon centerline CLequal to (e.g., within 5% of) a second atomic composition (and, e.g., germanium concentration) on surface Sof nanoribbonover midpoint M. In many embodiments, nanoribbonhas a first atomic composition (and, e.g., first germanium concentration) on midpoint Mon centerline CLequal to (e.g., within 5% of) a third atomic composition (and, e.g., germanium concentration) on surface Sof nanoribbonunder midpoint M. In many embodiments, nanoribbonhas a same composition (e.g., germanium concentration) along thickness Tat midpoint Mon centerline CLand on surfaces S, Sover and under midpoint M. In some embodiments, nanoribbonshave approximately equal first, second, and third atomic compositions on centerline CLwith a first atomic composition (and, e.g., first germanium concentration) at midpoint Mand second and third atomic compositions (and, e.g., germanium concentrations) at midpoints M, M, equidistant between midpoint Mand each of source and drain bodiesA.

1 FIG.E 102 120 110 120 110 120 110 110 120 110 4 2 3 3 4 4 1 A 4 2 3 A 4 shows embodiments of magnified view. In some embodiments, nanoribbonshave minimum thicknesses Tbetween midpoints M, Mand thicknesses Ton or adjacent bodiesA. In some such embodiments, nanoribbonshave a minimum thickness T, and the thickness monotonically increases from minimum thickness Tto maximum thickness Tat midpoint Mbetween source and drain bodiesA. In some embodiments, minimum thicknesses Tare in outer quarters of nanoribbons, e.g., between bodiesA and midpoints M, M(which may be equidistant between midpoint Mand bodiesA). In some such embodiments, minimum thicknesses Tare in outer tenths of nanoribbons(e.g., nearer bodiesA).

2 FIG. 2 FIG. 2 FIG. 2 FIG. 200 200 200 210 270 200 is a flow chart of methodsfor forming a nanoribbon with an element added to and interspersed in the nanoribbon lattice, in accordance with some embodiments. Methodsmay be utilized to add atoms of at least one element into a nanoribbon of another element while also retaining nanoribbons of the other element, e.g., for complementary applications. Methodsinclude operations-. Some operations shown inare optional. Additional operations may be included.shows an example sequence, but the operations can be done in other orders as well, and some operations may be omitted. Some operations can also be performed multiple times before other operations are performed. For example, multiple nanoribbons (and stacks of nanoribbons) may be formed and thinned before an additive element is deposited on the nanoribbons. Some operations may be included within other operations so that the number of operations illustratedis not a limitation of the methods.

3 4 5 6 7 8 9 FIGS.,,,,,, and 3 9 FIGS.- 2 FIG. 120 200 illustrate cross-sectional profile views of nanoribbonshaving an added element diffused into the crystal lattices, at various stages of manufacture, in accordance with some embodiments.show possible examples of intermediate structures during an embodiment of a practice of methodsof.

2 FIG. 200 210 Returning to, methodsbegin at operationwith forming or receiving a stack of material layers. The stack of material layers may be (or may be formed into) a stack of nanoribbons. The nanoribbons may each be more narrow than tall (e.g., nanowires) or much wider (e.g., nanosheets). In many embodiments, a stack of nanoribbons is formed by depositing alternating material layers in a stack, e.g., alternating layers of a crystalline (e.g., semiconducting) material and of a sacrificial material. The sacrificial material may be a semiconductor material. In some embodiments, the semiconducting and sacrificial materials share one or more constituent elements. For example, in some embodiments, the sacrificial material is silicon germanium, and the semiconducting material is pure (or predominantly) silicon (e.g., without germanium present). Any suitable materials may be employed, such as materials that may be semiconductors (e.g., enhanced) with the addition of one or more elements diffused into the crystalline lattice. Although the examples of silicon and germanium may be provided, the nanoribbons may be enhanced to include III-V materials, II-VI materials, and other semiconducting materials.

200 200 200 Methodsenable the use of preexisting processes (for example, leveraging existing infrastructure and proven, e.g., reliable, flows) to form nanoribbons (for example, without modifying a stack of material layers) before at least some nanoribbons are enhanced by the addition of an element. For example, silicon nanoribbons may be formed by a proven process, and some of the silicon nanoribbons may then be converted to silicon germanium nanoribbons, e.g., for NMOS and PMOS transistors, respectively. In many embodiments, silicon nanoribbons are fabricated using a conventional flow, and silicon germanium nanoribbons are fabricated using methodsto produce complementary transistors of the same size and with nanoribbon channels at same heights and with same pitches. Accordingly, benefits (e.g., flow and tool re-use) may be accrued from preserving a material stack (including layer thicknesses). However, the material stack (e.g., one or more layer thicknesses) may be altered from conventional flows as is necessary or convenient. In some embodiments, the thickness of a semiconductor material layer is reduced to standardize an eventual, resultant thickness of the enhanced semiconductor layer (e.g., nanoribbon) following a performance of methods. In some such embodiments, the semiconductor layer thickness is reduced in some regions of a received substrate and is not reduced in other regions.

200 210 Methods(e.g., processing or forming the stack of material layers at operation) may include cutting (e.g., etching) into nanoribbons by any suitable means, for example, photolithographic means. A wide-area stack of material layers may be separated by etches into multiple fins of layers (e.g., nanoribbons). Thin fins (e.g., from tightly spaced etches) may be formed into nanowires, and wide fins (e.g., from loosely spaced etches) may be formed into nanosheets. In many embodiments, sacrificial or dummy gates are deposited over fins of material layers, a spacer dielectric is conformally deposited over the fins and dummy gates, and the fins are cut into nanoribbon segments by etches between the spacer sidewalls on the dummy gates

3 FIG. 3 FIG. 100 122 121 320 210 121 121 200 121 121 122 320 121 121 122 122 121 121 122 320 122 121 199 320 122 122 199 320 1 2 1 2 3 illustrates workpiece or IC devicehaving material layers or nanoribbonsin alternating stackswith sacrificial material layers, in accordance with some embodiments, for example, following or during a performance of operation. StacksA,B are identical in the example of, but may be separately processed by methods. Identical stacksA,B include material layers or nanoribbonsand sacrificial material layers. In both stacksA,B, pitches Pare between layers or nanoribbons, which have thicknesses T. Layers or nanoribbonsin stacksA,B have coplanar centerlines CL at heights H, H, H. Material layers or nanoribbonshave a crystalline lattice, e.g., of silicon or another semiconductor material. Sacrificial layersinclude a material having an etch selectivity with layers or nanoribbons. In many embodiments, stacksare over a substrate(e.g., subfins) including a material having an etch selectivity with sacrificial layers, such as the material of layers or nanoribbons. In many embodiments, nanoribbons(and much of substrate) are pure silicon, and layersare silicon germanium. Any suitable material may be deployed.

200 210 Methods(e.g., processing or forming the stack of material layers at operation) may include further processing of the stack of layers or nanoribbons as necessary. A recess or dimple etch may remove exposed portions of the sacrificial layers between the crystalline (e.g., semiconductor) material layers, and another spacer dielectric may be deposited in the resultant cavities. Source and drain regions may be epitaxially grown from exposed ends of the nanoribbons (e.g., extending between the spacer dielectrics).

200 220 2 FIG. 1 1 FIGS.B andC Methodscontinue with optionally growing an interface layer on an end of a nanoribbon at operationof. The interface layer may serve as either or both of a nucleation layer for epitaxially growing source and drain bodies at ends of nanoribbon channels and a diffusion barrier for inhibiting diffusion between nanoribbon channels and source and drain bodies. In some embodiments, the interface layer is epitaxially grown on one or more ends of one or more nanoribbons. In some such embodiments, the source and drain bodies are epitaxially grown from the interface layers. Interface layers may be grown on both nanoribbons to be enhanced with a diffused element and nanoribbons to be retained without the added element. The interface layers and source and drain bodies may include any suitable materials (e.g., as described at least at). The interface layers and source and drain bodies may be grown by any suitable means, for example, epitaxially by an atomic layer deposition (ALD). Advantageously, the interface layers in particular are grown free of defects, which may aid in the inhibition of diffusion.

200 260 During methods(e.g., at operation), diffusion into and out of longitudinal nanoribbon surfaces may be promoted, for example, by a high-temperature anneal. However, diffusion (e.g., of dopants from the source and drain bodies) through the nanoribbon ends may be undesired. The interface layer may provide a diffusion barrier to prevent (or at least inhibit) diffusion between nanoribbon channels and source and drain bodies. The interface layer may have a high-quality lattice grown without dopants (or with a lower dopant concentration than the source and drain bodies) and without the element to be added to at least some nanoribbons (or with a lower concentration than is to be in the enhanced nanoribbons). For example, interface layers may be grown on ends of silicon nanoribbons in multiple stacks, some stacks to be enhanced with the addition of germanium and some stacks to be maintained as pure silicon. Doped-silicon source and drain bodies may be epitaxially grown from undoped silicon interface layers epitaxially grown from ends of maintained silicon nanoribbons. In the same embodiment (e.g., device or workpiece), doped-silicon germanium source and drain bodies may be epitaxially grown from undoped silicon germanium interface layers epitaxially grown from ends of to-be-enhanced silicon nanoribbons. The undoped silicon germanium interface layers may have a lower concentration of germanium than the silicon germanium source and drain bodies and a lower concentration of germanium than the eventual silicon germanium nanoribbons (e.g., those silicon nanoribbons that are coupled with the interface layers and that are to be enhanced with germanium).

200 Methodsmay include further processing, which may employ conventional (e.g., existing) processes. For example, the sacrificial layers may be removed from the stack of alternating material layers, e.g., following a covering with dielectric of epitaxial bodies in source-drain trenches between dummy gates. The dummy gates may be removed and the nanoribbons exposed by removal of the sacrificial layers between the nanoribbons and between spacer dielectrics.

4 FIG. 4 FIG. 100 121 122 122 210 220 122 122 200 122 illustrates workpiece or devicehaving stackswith released nanoribbons(e.g., with sacrificial material absent between nanoribbons), in accordance with some embodiments, for example, following a performance of operationsand/or. Nanoribbonsmay be coupled with source and drain epitaxial bodies, e.g., in front of and behind the viewing plane of, which may promote strain of enhanced nanoribbon lattices following the addition of a diffused element. The removal of sacrificial material and release of nanoribbonsprovides space for further operations of methodsand the growth (e.g., bulging) of lattices of selected nanoribbons.

200 122 122 122 122 121 122 121 122 121 Methodsmay add an element to some or all of layers or nanoribbons, e.g., to improve performance and reliability of nanoribbons. In some embodiments, an element (e.g., a semiconductor element) is diffused into some of layers or nanoribbonsfor a first type (e.g., n- or p-type) of transistors, and others of layers or nanoribbonsare retained for a second (e.g., complementary) type of transistors (e.g., in stackB). In some such embodiments, silicon nanoribbonsin stackA are converted into silicon germanium channels (e.g., in PMOS transistors), and silicon nanoribbonsin stackB are maintained as silicon channels (e.g., in NMOS transistors).

200 230 2 FIG. Methodscontinue with optionally thinning at least some of the nanoribbons at operationof. Nanoribbons to be enhanced with an added element will increase in size due to the addition and may be pre-thinned to control a final thickness. The nanoribbons may be thinned by any suitable means, e.g., by a selective plasma etch. In many embodiments, the nanoribbons are thinned by isotropically removing material from exposed surfaces of the nanoribbons. In some such embodiments, the nanoribbons are predominantly silicon, and (e.g., an outer layer of) silicon is removed isotropically from all exposed nanoribbon surfaces. In many embodiments, the nanoribbons to be enhanced are isotropically thinned, and the nanoribbons to be maintained (e.g., with an unchanged composition) are masked off or over to prevent undesired thinning. For example, stacks of nanoribbons to be remain unchanged may be masked off from adjacent stacks of nanoribbons to be enhanced.

240 200 260 200 The to-be-enhanced nanoribbons may be thinned to any suitable thickness. An additive element will be deposited in a material layer over a stack of nanoribbons (e.g., at operationof methods), and the added element will be diffused into the nanoribbon lattice (e.g., at operationof methods). The final concentration of the added element in an enhanced nanoribbon is influenced by a number of variables, such as the initial concentration of the added element in the initial nanoribbon (e.g., zero), the size (e.g., volume) of the initial nanoribbon, the initial concentration of the added element in the deposited material layer, and the size (e.g., thickness) of the deposited material layer. The final concentration of the added element can be increased by depositing a thicker material layer or a material layer with a higher concentration of the added element, but the final concentration of the added element in the enhanced nanoribbon is limited by the size of the initial nanoribbon. The smaller (e.g., thinner) the initial nanoribbon is, the more the final concentration of the added element in the enhanced nanoribbon can be influenced with the deposited material layer.

In some embodiments, the nanoribbons are thinned to approximately 2 nm (e.g., between 1.5 and 2.5 nm), which may enable higher final concentrations of an added element in enhanced nanoribbons, particularly thin nanoribbons. Thick final nanoribbons and final nanoribbons with lower allowed final concentrations of the added element may permit larger initial (thinned) thicknesses. Isotropic (e.g., balanced) removal of material from exposed surfaces (e.g., upper and lower surfaces) of the to-be-enhanced nanoribbons ensures that nanoribbon centerlines may be kept at same heights in enhanced and unchanged stacks.

5 FIG. 100 121 121 122 520 230 520 illustrates workpiece or devicehaving adjacent stacksB,A of standard and thinned nanoribbons,, in accordance with some embodiments, for example, following a performance of operation. Thinned nanoribbonsare prepared for further enhancement processing (such as the deposition and diffusion of an added, second element).

520 230 520 122 199 199 122 520 121 121 122 121 520 520 1 2 3 1A 2A 3A 1 2 3 1B 2B 3B Thinned nanoribbonsare at the same heights H, H, Has before thinning operation. Thinned nanoribbonsand centerlines CL, CL, CLare at same heights H, H, Has centerlines CL, CL, CLof standard nanoribbons. In some embodiments, material is isotropically removed from exposed surfaces of substrate(e.g., of subfins). In many embodiments, surfaces of substratebelow nanoribbons,are masked (e.g., not exposed). In many embodiments, stackB is covered by a mask material (not shown), e.g., to segregate stackB of nanoribbonsfrom stackA of nanoribbonsduring processing (such as thinning) of nanoribbons.

2 FIG. 200 240 200 200 Returning to, methodscontinue at operationwith depositing a material layer over a stack of nanoribbons. Any suitable material(s) may be deposited in one or more layers over the stack of nanoribbons, and any suitable means may be employed to deposit the layer(s). In many embodiments, the nanoribbons include a first element, and the deposited material layer includes a second element. Methodsmay add a second element (such as germanium) to nanoribbons entirely (i.e., purely) of a first element (such as silicon), but methodsmay also be used to add more of a second element (e.g., to increase a concentration of the second element) to nanoribbons of (at least) the first and second elements. The first and second elements may both be semiconductor elements (such as silicon and germanium), but, even though the compound or alloy formed by the first and second elements may be a semiconductor material, the first and second elements need not both be semiconductor elements. The deposited material layer may include elements besides the second element (e.g., to be added to the lattice of the first element). In many embodiments, the deposited material layer includes the first and second elements. For example, a material layer of silicon germanium may be deposited on nanoribbons of predominantly silicon.

In many embodiments, the material layer is deposited conformally over individual ones of the nanoribbons. In many embodiments, the material layer is deposited epitaxially, e.g., by an ALD, which allows for great control of the thickness of the deposited material layer, and so for great control of the final concentration of the added element in the enhanced nanoribbon. Epitaxial deposition by ALD may ensure a high-quality lattice is deposited on the nanoribbon, which may improve subsequent diffusion of the additive, second element into (and of the first element out of) the nanoribbon. Epitaxial deposition by ALD may also enable selective deposition of the additive, second element onto the nanoribbon.

230 200 As described elsewhere herein (e.g., at least at operationof methods), the final concentration of the added element can be increased by depositing a thicker material layer and/or a material layer with a higher concentration of the added element. When increasing the final (resultant) concentration of the added element by depositing a material layer, the final concentration of the added element is limited by (e.g., capped below) the concentration of the added element in the deposited material layer. While adding a thicker, higher-concentration layer may be desired to most-efficiently maximize a resultant concentration of the nanoribbon, a lattice mismatch between the nanoribbon and the deposited material layer may limit the thickness (and/or concentration) of the deposited material layer to below a critical thickness (e.g., to prevent dislocation defects). In many embodiments, the material layer is deposited over the stack of nanoribbons to a thickness of at least 1 nm, preferably to 1.5 nm or more, which may correspond to a sufficient concentration of the added element in the final nanoribbon.

Various constraints may impose deposited material layer thickness maximums. In many embodiments, the material layer is deposited over the stack of nanoribbons to a thickness of 3 nm or less, which may provide more of the added element while maintaining margin below a critical thickness to prevent dislocation defects. For embodiments having nanoribbons trimmed to approximate thicknesses of 2 nm, the material layer is deposited over the stack of nanoribbons to a thickness greater than or equal to half of a thickness of the nanoribbons and less than or equal to one-and-a-half times the thickness of the nanoribbons. While thicker (e.g., lower-concentration) material layers may be deposited, space may be limited between nanoribbons (e.g., for satisfactory deposition of both material layers and both subsequent retaining layers). Space between nanoribbons may also be limited by the need for space for eventual gate electrode materials. Limiting a deposited material layer thickness may also prevent the need for (and be less expensive than) thinning enhanced nanoribbons after fabrication.

In many embodiments, a material layer of silicon germanium is epitaxially and conformally deposited over initial nanoribbons of predominantly silicon. In many embodiments, the material layer is deposited over the stack of nanoribbons to an atomic composition including at least 20% germanium. Advantageously, an enhanced, silicon germanium nanoribbon has a germanium concentration of at least 20% (e.g., for increased strain and improved performance and reliability), so higher deposited concentrations may be preferred. In many embodiments, a material layer having a germanium concentration of 65% (or less) is deposited over silicon nanoribbons, which may provide more germanium (e.g., in less space) while maintaining margin below a critical thickness.

6 FIG. 100 620 121 520 240 620 520 121 122 620 1 2 3 illustrates a workpiece or IC devicehaving a material layerdeposited on and around stackA of thinned nanoribbons, in accordance with some embodiments, for example, following a performance of depositing operation. Material layerover nanoribbonsmay have faceted surfaces. StackB of conventional nanoribbonsis maintained, e.g., at heights H, H, Hand without material layer.

620 520 520 520 520 620 Material layershave a higher concentration than the eventual, resultant concentration of the eventual, resultant structures (e.g., enhanced nanoribbons) will be following an intermixing (e.g., diffusion) with the existing, thinned nanoribbons. As the concentration of nanoribbonsprior to diffusion of the second, added element into nanoribbonsmay be low (e.g., zero), the total bulk of a single nanoribbonand a corresponding material layermay have a greater thickness than the eventual, resultant structure (e.g., enhanced nanoribbon).

2 FIG. 200 250 Returning to, methodscontinue with encasing the nanoribbons and the material layer in a retaining layer at operation. The retaining layer may be any suitable material(s) and may encase the nanoribbons and material layer by any suitable means. The encapsulation of the retaining layer may be necessary to contain lattice materials during a high-temperature diffusion, e.g., lattice materials that might otherwise precipitate and agglomerate at an external nanoribbon surface. In some embodiments, the retaining layer is deposited to a thickness of 0.5 nm or more, which may be a sufficient thickness to retain the nanoribbon materials and the deposited material layer during diffusion. In some embodiments, the retaining layer is deposited to a thickness of 2 nm or less, which may be a sufficient thickness to ensure retention of the nanoribbon materials and the deposited material layer (e.g., even during a longer or higher-temperature diffusion), but to also provide sufficient clearance for material deposition and removal. In many embodiments, the nanoribbons and material layer are encased in the retaining layer by conformally depositing the retaining layer around each of the nanoribbons. In many embodiments, the retaining layer is epitaxially deposited (e.g., by ALD) as a high-quality, low-defect crystalline layer.

In many embodiments, the retaining layer is a dielectric layer. In many embodiments, the retaining layer is (or includes) an oxide or a nitride, which may provide lattice vacancies for assisting (e.g., enhancing) diffusion. In some embodiments, the retaining layer is deposited over a passivation layer (e.g., of a native oxide) is formed on the nanoribbons, which may also provide diffusion-assisting vacancies. The retaining layer may also enhance diffusion by providing compressive (or tensile) stress on the deposited material layer and nanoribbon. In some embodiments, the retaining layer is silicon nitride (e.g., an epitaxially and conformally deposited, high-quality, low-defect crystalline layer of silicon and nitrogen). A retaining layer of silicon nitride may advantageously provide both strain (e.g., from up to 3 GPa of compressive or tensile stress) and vacancies of oxygen and/or nitrogen for subsequent diffusion. Strain- and vacancy-assisted diffusion of the nanoribbon materials and the deposited material layer (e.g., while retained in a layer of silicon nitride) may enable a reduced diffusion temperature or duration, which may provide margin to thermal-budget requirements.

7 FIG. 100 720 520 620 250 720 620 720 520 620 720 520 illustrates a workpiece or IC devicehaving retaining layersconformally encasing thinned nanoribbonsand material layers, in accordance with some embodiments, for example, following a performance of encasing operation. Retaining layersare conformally on and around material layers. Layershave sufficient thickness to contain lattice materials of nanoribbonsand layerswhile still allowing for clearance between layers(around adjacent nanoribbons).

2 FIG. 200 260 250 Returning to, methodscontinue with diffusing the second element into the nanoribbons at operation. The second element may be an added element that diffuses into the nanoribbons from the deposited material layer. The first element in the nanoribbons concurrently diffuses from the nanoribbons into the deposited material layer such that the first and second elements intermix in the combined nanoribbon-deposited layer structure. The diffusion may be performed to a satisfactory mixing (e.g., a thorough evening out of the concentrations and elimination of any concentration gradient), for example, by diffusing for a sufficiently long duration, at a sufficiently high temperature, etc. For example, germanium may diffuse from a conformally deposited layer of silicon germanium into a silicon nanoribbon, and silicon may diffuse from the nanoribbon outward, until the silicon and germanium are thoroughly intermixed (e.g., into a thickened nanoribbon with no discernible border between the thinned nanoribbon and deposited layer). As described (at least at operation), strain and vacancies provided by the retaining layer may reduce a required diffusion temperature (e.g., to a few hundred degrees) and/or duration (e.g., to a few minutes or less than a minute) and provide margin to thermal-budget requirements.

220 200 112 1 1 FIGS.B andC As described (e.g., at operationof methodsand of layerat), an interface layer may inhibit undesired diffusion into a nanoribbon channel (e.g., from source and drain epi), which may affect or be affected by thermal-budget requirements. For example, after the second element is diffused into the nanoribbons, the interface layer has a concentration of the second element less than both a concentration of the second element in the source or drain body (e.g., epitaxially grown from the interface layer) and a concentration of the second element in the nanoribbons, which may provide a buffer to (and inhibit) diffusion through the nanoribbon ends.

The second, added element may be diffused into the nanoribbons by any suitable means, for example, a rapid thermal anneal (RTA), such as a plasma anneal at a low partial pressure of oxygen. Other convenient means may be employed.

8 FIG. 100 121 120 121 122 260 120 illustrates a workpiece or IC devicehaving stackA of enhanced nanoribbonsadjacent stackB of conventional nanoribbons, in accordance with some embodiments, for example, following a performance of diffusing operation. Enhanced nanoribbonsare larger than the initially thinned nanoribbons, but may have a smaller extent than with the deposited material layer, e.g., due to the diffusion.

720 720 Retaining layermay be degraded (e.g., less pure and with a defective lattice) following the diffusion. In many embodiments, layer(initially including a high-quality silicon nitride) has an irregular lattice of silicon, nitrogen, and germanium.

2 FIG. 200 270 Returning to, methodscontinue at operationwith removing some or all of the retaining layer around the nanoribbons. In many embodiments, removing the retaining layer provides space for a gate electrode (e.g., a higher-K gate dielectric and workfunction metals) between the nanoribbons. The retaining layer may be removed by any suitable means, e.g., a selective, dry etch.

In some embodiments, the enhanced nanoribbons are trimmed to a desired thickness. Advantageously, enhanced nanoribbons do not require a further trimming operation following diffusion.

9 FIG. 100 121 120 122 270 120 illustrates a workpiece or IC devicehaving adjacent stacksof enhanced and conventional nanoribbons,, respectively, in accordance with some embodiments, for example, following a performance of removing operation. The retaining layer is absent around nanoribbons.

120 121 122 122 121 122 120 122 1 1A 2A 3A 2 1 1B 2B 3B 1 1 2 3 Enhanced nanoribbonsin stackA have thickness Tat their midpoints (e.g., on centerlines CL, CL, CL) and include an added element relative to nanoribbons. Conventional nanoribbonsin stackB have a smaller thickness T(relative to thickness T) at their midpoints (e.g., on centerlines CL, CL, CL) and the added element is not present in nanoribbons. Nanoribbons,have a same pitch Pand are centered on the same heights H, H, H.

120 122 1 1 FIGS.A-E Further processing (such as conformal deposition of a gate dielectric layer and workfunction metal(s), etc.) may be performed to form transistor structures with nanoribbons,as channels (e.g., as described at least at).

10 FIG. 1006 1006 1050 illustrates a diagram of an example data server machineemploying an IC device having diffusion-enhanced nanoribbon channels, in accordance with some embodiments. Server machinemay be any commercial server, for example, including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes one or more deviceshaving diffusion-enhanced nanoribbon channels.

1006 1015 1050 1050 1010 1010 1020 1050 1050 1050 1050 1099 1030 1025 1035 1025 1030 1035 1050 Also as shown, server machineincludes a battery and/or power supplyto provide power to devices, and to provide, in some embodiments, power delivery functions such as power regulation. Devicesmay be deployed as part of a package-level integrated system. Integrated systemis further illustrated in the expanded view. In the exemplary embodiment, devices(labeled “Memory/Processor”) includes at least one memory chip (e.g., random-access memory (RAM)), and/or at least one processor chip (e.g., a microprocessor, a multi-core microprocessor, or graphics processor, or the like) having the characteristics discussed herein. In an embodiment, deviceis a microprocessor including a static RAM (SRAM) cache memory. As shown, devicemay be an IC device having diffusion-enhanced nanoribbon channels, as discussed herein. Devicemay be further coupled to (e.g., communicatively coupled to) a board, an interposer, or a substratealong with, one or more of a power management IC (PMIC), RF (wireless) IC (RFIC)including a wideband RF (wireless) transmitter and/or receiver (TX/RX) (e.g., including a digital baseband and an analog front end module further includes a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controllerthereof. In some embodiments, RFIC, PMIC, controller, and deviceinclude having diffusion-enhanced nanoribbon channels.

11 FIG. 11 FIG. 11 FIG. 1100 1100 1100 1100 1100 1100 1100 1103 1103 1100 1104 1105 1109 1110 1111 1104 1105 1109 1110 1111 is a block diagram of an example computing device, in accordance with some embodiments. For example, one or more components of computing devicemay include any of the devices or structures discussed herein. A number of components are illustrated inas being included in computing device, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in computing devicemay be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, computing devicemay not include one or more of the components illustrated in, but computing devicemay include interface circuitry for coupling to the one or more components. For example, computing devicemay not include a display device, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which display devicemay be coupled. In another set of examples, computing devicemay not include an audio output device, other output device, global positioning system (GPS) device, audio input device, or other input device, but may include audio output device interface circuitry, other output device interface circuitry, GPS device interface circuitry, audio input device interface circuitry, audio input device interface circuitry, to which audio output device, other output device, GPS device, audio input device, or other input devicemay be coupled.

1100 1101 1101 1121 1122 1123 1124 1125 1126 1127 1128 Computing devicemay include a processing device(e.g., one or more processing devices). As used herein, the term “processing device” or “processor” indicates a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Processing devicemay include a memory, a communication device, a refrigeration device, a battery/power regulation device, logic, interconnects(i.e., optionally including redistribution layers (RDL) or metal-insulator-metal (MIM) devices), a heat regulation device, and a hardware security device.

1101 Processing devicemay include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

1100 1102 1102 1101 Computing devicemay include a memory, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random-access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, memoryincludes memory that shares a die with processing device. This memory may be used as cache memory and may include embedded dynamic random-access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

1100 1106 1106 1101 1100 Computing devicemay include a heat regulation/refrigeration device. Heat regulation/refrigeration devicemay maintain processing device(and/or other components of computing device) at a predetermined low temperature during operation.

1100 1107 1107 1100 In some embodiments, computing devicemay include a communication chip(e.g., one or more communication chips). For example, the communication chipmay be configured for managing wireless communications for the transfer of data to and from computing device. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

1107 1107 1107 1107 1107 1100 1113 Communication chipmay implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. Communication chipmay operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. Communication chipmay operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication chipmay operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Communication chipmay operate in accordance with other wireless protocols in other embodiments. Computing devicemay include an antennato facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

1107 1107 1107 1107 1107 1107 In some embodiments, communication chipmay manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, communication chipmay include multiple communication chips. For instance, a first communication chipmay be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chipmay be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chipmay be dedicated to wireless communications, and a second communication chipmay be dedicated to wired communications.

1100 1108 1108 1100 1100 Computing devicemay include battery/power circuitry. Battery/power circuitrymay include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of computing deviceto an energy source separate from computing device(e.g., AC line power).

1100 1103 1103 Computing devicemay include a display device(or corresponding interface circuitry, as discussed above). Display devicemay include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

1100 1104 1104 Computing devicemay include an audio output device(or corresponding interface circuitry, as discussed above). Audio output devicemay include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

1100 1110 1110 Computing devicemay include an audio input device(or corresponding interface circuitry, as discussed above). Audio input devicemay include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

1100 1109 1109 1100 Computing devicemay include a GPS device(or corresponding interface circuitry, as discussed above). GPS devicemay be in communication with a satellite-based system and may receive a location of computing device, as known in the art.

1100 1105 1105 Computing devicemay include other output device(or corresponding interface circuitry, as discussed above). Examples of the other output devicemay include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

1100 1111 1111 Computing devicemay include other input device(or corresponding interface circuitry, as discussed above). Examples of the other input devicemay include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

1100 1112 1112 1100 Computing devicemay include a security interface device. Security interface devicemay include any device that provides security measures for computing devicesuch as intrusion detection, biometric validation, security encode or decode, access list management, malware detection, or spyware detection.

1100 Computing device, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

1 11 FIGS.A- The subject matter of the present description is not necessarily limited to specific applications illustrated in. The subject matter may be applied to other deposition applications, as well as any appropriate manufacturing application, as will be understood to those skilled in the art.

The following examples pertain to further embodiments, and specifics in the examples may be used anywhere in one or more embodiments.

In one or more first embodiments, an apparatus includes a source body and a drain body in a transistor structure, and a stack of nanoribbons coupling the source body with the drain body, wherein a first of the nanoribbons has a first thickness at a midpoint between the source body and the drain body, and has a second thickness at an intervening point between the midpoint and one of the source body or the drain body, and the first thickness is at least 5% greater than the second thickness.

In one or more second embodiments, further to the first embodiments, the transistor structure is a first transistor structure, the source and drain bodies are first source and drain bodies, the stack of nanoribbons is a first stack of first nanoribbons, and the apparatus also includes second source and drain bodies in a second transistor structure, a second stack of second nanoribbons between and coupling the second source and drain bodies, wherein a first thickness variation in the first of the first nanoribbons is greater than a second thickness variation in the first of the second nanoribbons, the first nanoribbons include a first semiconductor element, the second nanoribbons include a second semiconductor element, and the first semiconductor element is absent in the second nanoribbons.

In one or more third embodiments, further to the first or second embodiments, the first thickness variation is ten times or more than the second thickness variation.

In one or more fourth embodiments, further to the first through third embodiments, a first centerline through the first of the first nanoribbons is coplanar with a second centerline through the first of the second nanoribbons, the first nanoribbons have a first pitch, and the second nanoribbons have the first pitch.

In one or more fifth embodiments, further to the first through fourth embodiments, the first nanoribbons include silicon and germanium, and the second nanoribbons consist essentially of silicon.

In one or more sixth embodiments, further to the first through fifth embodiments, a surface of the first of the nanoribbons over the midpoint has a first concentration of germanium, the first of the nanoribbons has a second concentration of germanium on a centerline at the midpoint, and the first concentration of germanium is within 5% of the second concentration of germanium.

In one or more seventh embodiments, further to the first through sixth embodiments, a first concentration of germanium adjacent an interface between the first of the first nanoribbons is less than a second concentration of germanium in one of the first source or drain bodies and less than a third concentration of germanium in the first of the first nanoribbons.

In one or more eighth embodiments, further to the first through seventh embodiments, the midpoint is a first midpoint, the first of the second nanoribbons has a third thickness at a second midpoint between the second source and drain bodies, and the first thickness is at least 5% greater than the third thickness.

In one or more ninth embodiments, further to the first through eighth embodiments, the first of the nanoribbons includes a first atomic composition at the midpoint, the first of the nanoribbons includes a second atomic composition at the intervening point, and the first and second atomic compositions are approximately equal.

In one or more tenth embodiments, an apparatus includes a first transistor structure, including a first stack of first nanoribbons between and coupling first source and drain bodies, wherein a first thickness of a first of the first nanoribbons is at least 3% greater than a second thickness of the first of the first nanoribbons, the first thickness at a midpoint between the first source and drain bodies, and a second transistor structure, including a second stack of second nanoribbons between and coupling second source and drain bodies, wherein a maximum thickness of a first of the second nanoribbons is not more than 1% more than a minimum thickness of the first of the second nanoribbons.

In one or more eleventh embodiments, further to the tenth embodiments, the first and second nanoribbons include silicon, the first nanoribbons include germanium, and germanium is absent in the second nanoribbons.

In one or more twelfth embodiments, further to the tenth or eleventh embodiments, the first of the first nanoribbons and the first of the second nanoribbons are coplanar, the first stack includes a first pitch between the first nanoribbons, and the second stack includes the first pitch between the second nanoribbons.

In one or more thirteenth embodiments, further to the tenth through twelfth embodiments, the first of the first nanoribbons has a first germanium concentration on a centerline at the midpoint, the first of the first nanoribbons has a second germanium concentration on a surface over the midpoint, and the first germanium concentration is within 5% of the second germanium concentration.

In one or more fourteenth embodiments, a method includes depositing a material layer over a stack of nanoribbons, wherein the nanoribbons are between and coupling source and drain bodies, the nanoribbons include a first element, and the material layer includes a second element, encasing the nanoribbons and the material layer in a retaining layer, and diffusing the second element into the nanoribbons.

In one or more fifteenth embodiments, further to the fourteenth embodiments, also including thinning the nanoribbons to a thickness of approximately 2 nm by isotropically etching the nanoribbons.

In one or more sixteenth embodiments, further to the fourteenth or fifteenth embodiments, the depositing the material layer over the stack of nanoribbons includes epitaxially depositing at least the second element over individual ones of the nanoribbons.

In one or more seventeenth embodiments, further to the fourteenth through sixteenth embodiments, the depositing the material layer over the stack of nanoribbons includes depositing the first and second elements to between half a thickness of the nanoribbons and one-and-a-half times the thickness of the nanoribbons.

In one or more eighteenth embodiments, further to the fourteenth through seventeenth embodiments, the encasing the nanoribbons and the material layer in the retaining layer includes conformally depositing silicon and nitrogen around each of the nanoribbons.

In one or more nineteenth embodiments, further to the fourteenth through eighteenth embodiments, the encasing the nanoribbons and the material layer in the retaining layer conformally deposits the retaining layer to a first thickness of at least 0.5 nm and not more than a second thickness of the nanoribbons.

In one or more twentieth embodiments, further to the fourteenth through nineteenth embodiments, also including growing an interface layer on an end of a first of the nanoribbons, and epitaxially growing the source body or the drain body from the interface layer, wherein after the diffusing the second element into the nanoribbons the interface layer has a first concentration of the second element less than a second concentration of the second element in the source or drain body epitaxially grown from the interface layer and less than a third concentration of the second element in the first of the nanoribbons.

The disclosure can be practiced with modification and alteration, and the scope of the appended claims is not limited to the embodiments so described. For example, the above embodiments may include specific combinations of features. However, the above embodiments are not limiting in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the patent rights should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.