Electronic Structure, Electronic Package and Manufacturing Method Thereof

The present application is based upon and claims the right of priority to TW patent application Ser. No. 11/312,5350, filed Jul. 5, 2024, the disclosure of which is hereby incorporated by reference herein in its entirety for all purposes.

The present disclosure relates to an electronic packaging technology, and more particularly, to an electronic structure, an electronic package and a manufacturing method thereof.

1 FIG.A 1 FIG.D toare schematic cross-sectional views illustrating a manufacturing method of a conventional semiconductor package.

1 FIG.A 16 19 19 16 First, as shown in, a carrierand a package structureare provided, and a lower side of the package structureis disposed on an upper side of the carrier.

161 16 19 161 In detail, a bonding layeris formed as a sacrificial release layer on the upper side of the carrierby coating. The package structureis disposed on the bonding layer.

19 111 12 121 123 124 112 113 13 14 142 143 144 13 131 132 131 The package structureincludes a first insulating layer, at least one first semiconductor chip, an adhesive layer, conductive components, a second insulating layer, conductive pillars, a first encapsulant, a redistribution layer, a second semiconductor chip, first conductive bumps, an underfill, and a second encapsulant. The redistribution layerincludes an insulating layerand a circuit layerbonded to the insulating layer.

122 12 123 122 124 12 123 12 111 121 112 12 113 112 12 121 124 13 12 123 124 112 113 A plurality of electrode padsare disposed on an active surface at an upper side of the first semiconductor chip. The plurality of conductive componentsare coupled to the plurality of electrode pads. The second insulating layeris formed on the active surface of each first semiconductor chipand is located around the plurality of conductive components. An inactive surface at a lower side of the first semiconductor chipis bonded to the first insulating layervia the adhesive layer. A plurality of conductive pillarsare disposed around the first semiconductor chip. The first encapsulantcovers the plurality of conductive pillars, the first semiconductor chip, the adhesive layerand the second insulating layer. The redistribution layeris formed on the upper sides of the first semiconductor chip, the plurality of conductive components, the second insulating layer, the plurality of conductive pillarsand the first encapsulant.

14 141 142 14 13 141 142 143 142 144 13 14 143 The second semiconductor chiphas an inactive surface at an upper side and an active surface at a lower side, and the active surface has a plurality of electrode padsto be bonded to a plurality of first conductive bumps. The second semiconductor chipis flip-chip bonded to an upper side of the redistribution layervia the electrode padsand the first conductive bumps. The underfillcovers the plurality of first conductive bumps. The second encapsulantis disposed on the upper side of the redistribution layerand covers the second semiconductor chipand the underfill.

1 FIG.B 16 161 19 151 152 19 As shown in, the carrierand the bonding layerare removed, the package structureis flipped, and then an under bump metallurgy (UBM) layerand a plurality of second conductive bumpsare formed on an upper side of the package structure.

1 FIG.C 19 144 14 14 As shown in, the package structureis ground to remove part of the second encapsulantand the second semiconductor chip, and to expose the second semiconductor chip.

1 1 19 19 1 100 1 FIG.A 1 FIG.C 1 FIG.A 1 FIG.C 1 FIG.A 1 FIG.C 1 FIG.D The conventional semiconductor structureshown intois a large-layout semiconductor structure. In other words, the semiconductor structureincludes a plurality of package structures, and the manufacturing method shown intois a method in which the plurality of package structuresare manufactured simultaneously. After the manufacturing method shown into, the large-layout semiconductor structurecan be cut into a plurality of individual semiconductor packages, as shown in.

100 16 152 However, in the application of a central processing unit (CPU) of a thin notebook computer, its height limitation limits the conventional semiconductor packageto an extremely thin thickness, wherein a large amount of warpage is likely to occur after the carrieris removed, thereby resulting in difficulties in subsequent formation and grinding operations of the second conductive bumps.

Therefore, how to avoid the deficiencies of the prior art has become an urgent issue to be solved.

In view of the various deficiencies of the prior art, the present disclosure provides an electronic structure, which comprises: a package module defined with a wiring section and a component section disposed on the wiring section, wherein the wiring section has a first side and a second side opposite to the first side and includes a first electronic component and a redistribution layer, wherein the component section has a first side and a second side opposite to the first side and includes a second electronic component, and the second side of the component section is disposed on the first side of the wiring section, and wherein, at the same time, the redistribution layer is electrically connected to the first electronic component and the second electronic component; and a component-side carrier having a first side and a second side opposite to the first side, wherein the second side of the component-side carrier is disposed on the first side of the component section.

The present disclosure further provides an electronic package, which comprises: a package module defined with a wiring section and a component section disposed on the wiring section, wherein the wiring section has a first side and a second side opposite to the first side and includes a first electronic component and a redistribution layer, wherein the component section has a first side and a second side opposite to the first side and includes a second electronic component, and the second side of the component section is disposed on the first side of the wiring section, and wherein, at the same time, the redistribution layer is electrically connected to the first electronic component and the second electronic component; conductive bumps disposed on the second side of the wiring section; and an adhesive layer formed on the second side of the wiring section to cover the conductive bumps.

The present disclosure also provides a method for manufacturing an electronic package, which comprises: providing a wiring-side carrier and a package module, wherein the package module is defined a wiring section and a component section, each of the wiring-side carrier, the wiring section, and the component section has a first side and a second side opposite to the first side, and the second side of the component section is disposed on the first side of the wiring section; disposing the package module on the first side of the wiring-side carrier via the second side of the wiring section; and disposing a component-side carrier having a first side and a second side opposite to the first side on the first side of the component section via the second side of the component-side carrier.

In the present disclosure, a carrier and an adhesive layer are used to support or fix the electronic structure and the electronic package, and double carriers are used to support or fix the electronic structure and the electronic package, thereby avoiding the warpage problem of the electronic structure and the electronic package.

The following describes the implementation of the present disclosure with examples. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification.

2 FIG.A 2 FIG.E toare schematic cross-sectional views illustrating a manufacturing method of an electronic package according to a first embodiment of the present disclosure.

2 FIG.A 26 29 29 291 292 292 291 292 291 First, as shown in, a wiring-side carrierand a package moduleare provided, wherein the package moduleis defined with a wiring sectionand a component section, the component sectionis disposed on the wiring section, and a thickness of the component sectionis greater than that of the wiring section.

2 FIG.A 2 FIG.E 2 FIG.A 2 FIG.C 2 FIG.D 2 FIG.E 2 FIG.A 2 FIG.C 2 FIG.D 2 FIG.E 29 291 292 26 292 291 29 26 291 All elements into, such as the package module, the wiring section, the component section, the wiring-side carrier, and other elements, all have a first side and a second side opposite to the first side. The first side refers to the upper side intoand the lower side inand. Correspondingly, the second side refers to the lower side intoand the upper side inand. The second side of the component sectionis disposed on the first side of the wiring section, and the entire package moduleis disposed on the first side of the wiring-side carriervia the second side of the wiring section.

261 26 261 29 261 291 In detail, a wiring-side bonding layerhaving a release film or other adhesive film is formed on the first side of the wiring-side carrierby, for example, coating, wherein the wiring-side bonding layerserves as a sacrificial release layer. The package moduleis disposed on the first side of the wiring-side bonding layervia the second side of the wiring section.

291 29 211 22 22 221 223 224 212 213 23 2 2 FIGS.A-E The wiring sectionof the package moduleincludes a first insulating layer, at least one first electronic component(e.g., two first electronic componentsshown in), an adhesive material, a plurality of conductive components, a second insulating layer, a plurality of conductive pillars, a first packaging layer, and a redistribution layer.

211 The first insulating layermay be made of polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

22 Each first electronic componentmay be an active component, a passive component or a combination thereof, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.

223 224 The conductive componentcan be made of copper or other conductive materials, and the second insulating layermay be made of polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

212 The conductive pillarsmay be made of copper or other conductive materials.

213 213 The first coating layeris made of an insulating material, such as polyimide (PI), epoxy resin (epoxy) encapsulant or encapsulating material. The first packaging layercan be formed by molding, lamination or coating.

23 231 232 231 232 231 The redistribution layerincludes at least one insulating layerand at least one circuit layerbonded to the insulating layer. The circuit layercan be made of copper or other conductive materials, and the insulating layermay be made of polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

222 22 223 222 224 22 223 22 211 221 212 211 22 213 212 22 221 224 23 22 223 224 212 213 A plurality of electrode padsare disposed on the active surface at the first side of each first electronic component. The plurality of conductive componentsare bonded to the plurality of electrode pads. The second insulating layeris formed on the active surface of each first electronic componentand is formed around the conductive components. The inactive surface on the second side of each first electronic componentis bonded to the first side of the first insulating layervia the adhesive material. The conductive pillarsare disposed on the first side of the first insulating layerand around the first electronic component. The first packaging layercovers the conductive pillars, the first electronic component, the adhesive materialand the second insulating layer. The redistribution layeris formed on the first sides of the first electronic component, the conductive components, the second insulating layer, the conductive pillarsand the first packaging layer.

292 29 24 242 243 244 243 242 244 23 24 243 The component sectionof the package moduleincludes at least one second electronic component, a plurality of first conductive bumps, an underfill, and a second packaging layer. The underfillcovers the first conductive bumps. The second packaging layeris formed on the first side of the redistribution layerand covers the second electronic componentand the underfill.

24 24 241 242 The second electronic componentcan be an active component, a passive component, or a combination thereof, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. The second electronic componenthas an inactive surface on a first side and an active surface on a second side. The active surface has a plurality of electrode padsto be bonded to a plurality of first conductive bumps.

242 24 23 241 24 242 232 23 243 242 Each of the first conductive bumpsmay be formed of solder material or a conductive metal material. The second electronic componentis bonded to the first side of the redistribution layervia the electrode padson the active surface of the second electronic componentand the first conductive bumpsin a flip-chip manner, so as to be electrically connected to the circuit layerof the redistribution layer. For example, the underfillcan be used to cover the plurality of first conductive bumps.

244 244 The second packaging layeris made of an insulating material, such as polyimide (PI), epoxy resin (epoxy) encapsulant or encapsulating material. The second packaging layercan also be formed by molding, lamination or coating.

212 232 23 232 23 22 223 222 22 232 23 24 242 241 24 212 22 24 The conductive pillarsare electrically connected to the circuit layerof the redistribution layer. The circuit layerof the redistribution layeris electrically connected to each of the first electronic componentsvia the conductive componentsand the electrode padsof the first electronic component. In addition, the circuit layerof the redistribution layeris electrically connected to the second electronic componentvia the first conductive bumpsand the electrode padsof the second electronic component. Thereby, the conductive pillarsare electrically connected to the first electronic componentand the second electronic component.

2 FIG.B 29 244 24 24 As shown in, an upper end of the package moduleis ground to remove part of the second packaging layerand the second electronic component, and to expose the second electronic component.

2 FIG.C 27 27 292 27 29 As shown in, a component-side carrieris provided, and the second side of the component-side carrieris disposed on the first side of the component section. At this time, an external force must be applied to bond the component-side carrierto the package module.

271 27 271 29 271 292 26 27 In detail, a component-side bonding layerhaving a release film or other adhesive film is formed on the second side of the component-side carrierby, for example, coating, wherein the component-side bonding layerserves as a sacrificial release layer. The package moduleis disposed on the second side of the component-side bonding layervia the first side of the component section, so as to be sandwiched between the wiring-side carrierand the component-side carrier.

2 FIG.D 26 261 251 252 291 251 211 As shown in, the wiring-side carrierand the wiring-side bonding layerare removed, and then an under bump metallurgy (UBM) layerand a plurality of second conductive bumpsare formed on the second side of the wiring section. The UBM layermay be partially formed in the first insulating layer.

251 252 The UBM layercan be made of conductive metal material. Each of the second conductive bumpsmay be formed of solder material or a conductive metal material.

252 212 251 252 22 24 The second conductive bumpsare electrically connected to the conductive pillarsvia the UBM layer. Thereby, the second conductive bumpsare electrically connected to the first electronic componentand the second electronic component.

2 FIG.E 27 271 As shown in, the component-side carrierand the component-side bonding layerare removed.

2 2 29 29 2 200 2 FIG.A 2 FIG.D 2 FIG.A 2 FIG.D The electronic structureshown intois a large-layout electronic structure. In other words, the electronic structureincludes a plurality of package modules, and the manufacturing method shown intois a manufacturing method in which the plurality of package modulesare processed simultaneously. Therefore, at this stage, the large-layout electronic structurecan be cut into a plurality of individual electronic packages.

3 FIG.A 3 FIG.B andare schematic cross-sectional views illustrating a manufacturing method of an electronic package according to a second embodiment the present disclosure.

2 FIG.A 2 FIG.D 3 FIG.A 28 291 28 252 First, continuing the manufacturing method shown into, as shown in, an adhesive layeris formed on the second side of the wiring section, so that the adhesive layercovers the second conductive bumps.

3 FIG.B 27 271 Next, as shown in, the component-side carrierand the component-side bonding layerare removed.

3 3 300 3 FIG.A The electronic structureshown inis also a large-layout electronic structure. Therefore, at this stage, the large-layout electronic structurecan be cut into a plurality of individual electronic packages.

2 3 26 26 27 200 300 28 27 200 300 2 FIG.B Via process optimization, the electronic structuresandof the present disclosure still have the wiring-side carrierwhen grinding as shown in. Via the fixing effect of the wiring-side carrier, the occurrence of warpage can be reduced. Furthermore, by disposing the component-side carrierafter grinding, the warpage of the electronic packagesandcan be further reduced. In addition, the provision of the adhesive layercan avoid the warping problem caused when the component-side carrieris removed. Therefore, the electronic packagesandof the present disclosure are not warp significantly, which is helpful for wafer handling and manufacturing operations.

The foregoing embodiments are provided for the purpose of illustrating the principles and effects of the present disclosure, rather than limiting the present disclosure. Anyone skilled in the art can modify and alter the above embodiments without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection with regard to the present disclosure should be as defined in the accompanying claims listed below.