Dynamic Clamping for Power-Stage Ground-Bounce Protection in 1L Modulation

This nonprovisional application is a continuation of U.S. Patent Application No. 63/666,730, filed Jul. 2, 2024, which is hereby incorporated by reference in its entirety.

An electronic device may include high speed electronic components having high frequency switching events and low speed electronic components that do not have high frequency switching events or otherwise operate at a lower frequency. Switching noise may be coupled from the high speed electronic components to the low speed electronic components, and the switching noise may adversely affect the operation of the low speed electronic components.

In one example, an apparatus comprises a transistor, a switch, and a control circuit. The transistor has a first current terminal, a second current terminal, and a transistor control terminal. The switch is coupled between the transistor control terminal and a reference terminal, the switch having a switch control input. The control circuit has a control input and a control output, the control output coupled to the switch control input, and the control input coupled to at least one of the transistor control terminal, the first current terminal, or the second current terminal.

In one example, an apparatus comprises an amplifier, a first power stage, a second power stage, a modulator, and a clamp circuit. The amplifier has an amplifier input and an amplifier output. The first power stage has a first power stage input and a first power stage output, the first power stage input coupled to the amplifier output. The clamp circuit is coupled between the first power stage input and a reference terminal, the clamp circuit having a clamp control input coupled to the first power stage. The modulator has a modulator input and a modulator output, the modulator input coupled to the amplifier input. The second power stage has a second power stage input and a second power stage output, the second power stage input coupled to the modulator output;

1 FIG.A 100 100 102 104 102 106 102 illustrates an example audio system. As shown, systemincludes a first amplifier (labelled amplifier A) and a second amplifier (labelled amplifier B) driving speaker. Amplifier A can be coupled to terminalof speaker, and amplifier B can be coupled to terminalof speaker. Amplifiers A and B can be of different types with different control schemes. For example, amplifier A can be of a non-switching type, and amplifier B can be of a switching type.

A switching amplifier includes a power stage that generates a multilevel signal (e.g., a binary signal, a trilevel signal, etc.) by selectively connecting the power stage output to one of multiple voltage sources. In some examples, a switching amplifier may operate as a class D amplifier. The switching amplifier may be driven by a modulating circuit that receives a sinusoidal audio signal and generates pulse width modulated (PWM) signals, pulse density signals, and/or any other type of modulated control signals to control the power stage to also generate a modulated signal having discrete signal levels (e.g., binary, ternary, etc.). The modulated signal provided by the power stage can have a timing property, such as duty cycle, pulse width, etc., modulated/varied to reflect an instantaneous amplitude of the audio signal. The modulated signal generated by the power stage can be filtered (e.g., by a low pass filter, or by the inductance of a speaker) to generate an amplified version of the sinusoidal audio signal, and the amplified sinusoidal audio signal can be fed to the speaker. The low pass filter may include an LC filter including a series inductor coupled between the output of the switching amplifier and the speaker, and a shunt capacitor coupled between the speaker and the ground. The low pass filter may also include a capacitor coupled across terminals of the speaker.

A non-switching amplifier may include another power stage driven by a control circuit including a linear amplifier. The control circuit can receive a sinusoidal audio signal, and provide control signals having magnitudes that varies (e.g., linearly or closed to be linearly) according to an instantaneous magnitude of the audio signal to the non-switching amplifier. Responsive to the control signals, the non-switching amplifier can also generate an analog signal having a magnitude that can track the audio signal when the non-switching amplifier operates in a linear mode where the analog signal voltage level is below the supply voltage of the power stage. In a case where the analog signal voltage level is above the supply voltage, the non-switching amplifier may operate in a saturation mode where the analog signal is clipped and limited at the supply voltage. In some examples, the non-switching amplifier may operate as a class A amplifier, a class B amplifier, a class AB amplifier, etc. The output of the non-switching amplifier can also be filtered (e.g., by another low pass filter) to attenuate high frequency components (e.g., noise) and distortions caused by, for example, saturation/clipping, non-linear effects such as distortions at conduction angle hand-over, etc. But because the signal output by the non-switching amplifier is in analog and continuous form, the low pass filter can have fewer components. For example, instead of an LC filter, an audio system can include a capacitor at the non-switching amplifier output to perform the filtering.

1 FIG.B 1 FIG.A 1 FIG.B 1 FIG.A 1 FIG.A 1 FIG.A 100 100 1 108 2 110 1 2 108 110 112 104 106 112 102 illustrates examples of internal components of systemof. The systemofincludes a first power stage PShaving a first output terminal, and a second power stage PShaving a second output terminal. First power stage PScan represent (or can be part of) amplifier A of, and second power stage PScan represent (or can be part of) amplifier B of. The first output terminaland the second output terminalare coupled to a LC filter circuit. Two speaker terminalsand(also described with respect to) of the LC filter circuitare coupled to the speaker.

1 1 2 116 1 116 1 108 2 108 2 a a Power stage PScomprises a first transistor Sand a second transistor Scoupled in series between a power terminal(e.g., receiving a power supply PVDD) and a ground terminal. For example, a first current terminal of the transistor Sis coupled to the power terminal, and a second current terminal of the transistor Sis coupled to the output terminal. A first current terminal of the transistor Sis coupled to the output terminal, and a second current terminal of the transistor Sis coupled to the ground terminal.

1 1 1 2 2 2 1 2 108 1 1 2 1 1 2 1 2 1 1 1 2 2 2 1 1 FIG.B The transistor Sfurther includes a control terminal coupled to a first power stage input that receives a control signal CSfrom a driver D, and the transistor Sincludes a control terminal coupled to a second power stage input that receives a control signal CSfrom another driver D. The transistors Sand Scan set the VN voltage at output terminalof power stage PSresponsive to control signals CSand CS. In, power stage PScan be controlled as a non-switching amplifier (e.g., class AB, class A, etc.), where CSand CScan each have a magnitude that varies (e.g., linearly or closed to be linearly) according to an instantaneous magnitude of an audio signal. For example, during a first half cycle of an audio signal, the transistor Sis on or enabled, the transistor Sis off or disabled, the transistor Scan vary a magnitude of the VN voltage based on a magnitude of CS, which can reflect/track an instantaneous magnitude of the audio signal (if operating in linear mode) during the first half cycle. Also, during a second half cycle of the audio signal, the transistor Sis off or disabled, the transistor Sis on or enabled, and the transistor Scan vary a magnitude of the VN voltage based on a magnitude of CS, which can also reflect/track an instantaneous magnitude of the audio signal during the second half cycle (if operating in linear mode). In a case where the audio signal is a sinusoidal signal, the VN voltage can be (or close to be) an amplified version of the sinusoidal signal, and the VN voltage can have a same frequency as the audio signal. On the other hand, the audio signal may also saturate power stage PS, in which case the VN voltage may be clipped at the PVDD voltage or at the ground voltage.

2 3 4 116 116 116 1 2 116 116 116 116 b a b a b a b Also, power stage PScomprises a third transistor Sand a fourth transistor Scoupled in series between a power terminal(e.g., receiving a power supply PVDD) and a ground terminal. In an example, the power terminalsandmay be a same power terminal shared by both the power stages PSand PS(or the power terminalsandmay be coupled to a common power terminal), whereas in another example the power terminalsandcan be coupled to different voltage sources.

3 116 3 110 4 110 4 b As illustrated, a first current terminal of the transistor Sis coupled to the power terminal, and a second current terminal of the transistor Sis coupled to the output terminalhaving a voltage of VY. A first current terminal of the transistor Sis coupled to the output terminal, and a second current terminal of the transistor Sis coupled to the ground terminal.

3 3 3 4 4 4 3 4 110 2 3 4 The transistor Sfurther includes a control terminal coupled to a third power stage input that receives a control signal CSfrom a driver D, and the transistor Sfurther includes a control terminal coupled to a fourth power stage input that receives a control signal CSfrom another driver D. The transistors Sand Scan set the voltage VY at output terminalof power stage PSresponsive to control signals CSand CS.

1 FIG.B 2 3 4 3 4 116 110 3 4 2 3 4 110 4 110 108 b In, power stage PScan be controlled as a switching amplifier (e.g., class D), where control signals CSand CSare pulse width modulated signals, pulse density signals, and/or any other type of modulated control signals having binary magnitudes. Depending on the magnitude of the audio signal, one of transistors Sor Scan be turned on to connect one of power terminalor ground terminal to output terminal. Responsive to CSand CS, power stages PScan also generate a modulated signal. The modulated signal provided by the power stage can have a timing property, such as duty cycle, pulse width, etc., modulated/varied to reflect an instantaneous magnitude of the audio signal. The transistors Sand Scan provide VY as a modulated signal at output terminalresponsive to CS. The modulated signal VY at output terminalcan have a much higher frequency than the audio signal as well as the signal VN at output terminal.

1 FIG.B 1 2 3 4 1 2 3 4 In, the transistors S, S, S, and Sare illustrated as n-channel metal oxide semiconductor (NMOS) field effect transistors (FETs). In other examples, the transistors S, S, S, and Scan be other types of transistors, such as p-channel MOSFET (PMOS), laterally-diffused metal-oxide semiconductor (LDMOS) FETs, Gallium Nitride (GaN) FETs, NPN or PNP bipolar junction transistor (BJT), etc.

112 1 110 106 1 104 106 2 104 1 1 110 106 102 2 2 2 The LC filter circuitincludes an inductor Lcoupled between the output terminaland the speaker terminal, a capacitor Ccoupled between the speaker terminalsand, and another capacitor Ccoupled between the speaker terminaland the ground terminal. The inductor Land capacitor Cfilter the modulated signal VY provided at the output terminalinto a sinusoidal signal VP at the speaker terminalthat is output to the speakerto output corresponding audio. Capacitor Ccan also filter signal VN to further suppress non-linearities in the signal VN, and to provide a virtual ground with a relatively low impedance. Capacitor Cmay be relatively large (e.g., 200 nF or larger) to provide a low impedance virtual ground and reduce electromagnetic interference (EMI) and harmonic distortion in the signal VN (e.g., harmonic distortion caused by non-linear conduction angle hand-over in the power stage), as explained in related application U.S. application Ser. No. 18/385,848, entitled “METHODS AND APPARATUS TO MODULATE SIGNALS USING MULTI-CLASS MODULATION CIRCUITRY”, Attorney Docket Number T103189US01. The power stages may drive a current from few micro amps to several amps to charge up capacitor C.

100 1 2 3 4 100 1 FIG.B Systemalso includes a control circuit (not shown in) that generates control signals that respectively drives the driver circuits D, D, D, Dbased on audio signals. Example operations of systemare described in related U.S. application Ser. No. 17/402,264, entitled “Methods and Apparatus to Generated a Modulation Protocol to Output Audio,” filed on Aug. 13, 2021, and related U.S. application Ser. No. 17/491,133, entitled “Switching amplifier having linear transition totem pole modulation,” filed on Sep. 30, 2021, and in U.S. application Ser. No. 18/358,848, which are hereby incorporated by reference in their entireties as described above.

2 FIG. 2 FIG. 100 100 1 2 202 1 2 1 204 3 4 2 202 204 206 202 204 206 illustrates examples of internal components of system.illustrates that systemincludes, in addition to power stages PSand PS, a control circuitthat provides the control signals CSand CSto power stage PS, and a control circuitthat provides the control signals CSand CSto power stage PS. During startup and shutdown, both control circuitsandmay not receive an audio signal. During normal operation, control circuitsandmay receive audio signal.

2 FIG. 202 1 202 1 2 206 1 108 206 206 204 2 204 3 4 204 3 4 3 4 206 112 In the example of, control circuitcan control power stage PSto operate as a non-switching amplifier (e.g., a class AB amplifier). Control circuitcan include a linear amplifier to generate control signals CSand CSby amplifying audio signal(if present). Power stage PScan provide a VN voltage at first output terminalhaving a magnitude that tracks audio signal. The VN voltage can also be saturated/clamped if the magnitude of audio signalexceeds a certain threshold. Also, control circuitcan control power stage PSto operate as a switching amplifier (e.g., a class D amplifier). Control circuitcan include modulated signal generator to generate control signals CSand CSas modulated signals. In some examples, control circuitcan include a pulse width modulation (PWM) signal generator to generate control signals CSand CSas PWM signals, where the pulse width of CSand CScan be modulated based on an instantaneous amplitude of audio signal. The difference between VN and VP, after VN and VP being filtered by the LC filter circuit, can become an amplified audio signal.

2 FIG. 1 202 2 204 1 202 1 2 204 2 1 1 206 2 204 210 212 2 204 3 4 212 2 204 3 4 212 2 204 1 202 2 204 3 4 206 212 As shown in, to further improve the matching between the common mode voltages between VN and VP, PScontrol circuitand PScontrol circuitcan operate in a master-slave configuration. In the master-slave configuration, PScontrol circuitand power stage PSis a master, and PScontrol circuitand power stage PSis a slave. Specifically, PScontrol circuit can drive power stage PSbased on audio signal(if present), or other signals. On the other hand, PScontrol circuitcan include a subtraction circuit(e.g., an amplifier) that receives VN and VP (or a filtered version of VY) as feedback signals and generates a difference signalrepresenting a difference between VN and VP. PScontrol circuitcan adjust control signals CSand CS(and VY/VP) based on difference signal. For example, PScontrol circuitcan adjust control signals CSand CSto minimize (or reduce) difference signal, to improve the matching between the common mode voltages of VN and VP. PScontrol circuitcan have a higher bandwidth than PScontrol circuit, which allows PScontrol circuitto adjust CSand CSresponsive to both audio signaland difference signal.

3 FIG. 2 FIG. 3 FIG. 100 100 300 302 302 304 304 304 304 1 2 300 1 202 2 204 100 306 306 206 206 206 100 305 206 206 306 306 306 206 206 a b a b a b a b a b a b a b a b. illustrates examples of internal components of systemof. Referring to, systemcan include an audio driver circuithaving driver inputs,, and driver outputsand. The driver outputsandare coupled to, respectively, the inputs of power stages PSand PS. Audio driver circuitincludes PScontrol circuitand PScontrol circuit. Systemalso includes audio inputsandto receive differential audio signals(also labelled VINP) and(also labelled VINM) of sinusoidal audio signals. In some examples, systemalso includes an audio signal generation circuitto provide the differential audio signals/to audio inputsand. Audio signal generation circuitcan include a digital to analog converter (DAC) to convert a sequence of digital signals into differential audio signals/

1 202 308 306 306 308 308 308 206 206 1 2 206 206 106 a b a b a b PScontrol circuitincludes an amplifiercoupled to audio inputsand. In some examples, amplifiercan be a linear differential amplifier. Amplifiercan receive differential audio signalsand, and provide control signals CSand CSby amplifying audio signalsandto set VN voltage at first output terminal.

2 204 320 322 324 326 328 329 322 324 329 325 320 329 330 329 322 332 206 206 350 352 332 330 324 334 330 332 325 210 334 212 100 327 302 302 302 302 a b b b a b a b. 2 FIG. 2 FIG. Also, PScontrol circuitincludes a filter(e.g., a loop filter), a subtraction circuit, a subtraction circuit, a periodic ramp generator, a comparator, and a voltage scaler circuit. Subtraction circuit, subtraction circuit, and voltage scaler circuitare collectively part of a signal combination circuit. In some examples, filtercan include a multi-stage loop filter. Voltage scaler circuitprovides a scaled down version of the VN voltage as a feedback signal. Voltage scaler circuitcan also remove the common mode/DC bias component of the VN voltage, and provide a scaled down version of the AC (alternating current) component of the VN voltage. Also, subtraction circuitcan generate a difference signalrepresenting a difference between filtered audio signalsandand feedback signals through resistorsand, where the difference signalcan have an opposite polarity from the VN voltage (and feedback signal). Further, subtraction circuitcan generate another difference signalrepresenting a difference between signalsand. Signal combination circuitcan represent subtraction circuitof, and difference signalcan represent difference signalof. Systemcan also include a common mode regulatorcoupled to driver inputsandto define a same input common mode voltage for driver inputsand

328 3 4 334 326 3 4 326 334 206 3 4 206 206 332 204 3 4 a b Further, comparatorcan generate control signals CSand CSby comparing difference signalwith a periodic ramp signal provided by periodic ramp generatorand modulating the duty cycle/pulse widths of CSand CSbased on the difference. Periodic ramp generatorcan receive a clock signal (labelled CLK) and generate the periodic ramp signal synchronized to the clock signal and having a cycle period defined based on the clock signal. Difference signalcan have a component representing the audio signalsand a corrective component representing the difference between VP and VN caused by, for example, the aforementioned asymmetry and non-linear effects. Accordingly, the duty cycle/pulse widths of CSand CScan reflect the instantaneous magnitudes of audio signalsand(represented by difference signal) and a difference between VP and VN (as part of the master-slave configuration), and control circuitcan adjust CSand CSto reduce/minimize the aforementioned difference between VP and VN caused by asymmetry and non-linear effects.

100 350 352 100 350 352 350 350 306 302 350 302 110 352 352 306 302 352 302 108 350 352 350 352 350 352 a a a b a a b b b b a a b b Also, systemcan also include a pair of resistor networksandto set an overall amplification gain of the system. The overall amplification gain can be between the differential output voltage VP-VN (or VY-VN) and the differential input voltage VINP-VINM. Systemcan include resistor networkfor the signal path from VINP to VY, and resistor networkfor the signal path from VINM to VN. Resistor networkcan include an input resistorcoupled between audio inputand driver input, and a feedback resistorcoupled between driver inputand output terminal. Also, resistor networkcan include an input resistorcoupled between audio inputand driver input, and a feedback resistorcoupled between driver inputand output terminal. Resistor networksandare to be matched, where input resistorsandhave a same resistance (e.g., RIN) and feedback resistorsandhave a same resistance (e.g., RFB), to remove a component of differential output voltage VP-VN (or VY-VN) caused by the output common mode voltage VCM, and to provide an amplification gain for the differential input voltage VINP-VINM.

100 2 1 102 106 106 2 1 2 1 2 108 104 102 1 2 102 104 108 104 108 In audio system, the output of power stage PSis coupled to inductor L, which can discharge to provide a current to speakervia terminal, thereby driving terminalat voltage VP. Accordingly, power stage PSmay provide a current to charge inductor L, which can also improve the power efficiency of power stage PS. In contrast, the output of power stage PSis coupled to capacitor Cand output terminal, which is coupled to terminalof speaker. Power stage PSmay provide a current to charge/discharge capacitor C, and to provide a current to speakervia terminals/, thereby driving terminals/at the VN voltage.

100 1 202 308 1 2 204 326 328 2 2 204 3 4 1 326 1 2 308 1 2 308 308 As described above, in audio system, PScontrol circuitincluding amplifieroperates power stage PSas a non-switching amplifier, while PScontrol circuit, which includes periodic ramp generatorand comparator, operates power stage PSas a switching amplifier. PScontrol circuitprovides control signals CSand CSthat toggles between the supply rails of power stage PS(e.g., PVDD and ground) and at a high frequency (e.g., the frequency of periodic ramp generator) than CSand CS. On the other hand, amplifierprovides control signals CSand CSat a lower frequency (e.g., at the frequency of the audio signal), at a lower slew rate, and having a reduced voltage swing limited by, for example, the output voltage range of amplifierwhere the transistor devices of amplifierremain in saturation.

2 1 2 1 1 1 1 2 1 2 1 1 308 308 1 2 The high frequency switching of power stage PScan generate switching noise, and the switching noise can be coupled into the control terminals (gates) of the transistors Sand Sof power stage PSvia power supply, ground, capacitor Cand inductor L, or any other metal interconnect shared between the power stages PSand PS. Switching noise from other sources may also be coupled into the gates of the transistors Sand Sof power stage PS, which can adversely affect the operation of power stage PS. Because of, as well as the relatively low bandwidth and low slew rate of amplifier, amplifieralone may be unable to adjust the gate voltages of transistors Sand Sto compensate for the effect of the switching noise.

4 FIG. 4 FIG. 100 116 1 116 2 402 402 402 402 402 402 116 2 402 116 1 402 116 116 402 116 2 1 2 404 404 404 404 404 404 404 404 2 404 1 404 2 404 404 1 2 404 1 406 102 108 1 a b a b c d a b b a c a b d a a b c d e f a b c d e f illustrates examples of mechanisms of switching noise generation and coupling in audio system. Referring to, power terminalof power stage PSand power terminalof power stage PSare coupled to a power supply interconnect(e.g., a power plane), which can have a distributed network of parasitic inductances,,, and. Parasitic inductanceis between power supply PVDD and power terminalof power stage PS, parasitic inductanceis between PVDD and power terminalof power stage PS, parasitic inductanceis between power terminalsand, and parasitic inductanceis between power terminaland other systems, such as power stage PSof another audio channel, a clock generator, a high frequency digital system, etc. Also, power stages PSand PSare coupled to a ground interconnect(e.g., a ground plane), which can also have a distributed network of parasitic inductances,,,,, and. Parasitic inductanceis between power stage PSand ground, parasitic inductanceis between power stage PSand ground, parasitic inductanceis between capacitor Cand ground, parasitic inductancesandare between power stages PSand PS, and parasitic inductanceis between power stage PSand the aforementioned other systems. Further, there can be parasitic inductancebetween speakerand output terminalof power stage PS.

1 2 2 402 404 410 410 402 404 410 1 402 1 1 412 1 410 2 404 404 2 2 414 2 410 410 1 2 412 414 402 404 410 410 1 2 402 1 2 102 1 412 1 2 108 a a a b a a a c b e d c d d f c d a Switching noise can be coupled into the gates of transistor Sand Sfrom various sources. For example, as power stage PSoperates as a switching amplifier, there can be huge switching current through parasitic inductancesand. The switching current can induce voltage transition eventsandacross, respectively, parasitic inductancesand. Voltage transition event, in the form of switching noises, can be coupled into the gate of transistor Svia parasitic inductanceand gate-drain parasitic capacitance Cgdof transistor S, and induce a voltage transition eventat the gate of transistor S. Also, voltage transition event, in the form of switching noises, can be coupled into the gate of transistor Svia parasitic inductancesandand gate-source parasitic capacitance Cgsof transistor S, and induce a voltage transition eventat the gate of transistor S. Voltage transition eventsandcan also be coupled into, respectively, the gates of transistors Sand Sand contribute to the voltage transition eventsandvia parasitic inductancesand. Voltage transition eventsandcan be caused by, for example, switching noise from other parts of the integrated circuit including power stages PSand PS(e.g., a neighboring channel), switching noise from other components external to the integrated circuit, or within the integrated circuit coupled through the power plane of a printed circuit board (PCB) and parasitic inductance/b. The induction and coupling of these voltage transition events can be examples of ground bounce events. In addition, there can be other switching noise sources, such as the switching of other power stages PS/PS, in a case where speakergenerates switching noise, and/or in a case where power stage PSdrives a load that generates switching noise. In all these scenarios, the switching noise (represented by voltage transition event) can also be coupled into the gates of transistors Sand Svia output terminal.

308 308 1 2 1 2 1 2 1 100 As described above, because of the relatively low bandwidth and slew rate of amplifier, amplifieralone may be unable to adjust the gate voltages of transistors Sand Sto compensate for the effect of the switching noise. The aforementioned voltage events may inadvertently turn on transistors Sand Swhen they are to be turned off, or otherwise put transistors Sand Sin indeterministic states, which can adversely affect the operation of power stage PSand audio system.

5 FIG.A 5 FIG.B 5 FIG.A 5 FIG.B 5 FIG.A 1 502 504 506 508 510 512 502 1 504 1 506 2 508 2 510 2 512 1 502 512 andinclude graphs illustrating example effects of switching noise on the operation of power stage PS.includes graphs,,,,, and. Graphillustrates an example variation of the gate voltage of transistor Swith respect to time. Graphillustrates an example variation of the current conducted by transistor Swith respect to time. Graphillustrates an example variation of the gate voltage of transistor Swith respect to time. Graphillustrates an example variation of the current conducted by transistor Swith respect to time. Graphillustrates an example variation of power consumption (or power loss) at transistor Swith respect to time. Graphillustrates an example variation of power consumption (or power loss) at transistor Swith respect to time.includes zoomed-in view of graphs-of.

5 FIG.A 5 5 FIGS.A andB 308 0 1 1 1 2 2 2 1 0 1 308 1 1 1 0 2 Referring to, within an interval TO, which can correspond to a half period of the audio signal, amplifiercan provide a high voltage V(e.g., around 5V, or the PVDD voltage) at the gate of transistor Sto turn on transistor S, and a low voltage V(e.g., below or around Vth of transistor S) at the gate of transistor Sto turn off transistor S. The gate voltage of transistor Smay also track the audio signal until the gate voltage reaches V. Also, within an interval T, which can correspond to another half period of the audio signal, amplifiercan provide the low voltage V(e.g., below or around Vth of transistor S) to turn off transistor S, and provide the high voltage V(around 5V in) to turn on transistor S.

502 506 502 506 2 2 1 1 1 1 2 1 2 a a Graphsandalso show voltage transition events, such as eventsand, caused by coupling of switching noise from power stage PS. The voltage transition events and the switching noise can have similar frequency as the switching of power stage PS, which is much higher than the frequency of the audio signal. Because of the voltage transition events, the gate voltage of transistor Scan become higher than Vduring significant portions of interval Twhen transistor Sis to be turned off. Also, the gate voltage of transistor Scan also become higher than Vduring significant portions of interval TO when transistor Sis to be turned off.

1 1 2 1 2 1 2 1 1 308 1 2 1 1 502 512 2 2 308 2 1 2 1 1 1 1 5 FIG.B 4 FIG. The turning on of transistor Sduring interval T, when transistor Sis turned on and transistor Sis to be turned off, and the turning on of transistor Sduring interval TO when transistor Sis turned on and transistor Sis to be turned off, can create a short circuit between PVDD and ground via power stage PS, which can lead to conduction of a large current through power stage PS. Also, due to limited bandwidth and slew rate, amplifiermay be unable to set the gate voltages of the transistors Sand Sback to Vquickly, and the short circuit can happen within significant portions of interval TO and T, which can lead to substantial energy loss. For example, referring to, which illustrates zoomed-in version of graphs-within interval TO, the switching noise induce a voltage transition event at the gate of transistor Sat time T, and the gate voltage increases from 0V to 2.6V. It takes about 30 nanoseconds (ns) for amplifierto bring down the gate voltage of transistor Sback to V(below or around Vth of transistor S). Within the 30 ns, a short circuit is created between PVDD and ground via power stage PS, which lead to huge short circuit current pulses. With a peak power loss of 650 Watts (W), and over 30 ns, a substantial amount of energy can be wasted/lost at power stage PS. This short circuit can be created even when power stage PSis operated in idle mode and not being actively driven by an audio signal. For example, power stage PSof an idle channel can be affected by ground bounce events of a neighboring channel. The huge short circuit current pulses can also induce extra ground bounce events by creating huge current transient events through the parasitic inductances shown in.

1 2 100 100 1 2 1 1 100 100 The high frequency voltage transitions at the gates of transistors Sand Scan degrade the performance of audio systemin various ways. Specifically, the voltage transitions can lead to substantial power loss, which can degrade the overall power efficiency of audio systemand generate substantial heat, which may create safety hazard or at least degrade user experience. Thermal management to mitigate the substantial heat can also be bulky and expensive to the user. Also, the conduction of a large amount of current via transistors Sand Sdue to the short circuit can shorten the life times of the transistors. Further, in examples where power stage PSis coupled to an overcurrent detection circuit, the large current can trigger the overcurrent detection circuit to shut down power stage PSand disrupt its operation. Moreover, the high frequency voltage transitions can increase the electromagnetic interference (EMI) signature of audio system, which can disrupt the operations of other electronic devices near audio system.

1 2 2 1 1 2 308 308 308 308 1 308 308 4 FIG. One possible way of mitigating the switching noises is providing separate power supply and ground planes for power stage PSand power stage PS. Such arrangements can reduce the coupling of the switching noise from power stage PSvia the shared power supply plane and/or shared ground plane to power stage PS, as illustrated in. In examples where power stages PSand PSare within the same integrated circuit package, additional package interconnects (e.g., pins, pads, etc.), and/or a larger integrated circuit package, may be provided to connect the separate power supply planes and separate ground planes to different power supplies, which can increase package complexity and cost. Also, the bandwidth of amplifiercan be increased to shorten the time taken by amplifierto bring down the gate voltage, which can reduce the power loss incurred by the voltage transition events. But the bandwidth and slew rate of amplifiermay be increased multifold to effectively shorten the time. Because amplifierdrives power stage PS, which may be large, the power consumption of amplifiermay become prohibitively large. Peripheral circuit that drives amplifier, such as a charge pump circuit, may also become large and include more expensive external components.

6 FIG. 6 FIG. 100 600 600 602 604 604 1 2 1 606 606 602 604 606 604 604 604 604 604 1 1 100 602 604 1 602 600 308 604 1 2 308 a b illustrates an example of a circuit that can address at least some of issues described above. Referring to, audio systemcan include a clamp circuit. Clamp circuitincludes a switch(e.g., a transistor) coupled between the control terminal/gateof a transistor, which can be one of transistor S/Sof power stage PS, and a reference terminal. Reference terminalcan receive a reference voltage. When enabled, switchcan connect the gate of transistorto reference terminalto adjust the gate voltage by clamping/setting the gate voltage at the reference voltage. As to be described below, in some examples, the reference voltage can be a voltage to turn off transistor(e.g., a ground voltage, a reference voltage based on a voltage at one of current terminals of transistor, such as sourceof transistor, etc.). In some examples, the reference voltage can track an average of the gate voltage of transistor(e.g., in the off-state), with the voltage transition events removed or at least attenuated. With such arrangements, the duration of the short circuit via power stage PScaused by voltage transition events can be reduced, which can reduce power loss (and the resulting thermal dissipation), improve reliability of the transistor devices of power stage PS, and reduce the EMI signature of audio system. Moreover, switchcan be much smaller than transistor(and power stage PS), which can reduce the amount of power involved in driving switch. Accordingly, clamp circuitcan have a much higher bandwidth than amplifierin clamping the gate voltage of transistorwhile consuming limited amount of power. The aforementioned issues with providing separate power supply and ground planes for power stage PSand power stage PSand increasing the bandwidth/slew rate of amplifiercan also be avoided.

600 610 602 610 611 602 604 604 602 610 612 610 604 604 612 612 604 604 604 604 604 604 612 612 614 602 a a a c b b Clamp circuitalso includes a control circuitthat enables/disables switch. Control circuitcan provide a control signalto enable switchbased on detecting a voltage transition event at gateof transistor, and disable switchif no voltage transition event is detected. Control circuitcan include a voltage transition detection circuitto detect the voltage transition event. As to be described below, control circuitcan detect the voltage transition event in various ways, such as by detecting that an instantaneous gate voltage of transistorexceeds an average of the gate voltage over a short time window, by detecting that the edge rate of the gate voltage exceeds a voltage threshold, or by detecting that the current conducted by transistorexceeds a current threshold which indicates a short circuit. Accordingly, voltage transition detection circuithas an inputcoupled to the gateof transistoror current terminals (e.g., drain terminaland/or source terminal) of transistorto sense the gate voltage and/or current of transistor. Voltage transition detection circuitalso has an outputto provide a voltage transition detection signalto set the state of switch.

610 622 622 308 604 0 604 604 600 604 622 622 604 604 624 622 5 FIG.A a a b. Also, control circuitincludes a maximum voltage detection circuit. Maximum voltage detection circuitcan detect whether the output voltage of amplifier, and the gate voltage of transistor, is at or close to a maximum (e.g., the Vvoltage in). If the gate voltage of transistoris at or close to the maximum, transistoris to be turned on, and the clamping of clamp circuitcan be disabled/discontinued to avoid clamping the gate voltage of transistorand therefore disrupting its operation. Accordingly, maximum voltage detection circuithas an inputcoupled to the gateof transistor, and provide a maximum voltage detection signalat an output

610 632 632 632 622 632 612 632 602 602 632 614 632 624 632 611 632 614 624 632 611 602 614 624 604 632 611 602 614 624 604 632 611 602 600 604 a b b b c a a b c Control circuitalso includes a control signal generation circuit. Control signal generation circuithas an inputcoupled to output, an inputcoupled to output, and an outputcoupled to a switch control inputof switch. Control signal generation circuitcan receive voltage transition detection signalat input, receive maximum voltage detection signalat input, and provide control signalat outputbased on voltage transition detection signaland maximum voltage detection signal. Specifically, control signal generation circuitcan provide control signalat a first state (e.g., a high voltage state) to turn on switchif voltage transition detection signalindicates a voltage transition event and maximum voltage detection signalindicates that the gate voltage of transistoris not at or close to maximum. Control signal generation circuitcan also provide control signalat a second state (e.g., a low voltage state) to turn off switchif voltage transition detection signalindicates no voltage transition event, or maximum voltage detection signalindicates that the gate voltage of transistoris at or close to maximum. Control signal generation circuitmay also include circuits to speed up the transition of control signalbetween the first and second states to speed up the enabling and/or disabling of switch, which can improve the responsiveness of clamp circuitto the voltage transition events to reduce the durations of the short-circuit intervals, and also to reduce the disruption to the normal operation of transistordue to the clamping operation.

7 FIG. 7 FIG. 600 606 612 612 604 604 612 702 612 604 612 704 612 604 702 704 612 702 704 614 614 604 604 706 612 708 706 706 704 614 602 604 604 604 708 a a a a b a b a a illustrates examples of internal components of clamp circuit. In the example of, reference terminalis coupled to the ground, and inputof voltage transition detection circuitis coupled to the gateof transistor. Voltage transition detection circuitincludes a low pass filtercoupled to inputto receive an instantaneous gate voltage of transistor, which may rise due to the voltage transition events, and generate a time-averaged version of the gate voltage (or an average gate voltage) with the voltage transition events removed or at least attenuated. Voltage transition detection circuitalso includes a transistorhaving a gate coupled to inputto receive the instantaneous gate voltage of transistor, and a source coupled to low pass filterto receive the time-averaged version of the gate voltage. Transistoris coupled between outputand the output of low pass filter. Transistoris configured as a comparator and provide voltage transition detection signalbased on comparing between the instantaneous gate voltage and the time-averaged version of the gate voltage, so that voltage transition detection signalcan indicate whether a voltage transition event is detected at gateof transistor. A bias circuitis coupled between outputand a power supply terminal. Bias circuitincludes a capacitorto filter out noise (including switching noise) at the power supply terminal and to provide a bias current and a bias voltage with reduced disturbance to transistor. With such arrangements, the voltage transition detection signal, and the decision on whether to turn on/off switchto clamp the gate voltage of transistor, is generated based on whether voltage transition events occur at gateof transistorbut not at other places (e.g., power terminal).

704 614 704 704 612 704 706 612 704 614 604 b b a. Transistoris configured as a comparator and provide voltage transition detection signalbased on comparing between the instantaneous gate voltage and the time-averaged version of the gate voltage. For example, if the instantaneous gate voltage, due to the voltage transition event, exceeds the average gate voltage by at least one threshold voltage of transistor, transistorcan be turned on to bring down the voltage of outputto, for example, the average gate voltage. Also, if at the end of a voltage transition event, the difference between the instantaneous gate voltage and the average gate voltage is less than the threshold voltage, or the instantaneous gate voltage falls below the average gate voltage, transistorcan be turned off, and bias circuitcan pull the output of outputto the power supply voltage. Accordingly, the transistorcan provide voltage transition detection signalthat tracks/indicates a voltage transition event at gate

632 710 710 712 714 710 614 614 712 712 712 712 614 611 614 600 602 712 602 604 712 602 712 712 712 614 611 632 a b a b Also, control signal generation circuitincludes an alternating current (AC) capacitor(or an AC coupled capacitor), a metastable buffer, and a switch network. AC capacitorcan perform high pass filtering on voltage transition detection signal, and provide the filtered signalto metastable buffer. Metastable bufferincludes fast trigger metastable circuitsand, which can be triggered on both rising and falling edges of detection signal, to generate control signalbased on the filtered signaland with reduced delay, to improve the responsiveness of clamp circuitin enabling/disabling switch. Also, metastable bufferdrives (directly or indirectly) switch, which can be small compared with transistoras explained above. Accordingly, metastable buffermay consume a small amount of power while operating switchat a high speed. In some examples, metastable buffercan include one of circuitsorto be trigger based on rising or falling edge of detection signal, followed by a timer to set a pre-determined pulse width of control signal, which can further reduce the power consumption of control signal generation circuit.

714 624 611 712 632 604 632 602 604 c a c a. Further, switch networkcan receive maximum voltage detection signaland can either forward control signalprovided by metastable bufferat outputif maximum voltage is not detected at gate, or pull down the voltage of outputto ground to disable switchif maximum voltage is detected at gate

8 FIG. 9 FIG. 8 FIG. 600 612 804 612 604 604 802 804 612 804 604 804 802 614 806 802 614 806 802 614 a a b andillustrate additional examples of internal components of clamp circuit. As shown in, voltage transition detection circuitcan include a dv/dt circuitcoupled to input, which is coupled to gateof transistor, and a comparatorcoupled between dv/dt circuitand output. The dv/dt circuitcan generate a voltage signal representing an absolute edge rate (for both rising and falling edges) of the gate voltage of transistor. In some examples, dv/dt circuitcan include an AC capacitor to provide a current based on the edge rate of the gate voltage, and a current-to-voltage converter to convert the current to a voltage signal. Comparatorcan generate voltage transition detection signalby comparing the voltage signal against a voltage threshold. Comparatorcan set voltage transition detection signalto a first state if the voltage signal exceeds the voltage threshold, which can indicate the presence of a voltage transition event caused by the coupling of switching noise. Comparatorcan also set voltage transition detection signalto a second state, which can indicate the absence of (or the end of) the voltage transition event.

9 FIG. 612 904 612 604 604 604 902 904 612 904 604 802 614 904 906 604 1 902 614 906 1 604 604 902 614 1 604 a b c b a a. Also, as shown in, voltage transition detection circuitcan include a current sensorcoupled to input, which is coupled to one or more current terminals of transistor(e.g., source terminal, drain terminal), and a comparatorcoupled between current sensorand output. Current sensorcan provide a current sense signal (which can be a voltage signal) representing an amount of current conducted by transistor. Comparatorcan generate voltage transition detection signalby comparing the output of current sensoragainst a current threshold, which can be based on an amount of current conducted by transistorwhen power stage PSprovides a short circuit between PVDD and ground. Comparatorcan set voltage transition detection signalto a first state if the current sense signal exceeds the current threshold, which can indicate the presence of a short circuit in power stage PScaused by a voltage transition event at gateof transistor. Comparatorcan also set voltage transition detection signalto a second state, which can indicate no short circuit in power stage PS, which can also indicate the absence of (or the end of) the voltage transition event at gate

10 10 10 FIGS.A,B, andC 10 FIG.A 606 604 602 606 602 604 604 illustrate examples of connections of reference terminal, which can provide a reference voltage to which the gate voltage of transistoris clamped when switchis enabled. As shown in, reference terminalcan be coupled to ground, so that when switchis enabled, the gate voltage of transistoris set to the ground voltage to turn off transistor.

10 FIG.B 606 604 604 1000 604 604 604 604 604 604 1 308 604 308 c Also, as shown in, reference terminalcan be coupled to source terminalof transistorvia a diode-connected transistor, which can track the threshold voltage of transistoracross process variations and different temperatures, to provide a reference voltage equal to the threshold voltage above the source voltage of transistor. Such arrangements can reduce the voltage difference between the gate and source of transistorduring clamping, which can reduce voltage stress and disturbance, and improve reliability of transistor. Also, because the gate-source voltage difference of transistoris still below the threshold voltage, transistorcan be turned off during clamping to remove the short-circuit current path within power stage PS. Further, because of the reduced gate-source voltage difference, the driver of amplifieralso consumes less power to charge the gate of transistorback to the prior voltage state. This reduces the power handling rating of any peripheral that supplies the power to the driver of amplifier.

10 FIG.C 7 FIG. 10 FIG.C 606 1002 702 604 604 602 604 604 604 604 604 308 308 308 a a a Further, as shown in, reference terminalcan be coupled to an average generator circuit, which can be similar to low pass filterofand can be coupled to gateof transistorto generate a time-averaged version of the gate voltage with the voltage transition events removed or at least attenuated. Switchcan clamp gateof transistorto the average gate voltage to allow transistorto operate (e.g., providing a current that tracks the audio signal), instead of turning off transistor. Also, with the arrangements ofwhere gatecan be clamped to the average gate voltage, which tracks the dynamics of the system, the disturbance to the operation of amplifiercan be reduced. The signal quality of amplifiercan also be improved due to the reduced disturbance of amplifier.

11 FIG. 11 FIG. 11 FIG. 622 622 1102 622 604 604 308 1102 308 622 1104 604 604 1104 308 1102 1104 604 604 108 1 a a illustrates examples of internal components of maximum voltage detection circuit. Referring to, in some examples, maximum voltage detection circuitincludes a comparatorhaving a negative input coupled to input, which is coupled to gateof transistorand output of amplifier. The positive input of comparatorreceives a threshold representing a maximum output voltage of amplifier. In some examples, as shown in, maximum voltage detection circuitcan include a voltage drop circuitto generate the reference voltage. The reference voltage can be with respect to the transistorsource voltage to track the threshold voltage variation of transistor(e.g., due to PVT variations). Voltage drop circuitcan be coupled between a supply voltage of amplifier(e.g., AVDD as shown) and the positive input of comparator. The reference voltage generated by voltage drop circuitcan represent the gate voltage of transistorwhen transistoris fully turned on, and output terminalis saturated at the PVDD supply voltage of power stage PS.

12 FIG. 12 FIG. 12 FIG. 12 FIG. 5 FIG.B 600 1202 1204 1206 1208 1210 1212 1202 1 1204 1 1206 2 1208 2 1210 2 1212 1 600 2 3 2 600 2 1 includes graphs that illustrate examples of operations of clamp circuit.includes graphs,,,,, and. Graphillustrates an example variation of the gate voltage of transistor Swith respect to time. Graphillustrates an example variation of the current conducted by transistor Swith respect to time. Graphillustrates an example variation of the gate voltage of transistor Swith respect to time. Graphillustrates an example variation of the current conducted by transistor Swith respect to time. Graphillustrates an example variation of power consumption (or power loss) at transistor Swith respect to time. Graphillustrates an example variation of power consumption (or power loss) at transistor Swith respect to time. Referring to, clamp circuitdetects a voltage transition event at time T. At time T′, which is about 7 ns from T, clamp circuitclamps the gate voltage of transistor S, thereby disabling the short circuit in power stage PSand stops the short-circuit current. Although the peak power loss inis also 650 W, similar to as shown in, because of the reduced duration of the short-circuit interval (from 30 ns to 7 ns), the energy loss (and resulting thermal dissipation) caused by the switching noise can be substantially reduced. By reducing the duration of the voltage transition event, the EMI signature can also be substantially reduced as well.

13 FIG. 6 11 FIGS.- 1300 1 100 1300 600 illustrates a flowchart of an example methodof operating a transistor, such as a transistor of power stage PSof audio system, or any transistor in a high switching noise environment. Methodcan be performed by a clamp circuit, such as clamp circuitof.

1302 600 612 7 FIG. 8 FIG. 9 FIG. In operation, clamp circuitcan detect a voltage transition event at a control terminal of the transistor. The voltage transition event can be caused by the coupling of switching noise from other devices. The detection can be performed by voltage transition detection circuitand can be based on, for example, comparing the instantaneous gate voltage with an average gate voltage (as shown in), measuring the edge rate of the gate voltage (as shown in), and/or measuring the current through the transistor (as shown in).

1304 600 600 308 600 10 10 FIGS.A-C In operation, clamp circuitcan, responsive to detecting the voltage transition event, perform a clamp operation by setting the voltage of the control terminal to a reference voltage. The reference voltage can be a ground voltage or one threshold voltage above the source voltage of the transistor to disable the transistor, or an average gate voltage of the transistor to maintain the operation of the transistor, as shown in. In some examples, clamp circuitcan disable/discontinue the clamp operation if the gate voltage of the transistor is at a maximum voltage provided by a driver of the transistor, such as amplifier, which indicates that the transistor is to be turned on and not to be turned off by clamp circuit.

In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.

As used herein, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.

A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, such as by an end user and/or a third party.

While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, a p-channel field effect transistor (PFET) may be used in place of an n-channel field effect transistor (NFET) with little or no changes to the circuit. Furthermore, other types of transistors may be used, such as laterally-diffused metal-oxide semiconductor (LDMOS) FETs) and bipolar junction transistors (BJTs). Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).

References herein to a field effect transistor (FET) being “ON” means that the conduction channel of the FET is present and drain current may flow through the FET. References herein to a FET being “OFF” means that the conduction channel is not present and drain current does not flow through the FET. A FET that is OFF, however, may have current flowing through the transistor's body-diode.

Circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.

Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter.

Modifications are possible in the described embodiments and examples, and other embodiments and examples are possible, within the scope of the claims, such as the examples herein below.