Semiconductor Memory Device

This application is based on and claims priority to Korean Patent Application No. 10-2024-0086691, filed on Jul. 2, 2024 in the Korean Intellectual Property Office, the contents of which are herein incorporated by reference in its entirety.

The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a vertical channel transistor (VCT).

To meet consumer demands for excellent performance and low cost, increasing the integration density of semiconductor memory devices is necessary. Since the integration density of semiconductor memory devices is a crucial factor in determining the product price, higher integration density is required.

The integration density of two-dimensional (2D) or planar semiconductor memory devices is primarily determined by the area occupied by unit memory cells and is thus greatly influenced by the level of fine patterning technology. However, since ultra-high-cost equipment is needed for miniaturizing patterns, the integration density of 2D semiconductor memory devices, although increasing, remains limited. Accordingly, semiconductor memory devices including vertical channel transistors (VCT), where the channels extend vertically, have been proposed.

Provided is a semiconductor memory device with improved integration density and electrical characteristics.

According to an aspect of the disclosure, a semiconductor memory device includes: a contact pattern including a first surface, a second surface, and a sidewall, wherein the first surface and the second surface are opposite to each other in a first direction, and the sidewall connects the first and the second surfaces; a data storage pattern connected to the first surface; a channel pattern on at least part of the sidewall, wherein the channel pattern is connected to the second surface; a bitline on the channel pattern, wherein the bitline is connected to the channel pattern and extends in a second direction; and a wordline on the channel pattern, wherein the wordline extends in a third direction.

According to an aspect of the disclosure, a semiconductor memory device includes: a contact pattern including a first surface and a second surface opposite to each other in a first direction; a data storage pattern connected to the first surface; a channel pattern connected to the second surface; a bitline spaced apart from the contact pattern in the first direction, wherein the bitline is connected to the channel pattern and extends in a second direction; and a wordline on the channel pattern and extending in a third direction, wherein a height, in the first direction, of the channel pattern is greater than a height from the second surface to a lowermost portion of the bitline.

According to an aspect of the disclosure, a semiconductor memory device includes: a peripheral gate structure on a substrate; a contact pattern on the peripheral gate structure, the contact pattern including a first surface, a second surface, and a sidewall, wherein the first and the second surfaces are opposite to each other in a first direction, and wherein the sidewall connects the first and the second surfaces; a data storage pattern connected to the first surface; a channel pattern connected to the second surface, wherein the channel pattern is on a part of the sidewall; a bitline on the channel pattern, wherein the bitline is connected to the channel pattern and extends in a second direction; and a wordline on the channel pattern and extending in a third direction, wherein the channel pattern includes a vertical portion protruding in the first direction from the second surface, a horizontal portion extending along the second surface, and a contact cover portion on the sidewall.

However, aspects of the present disclosure are not restricted to those set forth herein. The above and other aspects of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

It should be noted that the effects of the present disclosure are not limited to those described above, and other effects of the present disclosure will be apparent from the following description.

It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the present disclosure.

In the following description, like reference numerals refer to like elements throughout the specification.

It will be understood that when an element is referred to as being “connected” with or to another element, it can be directly or indirectly connected to the other element.

Also, when a part “includes” or “comprises” an element, unless there is a particular description contrary thereto, the part may further include other elements, not excluding the other elements.

Throughout the description, when a member is “on” another member, this includes not only when the member is in contact with the other member, but also when there is another member between the two members.

As used herein, the expressions “at least one of a, b or c” and “at least one of a, b and c” indicate “only a,” “only b,” “only c,” “both a and b,” “both a and c,” “both b and c,” and “all of a, b, and c.”

As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

With regard to any method or process described herein, an identification code may be used for the convenience of the description but is not intended to illustrate the order of each step or operation. Each step or operation may be implemented in an order different from the illustrated order unless the context clearly indicates otherwise. One or more steps or operations may be omitted unless the context of the disclosure clearly indicates otherwise.

1 FIG. 2 FIG. 1 FIG. 3 FIG. 2 FIG. 4 FIG. 2 FIG. 5 FIG. 3 FIG. 6 8 FIGS.and 3 FIG. 7 FIG. 6 FIG. is a schematic layout view of a semiconductor memory device according to one or more embodiments of the present disclosure.is a layout view of a cell array area of.is a cross-sectional view taken along lines A-A and B-B of.is a cross-sectional view taken along lines C-C and D-D of.is an enlarged cross-sectional view of part P of.are plan views for explaining the shape in which channel patterns are disposed on contact patterns in.is a perspective view for explaining the shape of the channel patterns of.

The semiconductor memory device according to one or more embodiments of the present disclosure may include memory cells that include vertical channel transistors (VCTs).

1 7 FIGS.through 1 2 1 2 Referring to, the semiconductor memory device according to one or more embodiments of the present disclosure may include a peripheral gate structure PG, bitlines BL, wordlines (WLand WL), channel patterns (APand AP), contact patterns BC, and data storage patterns DSP.

100 100 A substratemay include a cell array area CAR where the data storage patterns DSP may be disposed, and a peripheral circuit area PCR that is defined around the cell array area CAR. The substratemay be a silicon substrate, or may include other materials, for example, silicon-germanium, indium antimonide, a lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the present disclosure is not limited thereto.

100 100 100 100 The peripheral gate structure PG may be disposed on the substrate. The substratemay include the cell array area CAR and the peripheral circuit area PCR. The peripheral gate structure PG may be arranged over both the cell array area CAR and the peripheral circuit area PCR. In other words, part of the peripheral gate structure PG may be disposed in the cell array area CAR of the substrate, and the rest of the peripheral gate structure PG may be disposed in the peripheral circuit area PCR of the substrate.

The peripheral gate structure PG may be included in sensing transistors, transfer transistors, and driving transistors. The types of transistors disposed in the cell array area CAR and the peripheral circuit area PCR may vary depending on the design layout of the semiconductor memory device according to one or more embodiments of the present disclosure.

215 223 225 215 The peripheral gate structure PG may include a peripheral gate insulating film, peripheral lower conductive patterns, and peripheral upper conductive patterns. The peripheral gate insulating filmmay include a silicon oxide film, a silicon oxynitride film, a high-k dielectric film with a higher dielectric constant than a silicon oxide film, or a combination thereof. The high-k dielectric film may include, for example, at least one of a metal oxide, a metal oxynitride, a metal silicon oxide, and a metal silicon oxynitride, but the present disclosure is not limited thereto.

223 225 223 225 The peripheral lower conductive patternsand the peripheral upper conductive patternsmay each include a conductive material. For example, the peripheral lower conductive patternsand the peripheral upper conductive patternsmay each include at least one of a doped semiconductor material, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, a two-dimensional (2D) material, a metal, and a metal alloy. The peripheral gate structure PG is illustrated as including multiple conductive patterns, but the present disclosure is not limited thereto.

2 2 2 2 In the semiconductor memory device according to one or more embodiments of the present disclosure, the 2D material may be a metallic and/or semiconductor material. The 2D material may include a 2D allotrope or 2D compound, for example, at least one of graphene, molybdenum disulfide (MoS), molybdenum diselenide (MoSe), tungsten diselenide (WSe), and tungsten disulfide (WS), but the present disclosure is not limited thereto. That is, these 2D materials are merely illustrative, and the present disclosure is not limited thereto.

227 228 100 227 228 A first peripheral lower insulating filmand a second peripheral lower insulating filmmay be disposed on the substrate. The first peripheral lower insulating filmand the second peripheral lower insulating filmmay each be formed of an insulating material.

228 223 225 223 225 The second peripheral lower insulating filmis illustrated as being in contact with the sidewalls of the peripheral lower conductive patternsand the sidewalls of the peripheral upper conductive patterns, but the present disclosure is not limited thereto. The peripheral gate structure PG may include peripheral gate spacers disposed on the sidewalls of the peripheral lower conductive patternsand the sidewalls of the peripheral upper conductive patterns.

241 241 227 228 241 100 241 223 225 a b b b Peripheral wiring linesand the peripheral contact plugmay be disposed within the first peripheral lower insulating filmand the second peripheral lower insulating film, respectively. Peripheral contact plugsmay be connected to a source/drain region disposed on at least one side of the peripheral gate structure PG. For example, the source/drain region may be a region doped with impurities in the substrate, but the present disclosure is not limited thereto. The peripheral contact plugsmay be connected to the peripheral conductive patterns (and) of the peripheral gate structure PG.

241 241 241 241 241 3 a b a b a The peripheral wiring linesmay be disposed on the peripheral contact plugs. The peripheral wiring linesmay be connected to the peripheral contact plugs. For example, the peripheral wiring linesmay be wiring lines closest to the peripheral gate structure PG in a third direction DR.

241 241 241 241 241 241 a b a b a b The peripheral wiring linesand the peripheral contact plugsare illustrated as being different layers, but the present disclosure is not limited thereto. The boundaries between the peripheral wiring linesand the peripheral contact plugsmay not be distinguishable. The peripheral wiring linesand the peripheral contact plugseach include a conductive material.

261 262 241 241 261 262 a b A first peripheral upper insulating filmand a second peripheral upper insulating filmmay be disposed on the peripheral wiring linesand the peripheral contact plugs. The first and second peripheral upper insulating filmsandmay each be formed of an insulating material.

243 242 241 242 261 243 262 a Peripheral connection wiringsand peripheral connection viasmay be disposed on the peripheral wiring lines. The peripheral connection viasmay be disposed within the first peripheral upper insulating film. The peripheral connection wiringsmay be disposed within the second peripheral upper insulating film.

243 242 241 242 241 243 243 242 243 242 243 242 a a The peripheral connection wiringsand the peripheral connection viasmay be connected to the peripheral wiring lines. The peripheral connection viasmay connect the peripheral wiring linesand the peripheral connection wirings. The peripheral connection wiringsand the peripheral connection viasmay each include a conductive material. The peripheral connection wiringsand the peripheral connection viasare illustrated as being different layers, but the present disclosure is not limited thereto. The boundaries between the peripheral connection wiringsand the peripheral connection viasmay not be distinguishable.

243 241 243 241 a a. Peripheral connection wiringsdisposed at a single metal level are illustrated as being arranged on the peripheral wiring lines, but the present disclosure is not limited thereto. Alternatively, multiple peripheral connection wiringsdisposed at different metal levels may be arranged on the peripheral wiring line

263 243 263 A first interlayer insulating filmmay be disposed on the peripheral connection wirings. The first interlayer insulating filmmay include an insulating material.

263 263 243 The data storage patterns DSP may be disposed on the first interlayer insulating film. The first interlayer insulating filmmay be disposed between the data storage patterns DSP and the peripheral connection wirings.

1 2 1 2 2 FIG. The data storage patterns DSP may be electrically connected respectively to first channel patterns APand second channel patterns AP. As illustrated in, the data storage patterns DSP may be arranged in a matrix form along a first direction DRand a second direction DR.

1 2 3 1 2 3 100 1 2 100 Here, the first and second directions DRand DRmay be orthogonal to the third direction DR. The first direction DRmay intersect the second direction DR. For example, the third direction DRmay be the thickness direction of the substrate. The first and second directions DRand DRmay be parallel to the upper surface of the substrate.

253 251 255 251 251 247 247 For example, the data storage patterns DSP may be capacitors. The data storage patterns DSP may include a capacitor dielectric film, which is interposed between storage electrodesand plate electrodes. From a planar perspective, the storage electrodesmay have various shapes such as circular, elliptical, rectangular, square, rhombic, and hexagonal. The storage electrodesmay penetrate a first etch stop film. The first etch stop filmmay be formed of an insulating material.

251 255 253 253 The storage electrodesand the plate electrodesmay each include at least one of, for example, conductive semiconductor material, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, and a metal. The capacitor dielectric filmmay include at least one of a ferroelectric material, an antiferroelectric material, and a paraelectric material. For example, the capacitor dielectric filmmay include one of a ferroelectric material, an antiferroelectric material, a paraelectric material, a combination of the ferroelectric and antiferroelectric materials, a combination of the ferroelectric and paraelectric materials, a combination of the paraelectric and antiferroelectric materials, or a combination of the ferroelectric, antiferroelectric, and paraelectric materials.

Alternatively, the data storage patterns DSP may be variable resistance patterns that can switch between two resistance states in response to electrical pulses applied to memory elements. For example, the data storage patterns DSP may include a phase-change material that changes its crystalline state based on the amount of current, a perovskite compound, transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

251 251 The contact patterns BC may be disposed on the data storage patterns DSP. The contact patterns BC may be disposed on the storage electrodes. The storage electrodesmay contact the contact patterns BC. From a planar perspective, the contact patterns BC may have various shapes such as circular, elliptical, rectangular, square, rhombic, and hexagonal.

235 247 235 1 2 235 A contact separation insulating filmmay be disposed on the first etch stop film. The contact separation insulating filmmay be disposed between the contact patterns BC. From a planar perspective, the contact patterns BC may be arranged in a matrix form along the first and second directions DRand DR. The contact separation insulating filmmay be formed of an insulating material.

1 2 3 1 2 Each of the contact patterns BC may include a first surface BC_Sand a second surface BC_S, which are opposite to each other in the third direction DR. Each of the contact patterns BC may also include sidewalls BC_SW, which connect the first and second surfaces BC_Sand BC_S. From a planar perspective, the sidewalls BC_SW of the contact patterns BC may define outer circumferential surfaces BC_CS of the contact patterns BC.

1 1 251 1 The first surfaces BC_Sof the contact patterns BC may face the data storage patterns DSP. The data storage patterns DSP may be connected to the first surfaces BC_Sof the contact patterns BC. The storage electrodesmay contact the first surfaces BC_Sof the contact patterns BC.

235 235 235 235 The contact separation insulating filmmay cover the sidewalls BC_SW of the contact patterns BC. For example, the contact separation insulating filmmay not cover the entire sidewalls BC_SW of the contact patterns BC. In other words, parts of the sidewalls BC_SW of the contact patterns BC may not be covered by the contact separation insulating film. Other parts of the sidewalls BC_SW of the contact patterns BC may be covered by the contact separation insulating film.

3 1 The data storage patterns DSP may completely or partially overlap with the contact patterns BC in the third direction DR. The data storage patterns DSP may contact all or parts of the first surfaces BC_Sof the contact patterns BC.

The contact patterns BC may include a conductive material. For example, the contact patterns BC may include at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbon nitride, conductive metal silicide, conductive metal oxide, a 2D material, a metal, and a metal alloy.

175 235 173 175 235 Protruding insulating patternsmay be disposed on the contact patterns BC and the contact separation insulating film. A second etch stop filmmay be disposed between the protruding insulating patternsand the contact separation insulating film.

175 175 175 175 175 175 235 175 175 173 175 175 175 The protruding insulating patternsmay include upper protruding insulating patternsU and lower protruding insulating patternsB. The lower protruding insulating patternsB may be disposed between the upper protruding insulating patternsU and the contact patterns BC, and between the upper protruding insulating patternsU and the contact separation insulating film. The lower protruding insulating patternsB may be disposed between the upper protruding insulating patternsU and the second etch stop film. The upper protruding insulating patternsU may include upper surfaces_US of the protruding insulating patterns.

175 175 175 175 175 175 The upper protruding insulating patternsU and the lower protruding insulating patternsB may each be formed of an insulating material. The upper protruding insulating patternsU and the lower protruding insulating patternsB may include different insulating materials. In the semiconductor memory device according to one or more embodiments of the present disclosure, the upper protruding insulating patternsU may include silicon nitride, and the lower protruding insulating patternsB may include silicon oxide.

173 173 175 173 175 235 The second etch stop filmmay be formed of an insulating material. The second etch stop filmmay include a material having an etch selectivity with respect to the lower protruding insulating patternsB. Alternatively, the second etch stop filmmay not be disposed between the lower protruding insulating patternsB and the contact separation insulating film.

175 175 175 175 175 175 The protruding insulating patternsare illustrated as having a double-layer structure, but the present disclosure is not limited thereto. Alternatively, the protruding insulating patternmay have a single-layer structure. If the protruding insulating patternshave a single-layer structure, the protruding insulating patternsmay include silicon oxide, but the present disclosure is not limited thereto. Alternatively, the protruding insulating patternsmay have a triple-layer structure (or a structure including more than three layers). In this example, the protruding insulating patternsmay have a laminated insulating film structure where silicon oxide, silicon nitride, and silicon oxide are stacked, but the present disclosure is not limited thereto.

175 1 2 The protruding insulating patternsmay include a plurality of channel trenches CH_T. The channel trenches CH_T may extend in the first direction DR. Each pair of adjacent channel trenches CH_T may be spaced apart in the second direction DR.

2 2 The channel trenches CH_T may expose the contact patterns BC. The second surfaces BC_Sof the contact patterns BC may be exposed by the channel trenches CH_T. For example, parts of the second surfaces BC_Sof the contact patterns BC may be exposed by the channel trenches CH_T.

3 235 3 In the areas where the contact patterns BC overlap with the channel trenches CH_T in the third direction DR, the contact separation insulating filmmay not cover parts of the sidewalls BC_SW of the contact patterns BC. The uncovered parts of the sidewalls BC_SW of the contact patterns BC may be located where the channel trenches CH_T overlap with the contact patterns BC in the third direction DR.

235 1 2 235 The bottom surfaces of the channel trenches CH_T may be defined by the contact patterns BC and the contact separation insulating film. The bottom surfaces of the channel trenches CH_T may have a concave-convex shape. Based on the first surfaces BC_Sof the contact patterns BC, the portions of the bottom surfaces of the channel trenches CH_T defined by the second surfaces BC_Sof the contact patterns BC may be higher than the portions of the bottom surfaces of the channel trenches CH_T defined by the contact separation insulating film.

235 3 3 235 3 235 235 235 The contact separation insulating filmmay include first regions that overlap with the channel trenches CH_T in the third direction DR, and second regions that do not overlap with the channel trenches CH_T in the third direction DR. The contact separation insulating filmmay include a first surface and a second surface opposite to each other in the third direction DR. The first surface of the contact separation insulating filmmay face the data storage patterns DSP. Relative to the first surface of the contact separation insulating film, the second surface of the contact separation insulating filmis lower in the first regions than in the second regions.

175 175 173 175 175 173 175 175 The sidewalls of the channel trenches CH_T may be defined by the lower protruding insulating patternsB, the upper protruding insulating patternsU, and the second etch stop film. At least parts of the sidewalls of the channel trenches CH_T may be sidewallsSW of the protruding insulating patterns. If the second etch stop filmis not present, the sidewalls of the channel trenches CH_T may be defined by the lower protruding insulating patternsB and the upper protruding insulating patternsU.

1 2 1 100 2 100 The first channel patterns APand the second channel patterns APmay be disposed on the data storage patterns DSP. The data storage patterns DSP may be disposed between the first channel patterns APand the substrate. The data storage patterns DSP may be disposed between the second channel patterns APand the substrate.

1 2 1 2 1 2 2 The first channel patterns APand the second channel patterns APmay be disposed on the contact patterns BC. The first channel patterns APand the second channel patterns APmay be connected to the contact patterns BC, respectively. The first channel patterns APand the second channel patterns APmay be connected to the second surfaces BC_Sof the contact patterns BC, respectively.

1 1 1 2 1 2 1 2 2 1 2 1 2 The first channel patterns APmay be spaced apart from one another in the first direction DR. The first channel patterns APmay be spaced apart at regular intervals. The second channel patterns APmay be spaced apart from one another in the first direction DR. The second channel patterns APmay be spaced apart at regular intervals. The first channel patterns APmay be spaced apart from the second channel patterns APin the second direction DR. The first channel patterns APand the second channel patterns APmay be arranged two-dimensionally along the first and second directions DRand DR.

1 2 1 1 2 The first channel patterns APand the second channel patterns APmay be disposed within the channel trenches CH_T that extend in the first direction DR. A plurality of first channel patterns APmay be disposed within a single channel trench CH_T. A plurality of second channel patterns APmay be disposed within a single channel trench CH_T.

1 2 1 2 3 1 2 1 The first channel patterns APand the second channel patterns APmay cover parts of the sidewalls BC_SW of the contact patterns BC. The first channel patterns APand the second channel patterns APmay extend in the third direction DRalong the sidewalls BC_SW of the contact patterns BC. The first channel patterns APand the second channel patterns APmay not extend to the first surfaces BC_Sof the contact patterns BC.

1 2 In the semiconductor memory device according to one or more embodiments of the present disclosure, the first channel patterns APand the second channel patterns APmay each include a vertical portion AP_V, a horizontal portion AP_H, a contact cover portion AP_CC, and a bottom portion AP_B.

1 2 3 2 1 2 1 2 175 175 The vertical portions AP_V of the channel patterns (APand AP) may protrude in the third direction DRfrom the second surfaces BC_Sof the contact patterns BC. The vertical portions AP_V of the channel patterns (APand AP) may extend along the sidewalls of the channel trenches CH_T. The vertical portions AP_V of the channel patterns (APand AP) may extend along the sidewallsSW of the protruding insulating patterns.

1 2 2 1 2 1 2 1 2 2 The horizontal portions AP_H of the channel patterns (APand AP) may extend along the second surfaces BC_Sof the contact patterns BC. The horizontal portions AP_H of the channel patterns (APand AP) may be directly connected to the vertical portions AP_V of the channel patterns (APand AP). From a cross-sectional perspective, the horizontal portions AP_H of the channel patterns (APand AP) may protrude in the second direction DRfrom the vertical portions AP_V.

1 2 1 2 3 1 2 1 The contact cover portions AP_CC of the channel patterns (APand AP) may be disposed on the sidewalls BC_SW of the contact patterns BC. The contact cover portions AP_CC of the channel patterns (APand AP) may extend in the third direction DRalong the sidewalls BC_SW of the contact patterns BC. The contact cover portions AP_CC of the channel patterns (APand AP) may not extend to the first surfaces BC_Sof the contact patterns BC.

1 2 1 2 The contact cover portions AP_CC of the channel patterns (APand AP) may cover the sidewalls BC_SW of the contact patterns BC. For example, the contact cover portions AP_CC of the channel patterns (APand AP) may cover parts of the sidewalls BC_SW of the contact patterns BC.

1 2 1 2 1 2 From a planar perspective, the contact cover portions AP_CC of the channel patterns (APand AP) may extend along the outer circumferential surfaces BC_CS of the contact patterns BC. For example, the contact cover portions AP_CC of the channel patterns (APand AP) may extend along parts of the outer circumferential surfaces BC_CS of the contact patterns BC. The contact cover portions AP_CC of the channel patterns (APand AP) do not extend along the rest of the outer circumferential surfaces BC_CS of the contact patterns BC.

1 2 235 235 The bottom portions AP_B of the channel patterns (APand AP) may be disposed on the second surface of the contact separation insulating film. The bottom portions AP_B may extend along the second surface of the contact separation insulating film.

6 FIG. 22 1 1 2 21 1 2 In, a width W, in the first direction DR, of the channel patterns (APand AP) may be greater than a width W, in the first direction DR, of the second surfaces BC_Sof the contact patterns BC.

8 FIG. 8 FIG. 6 FIG. 22 1 2 21 2 1 2 In, the width Wof the channel patterns (APand AP) may be less than or equal to the width Wof the second surfaces BC_Sof the contact patterns BC. The perspective view of the shape of the channel patterns (APand AP) ofmay be similar to that shown in.

1 2 1 2 1 2 1 2 1 2 1 2 The first channel patterns APand the second channel patterns APmay each include an oxide semiconductor material. The first channel patterns APand the second channel patterns APmay include, for example, a metal oxide. For example, the first channel patterns APand the second channel patterns APmay be amorphous metal oxide films. In another example, the first channel patterns APand the second channel patterns APmay be polycrystalline metal oxide films. In yet another example, the first channel patterns APand the second channel patterns APmay be a combination of amorphous metal oxide films and polycrystalline metal oxide films. In still another example, the first channel patterns APand the second channel patterns APmay be c-axis aligned crystalline (CAAC) metal oxide films.

1 2 The first channel patterns APand the second channel patterns APmay include, for example, indium oxide, tin oxide, zinc oxide, In—Zn-based oxide (IZO), Sn—Zn-based oxide, Al—Zn-based oxide, Zn—Mg-based oxide, Sn—Mg-based oxide, In—Mg-based oxide, In—Ga-based oxide (IGO), In—Ga—Zn-based oxide (IGZO), In—Al—Zn-based oxide, In—Sn—Zn-based oxide, Sn—Ga—Zn-based oxide, Al—Ga—Zn-based oxide, Sn—Al—Zn-based oxide, In—Hf—Zn-based oxide, In—La—Zn-based oxide, In—Ce—Zn-based oxide, In—Pr—Zn-based oxide, In—Nd—Zn-based oxide, In—Sm—Zn-based oxide, In—Eu—Zn-based oxide, In—Gd—Zn-based oxide, In—Tb—Zn-based oxide, In—Dy—Zn-based oxide, In—Ho—Zn-based oxide, In—Er—Zn-based oxide, In—Tm—Zn-based oxide, In—Yb—Zn-based oxide, In—Lu—Zn-based oxide, In—Sn—Ga—Zn-based oxide, In—Hf—Ga—Zn-based oxide, In—Al—Ga—Zn-based oxide, In—Sn—Al—Zn-based oxide, In—Sn—Hf—Zn-based oxide, or In—Hf—Al—Zn-based oxide, but the present disclosure is not limited thereto.

x y z Here, In—Ga—Zn-based oxide refers to an oxide having In, Ga, and Zn as its main components, but not necessarily the ratio of In, Ga, and Zn. For example, the channel structures AP_ST may include InGaZnO. IGZO (In:Ga:Zn=1:1:1) with In, Ga, and Zn included in the same ratios may be an In—Ga—Zn-based oxide. Ga-rich IGZO has a higher Ga ratio and a lower In ratio than IGZO (In:Ga:Zn=1:1:1). Ga-rich IGZO may also be an In—Ga—Zn-based oxide. Additionally, In-rich IGZO has a higher In ratio and a lower Ga ratio than IGZO (In:Ga:Zn=1:1:1). In-rich IGZO may also be an In—Ga—Zn-based oxide.

1 2 1 2 1 2 1 2 The first channel patterns APand the second channel patterns APhave been described above as including IGZO, but the present disclosure is not limited thereto. The above description may also be applicable if the first channel patterns APand the second channel patterns APeach include a ternary or higher metal oxide. Additionally, if the first channel patterns APand the second channel patterns APinclude an In—Ga—Zn-based oxide, the first channel patterns APand the second channel patterns APmay further include a doped metal element other than In, Ga, and Zn.

1 1 2 2 1 2 The first wordlines WLmay be disposed on the first channel patterns AP. The second wordlines WLmay be disposed on the second channel patterns AP. The first wordlines WLand the second wordlines WLmay be disposed within the channel trenches CH_T.

1 2 1 1 2 2 1 2 2 The first wordlines WLand the second wordlines WLmay extend in the first direction DR. The first wordlines WLand the second wordlines WLmay be alternately arranged in the second direction DR. The first wordlines WLmay be spaced apart from the second wordlines WLin the second direction DR.

1 2 3 1 2 1 2 3 The first wordlines WLand the second wordlines WLmay be spaced apart from the bitlines BL in the third direction DR. The first wordlines WLand the second wordlines WLintersect the bitlines BL. The first wordlines WLand the second wordlines WLmay be spaced apart from the contact patterns BC in the third direction DR.

1 2 1 2 1 2 1 2 The first wordlines WLand the second wordlines WLmay be disposed on the horizontal portions AP_H of the channel patterns (APand AP). The first wordlines WLand the second wordlines WLmay be disposed between the vertical portions AP_V of the first channel patterns APand the vertical portions AP_V of the second channel patterns AP.

1 2 1 2 1 1 2 2 2 1 The first wordlines WLand the second wordlines WLmay be disposed between the first channel patterns APand the second channel patterns AP. The first channel patterns APmay be closer to the first wordlines WLthan to the second wordlines WL. The second channel patterns APmay be closer to the second wordlines WLthan to the first wordlines WL.

1 2 2 1 1 2 3 1 2 3 2 1 2 3 1 2 3 The first wordlines WLand the second wordlines WLmay have a width in the second direction DR. The width of the first wordlines WLmay differ between the areas where the first channel patterns APand the second channel patterns APoverlap in the third direction DRand the areas where the first channel patterns APand the second channel patterns APmay not overlap in the third direction DR. Similarly, the width of the second wordlines WLmay differ between the areas where the first channel patterns APand the second channel patterns APoverlap in the third direction DRand the areas where the first channel patterns APand the second channel patterns APmay not overlap in the third direction DR.

1 2 2 1 2 2 1 2 1 2 1 2 For example, the first wordlines WLand the second wordlines WLmay each include first portions WLa and second portions WLb. The width, in the second direction DR, of the first portions WLa of the wordlines (WLand WL) may be smaller than the width, in the second direction DR, of the second portions WLb of the wordlines (WLand WL). For example, the first portions WLa of the wordlines (WLand WL) may be disposed on the first channel patterns APand the second channel patterns AP.

1 2 1 1 1 1 2 1 2 2 1 2 1 The first wordlines WLand the second wordlines WLmay each include first portions WLa and second portions WLb that are alternately arranged in the first direction DR. In the first wordlines WL, the first channel patterns APmay be disposed among the second portions WLb of the wordlines (WLand WL) that are adjacent in the first direction DR. In the second wordlines WL, the second channel patterns APmay be disposed among the second portions WLb of the wordlines (WLand WL) that are adjacent in the first direction DR.

2 1 2 2 1 2 1 1 2 1 Alternatively, the width, in the second direction DR, of the first portions WLa of the wordlines (WLand WL) may be the same as the width, in the second direction DR, of the second portions WLb of the wordlines (WLand WL). In this case, a gate insulating film GOX, which will be described later, may fill the space between each pair of adjacent first channel patterns APin the first direction DRand the space between each pair of adjacent second channel patterns APin the first direction DR.

1 2 1 2 1 2 1 2 1 2 1 2 1 2 The first channel patterns APand the second channel patterns APmay not disposed below the second portions WLb of the wordlines (WLand WL). The height of the first portions WLa of the wordlines (WLand WL) may be less than the height of the second portions WLb of the wordlines (WLand WL). For example, the height difference between the first portions WLa of the wordlines (WLand WL) and the second portions WLb of the wordlines (WLand WL) may be equal to the thickness of the channel patterns (APand AP).

1 2 The first wordlines WLand the second wordlines WLmay include a conductive material, such as doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, a 2D material, a metal, or a metal alloy.

1 2 3 1 2 2 Each of the first wordlines WLand the second wordlines WLmay include an upper surface WL_US and a lower surface in the third direction DR. The lower surfaces of the first wordlines WLand the second wordlines WLface the second surfaces BC_Sof the contact patterns BC.

5 FIG. 1 2 1 2 1 2 In, the upper surfaces WL_US of the wordlines (WLand WL) may be planar. Alternatively, the upper surfaces WL_US of the wordlines (WLand WL) may be convexly rounded. As another alternative, the upper surfaces WL_US of the wordlines (WLand WL) may be concavely rounded.

3 5 FIGS.and 2 1 2 1 2 12 2 1 2 14 2 1 2 The following description is provided from the perspective of a cross-sectional view such as. Based on the second surfaces BC_Sof the contact patterns BC, the upper surfaces WL_US of the wordlines (WLand WL) may be equal to or higher than uppermost surfaces AP_UUS of the first channel patterns APand uppermost surfaces AP_UUS of the second channel patterns AP. A height Hfrom the second surfaces BC_Sof the contact patterns BC to the uppermost surfaces AP_UUS of the channel patterns (APand AP) may be less than or equal to a height Hfrom the second surfaces BC_Sof the contact patterns BC to the upper surfaces WL_US of the wordlines (WLand WL).

2 1 2 175 175 12 2 1 2 11 2 175 175 Based on the second surfaces BC_Sof the contact patterns BC, the uppermost surfaces AP_UUS of the first channel patterns APand the uppermost surfaces AP_UUS of the second channel patterns APmay be lower than the upper surfaces_US of the protruding insulating patterns. The height Hfrom the second surfaces BC_Sof the contact patterns BC to the uppermost surfaces AP_UUS of the channel patterns (APand AP) is less than a height Hfrom the second surfaces BC_Sof the contact patterns BC to the upper surfaces_US of the protruding insulating patterns.

1 1 2 2 1 1 2 The gate insulating film GOX may be disposed between the first wordlines WLand the first channel patterns AP, and between the second wordlines WLand the second channel patterns AP. The gate insulating film GOX may extend in the first direction DRparallel to the first wordlines WLand the second wordlines WL.

5 FIG. 1 2 2 In a cross-sectional view such as, the horizontal portions AP_H of the channel patterns (APand AP) may be disposed between the gate insulating film GOX and the contact patterns BC, and thus, the gate insulating film GOX may not contact the second surfaces BC_Sof the contact patterns BC.

1 2 1 1 2 2 1 1 2 2 The gate insulating film GOX may extend along the vertical portions AP_V of the channel patterns (APand AP). From a cross-sectional perspective, the gate insulating film GOX between the first wordlines WLand the first channel patterns APmay be directly connected to the gate insulating film GOX between the second wordlines WLand the second channel patterns AP. Alternatively, the gate insulating film GOX between the first wordlines WLand the first channel patterns APmay be separated from the gate insulating film GOX between the second wordlines WLand the second channel patterns AP.

The gate insulating film GOX may include a silicon oxide film, a silicon oxynitride film, a high-k dielectric film with a higher dielectric constant than a silicon oxide film, or a combination thereof. For example, the gate insulating film GOX may include aluminum oxide, but the present disclosure is not limited thereto.

3 1 2 3 1 2 Part of the gate insulating film GOX may protrude in the third direction DRbeyond the upper surfaces WL_US of the first wordlines WLand the upper surfaces WL_US of the second wordlines WL. Part of the gate insulating film GOX may protrude in the third direction DRbeyond the uppermost surfaces AP_UUS of the first channel patterns APand the uppermost surfaces AP_UUS of the second channel patterns AP.

13 2 12 2 1 2 13 2 14 2 1 2 A height Hfrom the second surfaces BC_Sof the contact patterns BC to an uppermost surface GOX_UUS of the gate insulating film GOX may be greater than the height Hfrom the second surfaces BC_Sof the contact patterns BC to the uppermost surfaces AP_UUS of the channel patterns (APand AP). The height Hfrom the second surfaces BC_Sof the contact patterns BC to the uppermost surface GOX_UUS of the gate insulating film GOX may be greater than the height Hfrom the second surfaces BC_Sof the contact patterns BC to the upper surfaces WL_US of the wordlines (WLand WL).

1 2 1 2 1 2 1 1 2 Gate separation patterns GSS may be disposed between the first wordlines WLand the second wordlines WLthat are adjacent to the first wordlines WLin the second direction DR. The first wordlines WLand the second wordlines WLmay be separated by the gate separation patterns GSS. The gate separation patterns GSS may extend in the first direction DRbetween the first wordlines WLand the second wordlines WL.

1 1 2 2 The first wordlines WLmay be disposed between the gate separation patterns GSS and the first channel patterns AP. The second wordlines WLmay be disposed between the gate separation patterns GSS and the second channel patterns AP.

2 175 175 175 175 In the semiconductor memory device according to one or more embodiments of the present disclosure, relative to the second surfaces BC_Sof the contact patterns BC, the upper surfaces of the gate separation patterns GSS may be at the same height as the upper surfaces_US of the protruding insulating patterns. For example, the gate separation patterns GSS may not be disposed on the upper surfaces_US of the protruding insulating patterns.

The gate separation patterns GSS may be formed of an insulating material. The gate separation patterns GSS are illustrated as being single layers, but the present disclosure is not limited thereto.

1 2 1 2 1 2 The bitlines BL may be disposed on the first channel patterns APand the second channel patterns AP. The bitlines BL may be connected to the first channel patterns APand the second channel patterns AP. The bitlines BL may be connected to the vertical portions AP_V of the first channel patterns AP. The bitlines BL may be connected to the vertical portions AP_V of the second channel patterns AP.

2 1 The bitlines BL may extend in the second direction DR. The bitlines BL may be spaced apart from one another in the first direction DR.

In the semiconductor memory device according to one or more embodiments of the present disclosure, the data storage patterns DSP may be disposed between the peripheral gate structures PG and the bitlines BL.

2 1 175 The bitlines BL may include extension portions BLe and protruding portions BLp. The extension portions BLe of the bitlines BL may extend in the second direction DR. In the semiconductor memory device according to one or more embodiments of the present disclosure, the width of the extension portions BLe of the bitlines BL in the first direction DRmay decrease away from the protruding insulating patternsand the gate separation patterns GSS. For example, the extension portions BLe of the bitlines BL may be formed through a subtractive etching process.

3 1 2 The protruding portions BLp of the bitlines BL may protrude in the third direction DR. The protruding portions BLp of the bitlines BL may protrude from the extension portions BLe of the bitlines BL toward the first channel patterns AP. The protruding portions BLp of the bitlines BL may protrude from the extension portions BLe of the bitlines BL toward the second channel patterns AP.

1 2 1 2 2 The protruding portions BLp of the bitlines BL may be connected to the first channel patterns APand the second channel patterns AP. The protruding portions BLp of the bitlines BL may connect the first channel patterns APand the extension portions BLe of the bitlines BL. The protruding portions BLp of the bitlines BL may connect the second channel patterns APand the extension portions BLe of the bitlines BL. Based on the second surfaces BC_Sof the contact patterns BC, the protruding portions BLp of the bitlines BL may include the lowermost portions of the bitlines BL.

1 2 The protruding portions BLp of the bitlines BL may include first sub-protruding portions BLpand second sub-protruding portions BLp.

1 1 2 1 1 2 1 175 The first sub-protruding portions BLpof the bitlines BL may be connected to the first channel patterns APand the second channel patterns AP. For example, the first sub-protruding portions BLpof the bitlines BL may contact the first channel patterns APand the second channel patterns AP. For example, from a cross-sectional perspective, the first sub-protruding portions BLpof the bitlines BL may be disposed between the gate insulating film GOX and the protruding insulating patterns.

2 1 2 175 The second sub-protruding portions BLpof the bitlines BL may be disposed between the first sub-protruding portions BLpof the bitlines BL and the extension portions BLe of the bitlines BL. For example, from a cross-sectional perspective, the second sub-protruding portions BLpof the bitlines BL may be disposed between the gate separation patterns GSS and the protruding insulating patterns.

12 2 2 11 2 1 A width W, in the second direction DR, of the second sub-protruding portions BLpof the bitlines BL may be greater than a width W, in the second direction DR, of the first sub-protruding portions BLpof the bitlines BL.

The bitlines BL may include at least one of a doped semiconductor material, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, a 2D material, and a metal. The bitlines BL are illustrated as being single-layered, but the present disclosure is not limited thereto.

3 5 FIG.or 12 2 1 2 2 12 2 11 2 175 175 In a cross-sectional view such as, the height Hfrom the second surfaces BC_Sof the contact patterns BC to the uppermost surfaces AP_UUS of the channel patterns (APand AP) may be the same as the height from the second surfaces BC_Sof the contact patterns BC to the lowermost parts of the bitlines BL. The height Hfrom the second surfaces BC_Sof the contact patterns BC to the lowermost parts of the bitlines BL may be less than the height Hfrom the second surfaces BC_Sof the contact patterns BC to the upper surfaces_US of the protruding insulating patterns.

3 12 2 2 3 1 2 12 3 The distance, in the third direction DR, between the contact patterns BC and the bitlines BL may be the height Hfrom the second surfaces BC_Sof the contact patterns BC to the lowermost parts of the bitlines BL. The height Hin the third direction DRof the channel patterns (APand AP) may be greater than the distance (i.e., the height H), in the third direction DR, between the contact patterns BC and the bitlines BL.

1 2 1 2 13 2 12 2 1 2 Alternatively, the protruding portions BLp of the bitlines BL may not include the first sub-protruding portions BLp. In this case, the second sub-protruding portions BLpof the bitlines BL may contact the first channel patterns APand the second channel patterns AP, and the height Hfrom the second surfaces BC_Sof the contact patterns BC to the uppermost surface GOX_UUS of the gate insulating film GOX may be greater than the height Hfrom the second surfaces BC_Sof the contact patterns BC to the uppermost surfaces AP_UUS of the channel patterns (APand AP).

264 265 264 264 265 The extension portions BLe of the bitlines BL may be disposed within a second interlayer insulating film. A third interlayer insulating filmmay be disposed on the bitlines BL and the second interlayer insulating film. The second and third interlayer insulating filmsandmay each include an insulating material.

9 12 FIGS.through 9 12 FIGS.through 1 8 FIGS.through are cross-sectional or plan views for explaining a semiconductor memory device according to one or more embodiments of the present disclosure. For convenience of explanation, the embodiment ofwill hereinafter be described, focusing mainly on the differences from what has been described above with reference to.

9 FIG. 2 FIG. 10 FIG. 9 FIG. 11 FIG. 9 FIG. 12 FIG. 11 FIG. is a cross-sectional view, taken along lines A-A and B-B of.is an enlarged cross-sectional view of part P of.is a plan view for explaining the shape in which channel patterns are disposed on contact patterns in.is a perspective view for explaining the shape of the channel patterns of.

9 12 FIGS.through 1 2 1 2 Referring to, channel patterns (APand AP), in a semiconductor memory device according to one or more embodiments, first channel patterns APand second channel patterns APmay include vertical portions AP_V and contact cover portions AP_CC.

1 2 7 FIG. The first channel patterns APand the second channel patterns APmay not include the horizontal portions AP_H and bottom portions AP_B of.

1 2 1 2 1 2 1 2 22 1 1 2 21 1 2 The contact cover portions AP_CC of the channel patterns (APand AP) may be directly connected to the vertical portions AP_V of the channel patterns (APand AP). For the contact cover portions AP_CC of the channel patterns (APand AP) to be connected to the vertical portions AP_V of the channel patterns (APand AP), a width W, in a first direction DR, of the first channel patterns and the second channel patterns (APand AP) is greater than a width W, in the first direction DR, of second surfaces BC_Sof contact patterns BC.

10 FIG. 1 2 2 In a cross-sectional view such as, the horizontal portions AP_H of the channel patterns (APand AP) may not be disposed between a gate insulating film GOX and the contact patterns BC. The gate insulating film GOX may contact the second surfaces BC_Sof the contact patterns BC.

13 FIG. 14 FIG. 15 FIG. 16 FIG. 13 16 FIGS.through 1 8 FIGS.through is a cross-sectional view for explaining a semiconductor memory device according to one or more embodiments of the present disclosure.is a cross-sectional view for explaining a semiconductor memory device according to one or more embodiments of the present disclosure.is a cross-sectional view for explaining a semiconductor memory device according to one or more embodiments of the present disclosure.is a cross-sectional view for explaining a semiconductor memory device according to one or more embodiments of the present disclosure. For convenience of explanation, the embodiments ofwill hereinafter be described, focusing mainly on the differences from what has been described above with reference to.

13 15 FIGS.through 2 FIG. 16 FIG. 2 FIG. are cross-sectional views taken along lines A-A and B-B of.is a cross-sectional view taken along lines C-C and D-D of.

13 15 FIGS.through 175 Referring to, in the semiconductor memory devices according to one or more embodiments of the present disclosure, residual patterns GOX_R of a gate insulating film GOX may be disposed between protruding insulating patternsand bitlines BL.

175 175 175 175 175 175 The residual patterns GOX_R of the gate insulating film GOX may extend along upper surfaces_US of protruding insulating patterns. The residual patterns GOX_R of the gate insulating film GOX may be directly connected to the gate insulating film GOX. In this case, the residual patterns GOX_R of the gate insulating film GOX may be portions of the gate insulating film GOX disposed on the upper surfaces_US of the protruding insulating patterns. The gate insulating film GOX may include portions disposed below the upper surfaces_US of the protruding insulating patterns.

The residual patterns GOX_R of the gate insulating film GOX may include the same material as the gate insulating film GOX.

13 FIG. 175 In, the residual patterns GOX_R of the gate insulating film GOX may contact the bitlines BL and the protruding insulating patterns.

14 FIG. 1 2 175 1 2 1 2 In, residual patterns AP_R of channel patterns (APand AP) may be disposed between the residual patterns GOX_R of the gate insulating film GOX and the protruding insulating patterns. The residual patterns AP_R of the channel patterns (APand AP) may include the same material as the channel patterns (APand AP).

15 FIG. 175 175 In, parts of gate separation patterns GSS may be disposed on upper surfaces_US of protruding insulating patterns.

16 FIG. 1 175 Referring to, a width, in a first direction DR, of extension portions BLe of bitlines BL may increase away from protruding insulating patternsand gate separation patterns GSS.

For example, the extension portions BLe of the bitlines BL may be formed through a damascene process.

17 18 FIGS.and 19 20 FIGS.and 17 20 FIGS.through 1 8 FIGS.through are cross-sectional views for explaining a semiconductor memory device according to one or more embodiments of the present disclosure.are cross-sectional views for explaining a semiconductor memory device according to one or more embodiments of the present disclosure. For convenience of explanation, the embodiments ofwill hereinafter be described, focusing mainly on the differences from what has been described above with reference to.

17 18 FIGS.and 1 2 Referring to, the semiconductor memory device according to one or more embodiments of the present disclosure may further include first bonding pads BPand second bonding pads BP.

1 1 243 The first bonding pads BPmay be disposed on peripheral gate structures PG. The first bonding pads BPmay be connected to peripheral connection wirings.

1 1 243 1 1 243 First pad plugs BPLGmay be disposed between the first bonding pads BPand the peripheral connection wirings. The first pad plugs BPLGmay connect the first bonding pads BPand the peripheral connection wirings.

1 263 1 266 266 263 The first pad plugs BPLGmay be disposed within a first interlayer insulating film. The first bonding pads BPmay be disposed within a fourth interlayer insulating film. The fourth interlayer insulating filmmay be disposed on the first interlayer insulating film.

2 1 2 1 2 1 The second bonding pads BPmay be disposed on the first bonding pads BP. The second bonding pads BPmay be connected to the first bonding pads BP. The second bonding pads BPmay contact the first bonding pads BP.

2 2 2 1 2 2 Second pad plugs BPLGmay connect the bitlines BL to the second bonding pads BP. The second pad plugs BPLGmay connect first wordlines WLand second wordlines WLto the second bonding pads BP.

2 265 2 267 267 265 266 266 267 263 The second pad plugs BPLGmay be disposed within a third interlayer insulating film. The second bonding pads BPmay be disposed within a fifth interlayer insulating film. The fifth interlayer insulating filmmay be disposed between the third interlayer insulating filmand the fourth interlayer insulating film. The fourth interlayer insulating filmmay be disposed between the fifth interlayer insulating filmand the first interlayer insulating film.

1 2 1 2 266 267 The first pad plugs BPLGand the second pad plugs BPLGmay each include a conductive material containing metal. The first bonding pads BPand the second bonding pads BPmay each include a conductive material containing metal. The fourth and fifth interlayer insulating filmsandmay each include an insulating material.

1 2 A bonding insulating film may be disposed along the boundaries of the first bonding pads BPand the second bonding pads BP. For example, the bonding insulating film may include silicon carbonitride (SiCN). In another example, the bonding insulating film may include silicon oxide.

In the semiconductor memory device according to one or more embodiments of the present disclosure, the bitlines BL may be disposed between data storage patterns DSP and peripheral gate structures PG.

19 20 FIGS.and 100 Referring to, in the semiconductor memory device according to one or more embodiments of the present disclosure, peripheral gate structures PG may not be disposed in a cell array region CAR of a substrate.

100 The peripheral gate structures PG may be disposed only in a peripheral circuit region PCR of the substrate.

21 24 FIGS.through 21 24 FIGS.through 1 FIGS. 8 are layout views for explaining semiconductor memory devices according to one or more embodiments of the present disclosure. For convenience of explanation, the embodiments ofwill hereinafter be described, focusing mainly on the differences from what has been described above with reference tothrough.

21 FIG. 3 FIG. 1 2 1 2 100 Referring to, in the semiconductor memory device according to one or more embodiments of the present disclosure, first channel patterns APand second channel patterns APmay be alternately arranged in a diagonal direction relative to a first direction DRand a second direction DR. Here, the diagonal direction may be parallel to the upper surface of a substrateas illustrated in.

1 2 1 2 The first channel patterns APand the second channel patterns APmay be formed twisted in the diagonal direction. From a planar perspective, the first channel patterns APand the second channel patterns APmay each have a parallelogram or rhomboid shape.

22 FIG. Referring to, in the semiconductor memory device according to one or more embodiments of the present disclosure, contact patterns BC and data storage patterns DSP may be arranged in a zigzag or honeycomb shape from a planar perspective.

23 FIG. Referring to, in the semiconductor memory device according to one or more embodiments of the present disclosure, data storage patterns DSP may be arranged to deviate from contact patterns BC from a planar perspective.

The data storage pattern DSP may contact parts of the contact patterns BC.

24 FIG. 1 2 Referring to, in the semiconductor memory device according to one or more embodiments of the present disclosure, contact patterns BC, which are disposed on first channel patterns APand second channel patterns AP, may have a semicircular or semi-elliptical shape from a planar perspective.

From a planar perspective, the contact patterns BC may be arranged symmetrically to one another.

25 36 FIGS.through are cross-sectional views for explaining a method of manufacturing a semiconductor memory device according to one or more embodiments of the present disclosure.

25 26 FIGS.and 235 Referring to, a contact separation insulating filmmay be formed on a sub-substrate.

235 Contact patterns BC may be formed within the contact separation insulating film. The contact patterns BC may be formed on the sub-substrate.

235 Data storage patterns DSP may be formed on the contact patterns BC and the contact separation insulating film.

100 100 263 Thereafter, the sub-substrate on which the data storage patterns DSP and the contact patterns BC are formed may be bonded to a substrate. The data storage patterns DSP and the substratemay be bonded by a first interlayer insulating film.

100 100 100 3 FIG. Alternatively, before the bonding of the sub-substrate to the substrate, peripheral gate structures PG as illustrated inmay be formed on the substrate. In this case, the sub-substrate on which the data storage patterns DSP and the contact patterns BC are formed may be bonded to the substrateon which the peripheral gate structures PG are formed.

100 After the sub-substrate and the substrateare bonded together, the sub-substrate may be removed.

175 235 175 1 175 235 Thereafter, protruding insulating patternsmay be formed on the contact patterns BC and the contact separation insulating film. Channel trenches CH_T may be formed within the protruding insulating patterns. The channel trenches CH_T may extend in a first direction DR. As a result, the protruding insulating patterns, including channel trenches CH_T, may be formed on the contact patterns BC and the contact separation insulating film.

27 FIG. 235 Referring to, parts of the contact separation insulating filmexposed by the channel trenches CH_T may be removed through an etching process.

During the etching process, parts of the sidewalls of the contact patterns BC overlapping with the channel trenches CH_T may be exposed.

235 3 235 In the areas where the contact separation insulating filmoverlaps with the channel trenches CH_T in a third direction DR, the thickness of the contact separation insulating filmmay become thinner. As a result, parts of the sidewalls of the contact patterns BC may be exposed.

28 FIG. Referring to, a first channel film AP_P may be formed along the sidewalls and bottom surfaces of the channel trenches CH_T.

175 The first channel film AP_P may be formed along the upper surfaces of the protruding insulating patterns.

29 30 FIGS.and 28 FIG. Referring to, channel etching mask patterns AP_MASK may be formed on the first channel film AP_P of.

1 The first channel film AP_P may be patterned using channel etching mask patterns AP_MASK to form a second channel film AP_P.

29 FIG. 2 1 In, the channel etching mask patterns AP_MASK may have a contact-type shape. For example, from a planar perspective, the channel etching mask patterns AP_MASK may have a rectangular or square shape. The first channel film AP_P, which may be disposed between each pair of adjacent contact patterns BC in a second direction DRexposed by the channel trenches CH_T, may be removed. For example, from a planar perspective, the second channel film AP_Pmay have a rectangular or square shape.

30 FIG. 29 32 FIGS.through 2 2 1 2 In, the channel etching mask patterns AP_MASK may have a linear shape. For example, from a planar perspective, the channel etching mask patterns AP_MASK may have a linear shape extending in the second direction DR. The channel etching mask pattern AP_MASK may intersect the channel trenches CH_T. The first channel film AP_P, disposed between each pair of adjacent contact patterns BC in the second direction DRexposed by the channel trenches CH_T, may not be removed. For example, from a planar perspective, the second channel film AP_Pmay have a linear shape extending in the second direction DR. Referring to, the channel etching mask patterns AP_MASK

are removed.

1 The channel etching mask patterns AP_MASK are removed, exposing the second channel films AP_P.

29 31 FIGS.and 1 1 In, the second channel film AP_Pon one sidewall of each of the channel trenches CH_T may be separated from the second channel film AP_Pon the opposite sidewall of each of the channel trenches CH_T.

30 32 FIGS.and 1 1 In, the second channel film AP_Pon one sidewall of each of the channel trenches CH_T may be directly connected to the second channel films AP_Pon the opposite sidewall of each of the channel trenches CH_T.

31 34 FIGS.through 1 1 2 Referring to, the second channel film AP_Pmay be patterned to form first channel patterns APand second channel patterns APwithin the channel trenches CH_T.

31 33 FIGS.and 1 175 1 175 1 2 2 1 2 In, sacrificial patterns may be formed within the channel trenches CH_T. The sacrificial patterns may expose the second channel film AP_Pon the upper surfaces of the protruding insulating patterns. Using the sacrificial patterns as an etching mask, the second channel film AP_Pmay be removed from above the upper surfaces of the protruding insulating patterns. Through this process, the first channel patterns APand the second channel patterns AP, spaced apart from one another in the second direction DR, may be formed within the channel trenches CH_T. After the first channel patterns APand the second channel patterns APare formed, the sacrificial patterns are removed.

32 34 FIGS.and 1 175 1 175 1 2 1 235 1 2 2 Referring to, the second channel film AP_Pmay be removed from above the upper surfaces of the protruding insulating patternsthrough an etch-back process. During the removal of the second channel film AP_Pfrom above the upper surface of the protruding insulating pattern, the second channel film AP_Pmay also be removed from above second surfaces BC_Sof contact patterns BC. Additionally, the second channel film AP_Pmay also be removed from above the second surface of the contact separation insulating film. As a result, the first channel patterns APand the second channel patterns AP, spaced apart in the second direction DR, may be formed within the channel trenches CH_T.

1 2 33 FIG. Subsequent manufacturing process will be described using the shapes of the first channel patterns APand the second channel patterns APof.

1 175 1 175 Alternatively, the subsequent manufacturing processes may proceed with the second channel film AP_Premaining on the upper surfaces of the protruding insulating patterns. The resistance of channels, formed of a metal oxide semiconductor, increases in their off-state. Therefore, even if the second channel film AP_Premains on the upper surfaces of the protruding insulating patterns, it may not affect the operation of other memory cells.

35 FIG. 1 2 Referring to, a gate insulating film GOX may be formed on the first channel patterns APand the second channel patterns AP.

1 2 1 2 33 FIG. First wordlines WLand second wordlines WLmay be formed on the gate insulating film GOX. The first wordlines WLand the second wordlines WLmay be formed within the channel trenches CH_T of.

1 2 175 Thereafter, gate separation patterns GSS may be formed on the first wordlines WLand the second wordlines WL. The gate separation patterns GSS may fill the channel trenches CH_T. Portions of the gate separation patterns GSS may be formed on the upper surfaces of the protruding insulating patterns.

35 36 FIGS.and 175 Referring to, portions of the gate separation patterns GSS may be removed to expose the protruding insulating patterns.

175 175 While the protruding insulating patternsare being exposed, the gate insulating film GOX may also be removed from above the upper surfaces of the protruding insulating patterns.

3 FIG. 1 2 Thereafter, referring to, bitlines BL may be formed on the first channel patterns APand the second channel patterns AP.

175 175 175 1 2 Alternatively, the gate insulating film GOX may not be removed from above the upper surfaces of the protruding insulating patternswhile the protruding insulating patternsare being exposed. With the gate insulating film GOX kept in place above the upper surfaces of the protruding insulating patterns, the bitlines BL may be formed on the first channel patterns APand the second channel patterns AP.

1 2 175 As another alternative, the bitlines BL may be formed on the first channel patterns APand the second channel patterns APwithout removing the gate separation patterns GSS from above the upper surfaces of the protruding insulating patterns.

Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments, and may be fabricated in various forms. Those skilled in the art will appreciate that the present disclosure may be embodied in other specific forms without changing the technical spirit or essential features of the present disclosure. Accordingly, the above-described embodiments should be understood in all respects as illustrative and not restrictive.