Charge Coupled Field Effect Rectifier Diode and Method of Making

This application is a divisional of U.S. application for patent Ser. No. 17/730,895, filed Apr. 27, 2022, which claims priority from U.S. Provisional Application for Patent No. 63/197,599 filed Jun. 7, 2021, the disclosures of which are incorporated herein by reference.

The present invention generally relates to charge coupled integrated circuit devices and, in particular, to a charge coupled field effect rectifier diode and its method of making.

1 FIG. 10 10 12 12 14 16 12 10 12 12 38 16 12 a b Reference is made towhich shows a cross-section of an embodiment of a charge coupled field effect rectifier diode (FERD) deviceas taught by U.S. Patent Application Publication No. 2020/0105946, now U.S. Pat. No. 11,239,376 (incorporated herein by reference). The deviceis formed in and on a semiconductor substrate(for example, silicon). The substratehas a front sideand a back side. The substrateprovides a cathode region of the field effect diodethat includes a first doped regionthat is more heavily doped with an n-type dopant and an overlying second doped regionthat is less heavily doped with the n-type dopant. A cathode metal layerextends over the back sideof the substrateto provide a metal connection to the cathode region.

18 12 14 18 13 18 13 A plurality of trenchesextend depthwise into the substratefrom the front side. The trenchesare regularly spaced apart and extend lengthwise parallel to each other in a direction perpendicular to the cross-section (i.e., into and out the page of the illustration), with adjacent trenches delimiting side edges of a mesa regionof the diode. As a variation, trenchesmay be formed in the shape of rings surrounding the mesa region.

24 13 12 14 14 18 24 18 24 12 24 26 13 14 12 14 18 24 26 18 26 24 12 24 28 14 12 18 26 24 A regiondoped with a p-type dopant is buried in the mesa regionsof the substrateat a depth offset from (i.e., below) the front sideand positioned extending parallel to the front sideon opposite sides of each trench. The doped regionforms the body (channel) region of the field effect diode, with the trenchpassing completely through the doped body regionand into the substratebelow the doped body region. A surface regionheavily doped with an n-type dopant is provided in the mesa regionsat the front sideof the substrateand positioned extending parallel to the front sideon opposite sides of each trenchand in contact with the top of the doped body region. The doped regionforms the source region of the field effect diode, with the trenchpassing completely through the doped source regionand further extending, as noted above, completely through the doped body regioninto the substratebelow the doped body region. A contact regionheavily doped with a p-type dopant is provided at the front sideof the substratebetween adjacent trenchesand passes through the doped regionto make contact with the doped region.

18 20 18 20 18 20 18 22 20 18 22 18 18 22 22 22 20 22 22 22 18 22 22 a b a b a b. The side walls and bottom of each trenchare lined with an insulating layermade, for example, of silicon oxide. In a lower portion of the trench, the insulating layerhas a first thickness, and in an upper portion of the trench, the insulating layerhas a second thickness (where the second thickness is less than the first thickness). Each trenchis filled by a doped polysilicon material to form a conductive structure. Because of the difference in insulating layerthicknesses within the trench, the conductive structurehas a first lateral width in the lower portion of the trench, and has a second lateral width in the upper portion of the trench(where the second lateral width is greater than the first lateral width). The conductive structureis a unitary body of conductive material comprising a combination of a gate electrode(in the upper portion of the trench) and field plate electrode(in the lower portion of the trench) for the diode. In view of the difference in thicknesses of the insulating layer, when a potential is applied to the conductive structure, the gate electrodeand field plate electrodewill exert different electrostatic influences on semiconductor regions along the depth of the trenches. In particular, the gate electrodewill have a stronger electrostatic influence than the field plate electrode

22 22 22 26 28 32 12 18 32 34 32 12 18 34 34 34 a b The conductive structure(including its constituent gate electrodeand field plate electrode), the doped regionforming the source region and the doped regionforming the body contact are all electrically connected to an anode terminal of the field effect diode. An anode metal layerextends over the substrateand trenches. The layermay, for example, be made of aluminum, aluminum-copper, or aluminum-silicon-copper. A conductive interface layeris positioned between the anode metal layerand the substratewith trenches. The layermay, for example, comprise a silicide layer. Alternatively, the layermay comprise a metal barrier material such a titanium. The layermay not be a continuous layer (as shown), but rather may be discontinuous and locally present only at the locations where semiconductor material is present.

1 FIG. 22 22 22 b a Manufacture of the structure shown inhas proven to be a challenge and typically requires multiple precise etching operations and two separate polysilicon deposition steps to form, respectively, the field plate electrodeand the gate electrodeof the conductive structure.

2 2 FIGS.A-F 2 FIG. 22 22 22 18 19 32 a b Alternatively, as shown byof U.S. Patent Application Publication No. 2020/0105946, now U.S. Pat. No. 11,239,376, a process for manufacturing is used where the conductive structureis actually produced as two separate parts comprising a split gate electrode part′ and a field plate electrode part′ insulated from each other in the trenchby an oxide layerand electrically connected to each other by the anode metal layer. This structure is shown in.

10 1 FIG. There is a need in the art for a more effective and efficient method of manufacturing the charge coupled FERD devicewith the structural configuration as shown in.

In an embodiment, a method comprises: forming a trench in a semiconductor substrate which provides a cathode region of a field effect rectifier diode (FERD); lining the trench with a first insulation layer; depositing a hard mask layer on the first insulation layer; performing an etch controlled by the hard mask layer to selectively remove a first portion of the first insulating layer from an upper portion of the trench while leaving a second portion of first insulating layer in a lower portion of the trench; removing the hard mask layer from the trench; lining an upper portion of the trench with a second insulation layer that extends from the second portion of first insulating layer; making a single deposition of polysilicon material in the trench to fill an opening in the trench, said opening including a lower open portion delimited by the second portion of first insulating layer in the lower portion of the trench and an upper open portion delimited by the second insulation layer at the upper portion of the trench; wherein said polysilicon material filling the opening forms a unitary conductive structure in the trench comprising: a field plate of the FERD insulated from the semiconductor substrate by the second portion of first insulating layer and a gate of the FERD insulated from the semiconductor substrate by the second insulating layer; implanting and activating a first type dopant in the semiconductor substrate to form a body region of the FERD; and implanting and activating a second type dopant in the semiconductor substrate to form a source region of the FERD.

In an embodiment, a method comprises: forming a trench in a semiconductor substrate; lining the trench with a first insulation layer; depositing a hard mask layer on a surface of the first insulation layer in the trench; performing an etch controlled by the hard mask layer to selectively remove a first portion of the first insulating layer from an upper portion of the trench while leaving a second portion of first insulating layer in a lower portion of the trench; removing the hard mask layer from the trench; lining an upper portion of the trench with a second insulation layer extending from the second portion of first insulating layer; and making a single deposition of polysilicon material in the trench to fill an opening in the trench, said opening having a lower open portion delimited by the second portion of first insulating layer in the lower portion of the trench and an upper open portion delimited by the second insulation layer at the upper portion of the trench.

In an embodiment, an integrated circuit comprises: a semiconductor substrate having a front side and a back side; a trench extending into the semiconductor substrate from the front side, said trench including a lower part and an upper part; a first insulation layer lining sidewalls of the lower part of the trench; a second insulating layer lining sidewalls of the upper part of said trench; wherein said first insulating layer is thicker than said second insulating layer; wherein the first insulation layer includes a tapered thickness region transitioning between the first thickness and the second thickness; and a unitary body of polysilicon material filling an opening in the trench that has a lower open portion delimited by the first insulating layer in the lower part of the trench and an upper open portion delimited by the second insulation layer at the upper part of the trench.

In the following description, when reference is made to terms qualifying absolute positions, such as terms “front”, “rear”, “top”, “bottom”, “left”, “right”, etc., or relative positions, such as terms “above”, “under”, “upper”, “lower”, etc., or to terms qualifying directions, such as terms “horizontal”, “vertical”, etc., it is referred to the orientation of the drawings or to a normal position of use.

3 15 FIGS.- 16 FIG. 10 Reference is now made towhich show steps of a method for making a charge coupled FERD deviceas shown in.

3 FIG. 18 12 14 18 10 12 12 12 18 12 12 18 12 18 18 12 a b b a. shows the formation of a trenchextending into a semiconductor substratefrom a front sidethereof. The illustrated trenchis one of a plurality of trenches that are formed in connection with the fabrication of the diode. The semiconductor substrateincludes a first doped regionthat is more heavily doped with an n-type dopant and an overlying second doped regionthat is less heavily doped with the n-type dopant. The trenchhas a depth in the second doped regionthat does not reach the first doped regionThe trenchmay be formed using conventional lithographic processing techniques. For example, a mask is formed over the substratewith a mask opening at the location where each trenchis to be formed. An etching process is then used to open the trenchin the substrate.

18 120 12 14 18 120 18 121 18 a a 4 FIG. After the trenchis formed, an insulating dielectric layeris conformally formed, for example by thermal oxidation, on the exposed surfaces of the substrate. This would include the front sideof the substrate as well as the side walls and bottom of the trench. The thickness of the layeris controlled to be smaller than one-half of the lateral width of each trenchso as to leave an openingin the center of the trench. The result is shown in.

104 12 104 120 14 121 18 104 121 105 18 104 5 FIG. a A conformal (blanket) deposition of a nitride layeris then made over the substrateas shown in. The nitride layercovers the layerabove the front sideof the substrate as well as along the side walls and bottom of the openingthat was left in the trench. The thickness of the layeris controlled to be smaller than one-half of the lateral width of each openingso as to leave an openingin the center of the trench. This nitride layeris eventually used, as discussed below, as a hard mask.

106 104 105 6 FIG. A layer of resistis then deposited as shown into cover the layerand fill the opening.

106 18 106 105 18 18 104 106 a 7 7 FIGS.A andB 7 FIG.B 7 FIG.A The resistis then lithographically patterned to be removed from areas over and around the location of the trench. Portionsof the resist then remain in the openingin the center of the trench. The result is shown in(whereis a scanning electron micrograph (SEM) image of the cross-section shown infocusing at the top of the trench). It will be noted that horizontal portions of the layerare exposed as a result of the lithographically patterning of the resistlayer.

104 120 106 18 106 104 106 18 104 120 18 a. a b a a 8 8 FIGS.A andB 8 FIG.B 8 FIG.A A dry etch is then performed to remove the horizontal portions of the nitride layerand thus delimit the structure of the nitride hard mask relative to the layerThis etch also removes a portion of the resistat the upper part of the trench(leaving portionat the bottom of the trench). The result is shown in(whereis a scanning electron micrograph (SEM) image of the cross-section shown infocusing on the top part of the trench where the horizontal portions of the nitride layerand the portion of the resistat the upper part of the trenchhave been removed). The effect of this dry etch to remove the horizontal portion of the nitride layeris to expose an upper end of the layerin the trench.

120 106 120 107 104 18 20 120 101 120 18 101 104 120 a b a a a a. 9 9 FIG.A andB 9 FIG.B 9 FIG.A A field plate oxide wet etch is then performed to remove portions of the layerwhich are not protected by the nitride layer hard mask or the resiston top of the nitride hard mask. This is effectively a selective etch which performs a recessing of the layerfrom the exposed upper end. The result is shown in(whereis a scanning electron micrograph (SEM) image of the cross-section shown in). This etch forms an openingbetween the layerand the sidewalls of the trenchand shapes the portion of insulating layermade from layerat the bottom of the trench to include a tapered thickness regionwhere the thickness of the layerincreases from the side wall of the trenchwith increased depth into the trench. The provision and shaping of the tapered thickness regionarise as a result of the etch which is controlled by the presence of the hard mask layerand produces a recessing of the layer

104 120 120 18 120 120 120 a a a a a 9 FIG.B The advantages of using the nitride layeras a hard mask during the recessing of the layerwith the field plate oxide wet etch are clearly evident in. The quality of recessing of the layerover the plurality of trenchesfor the purpose of uniformly removing the portion of layerin the upper portion of the trench and uniformly defining the shape of the layerin the lower portion of the trench is assured. There is little to no variation from trench to trench as to the shape of the layerin the lower portion of the trench.

104 104 120 18 a It will be noted that the use of nitride for the material of the hard mask provided by layeris just an example. Any suitable material can be used for layerprovided it provides the requisite hard mask functionality in connection with the etching process for recessing the layerin the trenches.

106 18 105 18 120 106 b a b 10 FIG. The remaining portion of the resistin the trenchis then stripped, leaving the openingin the trench. The result is shown in. It is worth noting here that the recessing of the layeris associated with the nitride hard mask alone and, as an alternative step in the process, that the remaining portion of the resistmay have been etched away just after the nitride hard mask dry etch.

104 120 107 18 18 120 11 FIG. a a. A nitride wet etch is then performed to remove the nitride hard mask portion of the layer. The result is shown in. This leaves only the portion of the layerat the bottom of the trench and defines an openingin the center of the trenchhaving an upper part delimited by the side walls of the trenchand a lower part delimited by the remaining portion of the layer

120 12 14 18 107 120 120 120 120 120 20 10 109 18 109 20 120 109 20 120 120 10 b a. b a a b a a b b b 12 FIG. An insulating dielectric layeris then conformally formed, for example by thermal oxidation, on the exposed surfaces of the substrate. This would include the front sideof the substrate as well as the side walls at the upper portion of the trenchin openingwhich are not covered by the layerThe result is shown inwith the insulating dielectric layerextending along the trench side walls from the portion of layerwhich remains in the trench. The insulating layersandform the insulating layerof the diodeand delimit an openingin the trenchwhich includes a lower portionhaving a first width extending between the lower portion of the insulating layer(formed by the remaining portion of the layerin the trench) and an upper portionhaving a second width extending between the upper portion of the insulating layer(formed by the portion of layerin the trench). The second width is greater than the first width. The thickness of the layeris controlled to provide a desired gate oxide thickness for the diode.

122 109 22 10 14 12 22 120 12 122 22 22 22 b a b 13 13 FIGS.A andB 13 FIG.B 13 FIG.A A single deposition of n-type highly doped polysilicon materialis then made to fill the openingand form the conductive structureof the diode. Excess polysilicon material above the front sideof the substrateis removed using a polysilicon dry etch so that the upper surface of the conductive structureis coplanar (or substantially coplanar) with the upper surface of the layer(or the upper surface of the substrate). The result is shown in(whereis a scanning electron micrograph (SEM) image of the cross-section shown in). The deposited polysilicon materialforms the unitary body of the conductive structurewhich includes the gate electrode portion(in the upper portion of the trench) and field plate electrode portion(in the lower portion of the trench) for the diode.

24 26 28 122 14 FIG. Conventional processes well known in the art for implanting and activating dopants for forming the p-type doped body region, n-type doped source regionand p-type doped body contact regionare then performed. Because of its high doping level, there is no risk here of the formation of a p-n junction in the polysilicon material. The result is shown in.

34 120 14 12 34 122 22 26 28 34 32 34 16 12 38 10 b 15 FIG. 16 FIG. A conductive interface layeris then formed over the substrate. In an embodiment, the horizontal portions of the layerat the front sideof the substratemay be removed. The layermay comprise a silicide layer in contact with the polysilicon materialof the conductive structureand the semiconductor materials for the n-type doped source regionand p-type doped contact region. Alternatively, the layermay comprise a metal barrier. An anode metal layeris then blanket deposited over the interface layer, and lithographically patterned as needed, to provide electrical connection to the anode terminal of the field effect diode. The back sideof the substrateis further processed with a backlap and/or grind to provide a surface to which a cathode metal layeris deposited. The result is shown inand the process for forming the charge coupled FERD deviceas shown inis complete.

17 FIG. 17 FIG. 16 FIG. 10 10 10 14 12 200 14 12 202 200 22 204 200 26 24 28 204 202 204 202 204 206 32 200 Reference is now made towhich shows a cross-section of another embodiment of a charge coupled field effect rectifier diode (FERD) device. Like references refer to like or similar components. The deviceofdiffers from the deviceofin terms of the structures fabricated above the front sideof the substrate. A premetallization dielectric (PMD) layerextends over the front sideof the substrate. An openingis formed to extend through PMD layerto reach the conductive structure. Furthermore, an openingis formed to extend through the PMD layerand the doped source regionto reach at least the top of the doped body region. The p-type doped body contact regionis formed at the bottom of the opening. A silicide layer, not explicitly shown, may be formed at the bottom of each openingandto improve contact resistance. The openingsandare filled with a metal material to form electrical contacts. The anode metal layeris then blanket deposited over the PMD layer, and lithographically patterned as needed, to provide electrical connection to the anode terminal of the field effect diode.

10 17 FIG. 3 13 FIGS.- 13 FIG. 18 19 20 22 FIGS.,andA-A The process for making the diode deviceofutilizes the same steps of the process shown in. The steps for completing fabrication of the device after the step ofare shown in.

13 FIG. 18 FIG. 24 26 122 Following the processing step of, conventional processes well known in the art for implanting and activating dopants for forming the p-type doped body regionand n-type doped source regionare then performed. Because of its high doping level, there is no formation of p-n junctions in the polysilicon material. The result is shown in.

200 120 14 12 b 19 FIG. A layer of dielectric material is then formed over the substrate to provide the PMD layer. In an embodiment, the horizontal portions of the layerat the front sideof the substratemay be removed. The result is shown in.

20 FIG.A 202 204 200 202 200 22 204 200 26 24 202 204 200 202 204 204 28 24 204 shows the formation of openingsandextending from an upper surface of the PMD layer. The openingsextend completely through the PMD layerto reach the conductive structure. The openingsextend completely through both the PMD layerand the doped source regionto reach at least the top of the doped body region. The openingsandmay each be formed using conventional lithographic processing techniques. For example, a mask is formed over the PMD layerwith a mask opening at the location where the opening (or) is to be formed. An etching process then forms the opening with a desired depth. In connection with the formation of the openings, a dopant implantation process is performed to implant the body contact regionsin the body regionat the bottom of each opening.

202 204 206 21 FIG.A The openingsandare then filled with a metal material (for example, tungsten) to form electrical contacts. The result is shown in.

32 200 16 12 38 10 22 FIG.A 17 FIG. An anode metal layeris then blanket deposited over the PMD layer, and lithographically patterned as needed, to provide electrical connection to the anode terminal of the field effect diode. The back sideof the substrateis further processed with a backlap and/or grind to provide a surface to which a cathode metal layeris deposited. The result is shown inand the process for forming the diodeas shown inis complete.

20 21 22 FIGS.A,A andA 20 FIG.B 202 204 202 204 202 204 200 202 204 202 200 26 24 204 200 122 202 204 26 122 202 204 28 24 204 122 202 It will be noted that process described above in connection with, will typically require the use of two distinct masking and etching operations to form the openingsand. In an alternative implementation, only one masking and etching operation is used in connection with the formation of openingsand.shows the formation of openingsandextending from an upper surface of the PMD layer. The openingsandare simultaneously formed using conventional lithographic processing techniques with a single masking and etching operation. The openingsextend completely through both the PMD layerand the doped source regionto reach into the at least the top of the doped body region. The openingsextend completely through the PMD layerand into the polysilicon material. The openingsandmay, for example, have similar depths dependent on etch rate relative to the doped source regionand the doped polysilicon material. In connection with the formation of the openingsand, a dopant implantation process is performed to implant body contact regionsin the body regionat the bottom of each opening. It will be noted that the high dopant concentration level in the polysilicon materialwill prevent the formation of a p-n junction at the opening.

202 204 206 21 FIG.B The openingsandare then filled with a metal material (for example, tungsten) to form electrical contacts. The result is shown in.

32 200 16 12 38 10 22 FIG.B 23 FIG. An anode metal layeris then blanket deposited over the PMD layer, and lithographically patterned as needed, to provide electrical connection to the anode terminal of the field effect diode. The back sideof the substrateis further processed with a backlap and/or grind to provide a surface to which a cathode metal layeris deposited. The result is shown inand the process for forming the diodeas shown inis complete.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.