Semiconductor Device

This application is a continuation of U.S. patent application Ser. No. 18/454,820, filed Aug. 24, 2023, entitled SEMICONDUCTOR DEVICE, which is a continuation of U.S. patent application Ser. No. 17/680,864, filed Feb. 25, 2022, entitled SEMICONDUCTOR DEVICE, issued as U.S. Pat. No. 11,777,030 on Oct. 3, 2023, which is a continuation of U.S. patent application Ser. No. 17/464,303, filed Sep. 1, 2021, entitled SEMICONDUCTOR DEVICE, issued as U.S. Pat. No. 11,296,223 on Apr. 5, 2022, which is a continuation of U.S. patent application Ser. No. 17/328,822, filed May 24, 2021, entitled SEMICONDUCTOR DEVICE, issued as U.S. Pat. No. 11,610,992 on Mar. 21, 2023, which is a continuation of U.S. patent application Ser. No. 17/016,989, filed Sep. 10, 2020, entitled SEMICONDUCTOR DEVICE, issued as U.S. Pat. No. 11,043,589 on Jun. 22, 2021, which is a continuation of U.S. patent application Ser. No. 16/714,038, filed Dec. 13, 2019, entitled SEMICONDUCTOR DEVICE, issued as U.S. Pat. No. 10,804,392 on Oct. 13, 2020, which is a continuation of U.S. patent application Ser. No. 16/418,360, filed May 21, 2019, entitled SEMICONDUCTOR DEVICE, now U.S. Pat. No. 10,546,954, issued on Jan. 28, 2020, which is a continuation of U.S. patent application Ser. No. 15/868,389, filed Jan. 11, 2018, issued as U.S. Pat. No. 10,319,853 on Jun. 11, 2019, which is a continuation of U.S. application Ser. No. 15/273,230, filed Sep. 22, 2016, issued as U.S. Pat. No. 9,893,180 on Feb. 13, 2018, which is a continuation of U.S. application Ser. No. 14/995,454, filed Jan. 14, 2016, issued as U.S. Pat. No. 9,496,393 on Nov. 15, 2016, which is a continuation of U.S. application Ser. No. 14/601,345, filed Jan. 21, 2015, issued as U.S. Pat. No. 9,257,521 on Feb. 9, 2016, which is a continuation of U.S. application Ser. No. 14/148,766, filed Jan. 7, 2014, issued as U.S. Pat. No. 8,969,877 on Mar. 3, 2015, which is a continuation of U.S. application Ser. No. 13/394,549, filed May 17, 2012, issued as a U.S. Pat. No. 8,653,533 on Feb. 18, 2014, which is a 371 National Stage application of PCT/JP2010/065057, filed Sep. 2, 2010, which claimed benefit from Japanese Patent Application Nos. 2009-206372, filed Sep. 7, 2009, 2009-206373, filed Sep. 7, 2009, and 2009-206374, filed Sep. 7, 2009, the specifications of each are incorporated by reference herein in their entireties.

The present invention relates to a semiconductor device and a method of manufacturing the same.

SiC (silicon carbide) is superior in dielectric breakdown resistance and thermal conductivity etc. to Si (silicon). Therefore, SiC is watched with interest as a semiconductor suitable to a use for an inverter of a hybrid car or the like, for example. More specifically, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) employing SiC is expected as a high withstand voltage device suitable to an inverter of a hybrid car or the like.

2 A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example of a MISFET employing SiC has an SiC-MOS structure obtained by stacking a gate electrode on an SiC substrate through a gate insulating film made of SiO(silicon oxide). A well region is formed on a surface layer portion of the SiC substrate. A source region and a drain region are formed on a surface layer portion of the well region at an interval from each other. The gate insulating film is formed on a region between the source region and the drain region.

Patent Document 1: Japanese Unexamined Patent Publication No. 2009-16530

2 2 The SiC-MOS structure has such a problem that high-density interface states are formed on the interface (SiO/SiC interface) between the SiC substrate and the gate insulating film. The number of the interface states (interface defects) increases as the thickness of the gate insulating film made of SiOenlarges.

2 2 2 Therefore, the inventors of this application examine employment of a gate insulating film having not a single-layer structure of SiO, but an AlON/SiOmultilayer structure obtained by stacking an AlON (aluminum oxynitride) film on a relatively thin SiOfilm.

2 2 2 2 In a case of comparing a gate insulating film of a single layer of SiOhaving a thickness of 40 nm and a gate insulating film of a multilayer structure of an AlON film having a thickness of 65 nm and an SiOfilm having a thickness of 6 nm with each other, for example, reduction of interface state density is expected in the AlON/SiOmultilayer gate insulating film, since the thickness of the SiOfilm is small.

11 FIG. 12 FIG. 2 2 2 2 is a graph showing field strength-leakage current characteristics (relations between the strength of electric fields (Oxide Field) formed in the gate insulating films and leakage current density (Gate Current Density)) of the AlON/SiOmultilayer gate insulating film and the SiOsingle-layer gate insulating film at room temperature.is a graph showing field strength-leakage current characteristics of the AlON/SiOmultilayer gate insulating film and the SiOsingle-layer gate insulating film at high temperature.

11 12 FIGS.and 2 2 2 As shown in, it has been confirmed that leakage current is more reduced in the AlON/SiOmultilayer gate insulating film than in the SiOsingle-layer gate insulating film, not only at room temperature (about 25° C.) but also at high temperature of 200° C. The effect of the reduction is particularly strong in the range where the strength of the electric field formed in the AlON/SiOmultilayer gate insulating film is greater than 6 MV/cm.

13 FIG. 2 2 is a graph showing evaluation results of interface state density of an SiC-MIS structure employing the AlON/SiOmultilayer gate insulating film and an SiC-MOS structure employing the SiOsingle-layer gate insulating film. In this graph, the axis of abscissas shows energy (Ec-E) from valence band edges of the gate insulating films, and the axis of ordinates shows the interface state density Dit.

2 2 As to the respective ones of the SiC-MIS structure employing the AlON/SiOmultilayer gate insulating film and the SiC-MOS structure employing the SiOsingle-layer gate insulating film, high-frequency CV characteristics (at a measuring frequency of 100 kHz, for example) and low-frequency CV characteristics (quasi-static CV characteristics) were measured, and the differences between high-frequency measured values and low-frequency measured values were calculated as the interface state density Dit by a High-Low method.

2 2 2 13 FIG. While reduction of the interface state density resulting from the reduction of the thickness of the SiOfilm is expected in the SiC-MIS structure employing the AlON/SiOmultilayer gate insulating film as compared with the SiC-MOS structure employing the SiOsingle-layer gate insulating film, it has been recognized from the results shown inthat the interface state density increases in practice. In a MISFET, increase of interface state density causes reduction of channel mobility.

An object of the present invention is to provide a semiconductor device in which the state of an interface between a silicon carbide substrate and a silicon oxide film is excellent and a method of manufacturing the same.

2 A method of manufacturing a semiconductor device according to one aspect of the present invention includes the steps of forming a silicon oxide (SiO) film on a silicon carbide (SiC) substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride (AlON) film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film.

In the state where the silicon oxide film is simply formed on the silicon carbide substrate, dangling bonds of carbon (C) atoms and silicon (Si) atoms are present on the interface between the silicon carbide substrate and the silicon oxide film. After the formation of the silicon oxide film, the silicon carbide substrate and the silicon oxide film are annealed in the gas containing hydrogen, whereby hydrogen (H) atoms are bonded to the dangling bonds of the carbon atoms and the silicon atoms, and the interface between the silicon carbide substrate and the silicon oxide film is hydrogen-terminated. Consequently, the number of defects (interface state density) on the interface between the silicon carbide substrate and the silicon oxide film decreases, and the state of the interface is improved.

After the annealing of the silicon carbide substrate and the silicon oxide film, the aluminum oxynitride film is formed on the silicon oxide film. The aluminum oxynitride film is present on the silicon oxide film, whereby dehydrogenation from the silicon carbide substrate and the silicon oxide film is prevented. Therefore, the state of the interface between the silicon carbide substrate and the silicon oxide film improved by the hydrogen termination is maintained.

According to the manufacturing method according to one aspect of the present invention, therefore, the state of the interface between the silicon carbide substrate and the silicon oxide film can be improved, and the improved state can be maintained. Consequently, a semiconductor device in which the state of an interface between a silicon carbide substrate and a silicon oxide film is excellent can be obtained. In other words, a semiconductor device including a silicon carbide substrate, a silicon oxide film formed on the silicon carbide substrate and an aluminum oxynitride film formed on the silicon oxide film, in which the interface between the silicon carbide substrate and the silicon oxide film is hydrogen-terminated, can be manufactured by the manufacturing method according to the present invention.

In a case where the semiconductor device includes a MISFET having the silicon oxide film and the aluminum oxynitride film as a gate insulating film, improvement of channel mobility can be attained due to reduction of interface state density.

The aluminum oxynitride film is a high dielectric constant film (High-k film). In the gate insulating film consisting of the silicon oxide film and the aluminum oxynitride film, therefore, leakage current can be reduced while ensuring equivalent or higher electric characteristics as compared with a gate insulating film consisting of only a silicon oxide film, by enlarging the thickness of the aluminum oxynitride film. Consequently, reliability of the gate insulating film can be improved.

A gate electrode formed on the aluminum oxynitride film is preferably made of a metallic material containing aluminum. Thus, improvement in operating speed of the MISFET and reduction of power consumption can be attained as compared with such a structure that a gate electrode is made of polycrystalline silicon.

After the formation of the aluminum oxynitride film, the aluminum oxynitride film is preferably subjected to annealing (PDA: Post Deposition Annealing). Due to the annealing, crystallinity of the aluminum oxynitride film can be raised, and quality of the aluminum oxynitride film can be improved.

2 2 The annealing of the silicon carbide substrate and the silicon oxide film is preferably FGA (Forming Gas Annealing), and suitably performed in forming gas prepared by mixing hydrogen (H) and nitrogen (N) with each other under a temperature condition of 450 to 1000° C. The forming gas suitably contains hydrogen in a ratio smaller than the explosion limit, and more specifically, the forming gas suitably contains 3% of hydrogen and 97% of nitrogen. The annealing of the silicon carbide substrate and the silicon oxide film is suitably performed in the forming gas at a temperature of 1000° C. for 30 minutes and thereafter performed at a temperature of 450° C. for 30 minutes. Thus, hydrogen atoms can be excellently introduced into the silicon oxide film, and the number of dangling bonds of carbon atoms and silicon atoms present on the interface between the silicon carbide substrate and the silicon oxide film can be effectively reduced.

Before the annealing of the silicon carbide substrate and the silicon oxide film, nitrogen plasma is preferably applied to the silicon oxide film. Thus, Si—O—C bonds and C—C clusters can be cut and dangling bonds of carbon atoms and silicon atoms can be formed on the interface between the silicon carbide substrate and the silicon oxide film. Then, the annealing of the silicon carbide substrate and the silicon oxide film is performed after the application of the nitrogen plasma, whereby hydrogen atoms can be easily bonded to the dangling bonds of the carbon atoms and the silicon atoms present on interface between the silicon carbide substrate and the silicon oxide film. Consequently, the interface between the silicon carbide substrate and the silicon oxide film can be excellently hydrogen-terminated.

x The silicon oxide film is preferably formed by thermal oxidation employing gas containing a nitrogen oxide (NO). Thus, nitrogen atoms can be introduced into the silicon oxide film, and the dielectric constant of the silicon oxide film can be raised. Consequently, leakage current can be further reduced. Besides, further reduction of interface state density can be attained due to nitrogen termination on the interface between the silicon carbide substrate and the silicon oxide film, and further improvement (betterment) of the channel mobility can be expected.

A semiconductor device according to another aspect of the present invention includes a silicon carbide layer, a silicon oxynitride film formed on the silicon carbide layer, a silicon oxide film formed on the silicon oxynitride film, a high dielectric constant insulating film (High-k insulating film) formed on the silicon oxide film, and a gate electrode formed on the high dielectric constant insulating film.

In other words, the semiconductor device according to the other aspect of the present invention includes a silicon carbide layer, a gate insulating film formed on the silicon carbide layer, and a gate electrode formed on the gate insulating film. The gate insulating film has a structure obtained by stacking a silicon oxynitride film, a silicon oxide film and a high dielectric constant insulating film from the side of the silicon carbide layer.

The silicon oxynitride film is interposed between the silicon carbide layer and the silicon oxide film, whereby reduction of interface state density on the interface between the silicon carbide layer and the gate insulating film can be attained as compared with such a structure that a gate insulating film consists of only a silicon oxide film. Further, improvement of channel mobility can be attained due to the reduction of the interface state density.

In addition, reduction of leakage current resulting from increase in thickness of the gate insulating film can be attained while suppressing increase of interface state density on the interface between the silicon carbide layer and the gate insulating film by reducing the total thickness of the silicon oxynitride film and the silicon oxide film and enlarging the thickness of the high dielectric constant insulating film.

Therefore, both of the improvement of the channel mobility resulting from the reduction of the interface state density and improvement of reliability of the gate insulating film resulting from the reduction of the leakage current can be attained.

In a case where the total thickness of the silicon oxynitride film and the silicon oxide film is not less than 1 nm and not more than 10 nm, the interface between the silicon carbide layer and the gate insulating film can be brought into a particularly excellent state.

The high dielectric constant insulating film may be an aluminum oxynitride film.

The gate electrode is preferably made of a metallic material containing aluminum. Thus, improvement in operating speed of a MISFET and reduction of power consumption can be attained as compared with such a structure that a gate electrode is made of polycrystalline silicon.

A semiconductor device according to still another aspect of the present invention includes a semiconductor layer made of first conductivity type SiC, a second conductivity type well region formed on a surface layer portion of the semiconductor layer, a first conductivity type source region formed on a surface layer portion of the well region, a gate insulating film formed on the semiconductor layer, and a gate electrode formed on the gate insulating film and opposed to a channel region of the well region where a channel is formed through the gate insulating film. In the source region, the impurity concentration in a first region of a prescribed width adjacent to the channel region is lower than the impurity concentration in a second region other than the first region.

Thus, the rate (rate of oxidation) of growth of an oxide film on the surface of the first region can be suppressed low by lowering the impurity concentration in the first region of the source region adjacent to the channel region. Therefore, formation of a large step between the surface of the first region and the surface of the channel region (well region) can be prevented after removal of the oxide film. Consequently, a path (movement path) of carriers moving from the source region to the channel region can be approximated to a straight line, whereby reduction of channel resistance can be attained.

The impurity concentration in the second region of the source region other than the first region is higher than the impurity concentration in the first region, whereby a step where the surface of the second region is lower by one stage than the surface of the first region is formed between the surface of the first region and the surface of the second region. Even if the step is formed between the surface of the first region and the surface of the second region, the step does not influence the flow of the carriers in the channel region. Therefore, the channel resistance can be reduced without reducing the carrier concentration in the source region by relatively lowering the impurity concentration in the first region and relatively raising the impurity concentration in the second region.

In a case where the source region and the channel region are adjacently formed in a direction along the upper surface of the semiconductor layer, the respective upper surfaces of the source region and the channel region become the surfaces thereof, and the gate insulating film is formed on the upper surface of the semiconductor layer. Then, the gate electrode is provided on the gate insulating film, to be opposed to the upper surface of the channel region. In other words, the semiconductor device has a planar gate MIS (Metal Insulator Semiconductor) structure.

In a case where the source region and the channel region are adjacently formed in a direction orthogonal to the upper surface of the semiconductor layer, a trench dug down from the upper surface of the source region is formed in the semiconductor layer, and the gate insulating film is formed on the inner surface of the trench. The trench passes through the source region and the well region. Then, the gate electrode is provided inside the gate insulating film, and embedded in the trench. In other words, the semiconductor device has a trench gate MIS structure.

The foregoing and other objects, features and effects of the present invention will become more apparent from the following detailed description of the embodiments with reference to the attached drawings.

1 FIG. is a schematic sectional view of a semiconductor device according to a first embodiment of the present invention.

1 2 A semiconductor deviceincludes an SiC substratemade of SiC (silicon carbide) doped with an N-type impurity.

3 2 A P-type well regionis formed on a surface layer portion of the SiC substrate.

+ 4 2 5 3 4 5 3 An N-type source regiondoped with an N-type impurity in a higher concentration than in the SiC substrateand a drain regionare formed on a surface layer portion of the well region. The source regionand the drain regionare formed at intervals from a peripheral edge portion of the well regionrespectively, and at an interval from each other.

+ 6 3 3 6 4 5 A P-type contact regiondoped with a P-type impurity in a higher concentration than in the well regionis formed on the surface layer portion of the well region. The contact regionis formed adjacently to a side of the source regionopposite to the drain region.

7 4 5 7 4 5 4 5 7 8 9 8 8 9 2 2 2 2 2 A gate insulating filmis formed on a region (channel region) between the source regionand the drain region. More specifically, the gate insulating filmis opposed to the region between the source regionand the drain region, and extends over a peripheral edge portion of the source regionand a peripheral edge portion of the drain region. The gate insulating filmhas an AlON/SiOmultilayer structure including a relatively thin SiOfilmmade of SiO(silicon oxide) containing N (nitrogen) and an AlON filmmade of AlON (aluminum oxynitride) and formed on the SiOfilm. The thickness of the SiOfilmis 1 to 20 nm. The thickness of the AlON filmis 30 to 100 μm.

10 7 7 10 A gate electrodehaving the same shape as the gate insulating filmin plan view is formed on the gate insulating film. The gate electrodeis made of a metallic material containing Al (aluminum).

11 4 6 11 4 6 11 A source electrodeis formed on the source regionand the contact region. The source electrodeis in contact with the surfaces of the source regionand the contact regionwhile extending over the same. The source electrodeis made of a metallic material containing Al.

12 5 12 5 12 A drain electrodeis formed on the drain region. The drain electrodeis in contact with the surface of the drain region. The drain electrodeis made of a metallic material containing Al.

1 10 11 12 3 12 11 Thus, the semiconductor deviceincludes an N-channel MISFET (Negative-channel Metal Insulator Semiconductor Field Effect Transistor). Voltage of not less than a threshold is applied to the gate electrodein a state where the source electrodeis grounded and positive voltage is applied to the drain electrode, whereby a channel is formed in the channel region of the well regionin the vicinity of the interface between the same and the gate insulating film, and current flows from the drain electrodetoward the source electrode.

1 13 2 3 13 14 15 14 14 15 8 9 2 2 2 2 2 2 In the semiconductor device, a capacitance filmis selectively formed on a region of the SiC substrateother than the well region. The capacitance filmhas an AlON/SiOmultilayer structure including an SiOfilmmade of SiOcontaining N and an AlON filmmade of AlON and formed on the SiOfilm. The thicknesses of the SiOfilmand the AlON filmare identical to the thicknesses of the SiOfilmand the AlON filmrespectively.

16 13 13 16 10 10 A capacitor electrodehaving the same shape as the capacitance filmin plan view is formed on the capacitance film. The capacitor electrodeis made of the same material as the gate electrode, and has the same thickness as the gate electrode.

1 Thus, the semiconductor deviceincludes a MIS capacitor.

2 FIG. 2 is a sectional view illustratively showing the structure of the interface between the SiC substrate and the SiOfilm.

2 8 14 2 8 14 2 8 14 2 2 2 Dangling bonds of C (carbon) atoms and Si (silicon) atoms present on the interface between the SiC substrateand the SiOfilmorare small in number or generally nonexistent, and H (hydrogen) atoms are bonded to the C atoms and the Si atoms present on the interface between the SiC substrateand the SiOfilmor. In other words, the interface between the SiC substrateand the SiOfilmoris hydrogen-terminated.

3 FIG. is a manufacturing step diagram for the semiconductor device.

1 1 2 3 4 5 2 In order to manufacture the semiconductor device, an SiOfilm formation step (S), a nitrogen plasma application step (S), an FGA (Forming Gas Annealing) step (S), an AlON film formation step (S) and a PDA (Post Deposition Annealing) step (S) are carried out in this order.

2 2 2 2 1 2 In the SiOfilm formation step (S), an SiOfilm made of SiOcontaining N is formed on the SiC substrateby thermal oxidation employing gas containing NO (nitrogen oxide).

2 2 2 2 2 2 In the nitrogen plasma application step (S), nitrogen plasma is applied to the SiOfilm. The nitrogen plasma is continuously applied over 30 minutes in a state where the SiC substrateis heated to 500° C., for example. Atmospheric pressure and RF output at this time are 7.5 Torr and 50 W respectively, for example. The nitrogen plasma is applied to the SiOfilm, whereby Si—O—C bonds and C—C clusters are cut and dangling bonds of C atoms and Si atoms are formed on the interface between the SiC substrateand the SiOfilm.

3 2 2 2 2 2 2 2 In the FGA step (S), the SiC substrateand the SiOfilm are annealed in forming gas containing 3% of H(hydrogen gas) and 97% of N(nitrogen gas). For example, annealing at a temperature of 1000° C. is performed for 30 minutes, and annealing at a temperature of 450° C. is thereafter performed for 30 minutes. Thus, H atoms are excellently introduced into the SiOfilm, and the number of the dangling bonds of the C atoms and the Si atoms present on the interface between the SiC substrateand the SiOfilm decreases.

4 2 2 2 In the AlON film formation step (S), an AlON film is formed on the SiOfilm by reactive sputtering employing mixed gas of Nand O(oxygen gas) and an Al target.

5 2 In the PDA step (S), the AlON film is annealed in N. The annealing is performed at a temperature of 900° C. for 30 minutes, for example. Thus, crystallinity of the AlON film rises, and quality of the AlON film improves.

10 16 10 16 10 16 9 15 8 14 11 12 1 2 2 2 1 FIG. Thereafter the gate electrodeand the capacitor electrodeare formed on the AlON film. The gate electrodeand the capacitor electrodeare formed by selectively vapor-depositing the material (Al) for the gate electrode on the surface of the AlON film with a mask, for example. Then, exposed portions (portions not opposed to the gate electrodeand the capacitor electrode) of the AlON film and the SiOfilm are removed by photolithography and etching, and the AlON film and the SiOfilm are worked into the AlON filmsandand the SiOfilmsandrespectively. When the source electrodeand the drain electrodeare thereafter formed, the semiconductor deviceshown inis obtained.

2 2 2 2 2 2 2 2 2 2 2 2 In the state where the SiOfilm is simply formed on the SiC substrate, dangling bonds of C atoms and Si atoms are present on the interface between the SiC substrateand the SiOfilm. After the formation of the SiOfilm, therefore, the SiC substrateand the SiOfilm are annealed in the forming gas containing H. Thus, H atoms are bonded to the dangling bonds of the C atoms and the Si atoms, and the interface between the SiC substrateand the SiOfilm is hydrogen-terminated. Consequently, the number of defects (interface state density) on the interface between the SiC substrateand the SiOfilm decreases, and the state of the interface is improved.

2 2 2 2 2 2 2 2 After the annealing of the SiC substrateand the SiOfilm, the AlON film is formed on the SiOfilm. The AlON film is present on the SiOfilm, whereby dehydrogenation from the SiC substrateand the SiOfilm is prevented. Therefore, the state of the interface between the SiC substrateand the SiOfilm improved by the hydrogen termination is maintained.

2 2 Thus, the state of the interface between the SiC substrateand the SiOfilm can be improved, and the improved state can be maintained.

1 2 8 14 1 3 FIG. 2 2 In the semiconductor devicemanufactured by the manufacturing method shown in, therefore, the interfaces between the SiC substrateand the SiOfilmsandare hydrogen-terminated. Therefore, the semiconductor devicehas lower interface state density and can exhibit higher channel mobility as compared with a structure having large numbers of dangling bonds on interfaces between an SiC substrate and SiOfilms.

7 8 9 9 1 7 2 2 2 In the gate insulating filmconsisting of the SiOfilmand the AlON film, leakage current can be reduced while ensuring equivalent or higher electric characteristics as compared with a gate insulating film consisting of only an SiOfilm, by enlarging the thickness of the AlON film. In the semiconductor device, therefore, reliability of the gate insulating filmis high as compared with the structure employing the gate insulating film consisting of only an SiOfilm.

10 9 10 The gate electrodeformed on the AlON filmis made of the metallic material containing Al. Thus, improvement in operating speed of the MISFET and reduction of power consumption can be attained as compared with such a structure that the gate electrodeis made of polycrystalline silicon.

1 In the manufacturing steps for the semiconductor device, the AlON film is annealed after the formation of the AlON film. Thus, the crystallinity of the AlON film can be raised, and the quality of the AlON film can be improved.

2 2 2 2 2 2 2 2 2 2 2 Further, the nitrogen plasma is applied to the SiOfilm before the annealing of the SiC substrateand the SiOfilm. Thus, Si—O—C bonds and C—C clusters can be cut and dangling bonds of carbon atoms and silicon atoms can be formed on the interface between the SiC substrateand the SiOfilm. Then, the annealing of the SiC substrateand the SiOfilm is performed after the application of the nitrogen plasma, whereby H atoms can be easily bonded to the dangling bonds of the C atoms and the Si atoms present on the interface between the SiC substrateand the SiOfilm. Consequently, the interface between the SiC substrateand the SiOfilm can be excellently hydrogen-terminated.

2 2 2 2 The SiOfilm is formed by the thermal oxidation employing the gas containing the nitrogen oxide (NO). Thus, N atoms can be introduced into the SiOfilm, and the dielectric constant of the SiOfilm can be raised. Consequently, the leakage current can be further reduced.

1 1 8 9 2 2 1 FIG. 3 FIG. A sample(AlON/SiO) having a MISFET of the structure shown inwas prepared by the manufacturing method shown in. In the sample, the thickness of an SiOfilmis 10 nm, and the thickness of an AlON filmis 65 nm.

2 2 2 2 Further, a sample(SiO) having a MOSFET of a structure obtained by stacking a gate electrode on an SiC substrate through a gate insulating film consisting of a single layer of SiOwas prepared. In the sample, the thickness of the gate insulating film is 40 nm.

4 FIG. 1 2 is a graph showing the relations between gate voltage (Gate Voltage) and drain current (Drain Current) in the samplesand.

1 2 As to the respective ones of the samplesand, magnitudes of the drain current at times of varying the gate voltage were examined.

4 FIG. 1 1 2 2 shows the relation between the gate voltage and the drain current in the samplewith a curve C, and shows the relation between the gate voltage and the drain current in the samplewith a curve C.

5 FIG. is a graph showing the relations between the strength of electric fields (Gate Oxide Field) formed in gate insulating films and field effect mobility (Field Effect Mobility).

1 2 As to the respective ones of the samplesand, the magnitudes of the field effect mobility at times of varying the electric fields formed in the gate insulating films were examined.

5 FIG. 7 1 3 2 4 shows the relation between the strength of the electric field formed in a gate insulating filmand the field effect mobility in the samplewith a curve C, and shows the relation between the strength of the electric field formed in the gate insulating film and the field effect mobility in the samplewith a curve C.

1 4 1 2 7 8 9 9 8 4 5 FIGS.and 2 2 2 From the curves Cto Cshown in, it is understood that transistor operating characteristics of the samplesandare generally identical to each other. Also in the MISFET employing the gate insulating filmconsisting of the SiOfilmand the AlON film, the field effect mobility is generally identical to that of the MOSFET employing the gate insulating film consisting of the single layer of SiO, and hence no increase is conceivably caused in interface state density by stacking the AlON filmon the SiOfilm.

13 FIG. 2 2 2 2 2 In the evaluation (see) of the interface state density previously executed by the inventors of this application, therefore, the interface state density of the SiC-MIS structure employing the AlON/SiOmultilayer gate insulating film more increased than the interface state density of the SiC-MOS structure employing the SiOsingle-layer gate insulating film, is conceivable as a result of reflecting defects (defects on the AlON/SiOinterface, for example) not influencing the transistor operating characteristics. More specifically, this evaluation is evaluation performed by calculating each interface state density of the SiC-MIS structure employing the AlON/SiOmultilayer gate insulating film and the SiC-MOS structure employing the SiOsingle-layer gate insulating film by a High-Low method and comparing the same.

6 FIG. 7 FIG. 8 FIG. 6 7 FIGS.and 6 7 FIGS.and 1 2 is a graph showing temperature dependency of the field effect mobility of the sample.is a graph showing temperature dependency of the field effect mobility of the sample.is a graph showing the relation between each temperature and a maximum value of the field effect mobility at each temperature at the time of examining the temperature dependency shown in. In the graphs shown in, the axes of abscissas show the strength of the electric fields formed in the gate insulating films, and the axes of ordinates show the field effect mobility.

1 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 7 1 21 2 22 6 FIG. 7 FIG. 8 FIG. As to the respective ones of the samplesand, temperatures of SiC substrates were set to 110 K, 150 K, 200 K, 250 K, 300 K, 400 K, 500 K and 600 K, and the relations between the strength of the electric fields formed in the gate insulating films and the field effect mobility at each temperature were examined.shows the relations at the times when the temperatures of the SiC substrate were 110 K, 150 K, 200 k, 250 K, 300 K, 400 K, 500 K and 600 K with curves C, C, C, C, C, C, Cand Crespectively.shows the relations at the times when the temperatures of the SiC substrate were 110 K, 150 K, 200 k, 250 K, 300 K, 400 K, 500 K and 600 K with curves C, C, C, C, C, C, Cand Crespectively.shows the relation between the strength of the electric field formed in the gate insulating filmand the field effect mobility at each temperature in the samplewith a curve C, and shows the relation between the strength of the electric field formed in the gate insulating film and the field effect mobility at each temperature in the samplewith a curve C.

21 22 1 2 1 2 8 FIG. Comparing the curves Cand Cshown inwith each other, it is understood that the temperature dependency of the field effect mobility of the sampleis smaller than the temperature dependency of the field effect mobility of the sample, although the maximum value of the field effect mobility of the sampleat each temperature is slightly lower than the maximum value of the field effect mobility of the sampleat each temperature.

12 20 1 2 1 1 7 6 FIG. 7 FIG. 1 FIG. Comparing the curve Cshown inand the curve Cshown inwith each other, it is understood that the field effect mobility of the sampleis greater than the field effect mobility of the sampleunder the condition that high electric fields (electric fields of not less than 2 MV/cm) are formed in the gate insulating films at high temperature. Therefore, the sample, i.e., the semiconductor devicehaving the MISFET of the structure shown inis suitable as a power device operating under the condition that an electric field of 3 to 4 MV/cm is formed in the gate insulating film.

3 2 3 3 8 9 1 FIG. 3 FIG. 2 Further, a samplehaving a MISFET of the structure shown inwas prepared by a method omitting the nitrogen plasma application step (S) and the FGA step (S) from the manufacturing steps shown in. In the sample, the thickness of an SiOfilmis 10 nm, and the thickness of an AlON filmis 65 nm.

9 FIG. 1 3 is a graph showing the relations between gate voltage (Gate Voltage) and drain current (Drain Current) in the samplesand.

1 3 As to the respective ones of the samplesand, the magnitudes of the drain current at times of varying the gate voltage were examined.

9 FIG. 1 23 3 24 shows the relation between the gate voltage and the drain current in the samplewith a curve C, and shows the relation between the gate voltage and the drain current in the samplewith a curve C.

23 24 1 3 2 3 9 FIG. Comparing the curves Cand Cshown inwith each other, it is understood that the drain current obtained in the sampleis greater than the drain current obtained in the sample. Therefore, the nitrogen plasma application step (S) and the FGA step (S) are conceivably effective for increase of the drain current.

10 FIG. is a graph showing the relations between the strength of electric fields (Gate Oxide Field) formed in gate insulating films and field effect mobility (Field Effect Mobility).

1 3 As to the respective ones of the samplesand, the magnitudes of the field effect mobility at times of varying the electric fields formed in the gate insulating films were examined.

10 FIG. 7 1 26 7 3 25 shows the relation between the strength of the electric field formed in the gate insulating filmand the field effect mobility in the samplewith a curve C, and shows the relation between the strength of the electric field formed in a gate insulating filmand the field effect mobility in the samplewith a curve C.

25 26 1 3 2 3 2 8 14 10 FIG. 2 Comparing the curves Cand Cshown inwith each other, it is understood that the field effect mobility of the sampleis greater than the field effect mobility of the sample. Therefore, the nitrogen plasma application step (S) and the FGA step (S) are conceivably effective as methods of improving the states of the interfaces between the SiC substrateand the SiOfilmsand.

While a structure including a lateral MISFET has been illustrated in the aforementioned embodiment, the present invention can also be applied to a structure including a vertical MISFET.

30 FIG. is a schematic sectional view of a semiconductor device according to reference example studied by the inventor in the process of completing a second embodiment of the present invention.

201 202 203 202 A semiconductor deviceincludes an N-type SiC substrate. An N-type SiC layeris formed on the N-type SiC substrateby epitaxy.

204 203 205 204 204 + A P-type well regionis selectively formed on a surface layer portion of the N-type SiC layer. An N-type source regionis formed on a surface layer portion of the well regionat an interval from a peripheral edge of the well region.

+ 206 204 205 206 205 A P-type contact regiondoped with a P-type impurity in a higher concentration than in the well regionis formed inside each source region. Each contact regionis formed to pass through the source regionin the depth direction.

207 202 2 A gate oxide filmmade of silicon oxide (SiO) is formed on the N-type SiC substrate.

208 207 208 204 205 A gate electrodemade of N-type polycrystalline silicon (N-type Poly-Si) is formed on the gate oxide film. The gate electrodeis opposed to a region (channel region) between the peripheral edge of the well regionand a peripheral edge of the source region.

209 203 An interlayer dielectric filmmade of silicon oxide is stacked on the N-type SiC layer.

209 210 206 210 207 206 205 206 210 In the interlayer dielectric film, a contact holeis formed on a position opposed to each contact region. Each contact holepasses through the gate oxide film. The whole area of the contact regionand a portion of the source regionaround the contact regionface the inner portion of each contact hole.

211 209 211 210 209 205 206 A source metalmade of a metallic material containing aluminum (Al) as a main component is formed on the interlayer dielectric film. The source metalenters each contact holeformed in the interlayer dielectric film, and is connected to the source regionand the contact region.

202 212 213 202 On the back surface of the N-type SiC substrate, an ohmic metalmade of nickel (Ni) or the like and a drain metalmade of a metallic material containing aluminum as a main component are formed in this order from the side of the N-type SiC substrate.

208 211 213 204 207 211 213 The potential (gate voltage) of the gate electrodeis controlled in a state where the source metalis grounded and proper positive voltage is applied to the drain metal, whereby a channel is formed in the well regionin the vicinity of the interface between the same and the gate oxide film, and current flows between the source metaland the drain metal.

201 204 205 203 204 205 207 203 203 In manufacturing steps for the semiconductor device, annealing for activating an N-type impurity is performed after implantation of the N-type impurity into the well regionfor forming the source region. After the annealing, an oxide film formed in the annealing is removed from the upper surface of the N-type SiC layerincluding the upper surfaces of the well regionand the source region. Before the formation of the gate oxide film, a treatment of forming a sacrificial oxide film on the upper surface of the N-type SiC layerby thermal oxidation and removing the sacrificial oxide film may be performed in order to improve the state of the upper surface of the N-type SiC layer.

205 203 204 205 203 204 205 204 205 31 FIG. The source regioncontains the impurity in a higher concentration as compared with the N-type SiC layerand the well region. In the annealing or the thermal oxidation, therefore, growth of the oxide film progresses on the upper surface of the source regionat a higher rate than on the upper surfaces of the N-type SiC layerand the well region. Consequently, a step where the upper surface of the source regionis lower by one stage than the upper surface of the well regionis formed after the oxide film is removed, asshows the vicinity of a peripheral edge portion of the source regionin an enlarged manner.

205 213 205 204 204 204 204 204 204 When such a step is formed, electrons (e) flowing from the source regiontoward the drain metalthrough the channel region move from the source regionto the well region, rise in the well regiontoward the upper surface thereof, and thereafter move along the upper surface of the well region. In other words, the flow of the electrons in the channel region becomes not a straight line, but a path directed toward the upper surface of the well regionand thereafter bent to be along the upper surface of the well region. Therefore, channel resistance enlarges due to the path in which the electrons flow toward the upper surface of the well region.

Therefore, the second embodiment provides a semiconductor device capable of approximating a movement path of carriers in a channel region to a straight line thereby reducing channel resistance.

14 FIG. 15 FIG. 14 FIG. 15 FIG. 16 FIG. 15 FIG. is a schematic plan view of a semiconductor device according to the second embodiment of the present invention.is a schematic sectional view of the semiconductor device taken along a cutting plane line A-A shown in. Referring to, only portions consisting of conductors are hatched, while hatching on the remaining portions is omitted.is a schematic enlarged sectional view in the vicinity of a first region of a source region and a channel region shown in.

101 14 FIG. A semiconductor devicehas a quadrangular (generally square) outer shape in plan view, as shown in.

101 102 102 103 102 103 15 FIG. The semiconductor deviceincludes a semiconductor substrate, as shown in. The semiconductor substrateis made of SiC (N-type SiC) doped with an N-type impurity. A semiconductor layeris formed on the semiconductor substrateby epitaxy. In other words, the semiconductor layeris an epitaxial layer made of N-type SiC.

104 103 104 104 104 16 19 −3 A plurality of P-type well regionsare formed on a surface layer portion of the semiconductor layer. The plurality of well regionsare quadrangular (generally square) in plan view, and arrayed in the form of a matrix. The depth of the well regionsis 0.5 to 2 μm, for example. The well regionshave such an impurity concentration profile that the P-type impurity concentration in portions whose depth from the upper surfaces thereof is not more than 0.5 μm is 1×10to 1×10cm, for example.

104 105 104 105 On a surface layer portion of each well region, an N-type source regionis formed at an interval from a peripheral edge of the well region. The depth of the source regionis 0.2 to 1 μm, for example.

105 105 105 105 105 105 105 105 105 105 + − 17 19 −3 19 20 −3 In the source region, the N-type impurity concentration in a first regionA of a prescribed width (0.2 μm, for example) from a peripheral edge thereof in plan view is lower by one to three digits than the N-type impurity concentration in a remaining second region (region inside the first regionA)B. In other words, the source regionhas the N-type second regionB whose N-type impurity concentration is relatively high and the N-type first regionA, in the form of an annulus surrounding the second regionB, whose N-type impurity concentration is relatively low. The first regionA has such an impurity concentration profile that the N-type impurity concentration in a portion whose depth from the upper surface thereof is not more than 0.2 μm is 5×10to 5×10cm, for example. The second regionB has such an impurity concentration profile that the N-type impurity concentration in a portion whose depth from the upper surface thereof is not more than 0.2 μm is 5×10to 5×10cm, for example.

105 105 105 105 105 104 16 FIG. A step S where the upper surface of the second regionB is lower by one stage than the upper surface of the first regionA is formed between the upper surface of the first regionA and the upper surface of the second regionB (see). The magnitude of the step S is 0.2 μm, for example. No large step is formed between the upper surface of the first regionA and the upper surface of the well region(channel region C), but the upper surfaces are generally flush with each other.

+ 106 104 105 105 106 105 104 105 A P-type contact regiondoped with a P-type impurity in a higher concentration than in the well regionis formed at the center of the second regionB of each source region. Each contact regionis formed to pass through the second regionB in the depth direction, and the deepest portion reaches the well regionpresent under the source region.

107 103 107 107 107 107 107 107 2 2 2 2 2 A gate insulating filmis formed on the semiconductor layer. The gate insulating filmhas an AlON/SiOmultilayer structure including a relatively thin SiOfilmA made of SiO(silicon oxide) containing N (nitrogen) and an AlON filmB made of AlON (aluminum oxynitride) and formed on the SiOfilmA. The thickness of the SiOfilmA is 1 to 20 nm. The thickness of the AlON filmB is 30 to 100 μm.

17 FIG. 2 is a sectional view illustratively showing the structure of the interface between the SiC substrate and the SiOfilm.

103 107 103 107 103 107 2 2 2 Dangling bonds of C (carbon) atoms and Si (silicon) atoms present on the interface between the semiconductor layerand the SiOfilmA are small in number or generally nonexistent, and H (hydrogen) atoms are bonded to the C atoms and the Si atoms present on the interface between the semiconductor layerand the SiOfilmA. In other words, the interface between the semiconductor layerand the SiOfilmA is hydrogen-terminated.

15 FIG. 14 FIG. 108 107 107 108 103 104 104 105 105 105 107 108 101 108 As shown in, a gate electrodeis formed on the gate insulating film(the AlON filmB). The gate electrodeis opposed to the semiconductor layerbetween the well regions, the channel region C between the peripheral edge of each well regionand a peripheral edge of the source regioninside the same and part of the first regionA of the source regionthrough the gate insulating film. The gate electrodeis provided in the form of a lattice in plan view as a whole, as shown in. Thus, the semiconductor devicehas a planar gate MIS structure. The gate electrodeis made of polysilicon doped with an N-type impurity or a P-type impurity, or a metallic material containing Al (aluminum).

14 FIG. 108 109 111 In, the gate electrodeis shown through an interlayer dielectric filmand a source metaldescribed later.

109 103 103 109 108 109 15 FIG. The interlayer dielectric filmis formed on the semiconductor layer, as shown in. The upper surface of the semiconductor layeris covered with the interlayer dielectric film, along with the gate electrode. The interlayer dielectric filmis made of silicon oxide, for example.

109 110 106 110 107 106 105 106 110 In the interlayer dielectric film, a contact holeis formed on a position opposed to each contact region. Each contact holepasses through the gate insulating film, and the whole area of the contact regionand a portion of the source regionaround the contact regionface the inner portion of each contact hole.

111 109 111 110 109 105 106 111 The source metalis formed on the interlayer dielectric film. The source metalenters each contact holeformed in the interlayer dielectric film, and is connected to the source regionand the contact region. The source metalis made of a metallic material containing aluminum (Al) as a main component, for example.

109 111 101 108 112 14 FIG. The interlayer dielectric filmand the source metalare selectively removed at the centers of portions along one side edge of the semiconductor device, whereby an opening exposing part of the gate electrodeas a gate padfor connection with an external portion is formed, as shown in.

102 113 114 102 15 FIG. On the back surface of the semiconductor substrate, an ohmic metalmade of nickel (Ni) or the like and a drain metalmade of a metallic material containing aluminum as a main component are formed on the whole surface thereof in this order from the side of the semiconductor substrate, as shown in.

101 Thus, the semiconductor deviceincludes an N-channel MISFET (Negative-channel Metal Insulator Semiconductor Field Effect Transistor).

108 111 114 104 107 111 114 The potential (gate voltage) of the gate electrodeis controlled in a state where the source metalis grounded and proper positive voltage is applied to the drain metal, whereby a channel is formed in the channel region C of the well regionin the vicinity of the interface between the same and the gate insulating film, and current flows between the source metaland the drain metal.

105 105 101 105 104 16 FIG. The N-type impurity concentration in the first regionA of the source regionadjacent to the channel region C is lowered in the semiconductor device, whereby no large step is formed between the upper surface of the first regionA and the upper surface of the channel region C (the well region), as shown in.

− 111 114 105 105 101 30 FIG. Therefore, electrons (e) flowing between the source metaland the drain metalmove from the source regionto the channel region C along the upper surface of the first regionA, and move in the channel region C along the upper surface thereof. In other words, the path of the electrons in the channel region C becomes a linear path along the upper surface of the channel region C. Therefore, channel resistance of the semiconductor deviceis lower than the channel resistance of the semiconductor device ofin which the movement path of the electrons in the channel region becomes a bent path.

18 18 FIGS.A toK 18 18 FIGS.A toK 19 FIG. are schematic sectional views successively showing manufacturing steps for the semiconductor device. Referring to, only portions consisting of conductors are hatched, while hatching on the remaining portions is omitted.is a manufacturing step diagram for the gate insulating film.

101 103 103 104 141 103 103 141 18 FIG.A In the manufacturing steps for the semiconductor device, a deposition layer of polysilicon is first formed on the semiconductor layerby CVD (Chemical Vapor Deposition). Then, the deposition layer (not shown) of polysilicon is selectively removed from a portion of the semiconductor layerto become the well regionby photolithography and etching. Thus, a maskmade of polysilicon is formed on the semiconductor layer, as shown in. Thereafter a portion of the semiconductor layerexposed from the maskis doped with a P-type impurity (aluminum, for example) by ion implantation.

103 141 141 142 141 142 143 103 106 103 141 142 143 18 FIG.B Then, an oxide film (not shown) made of silicon oxide is formed to collectively cover the semiconductor layerand the mask. Thereafter a deposition layer (not shown) of polysilicon is formed on the oxide film. Then, the deposition layer of polysilicon is etched back through the oxide film serving as an etching stopper and only prescribed portions of the deposition layer in contact with the side surfaces of the maskare left, whereby a maskintegrated with the maskis formed as shown in. Then, the oxide film exposed from the maskis removed. Then, a resist patternis formed on a portion of the semiconductor layerto become the contact regionby photolithography. Thereafter portions of the semiconductor layerexposed from the masksandand the resist patternare doped with an N-type impurity (phosphorus (P), for example) by ion implantation.

143 103 141 142 142 144 141 142 144 145 103 106 103 141 142 144 145 141 142 144 145 18 FIG.C After the resist patternis removed, an oxide film (not shown) made of silicon oxide is formed again, to collectively cover the semiconductor layerand the masksand. Thereafter a deposition layer (not shown) of polysilicon is formed on the oxide film. Then, the deposition layer of polysilicon is etched back through the oxide film serving as an etching stopper and only prescribed portions of the deposition layer in contact with the side surfaces of the maskare left, whereby a maskintegrated with the masksandis formed as shown in. Then, the oxide film exposed from the maskis removed. Then, a resist patternis formed on the portion of the semiconductor layerto become the contact regionby photolithography. Thereafter portions of the semiconductor layerexposed from the masks,andand the resist patternare additionally doped with the N-type impurity by ion implantation. After the doping of the N-type impurity, the masks,andand the resist patternare removed.

18 18 FIGS.B andC 143 145 103 106 143 145 101 In the steps shown in, the formation of the resist patternsandmay be omitted, and the portion of the semiconductor layerto become the contact regionmay be doped with the N-type impurity. Thus, photomasks necessary for the formation of the resist patternsandcan be omitted, and the manufacturing steps for the semiconductor devicecan be simplified.

146 103 146 103 106 103 146 103 104 105 105 105 106 103 103 147 105 105 106 103 104 105 105 147 105 106 18 FIG.D 18 FIG.E Then, a resist patternis formed on the semiconductor layer, as shown in. The resist patternexposes only the portion of the semiconductor layerto become the contact region. Then, the portion of the semiconductor layerexposed from the resist patternis doped with a P-type impurity by ion implantation. Thereafter annealing for activating the P-type impurity and the N-type impurity doped into the semiconductor layeris performed, and the well region, the source region(the first regionA and the second regionB) and the contact regionare formed on the surface layer portion of the semiconductor layer, as shown in. At the annealing, the upper surface of the semiconductor layeris thermally oxidized, whereby an oxide filmis formed. The second regionB of the source regionand the contact regionhave higher impurity concentrations as compared with the semiconductor layer, the well regionand the first regionA of the source region, whereby the oxide filmrelatively thickly grows on the second regionB and the contact region.

147 105 106 103 104 105 105 105 105 18 FIG.F After the oxide filmis removed, therefore, the upper surfaces of the second regionB and the contact regionenter states lower by one stage than the upper surfaces of the semiconductor layer, the well regionand the first regionA of the source region, and the step S is formed between the first regionA and the second regionB, as shown in.

147 103 104 105 106 103 104 105 106 105 105 After the removal of the oxide film, the states of the upper surfaces of the semiconductor layer, the well region, the source regionand the contact regionmay be improved by forming a sacrificial oxide film on the upper surfaces of the semiconductor layer, the well region, the source regionand the contact regionby thermal oxidation and removing the sacrificial oxide film. In this case, a larger step S is formed between the first regionA and the second regionB after the removal of the sacrificial oxide film.

107 103 104 105 106 18 FIG.G Thereafter the gate insulating filmis formed on the upper surfaces of the semiconductor layer, the well region, the source regionand the contact region, as shown in.

107 11 12 13 14 15 2 19 FIG. In order to form the gate insulating film, an SiOfilm formation step (S), a nitrogen plasma application step (S), an FGA (Forming Gas Annealing) step (S), an AlON film formation step (S) and a PDA (Post Deposition Annealing) step (S) are carried out in this order, as shown in.

2 2 2 2 11 107 103 104 105 106 In the SiOfilm formation step (S), an SiOfilmA made of SiOcontaining N is formed on the semiconductor layer, the well region, the source regionand the contact regionby thermal oxidation employing gas containing NO (nitrogen oxide).

12 107 102 107 103 107 2 2 2 In the nitrogen plasma application step (S), nitrogen plasma is applied to the SiOfilmA. The nitrogen plasma is continuously applied over 30 minutes in a state where the semiconductor substrateis heated to 500° C., for example. Atmospheric pressure and RF output at this time are 7.5 Torr and 50 W respectively, for example. The nitrogen plasma is applied to the SiOfilmA, whereby Si—O—C bonds and C—C clusters are cut and dangling bonds of C atoms and Si atoms are formed on the interface between the semiconductor layerand the SiOfilmA.

13 102 103 107 107 103 107 2 2 2 2 2 In the FGA step (S), the semiconductor substrate(the semiconductor layer) and the SiOfilmA are annealed in forming gas containing 3% of H(hydrogen gas) and 97% of N(nitrogen gas). For example, annealing at a temperature of 1000° C. is performed for 30 minutes, and annealing at a temperature of 450° C. is thereafter performed for 30 minutes. Thus, H atoms are excellently introduced into the SiOfilmA, and the number of the dangling bonds of the C atoms and the Si atoms present on the interface between the semiconductor layerand the SiOfilmA decreases.

14 107 107 2 2 2 In the AlON film formation step (S), an AlON filmB is formed on the SiOfilmA by reactive sputtering employing mixed gas of Nand O(oxygen gas) and an Al target.

15 107 107 107 2 In the PDA step (S), the AlON filmB is annealed in N. The annealing is performed at a temperature of 900° C. for 30 minutes, for example. Thus, crystallinity of the AlON filmB rises, and quality of the AlON filmB improves.

107 18 FIG.G Thus, the gate insulating filmis formed as shown in.

148 107 107 18 FIG.H Then, a deposition layerof polysilicon is formed on the gate insulating film(the AlON filmB) by CVD, as shown in.

148 108 107 108 107 18 FIG.I Then, the deposition layeris selectively removed by photolithography and etching, and the gate electrodemade of polysilicon is formed on the gate insulating film, as shown in. Alternatively, a gate electrodemade of a metallic material may be formed by forming a deposition layer of the metallic material containing Al (aluminum) on the gate insulating filmand selectively removing the deposition layer.

109 107 108 18 FIG.J Then, the interlayer dielectric filmis formed on the gate insulating filmand the gate electrodeby CVD, as shown in.

110 109 107 18 FIG.K Then, the contact holepassing through the interlayer dielectric filmand the gate insulating filmis formed by photolithography and etching, as shown in.

111 109 112 113 114 102 101 15 FIG. Thereafter the source metalis formed on the interlayer dielectric filmby sputtering. Then, the gate padis formed by photolithography and etching. Further, the ohmic metaland the drain metalare formed on the back surface of the semiconductor substrateby sputtering. Thus, the semiconductor deviceshown inis obtained.

147 105 105 105 105 104 147 105 As hereinabove described, the rate (rate of oxidation) of the growth of the oxide filmon the upper surface of the first regionA can be suppressed low by lowering the impurity concentration in the first regionA of the source regionadjacent to the channel region C. Therefore, formation of a large step between the upper surface of the first regionA and the upper surface of the channel region C (the well region) can be prevented after the removal of the oxide film. Consequently, the path (movement path) of electrons moving from the source regionto the channel region C can be approximated to a straight line, whereby reduction of channel resistance can be attained.

105 105 105 105 105 105 105 105 105 105 105 105 105 The impurity concentration in the second regionB of the source regionother than the first regionA is higher than the impurity concentration in the first regionA, whereby the step S where the upper surface of the second regionB is lower by one stage than the upper surface of the first regionA is formed between the upper surface of the first regionA and the upper surface of the second regionB. Even if the step S is formed between the upper surface of the first regionA and the upper surface of the second regionB, the step S does not influence the flow of the electrons in the channel region C. Therefore, the channel resistance can be reduced without reducing the carrier concentration in the source regionby relatively lowering the impurity concentration in the first regionA and relatively raising the impurity concentration in the second regionB.

107 102 107 107 102 103 107 102 107 13 102 107 102 107 2 2 2 2 2 2 2 19 FIG. In relation to the manufacturing of the gate insulating film, dangling bonds of C atoms and Si atoms are present on the interface between the semiconductor substrateand the SiOfilmA in the state where the SiOfilmA is simply formed on the semiconductor substrate(the semiconductor layer). After the formation of the SiOfilmA, therefore, the semiconductor substrateand the SiOfilmA are annealed in the forming gas containing H(the FGA step Sin). Thus, H atoms are bonded to the dangling bonds of the C atoms and the Si atoms, and the interface between the semiconductor substrateand the SiOfilmA is hydrogen-terminated. Consequently, the number of defects (interface state density) on the interface between the semiconductor substrateand the SiOfilmA decreases, and the state of the interface is improved.

102 107 107 107 14 107 107 102 107 102 107 2 2 2 2 2 19 FIG. After the annealing of the semiconductor substrateand the SiOfilmA, the AlON filmB is formed on the SiOfilmA (the AlON film formation step Sin). The AlON filmB is present on the SiOfilmA, whereby dehydrogenation from the semiconductor substrateand the SiOfilmA is prevented. Therefore, the state of the interface between the semiconductor substrateand the SiOfilmA improved by the hydrogen termination is maintained.

102 107 2 Thus, the state of the interface between the semiconductor substrateand the SiOfilmA can be improved, and the improved state can be maintained.

101 107 102 107 101 19 FIG. 2 2 In the semiconductor devicewhose gate insulating filmis manufactured by the manufacturing method shown in, therefore, the interface between the semiconductor substrateand the SiOfilmA is hydrogen-terminated. Therefore, the semiconductor devicehas lower interface state density and can exhibit higher channel mobility, as compared with a structure having a large number of dangling bonds on an interface between an SiC substrate and an SiOfilm.

107 107 107 107 101 107 2 2 2 In the gate insulating filmconsisting of the SiOfilmA and the AlON filmB, leakage current can be reduced while ensuring equivalent or higher electric characteristics as compared with a gate insulating film consisting of only an SiOfilm, by enlarging the thickness of the AlON filmB. In the semiconductor device, therefore, reliability of the gate insulating filmis high as compared with the structure employing the gate insulating film consisting of only the SiOfilm.

108 107 108 The gate electrodeformed on the AlON filmB is suitably made of a metallic material containing Al. Thus, improvement in operating speed of the MISFET and reduction of power consumption can be attained as compared with such a structure that the gate electrodeis made of polycrystalline silicon.

107 107 107 15 107 107 19 FIG. In the manufacturing steps for the gate insulating film, the AlON filmB is annealed after the formation of the AlON filmB (the PDA step Sin). Thus, crystallinity of the AlON filmB can be raised, and quality of the AlON filmB can be improved.

2 2 2 2 2 2 107 102 107 12 102 107 102 107 102 107 102 107 19 FIG. Further, the nitrogen plasma is applied to the SiOfilmA before the annealing of the semiconductor substrateand the SiOfilmA (the nitrogen plasma application step Sin). Thus, Si—O—C bonds and C—C clusters can be cut and dangling bonds of carbon atoms and silicon atoms can be formed on the interface between the semiconductor substrateand the SiOfilmA. The annealing of the semiconductor substrateand the SiOfilmA is performed after the application of the nitrogen plasma, whereby H atoms can be easily bonded to the dangling bonds of the C atoms and the Si atoms present on the interface between the semiconductor substrateand the SiOfilmA. Consequently, the interface between the semiconductor substrateand the SiOfilmA can be excellently hydrogen-terminated.

2 2 2 2 107 107 107 Further, the SiOfilmA is formed by the thermal oxidation employing the gas containing the nitrogen oxide (NO). Thus, N atoms can be introduced into the SiOfilmA, and the dielectric constant of the SiOfilmA can be raised. Consequently, the leakage current can be further reduced.

20 FIG. 20 FIG. 15 FIG. 15 FIG. 20 FIG. 20 FIG. is a schematic sectional view of a semiconductor device according to a modification. Referring to, portions corresponding to the respective portions shown inare denoted by the same reference numerals as the reference numerals assigned to the respective portions. In the following, only a point different from the structure shown inis described as to the structure shown in, and description of the respective portions denoted by the same reference numerals is omitted. Referring to, only portions consisting of conductors are hatched, while hatching on the remaining portions is omitted.

105 105 105 101 105 105 105 151 105 105 151 101 15 FIG. 20 FIG. 15 FIG. While the depth of the first regionA of the source regionand the depth of the second regionB are generally identical to each other in the semiconductor deviceshown in, the depth of a first regionA of a source regionis smaller than the depth of a second regionB in a semiconductor deviceshown in. Also when the depth of the first regionA is smaller than the depth of the second regionB as in the semiconductor device, effects similar to those of the semiconductor deviceshown incan be attained.

21 FIG. 21 FIG. is a schematic sectional view of a semiconductor device according to another modification. Referring to, only portions consisting of conductors are hatched, while hatching on the remaining portions is omitted.

101 151 161 15 FIG. 20 FIG. 21 FIG. While the semiconductor deviceshown inand the semiconductor deviceshown inhave planar gate MIS structures, a semiconductor deviceshown inhas a trench gate MIS structure.

161 162 162 163 162 163 The semiconductor deviceincludes a semiconductor substrate. The semiconductor substrateis made of SiC (N-type SiC) doped with an N-type impurity. A semiconductor layeris formed on the semiconductor substrateby epitaxy. In other words, the semiconductor layeris an epitaxial layer made of N-type SiC.

163 164 163 165 − A base layer portion of the semiconductor layermaintains the state after the epitaxy, and forms an N-type drain region. A surface layer portion of the semiconductor layeris doped with a P-type impurity, to be converted to a P-type well region.

163 166 166 108 166 165 164 14 FIG. In the semiconductor layer, a gate trenchis formed to be dug down from the surface thereof. The gate trenchis provided in the form of a lattice in plan view, similarly to the gate electrodeshown in, for example. The gate trenchpasses through the well region, and the deepest portion thereof reaches the drain region.

167 166 167 167 167 167 166 167 167 2 2 2 2 2 A gate insulating filmis formed on the inner surface of the gate trench. The gate insulating filmhas an AlON/SiOmultilayer structure including a relatively thin SiOfilmA made of SiO(silicon oxide) containing N (nitrogen) and an AlON filmB made of AlON (aluminum oxynitride). The SiOfilmA is in contact with the inner surface of the gate trench, and the AlON filmB is formed on the SiOfilmA.

167 168 166 168 The inner side of the gate insulating filmis filled up with polysilicon doped with an N-type impurity or a P-type impurity, whereby a gate electrodemade of the doped polysilicon is embedded in the gate trench. Alternatively, the gate electrodemay be made of a metallic material containing Al (aluminum).

169 165 169 169 169 An N-type source regionis formed on a surface layer portion of the well region. The depth of the source region(the total depth of a first regionA and a second regionB described later) is 0.5 to 2 μm, for example.

169 169 169 169 169 169 169 169 169 169 + − 17 19 −3 19 20 −3 In the source region, the N-type impurity concentration in the first regionA of a prescribed depth (0.2 μm, for example) on the bottom portion thereof is lower by one to three digits than the N-type impurity concentration in the remaining second region (region on the first regionA)B. In other words, the source regionhas the N-type second regionB whose N-type impurity concentration is relatively high and the N-type first regionA, formed under the second regionB, whose N-type impurity concentration is relatively low. The N-type impurity concentration in the first regionA is 5×10to 5×10cm, for example, and the N-type impurity concentration in the second regionB is 5×10to 5×10cm, for example.

169 168 169 169 169 169 169 169 165 167 169 169 169 A step S where the side surface of the second regionB more separates from the gate electrodethan the side surface of the first regionA is formed between the side surface of the first regionA and the side surface of the second regionB, due to the difference between the N-type impurity concentrations in the first regionA and the second regionB. The magnitude of the step S is 0.1 μm, for example. No large step is formed between the side surface of the first regionA and the side surface of the well region(channel region C), but the side surfaces are generally flush with each other. The gate insulating filmhas a relatively large thickness on the side surface of the second regionB, due to the difference between the N-type impurity concentrations in the first regionA and the second regionB.

165 170 169 166 166 + On the surface layer portion of the well region, a P-type contact regionis formed to pass through the source regionin the thickness direction on a position at an interval from the gate trenchin each region surrounded by the gate trench.

171 163 171 An interlayer dielectric filmis stacked on the semiconductor layer. The interlayer dielectric filmis made of silicon oxide, for example.

171 172 170 170 169 170 172 In the interlayer dielectric film, a contact holeis penetratingly formed on a position opposed to each contact region. The whole area of the contact regionand a portion of the source regionaround the contact regionface the inner portion of each contact hole.

173 171 173 172 169 170 173 A source metalis formed on the interlayer dielectric film. The source metalenters each contact hole, and is connected to the source regionand the contact region. The source metalis made of a metallic material containing Al as a main component, for example.

162 174 175 162 On the back surface of the semiconductor substrate, an ohmic metalmade of nickel (Ni) or the like and a drain metalmade of a metallic material containing aluminum as a main component are formed on the whole surface thereof in this order from the side of the semiconductor substrate.

168 173 175 165 167 173 175 The potential (gate voltage) of the gate electrodeis controlled in a state where the source metalis grounded and proper positive voltage is applied to the drain metal, whereby a channel is formed in the channel region C of the well regionin the vicinity of the interface between the same and the gate insulating film, and current flows between the source metaland the drain metal.

22 FIG. 21 FIG. is a schematic enlarged sectional view in the vicinity of the first region of the source region and the channel region shown in.

169 169 161 169 165 The N-type impurity concentration in the first regionA of the source regionadjacent to the channel region C is lowered in the semiconductor device, whereby no large step is formed between the side surface of the first regionA and the side surface of the channel region C (the well region).

− 173 175 169 169 166 161 101 151 161 Therefore, electrons (e) flowing between the source metaland the drain metalmove from the source regionto the channel region C along the side surface of the first regionA (the inner surface of the gate trench), and move in the channel region C along the side surface thereof. In other words, the path of the electrons in the channel C becomes a linear path along the side surface of the channel region C. Also according to the structure of the semiconductor device, therefore, functions/effects similar to those of the semiconductor devicesandcan be exhibited, and channel resistance of the semiconductor deviceis lower than the channel resistance of the conventional semiconductor device in which the movement path of the electrons in the channel region becomes a bent path.

103 163 102 162 103 163 104 165 105 169 102 162 While such structures that the semiconductor layersandare stacked on the semiconductor substratesandhave been adopted, the semiconductor layersandmay be omitted, and the well regionsandand the source regionsandetc. may be formed on the surface layer portions of the semiconductor substratesand.

Further, the conductivity type of each portion may be inverted. In other words, while the case where the first conductivity type is the N type and the second conductivity type is the P type has been adopted, the first conductivity type may be the P type, and the second conductivity type may be the N type.

101 101 107 107 2 2 15 FIG. 18 19 FIGS.to A sample(AlON/SiO) having a MISFET of the structure shown inwas prepared by the manufacturing method shown in. In the sample, the thickness of an SiOfilmA is 10 nm, and the thickness of an AlON filmB is 65 nm.

102 102 102 2 2 Further, a sample(SiO) having a MOSFET of a structure obtained by stacking a gate electrode on a semiconductor substratethrough a gate insulating film consisting of a single layer of SiOwas prepared. In the sample, the thickness of the gate insulating film is 40 nm.

23 FIG. 101 102 is a graph showing the relations between gate voltage (Gate Voltage) and drain current (Drain Current) in the samplesand.

101 102 As to the respective ones of the samplesand, the magnitudes of the drain current at times of varying the gate voltage were examined.

23 FIG. 101 101 102 102 assigns Cto a curve showing the relation between the gate voltage and the drain current in the sample, and assigns Cto a curve showing the relation between the gate voltage and the drain current in the sample.

24 FIG. is a graph showing the relations between the strength of electric fields (Gate Oxide Field) formed in gate insulating films and field effect mobility (Field Effect Mobility).

101 102 As to the respective ones of the samplesand, the magnitudes of the field effect mobility at times of varying the electric fields formed in the gate insulating films were examined.

24 FIG. 103 107 101 104 102 assigns Cto a curve showing the relation between the strength of the electric field formed in a gate insulating filmand the field effect mobility in the sample, and assigns Cto a curve showing the relation between the strength of the electric field formed in the gate insulating film and the field effect mobility in the sample.

101 104 101 102 107 107 107 107 107 23 24 FIGS.and 2 2 2 From the curves Cto Cshown in, it is understood that transistor operating characteristics of the samplesandare generally identical to each other. Also in the MISFET employing the gate insulating filmconsisting of the SiOfilmA and the AlON filmB, the field effect mobility is generally identical to that of the MOSFET employing the gate insulating film consisting of the single layer of SiO, and hence no increase of interface state density is conceivably caused by stacking the AlON filmB on the SiOfilmA.

13 FIG. 2 2 2 2 2 In the evaluation (see) of the interface state density previously executed by the inventors of this application, therefore, the interface state density of the SiC-MIS structure employing the AlON/SiOmultilayer gate insulating film more increased than the interface state density of the SiC-MOS structure employing the SiOsingle-layer gate insulating film, is conceivable as a result of reflecting defects (defects on the AlON/SiOinterface, for example) not influencing the transistor operating characteristics. More specifically, this evaluation is evaluation performed by calculating each interface state density of the SiC-MIS structure employing the AlON/SiOmultilayer gate insulating film and the SiC-MOS structure employing the SiOsingle-layer gate insulating film by a High-Low method and comparing the same.

25 FIG. 26 FIG. 27 FIG. 25 26 FIGS.and 25 26 FIGS.and 101 102 is a graph showing temperature dependency of the field effect mobility of the sample.is a graph showing temperature dependency of the field effect mobility of the sample.is a graph showing the relation between each temperature and a maximum value of the field effect mobility at each temperature at the time of examining the temperature dependency shown in. In the graphs shown in, the axes of abscissas show the strength of the electric fields formed in the gate insulating films, and the axes of ordinates show the field effect mobility.

101 102 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 107 101 121 102 122 25 FIG. 26 FIG. 27 FIG. As to the respective ones of the samplesand, temperatures of the semiconductor substrates (SiC substrates) were set to 110 K, 150 K, 200 K, 250 K, 300 K, 400 K, 500 K and 600 K, and the relations between the strength of the electric fields formed in the gate insulating films and the field effect mobility at each temperature were examined.shows the relations at the times when the temperatures of the SiC substrate were 110 K, 150 K, 200 k, 250 K, 300 K, 400 K, 500 K and 600 K with curves C, C, C, C, C, C, Cand Crespectively.shows the relations at the times when the temperatures of the SiC substrate were 110 K, 150 K, 200 k, 250 K, 300 K, 400 K, 500 K and 600 K with curves C, C, C, C, C, C, Cand Crespectively.shows the relation between the strength of the electric field formed in the gate insulating filmand the field effect mobility at each temperature in the samplewith a curve C, and shows the relation between the strength of the electric field formed in the gate insulating film and the field effect mobility at each temperature in the samplewith a curve C.

121 122 101 102 101 102 27 FIG. Comparing the curves Cand Cshown inwith each other, it is understood that the temperature dependency of the field effect mobility of the sampleis smaller than the temperature dependency of the field effect mobility of the sample, although the maximum value of the field effect mobility of the sampleat each temperature is slightly lower than the maximum value of the field effect mobility of the sampleat each temperature.

112 120 101 102 101 101 107 25 FIG. 26 FIG. 15 FIG. Comparing the curve Cshown inand the curve Cshown inwith each other, it is understood that the field effect mobility of the sampleis greater than the field effect mobility of the sampleunder the condition that high electric fields (electric fields of not less than 2 MV/cm) are formed in the gate insulating films at high temperature. Therefore, the sample, i.e., the semiconductor devicehaving the MISFET of the structure shown inis suitable as a power device operating under the condition that an electric field of 3 to 4 MV/cm is formed in the gate insulating film.

103 12 13 103 107 107 15 FIG. 19 FIG. 2 Further, a samplehaving a MISFET of the structure shown inwas prepared by a method omitting the nitrogen plasma application step (S) and the FGA step (S) from the manufacturing steps shown in. In the sample, the thickness of an SiOfilmA is 10 nm, and the thickness of an AlON filmB is 65 nm.

28 FIG. 101 103 is a graph showing the relations between gate voltage (Gate Voltage) and drain current (Drain Current) in the samplesand.

101 103 As to the respective ones of the samplesand, the magnitudes of the drain current at times of varying the gate voltage were examined.

28 FIG. 101 123 103 124 shows the relation between the gate voltage and the drain current in the samplewith a curve C, and shows the relation between the gate voltage and the drain current in the samplewith a curve C.

123 124 101 103 12 13 28 FIG. Comparing the curves Cand Cshown inwith each other, it is understood that the drain current obtained in the sampleis greater than the drain current obtained in the sample. Therefore, the nitrogen plasma application step (S) and the FGA step (S) are conceivably effective for increase of the drain current.

29 FIG. is a graph showing the relations between the strength of electric fields (Gate Oxide Field) formed in gate insulating films and field effect mobility (Field Effect Mobility).

101 103 107 As to the respective ones of the samplesand, the magnitudes of the field effect mobility at times of varying the electric fields formed in gate insulating filmswere examined.

29 FIG. 107 101 126 107 103 125 shows the relation between the strength of the electric field formed in the gate insulating filmand the field effect mobility in the samplewith a curve C, and shows the relation between the strength of the electric field formed in the gate insulating filmand the field effect mobility in the samplewith a curve C.

125 126 101 103 12 13 102 107 29 FIG. 2 Comparing the curves Cand Cshown inwith each other, it is understood that the field effect mobility of the sampleis greater than the field effect mobility of the sample. Therefore, the nitrogen plasma application step (S) and the FGA step (S) are conceivably effective as methods of improving the state of the interface between the semiconductor substrateand the SiOfilmA.

2 As hereinabove described, high-density interface states (interface defects) are formed on the interface (SiO/SiC interface) between the SiC substrate and the gate insulating film in the MOSFET (SiC-MOSFET) employing SiC. Therefore, the SiC-MOSFET has low channel mobility.

2 2 The density of the interface states (interface state density) on the SiO/SiC interface can be lowered by thinning the gate insulating film made of SiO. When the gate insulating film is thinned, however, leakage current increases as a result.

Therefore, a third embodiment provides a semiconductor device capable of attaining reduction of both of interface state density on an interface between a silicon carbide layer and a gate insulating film and leakage current.

32 FIG. is a schematic sectional view of a semiconductor device according to the third embodiment of the present invention.

301 302 303 302 A semiconductor deviceincludes an SiC substratemade of SiC (N-type SiC) doped with an N-type impurity. An SiC layermade of N-type SiC is formed on the SiC substrateby epitaxy.

304 303 304 A plurality of P-type well regionsare formed on a surface layer portion of the SiC layer. The plurality of well regionsare quadrangular (generally square) in plan view, and arrayed in the form of a matrix.

304 305 304 305 303 + On a surface layer portion of each well region, a source regionis formed at an interval from a peripheral edge of the well region. The source regionis doped with an N-type impurity in a higher concentration than in the SiC layer, to exhibit an Nconductivity type.

306 305 306 305 304 305 306 304 + A contact regionis formed at the center of each source region. The contact regionis formed to pass through the source regionin the depth direction, and the deepest portion reaches the well regionpresent under the source region. The contact regionis doped with a P-type impurity in a higher concentration than in the well region, to exhibit a Pconductivity type.

307 303 307 303 304 304 305 305 307 A gate insulating filmis formed on the SiC layer. The gate insulating filmis opposed to the SiC layerbetween the well regions, a region (channel region) between the peripheral edge of each well regionand a peripheral edge of the source regioninside the same and part of the source region. The gate insulating filmis provided in the form of a lattice in plan view as a whole.

307 307 307 307 307 307 2 x y x y 2 2 2 The gate insulating filmhas an AlON/SiO/SiONmultilayer structure including an SiON filmA made of SiON(silicon oxynitride), an SiOfilmB made of SiO(silicon oxide) and formed on the SiON filmA, and an AlON filmC made of AlON (aluminum oxynitride) which is a high dielectric constant (High-k) insulating material and formed on the SiOfilmB.

307 307 307 307 307 2 2 The thickness of the SiON filmA is 1 to 5 nm. The thickness of the SiOfilmB is 1 to 5 nm. The total thickness of the SiON filmA and the SiOfilmB is 2 to 10 nm. The thickness of the AlON filmC is 10 to 200 nm. Each range includes the lower limit and the upper limit thereof.

308 307 301 308 A gate electrodeis formed on the gate insulating film. Thus, the semiconductor devicehas a planar gate MIS structure. The gate electrodeis made of a metallic material containing Al (aluminum) as a main component.

309 303 303 309 307 308 309 2 An interlayer dielectric filmis formed on the SiC layer. The upper surface of the SiC layeris covered with the interlayer dielectric film, along with the gate insulating filmand the gate electrode. The interlayer dielectric filmis made of SiO, for example.

309 310 306 306 305 306 310 In the interlayer dielectric film, a contact holeis formed on a position opposed to each contact region. The whole area of the contact regionand a portion of the source regionaround the contact regionface the inner portion of each contact hole.

311 309 311 310 309 305 306 311 A source metalis formed on the interlayer dielectric film. The source metalenters each contact holeformed in the interlayer dielectric film, and is connected to the source regionand the contact region. The source metalis made of a metallic material containing Al as a main component, for example.

302 312 On the back surface of the SiC substrate, a drain metalmade of a metallic material containing Al as a main component is formed on the whole surface thereof through an ohmic metal (not shown) made of Ni (nickel) or the like.

308 311 312 304 307 311 312 The potential (gate voltage) of the gate electrodeis controlled in a state where the source metalis grounded and proper positive voltage is applied to the drain metal, whereby a channel is formed in the channel region of the well regionin the vicinity of the interface between the same and the gate insulating film, and current flows between the source metaland the drain metal.

33 FIG. is a manufacturing step diagram for the gate insulating film.

301 303 302 304 305 306 303 21 22 23 24 25 307 x 2 In order to manufacture the semiconductor device, the SiC layeris formed on the SiC substrateby epitaxy. Then, the well region, the source regionand the contact regionare formed on the SiC layerby a well-known technique including ion implantation or the like. Thereafter an NOthermal oxidation step (S), an Othermal oxidation step (S), an FGA (Forming Gas Annealing) step (S), an AlON film formation step (S) and a PDA (Post Deposition Annealing) step (S) are carried out in this order, in order to form the gate insulating film.

x x y 2 21 303 In the NOthermal oxidation step (S), an SiON film made of SiONis formed on the SiC layerby thermal oxidation employing gas containing NO (nitrogen oxide).

2 2 2 2 22 In the Othermal oxidation step (S), an SiOfilm made of SiOis formed on the SiON film by thermal oxidation employing dry gas of O.

23 303 2 2 2 2 In the FGA step (S), the SiOfilm is annealed in forming gas containing 3% of H(hydrogen gas) and 97% of N(nitrogen gas). For example, annealing at a temperature of 1000° C. is performed for 30 minutes, and annealing at a temperature of 450° C. is thereafter performed for 30 minutes. Thus, H atoms are excellently introduced into the SiOfilm, and the number of dangling bonds of C atoms and Si atoms present on the interface between the SiC layerand the SiON film decreases.

24 2 2 2 In the AlON film formation step (S), an AlON film is formed on the SiOfilm by reactive sputtering employing mixed gas of Nand O(oxygen gas) and an Al target.

25 2 In the PDA step (S), the AlON film is annealed in N. The annealing is performed at a temperature of 900° C. for 10 minutes, for example. Thus, crystallinity of the AlON film rises, and quality of the AlON film improves.

308 308 308 307 307 307 309 310 311 312 301 2 2 2 32 FIG. Thereafter the gate electrodeis formed on the AlON film. The gate electrodeis formed by selectively vapor-depositing the material (Al) for the gate electrode on the surface of the AlON film with a mask, for example. Then, exposed portions (portions not opposed to the gate electrode) of the AlON film, the SiOfilm and the SiON film are removed in this order by photolithography and etching, and the AlON film, the SiOfilm and the SiON film are worked into the AlON filmC, the SiOfilmB and the SiON filmA respectively. When the interlayer dielectric film, the contact hole, the source metaland the drain metalare thereafter formed by well-known methods, the semiconductor deviceshown inis obtained.

307 307 307 307 303 2 As hereinabove described, the gate insulating filmhas the structure obtained by stacking the SiON filmA, the SiOfilmB and the AlON filmC from the side of the SiC layer.

307 303 307 303 307 2 The SiON filmA is interposed between the SiC layerand the SiOfilmB, whereby reduction of interface state density Dit on the interface between the SiC layer(SiC) and the gate insulating filmcan be attained as compared with such a structure that a gate insulating film consists of only a silicon oxide film. Further, improvement of channel mobility can be attained due to the reduction of the interface state density Dit.

307 303 307 307 307 307 2 In addition, reduction of leakage current resulting from increase in the thickness of the gate insulating filmcan be attained while suppressing increase in the interface state density on the interface between the SiC layerand the gate insulating filmby reducing the total thickness of the SiON filmA and the SiOfilmB and increasing the thickness of the AlON filmC.

307 Therefore, both of improvement of the channel mobility resulting from the reduction of the interface state density Dit and improvement of reliability of the gate insulating filmresulting from the reduction of the leakage current can be attained.

308 303 307 308 308 The gate electrodeis made of the metallic material containing Al. Thus, improvement in operating speed of the MISFET (field effect transistor of a planar gate MIS structure) constituted of the SiC layer, the gate insulating filmand the gate electrodeetc. and reduction of power consumption can be attained as compared with such a structure that the gate electrodeis made of polycrystalline silicon.

201 201 307 307 307 2 x y 2 32 FIG. A samplehaving the SiC-MIS structure (the structure including the AlON/SiO/SiONmultilayer gate insulating film on SiC) shown inwas prepared. In the sample, the thickness of an SiON filmA is 5 nm, the thickness of an SiOfilmB is 5 nm and the thickness of an AlON filmC is 80 nm.

202 202 2 2 2 2 Further, a samplehaving an SiC-MIS structure employing an AlON/SiOmultilayer gate insulating film (gate insulating film of a structure obtained by stacking an SiOfilm made of SiOand an AlON film made of AlON on SiC in this order) was prepared. In the sample, the thickness of the SiOfilm is 10 nm, and the thickness of the AlON film is 80 nm.

201 202 34 FIG. 34 FIG. As to the respective ones of the samplesand, high-frequency CV characteristics (at a measuring frequency of 100 kHz, for example) and low-frequency CV characteristics (quasi-static CV characteristics) were measured, and the differences between high-frequency measured values and low-frequency measured values were calculated as the interface state density Dit by a High-Low method.shows the results. Referring to, the axis of abscissas shows energy (Ec-E) from valence band edges of the gate insulating films, and the axis of ordinates shows the interface state density Dit.

34 FIG. 201 202 From the results shown in, it is understood that the interface state density Dit in the sampleis lower than the interface state density Dit of the sample.

35 FIG. is another manufacturing step diagram for the gate insulating film.

307 31 32 33 34 35 32 FIG. 35 FIG. 33 FIG. 35 FIG. 2 The gate insulating filmshown incan be formed by a technique including the manufacturing steps shown in, in place of the technique including the manufacturing steps shown in. In the manufacturing steps shown in, a nitrogen plasma application step (S), an Othermal oxidation step (S), an FGA step (S), an AlON film formation step (S) and a PDA step (S) are carried out in this order.

31 303 303 303 In the nitrogen plasma application step (S), nitrogen plasma is applied to the SiC layer. The nitrogen plasma is continuously applied over 30 minutes in a state where the SiC layeris heated to 500° C., for example. Atmospheric pressure and RF output at this time are 9.5 Torr and 50 W respectively, for example. Thus, an SiON film is formed on the SiC layer.

2 2 2 2 32 In the Othermal oxidation step (S), an SiOfilm made of SiOis formed on the SiON film by thermal oxidation employing dry gas of O.

33 34 35 23 24 25 33 FIG. In the FGA step (S), the AlON film formation step (S) and the PDA step (S), treatments similar to those in the FGA step (S), the AlON film formation step (S) and the PDA step (S) shown inare performed respectively.

36 FIG. is a schematic sectional view of a semiconductor device according to a modification.

301 351 32 FIG. 36 FIG. While the semiconductor deviceshown inhas the planar gate MIS structure, a semiconductor deviceshown inhas a trench gate MIS structure.

351 352 353 352 The semiconductor deviceincludes an SiC substratemade of N-type SiC. An SiC layermade of N-type SiC is formed on the SiC substrateby epitaxy.

353 354 353 355 − A base layer portion of the SiC layermaintains the state after the epitaxy, and forms an N-type drain region. A surface layer portion of the SiC layeris doped with a P-type impurity, to be converted to a P-type well region.

353 356 356 356 355 354 In the SiC layer, a gate trenchis formed to be dug down from the surface thereof. The gate trenchis provided in the form of a lattice in plan view, for example. The gate trenchpasses through the well region, and the deepest portion thereof reaches the drain region.

357 356 357 353 356 357 357 357 357 357 357 2 x y x y 2 2 2 A gate insulating filmis formed on the inner surface of the gate trench. A peripheral edge portion of the gate insulating filmis in contact with the upper surface of the SiC layeron the outside of the gate trench. The gate insulating filmhas an AlON/SiO/SiONmultilayer structure including an SiON filmA made of SiON, an SiOfilmB made of SiOand formed on the SiON filmA, and an AlON filmC made of AlON which is a high dielectric constant insulating material and formed on the SiOfilmB.

357 357 357 357 357 2 2 The thickness of the SiON filmA is 1 to 5 nm. The thickness of the SiOfilmB is 1 to 5 nm. The total thickness of the SiON filmA and the SiOfilmB is 2 to 10 nm. The thickness of the AlON filmC is 10 to 200 nm. Each range includes the lower limit and the upper limit thereof.

358 357 A gate electrodemade of a metallic material containing Al as a main component is formed on the gate insulating film.

359 355 An N-type source regionis formed on a surface layer portion of the well region.

355 360 359 356 356 360 355 + On the surface layer portion of the well region, further, a contact regionis formed to pass through the source regionin the thickness direction on a position at an interval from the gate trenchin each region surrounded by the gate trench. The contact regionis doped with a P-type impurity in a higher concentration than in the well region, to exhibit a Pconductivity type.

361 353 361 An interlayer dielectric filmis stacked on the SiC layer. The interlayer dielectric filmis made of silicon oxide, for example.

361 362 360 360 359 360 362 In the interlayer dielectric film, a contact holeis penetratingly formed on a position opposed to each contact region. The whole area of the contact regionand a portion of the source regionaround the contact regionface the inner portion of each contact hole.

363 361 363 362 359 360 363 A source metalis formed on the interlayer dielectric film. The source metalenters each contact hole, and is connected to the source regionand the contact region. The source metalis made of a metallic material containing Al as a main component, for example.

352 364 On the back surface of the SiC substrate, a drain metalmade of a metallic material containing Al as a main component is formed on the whole surface thereof through an ohmic metal (not shown) made of Ni or the like.

358 363 364 355 357 363 364 The potential (gate voltage) of the gate electrodeis controlled in a state where the source metalis grounded and proper positive voltage is applied to the drain metal, whereby a channel is formed in a channel region of the well regionin the vicinity of the interface between the same and the gate insulating film, and current flows between the source metaland the drain metal.

351 301 32 FIG. Also in the semiconductor device, functions/effects similar to those of the semiconductor deviceshown incan be attained.

37 FIG. is a schematic sectional view of a semiconductor device according to another modification.

301 351 381 32 FIG. 36 FIG. 37 FIG. While the semiconductor deviceshown inand the semiconductor deviceshown ininclude vertical MISFETS, a semiconductor deviceshown inincludes a lateral MISFET.

381 382 The semiconductor deviceincludes an SiC substrateas a silicon carbide layer made of N-type SiC.

383 382 384 385 383 384 385 383 384 385 382 + A P-type well regionis formed on a surface layer portion of the SiC substrate. A source regionand a drain regionare formed on a surface layer portion of the well region. The source regionand the drain regionare formed at intervals from a peripheral edge portion of the well regionrespectively, and at an interval from each other. The source regionand the drain regionare doped with an N-type impurity in higher concentrations than in the SiC substrate, to exhibit Nconductivity types.

386 383 386 384 385 386 383 + A contact regionis formed on the surface layer portion of the well region. The contact regionis formed adjacently to a side of the source regionopposite to the drain region. The contact regionis doped with a P-type impurity in a higher concentration than in the well region, to exhibit a Pconductivity type.

387 384 385 387 384 385 384 385 387 387 387 387 387 387 2 x y x y 2 2 2 A gate insulating filmis formed on a region (channel region) between the source regionand the drain region. More specifically, the gate insulating filmis opposed to the region between the source regionand the drain region, and extends over a peripheral edge portion of the source regionand a peripheral edge portion of the drain region. The gate insulating filmhas an AlON/SiO/SiONmultilayer structure including an SiON filmA made of SiON, an SiOfilmB made of SiOand formed on the SiON filmA, and an AlON filmC made of AlON which is a high dielectric constant insulating material and formed on the SiOfilmB.

387 387 387 387 387 2 2 The thickness of the SiON filmA is 1 to 5 nm. The thickness of the SiOfilmB is 1 to 5 nm. The total thickness of the SiON filmA and the SiOfilmB is 2 to 10 nm. The thickness of the AlON filmC is 10 to 200 nm. Each range includes the lower limit and the upper limit thereof.

388 387 387 388 A gate electrodehaving the same shape as the gate insulating filmin plan view is formed on the gate insulating film. The gate electrodeis made of a metallic material containing Al.

389 384 386 389 384 386 389 A source electrodeis formed on the source regionand the contact region. The source electrodeis in contact with the surfaces of the source regionand the contact regionwhile extending over the same. The source electrodeis made of a metallic material containing Al.

390 385 390 385 390 A drain electrodeis formed on the drain region. The drain electrodeis in contact with the surface of the drain region. The drain electrodeis made of a metallic material containing Al.

388 389 390 383 390 389 Voltage of not less than a threshold is applied to the gate electrodein a state where the source electrodeis grounded and positive voltage is applied to the drain electrode, whereby a channel is formed in the channel region of the well regionin the vicinity of the interface between the same and the gate insulating film, and current flows from the drain electrodetoward the source electrode.

381 301 32 FIG. Also in the semiconductor device, functions/effects similar to those of the semiconductor deviceshown incan be attained.

303 353 302 352 303 353 304 355 305 359 302 352 While such structures that the SiC layersandare stacked on the SiC substratesandhave been adopted, the SiC layersandmay be omitted, and the well regionsandand the source regionsandetc. may be formed on the surface layer portions of the SiC substratesand.

301 351 381 Further, the conductivity type of each portion of the semiconductor devices,andmay be inverted.

308 358 388 The materials for the gate electrodes,andare not restricted to the metallic materials containing Al, but may be polysilicon doped with an N-type impurity or a P-type impurity.

307 357 387 2 3 While the AlON filmC, the AlON filmC and the AlON filmC have been illustrated as high dielectric constant insulating films, the material for the high dielectric constant insulating films is not restricted to AlON, but may be a high dielectric constant material such as AlO(aluminum oxide), ZrO (zirconium oxide), HfO (hafnium oxide) or AlN (aluminum nitride).

A fourth embodiment provides a semiconductor device capable of approximating a movement path of carriers in a channel region to a straight line thereby reducing channel resistance.

38 FIG. 39 FIG. 38 FIG. 39 FIG. is a schematic plan view of a semiconductor device according to the fourth embodiment of the present invention.is a schematic sectional view of the semiconductor device taken along a cutting plane line B-B shown in. Referring to, only portions consisting of conductors are hatched, while hatching on the remaining portions is omitted.

401 38 FIG. A semiconductor devicehas a quadrangular (generally square) outer shape in plan view, as shown in.

401 402 402 403 402 403 39 FIG. The semiconductor deviceincludes a semiconductor substrate (SiC substrate), as shown in. The semiconductor substrateis made of SiC (N-type SiC) doped with an N-type impurity. A semiconductor layer (SiC layer)is formed on the semiconductor substrateby epitaxy. In other words, the semiconductor layeris an epitaxial layer made of N-type SiC.

404 403 404 404 404 16 19 −3 A plurality of P-type well regionsare formed on a surface layer portion of the semiconductor layer. The plurality of well regionsare quadrangular (generally square) in plan view, and arrayed in the form of a matrix. The depth of the well regionsis 0.5 to 2 μm, for example. The well regionshave such an impurity concentration profile that the P-type impurity concentration in portions whose depth from the upper surfaces thereof is not more than 0.5 μm is 1×10to 1×10cm, for example.

404 405 404 405 403 405 + On a surface layer portion of each well region, a source regionis formed at an interval from a peripheral edge of the well region. The source regionis doped with an N-type impurity in a higher concentration than in the semiconductor layer, to exhibit an Nconductivity type. The depth of the source regionis 0.2 to 1 μm, for example.

405 405 405 405 405 405 405 405 405 405 + − 17 19 −3 19 20 −3 In the source region, the N-type impurity concentration in a first regionA of a prescribed width (0.2 μm, for example) from a peripheral edge thereof in plan view is lower by one to three digits than the N-type impurity concentration in a remaining second region (region inside the first regionA)B. In other words, the source regionhas the N-type second regionB whose N-type impurity concentration is relatively high and the N-type first regionA, in the form of an annulus surrounding the second regionB, whose N-type impurity concentration is relatively low. The first regionA has such an impurity concentration profile that the N-type impurity concentration in a portion whose depth from the upper surface thereof is not more than 0.2 μm is 5×10to 5×10cm, for example. The second regionB has such an impurity concentration profile that the N-type impurity concentration in a portion whose depth from the upper surface thereof is not more than 0.2 μm is 5×10to 5×10cm, for example.

405 405 405 405 405 404 A step S where the upper surface of the second regionB is lower by one stage than the upper surface of the first regionA is formed between the upper surface of the first regionA and the upper surface of the second regionB. The magnitude of the step S is 0.2 μm, for example. No large step is formed between the upper surface of the first regionA and the upper surface of the well region(channel region C), but the upper surfaces are generally flush with each other.

+ 406 404 405 405 406 405 404 405 A P-type contact regiondoped with a P-type impurity in a higher concentration than in the well regionis formed at the center of the second regionB of each source region. Each contact regionis formed to pass through the second regionB in the depth direction, and the deepest portion reaches the well regionpresent under the source region.

407 403 407 403 404 404 405 405 407 A gate insulating filmis formed on the semiconductor layer. The gate insulating filmis opposed to the semiconductor layerbetween the well regions, a region (channel region) between the peripheral edge of each well regionand a peripheral edge of the source regioninside the same and part of the source region. The gate insulating filmis provided in the form of a lattice in plan view as a whole.

407 407 407 407 407 407 2 x y x y 2 2 2 The gate insulating filmhas an AlON/SiO/SiONmultilayer structure including an SiON filmA made of SiON(silicon oxynitride), an SiOfilmB made of SiO(silicon oxide) and formed on the SiON filmA, and an AlON filmC made of AlON (aluminum oxynitride) which is a high dielectric constant (High-k) insulating material and formed on the SiOfilmB.

407 407 407 407 407 2 2 The thickness of the SiON filmA is 1 to 5 nm. The thickness of the SiOfilmB is 1 to 5 nm. The total thickness of the SiON filmA and the SiOfilmB is 2 to 10 nm. The thickness of the AlON filmC is 10 to 200 nm. Each range includes the lower limit and the upper limit thereof.

408 407 408 403 404 404 405 405 405 407 408 401 408 38 FIG. A gate electrodeis formed on the gate insulating film. The gate electrodeis opposed to the semiconductor layerbetween the well regions, the channel region C between the peripheral edge of each well regionand the peripheral edge of the source regioninside the same and part of the first regionA of the source regionthrough the gate insulating film. The gate electrodeis provided in the form of a lattice in plan view as a whole, as shown in. Thus, the semiconductor devicehas a planar gate MIS structure. The gate electrodeis made of polysilicon doped with an N-type impurity or a P-type impurity, or a metallic material containing Al (aluminum) as a main component.

38 FIG. 408 409 411 In, the gate electrodeis shown through an interlayer dielectric filmand a source metaldescribed later.

409 403 403 409 407 408 409 39 FIG. The interlayer dielectric filmis formed on the semiconductor layer, as shown in. The upper surface of the semiconductor layeris covered with the interlayer dielectric film, along with the gate insulating filmand the gate electrode. The interlayer dielectric filmis made of silicon oxide, for example.

409 410 406 410 407 406 405 406 410 In the interlayer dielectric film, a contact holeis formed on a position opposed to each contact region. Each contact holepasses through the gate insulating film, and the whole area of the contact regionand a portion of the source regionaround the contact regionface the inner portion of each contact hole.

411 409 411 410 409 405 406 411 The source metalis formed on the interlayer dielectric film. The source metalenters each contact holeformed in the interlayer dielectric film, and is connected to the source regionand the contact region. The source metalis made of a metallic material containing aluminum (Al) as a main component, for example.

409 411 401 408 412 38 FIG. The interlayer dielectric filmand the source metalare selectively removed at the centers of portions along one side edge of the semiconductor device, whereby an opening exposing part of the gate electrodeas a gate padfor connection with an external portion is formed, as shown in.

402 413 414 402 On the back surface of the semiconductor substrate, an ohmic metalmade of nickel (Ni) or the like and a drain metalmade of a metallic material containing aluminum as a main component are formed on the whole surface thereof in this order from the side of the semiconductor substrate.

408 411 414 404 407 411 414 The potential (gate voltage) of the gate electrodeis controlled in a state where the source metalis grounded and proper positive voltage is applied to the drain metal, whereby a channel is formed in the channel region C of the well regionin the vicinity of the interface between the same and the gate insulating film, and current flows between the source metaland the drain metal.

40 FIG. 39 FIG. is a schematic enlarged sectional view in the vicinity of the first region of the source region and the channel region shown in.

405 405 401 405 404 The N-type impurity concentration in the first regionA of the source regionadjacent to the channel region C is lowered in the semiconductor device, whereby no large step is formed between the upper surface of the first regionA and the upper surface of the channel region C (the well region).

− 411 414 405 405 401 30 FIG. Therefore, electrons (e) flowing between the source metaland the drain metalmove from the source regionto the channel region C along the upper surface of the first regionA, and move in the channel region C along the upper surface thereof. In other words, the path of the electrons in the channel region C becomes a linear path along the upper surface of the channel region C. Therefore, channel resistance of the semiconductor deviceis lower than the channel resistance of the semiconductor device ofin which the movement path of the electrons in the channel region becomes a bent path.

41 41 FIGS.A toK 41 41 FIGS.A toK 42 FIG. are schematic sectional views successively showing manufacturing steps for the semiconductor device. Referring to, only portions consisting of conductors are hatched, while hatching on the remaining portions is omitted.is a manufacturing step diagram for the gate insulating film.

401 403 403 404 441 403 403 441 41 FIG.A In the manufacturing steps for the semiconductor device, a deposition layer of polysilicon is first formed on the semiconductor layerby CVD (Chemical Vapor Deposition). Then, the deposition layer (not shown) of polysilicon is selectively removed from a portion of the semiconductor layerto become the well regionby photolithography and etching. Thus, a maskmade of polysilicon is formed on the semiconductor layer, as shown in. Thereafter a portion of the semiconductor layerexposed from the maskis doped with a P-type impurity (aluminum, for example) by ion implantation.

403 441 441 442 441 442 443 403 406 403 441 442 443 41 FIG.B Then, an oxide film (not shown) made of silicon oxide is formed to collectively cover the semiconductor layerand the mask. Thereafter a deposition layer (not shown) of polysilicon is formed on the oxide film. Then, the deposition layer of polysilicon is etched back through the oxide film serving as an etching stopper and only prescribed portions of the deposition layer in contact with the side surfaces of the maskare left, whereby a maskintegrated with the maskis formed, as shown in. Then, the oxide film exposed from the maskis removed. Then, a resist patternis formed on a portion of the semiconductor layerto become the contact regionby photolithography. Thereafter portions of the semiconductor layerexposed from the masksandand the resist patternare doped with an N-type impurity (phosphorus (P), for example) by ion implantation.

443 403 441 442 442 444 441 442 444 445 403 406 403 441 442 444 445 441 442 444 445 41 FIG.C After the resist patternis removed, an oxide film (not shown) made of silicon oxide is formed again, to collectively cover the semiconductor layerand the masksand. Thereafter a deposition layer (not shown) of polysilicon is formed on the oxide film. Then, the deposition layer of polysilicon is etched back through the oxide film serving as an etching stopper and only prescribed portions of the deposition layer in contact with the side surfaces of the maskare left, whereby a maskintegrated with the masksandis formed, as shown in. Then, the oxide film exposed from the maskis removed. Then, a resist patternis formed on the portion of the semiconductor layerto become the contact regionby photolithography. Thereafter portions of the semiconductor layerexposed from the masks,andand the resist patternare additionally doped with the N-type impurity by ion implantation. After the doping of the N-type impurity, the masks,andand the resist patternare removed.

41 41 FIGS.B andC 443 445 403 406 443 445 401 In the steps shown in, the formation of the resist patternsandmay be omitted, and the portion of the semiconductor layerto become the contact regionmay be doped with the N-type impurity. Thus, photomasks necessary for the formation of the resist patternsandcan be omitted, and the manufacturing steps for the semiconductor devicecan be simplified.

446 403 446 403 406 403 446 41 FIG.D Then, a resist patternis formed on the semiconductor layer, as shown in. The resist patternexposes only the portion of the semiconductor layerto become the contact region. Then, the portion of the semiconductor layerexposed from the resist patternis doped with a P-type impurity by ion implantation.

403 404 405 405 405 406 403 403 447 405 405 406 403 404 405 405 447 405 406 41 FIG.E Thereafter annealing for activating the P-type impurity and the N-type impurity doped into the semiconductor layeris performed, and the well region, the source region(the first regionA and the second regionB) and the contact regionare formed on the surface layer portion of the semiconductor layer, as shown in. Further, the upper surface of the semiconductor layeris thermally oxidized in the annealing, whereby an oxide filmis formed. The second regionB of the source regionand the contact regionhave higher impurity concentrations as compared with the semiconductor layer, the well regionand the first regionA of the source region, whereby the oxide filmrelatively thickly grows on the second regionB and the contact region.

447 405 406 403 404 405 405 405 405 41 FIG.F After the oxide filmis removed, therefore, the upper surfaces of the second regionB and the contact regionenter states lower by one stage than the upper surfaces of the semiconductor layer, the well regionand the first regionA of the source region, and a step S is formed between the first regionA and the second regionB, as shown in.

447 403 404 405 406 403 404 405 406 405 405 After the removal of the oxide film, the states of the upper surfaces of the semiconductor layer, the well region, the source regionand the contact regionmay be improved by forming a sacrificial oxide film on the upper surfaces of the semiconductor layer, the well region, the source regionand the contact regionby thermal oxidation and removing the sacrificial oxide film. In this case, a larger step S is formed between the first regionA and the second regionB after removal of the sacrificial oxide film.

407 403 404 405 406 41 FIG.G Thereafter the gate insulating filmis formed on the upper surfaces of the semiconductor layer, the well region, the source regionand the contact regionby thermal oxidation, as shown in.

407 41 42 43 44 45 x 2 42 FIG. In order to form the gate insulating film, an NOthermal oxidation step (S), an Othermal oxidation step (S), an FGA (Forming Gas Annealing) step (S), an AlON film formation step (S) and a PDA (Post Deposition Annealing) step (S) are carried out in this order, as shown in.

x x y 2 41 407 403 In the NOthermal oxidation step (S), the SiON filmA made of SiONis formed on the semiconductor layerby thermal oxidation employing gas containing NO (nitrogen oxide).

2 2 2 2 42 407 407 In the Othermal oxidation step (S), the SiOfilmB made of SiOis formed on the SiON filmA by thermal oxidation employing dry gas of O.

43 407 407 403 407 2 2 2 2 In the FGA step (S), the SiOfilmB is annealed in forming gas containing 3% of H(hydrogen gas) and 97% of N(nitrogen gas). For example, annealing at a temperature of 1000° C. is performed for 30 minutes, and annealing at a temperature of 450° C. is thereafter performed for 30 minutes. Thus, H atoms are excellently introduced into the SiOfilmB, and the number of dangling bonds of C atoms and Si atoms present on the interface between the semiconductor layerand the SiON filmA decreases.

44 407 407 2 2 2 In the AlON film formation step (S), the AlON filmC is formed on the SiOfilmB by reactive sputtering employing mixed gas of Nand O(oxygen gas) and an Al target.

45 407 407 407 2 In the PDA step (S), the AlON filmC is annealed in N. The annealing is performed at a temperature of 900° C. for 10 minutes, for example. Thus, crystallinity of the AlON filmC rises, and quality of the AlON filmC improves.

407 41 FIG.G Thus, the gate insulating filmis formed as shown in.

448 407 41 FIG.H Then, a deposition layerof polysilicon is formed on the gate insulating filmby CVD, as shown in.

448 408 407 408 407 41 FIG.I Then, the deposition layeris selectively removed by photolithography and etching, and the gate electrodemade of polysilicon is formed on the gate insulating film, as shown in. Alternatively, a gate electrodemade of a metallic material may be formed by forming a deposition layer of the metallic material containing Al (aluminum) on the gate insulating filmand selectively removing the deposition layer.

409 407 408 41 FIG.J Then, the interlayer dielectric filmis formed on the gate insulating filmand the gate electrodeby CVD, as shown in.

410 409 407 41 FIG.K Then, the contact holepassing through the interlayer dielectric filmand the gate insulating filmis formed by photolithography and etching, as shown in.

411 409 412 413 414 402 401 39 FIG. Thereafter the source metalis formed on the interlayer dielectric filmby sputtering. Then, the gate padis formed by photolithography and etching. Further, the ohmic metaland the drain metalare formed on the back surface of the semiconductor substrateby sputtering. Thus, the semiconductor deviceshown inis obtained.

447 405 405 405 405 404 447 405 As hereinabove described, the rate (rate of oxidation) of growth of the oxide filmon the upper surface of the first regionA can be suppressed low by lowering the impurity concentration in the first regionA of the source regionadjacent to the channel region C. Therefore, formation of a large step between the upper surface of the first regionA and the upper surface of the channel region C (the well region) can be prevented after removal of the oxide film. Consequently, the path (movement path) of electrons moving from the source regionto the channel region C can be approximated to a straight line, whereby reduction of channel resistance can be attained.

405 405 405 405 405 405 405 405 405 405 405 405 405 The impurity concentration in the second regionB of the source regionother than the first regionA is higher than the impurity concentration in the first regionA, whereby the step S where the upper surface of the second regionB is lower by one stage than the upper surface of the first regionA is formed between the upper surface of the first regionA and the upper surface of the second regionB. Even if the step S is formed between the upper surface of the first regionA and the upper surface of the second regionB, the step S does not influence the flow of the electrons in the channel region C. Therefore, the channel resistance can be reduced without reducing the carrier concentration in the source regionby relatively lowering the impurity concentration in the first regionA and relatively raising the impurity concentration in the second regionB.

407 407 407 407 403 2 The gate insulating filmhas the structure obtained by stacking the SiON filmA, the SiOfilmB and the AlON filmC from the side of the semiconductor layer.

407 403 407 403 407 2 The SiON filmA is interposed between the semiconductor layerand the SiOfilmB, whereby reduction of interface state density Dit on the interface between the semiconductor layer(SiC) and the gate insulating filmcan be attained as compared with such a structure that a gate insulating film consists of only a silicon oxide film. Further, improvement of the channel mobility can be attained due to the reduction of the interface state density Dit.

407 403 407 407 407 407 2 In addition, reduction of leakage current resulting from increase in the thickness of the gate insulating filmcan be attained while suppressing increase in the interface state density on the interface between the semiconductor layerand the gate insulating filmby reducing the total thickness of the SiON filmA and the SiOfilmB and increasing the thickness of the AlON filmC.

407 Therefore, both of improvement of the channel mobility resulting from the reduction of the interface state density Dit and improvement of reliability of the gate insulating filmresulting from the reduction of the leakage current can be attained.

408 403 407 408 408 The gate electrodeis suitably made of a metallic material containing Al. Thus, improvement in operating speed of a MISFET (field effect transistor of a planar gate MIS structure) constituted of the semiconductor layer, the gate insulating filmand the gate electrodeetc. and reduction of power consumption can be attained as compared with such a structure that the gate electrodeis made of polycrystalline silicon.

301 301 407 407 407 2 x y 2 39 FIG. A samplehaving the SiC-MIS structure (the structure including the AlON/SiO/SiONmultilayer gate insulating film on SiC) shown inwas prepared. In the sample, the thickness of an SiON filmA is 5 nm, the thickness of an SiOfilmB is 5 nm, and the thickness of an AlON filmC is 80 nm.

302 302 2 2 2 2 A samplehaving an SiC-MIS structure employing an AlON/SiOmultilayer gate insulating film (gate insulating film of a structure obtained by stacking an SiOfilm made of SiOand an AlON film made of AlON on SiC in this order) was prepared. In the sample, the thickness of the SiOfilm is 10 nm, and the thickness of the AlON film is 80 nm.

301 302 43 FIG. 34 FIG. As to the respective ones of the samplesand, high-frequency CV characteristics (at a measuring frequency of 100 kHz, for example) and low-frequency CV characteristics (quasi-static CV characteristics) were measured, and the differences between high-frequency measured values and low-frequency measured values were calculated as the interface state density Dit by a High-Low method.shows the results. Referring to, the axis of abscissas shows energy (Ec-E) from valence band edges of the gate insulating films, and the axis of ordinates shows the interface state density Dit.

43 FIG. 301 302 From the results shown in, it is understood that the interface state density Dit in the sampleis lower than the interface state density Dit of the sample.

44 FIG. is another manufacturing step diagram for the gate insulating film.

407 51 52 53 54 55 39 FIG. 44 FIG. 42 FIG. 44 FIG. 2 The gate insulating filmshown incan be formed by a technique including the manufacturing steps shown in, in place of the technique including the manufacturing steps shown in. In the manufacturing steps shown in, a nitrogen plasma application step (S), an Othermal oxidation step (S), an FGA step (S), an AlON film formation step (S) and a PDA step (S) are carried out in this order.

51 403 403 407 403 In the nitrogen plasma application step (S), nitrogen plasma is applied to the semiconductor layer. The nitrogen plasma is continuously applied over 30 minutes in a state where the semiconductor layeris heated to 500° C., for example. Atmospheric pressure and RF output at this time are 9.5 Torr and 50 W respectively, for example. Thus, the SiON filmA is formed on the semiconductor layer.

2 2 2 2 52 407 407 In the Othermal oxidation step (S), the SiOfilmB made of SiOis formed on the SiON filmA by thermal oxidation employing dry gas of O.

53 54 55 43 44 45 42 FIG. In the FGA step (S), the AlON film formation step (S) and the PDA step (S), treatments similar to those in the FGA step (S), the AlON film formation step (S) and the PDA step (S) shown inare performed respectively.

45 FIG. 45 FIG. 39 FIG. 39 FIG. 45 FIG. 45 FIG. is a schematic sectional view of a semiconductor device according to a modification. Referring to, portions corresponding to the respective portions shown inare denoted by the same reference numerals as the reference numerals assigned to the respective portions. In the following, only a point different from the structure shown inis described as to the structure shown in, and description of the respective portions denoted by the same reference numerals is omitted. Referring to, only portions consisting of conductors are hatched, while hatching on the remaining portions is omitted.

405 405 405 401 405 405 405 451 405 405 451 401 39 FIG. 45 FIG. 39 FIG. While the depth of the first regionA of the source regionand the depth of the second regionB are generally identical to each other in the semiconductor deviceshown in, the depth of a first regionA of a source regionis smaller than the depth of a second regionB in a semiconductor deviceshown in. Also when the depth of the first regionA is smaller than the depth of the second regionB as in the semiconductor device, effects similar to those of the semiconductor deviceshown incan be attained.

46 FIG. 46 FIG. is a schematic sectional view of a semiconductor device according to another modification. Referring to, only portions consisting of conductors are hatched, while hatching on the remaining portions is omitted.

401 451 461 39 FIG. 45 FIG. 46 FIG. While the semiconductor deviceshown inand the semiconductor deviceshown inhave planar gate MIS structures, a semiconductor deviceshown inhas a trench gate MIS structure.

461 462 462 463 462 463 The semiconductor deviceincludes a semiconductor substrate. The semiconductor substrateis made of SiC (N-type SiC) doped with an N-type impurity. A semiconductor layeris formed on the semiconductor substrateby epitaxy. In other words, the semiconductor layeris an epitaxial layer made of N-type SiC.

463 464 463 465 − A base layer portion of the semiconductor layermaintains the state after the epitaxy, and forms an N-type drain region. A surface layer portion of the semiconductor layeris doped with a P-type impurity, to be converted to a P-type well region.

463 466 466 408 466 465 464 38 FIG. In the semiconductor layer, a gate trenchis formed to be dug down from the surface thereof. The gate trenchis provided in the form of a lattice in plan view, similarly to the gate electrodeshown in, for example. The gate trenchpasses through the well region, and the deepest portion thereof reaches the drain region.

467 466 467 467 467 467 467 467 2 x y x y 2 2 2 A gate insulating filmis formed on the inner surface of the gate trench. The gate insulating filmhas an AlON/SiO/SiONmultilayer structure including an SiON filmA made of SiON, an SiOfilmB made of SiOand formed on the SiON filmA, and an AlON filmC made of AlON which is a high dielectric constant insulating material and formed on the SiOfilmB.

467 467 467 467 467 2 2 The thickness of the SiON filmA is 1 to 5 nm. The thickness of the SiOfilmB is 1 to 5 nm. The total thickness of the SiON filmA and the SiOfilmB is 2 to 10 nm. The thickness of the AlON filmC is 10 to 200 nm. Each range includes the lower limit and the upper limit thereof.

467 468 466 468 The inner side of the gate insulating filmis filled up with polysilicon doped with an N-type impurity or a P-type impurity, whereby a gate electrodemade of the doped polysilicon is embedded in the gate trench. Alternatively, the gate electrodemay be made of a metallic material containing Al (aluminum).

469 465 469 469 469 An N-type source regionis formed on a surface layer portion of the well region. The depth (the total depth of a first regionA and a second regionB described later) of the source regionis 0.5 to 2 μm, for example.

469 469 469 469 469 469 469 469 469 469 + − 17 19 −3 19 20 −3 In the source region, the N-type impurity concentration in the first regionA of a prescribed depth (0.2 μm, for example) on the bottom portion thereof is lower by one to three digits than the N-type impurity concentration in the remaining second region (region on the first regionA)B. In other words, the source regionhas the N-type second regionB whose N-type impurity concentration is relatively high and the N-type first regionA, formed under the second regionB, whose N-type impurity concentration is relatively low. The N-type impurity concentration in the first regionA is 5×10to 5×10cm, for example, and the N-type impurity concentration in the second regionB is 5×10to 5×10cm, for example.

469 468 469 469 469 469 469 469 465 467 469 469 469 A step S where the side surface of the second regionB more separates from the gate electrodethan the side surface of the first regionA is formed between the side surface of the first regionA and the side surface of the second regionB, due to the difference between the N-type impurity concentrations in the first regionA and the second regionB. The magnitude of the step S is 0.1 μm, for example. No large step is formed between the side surface of the first regionA and the side surface of the well region(channel region C), but the side surfaces are generally flush with each other. The gate insulating filmhas a relatively large thickness on the side surface of the second regionB, due to the difference between the N-type impurity concentrations in the first regionA and the second regionB.

465 470 469 466 466 + On the surface layer portion of the well region, a P-type contact regionis formed to pass through the source regionin the thickness direction on a position at an interval from the gate trenchin each region surrounded by the gate trench.

471 463 471 An interlayer dielectric filmis stacked on the semiconductor layer. The interlayer dielectric filmis made of silicon oxide, for example.

471 472 470 470 469 470 472 In the interlayer dielectric film, a contact holeis penetratingly formed on a position opposed to each contact region. The whole area of the contact regionand a portion of the source regionaround the contact regionface the inner portion of each contact hole.

473 471 473 472 469 470 473 A source metalis formed on the interlayer dielectric film. The source metalenters each contact hole, and is connected to the source regionand the contact region. The source metalis made of a metallic material containing Al as a main component, for example.

462 474 475 462 On the back surface of the semiconductor substrate, an ohmic metalmade of nickel (Ni) or the like and a drain metalmade of a metallic material containing aluminum as a main component are formed on the whole surface thereof in this order from the side of the semiconductor substrate.

468 473 475 465 467 473 475 The potential (gate voltage) of the gate electrodeis controlled in a state where the source metalis grounded and proper positive voltage is applied to the drain metal, whereby a channel is formed in the channel region C of the well regionin the vicinity of the interface between the same and the gate insulating film, and current flows between the source metaland the drain metal.

47 FIG. 46 FIG. is a schematic enlarged sectional view in the vicinity of the first region of the source region and the channel region shown in.

469 469 461 469 465 The N-type impurity concentration in the first regionA of the source regionadjacent to the channel region C is lowered in the semiconductor device, whereby no large step is formed between the side surface of the first regionA and the side surface of the channel region C (the well region).

− 473 475 469 469 466 461 401 451 461 30 FIG. Therefore, electrons (e) flowing between the source metaland the drain metalmove from the source regionto the channel region C along the side surface of the first regionA (the inner surface of the gate trench), and move in the channel region C along the side surface thereof. In other words, the path of the electrons in the channel region C becomes a linear path along the side surface of the channel region C. Also according to the structure of the semiconductor device, therefore, functions/effects similar to those of the semiconductor devicesandcan be exhibited, and channel resistance of the semiconductor deviceis lower than the channel resistance of the semiconductor device ofin which the movement path of the electrons in the channel region becomes a bent path.

461 467 401 39 FIG. Also in the semiconductor device, both of improvement of channel mobility and improvement of reliability of the gate insulating filmcan be attained, similarly to the semiconductor deviceshown in.

48 FIG. is a schematic sectional view of a semiconductor device according to still another modification.

401 451 481 39 FIG. 45 FIG. 48 FIG. While the semiconductor deviceshown inand the semiconductor deviceshown ininclude vertical MISFETS, a semiconductor deviceshown inincludes a lateral MISFET.

481 482 The semiconductor deviceincludes an SiC substrateas a silicon carbide layer made of N-type SiC.

483 482 A P-type well regionis formed on a surface layer portion of the SiC substrate.

484 485 483 484 485 483 484 485 482 + A source regionand a drain regionare formed on a surface layer portion of the well region. The source regionand the drain regionare formed at intervals from a peripheral edge portion of the well regionrespectively, and at an interval from each other. The source regionand the drain regionare doped with an N-type impurity in higher concentrations than in the SiC substrate, to exhibit Nconductivity types.

486 483 486 484 485 486 483 + A contact regionis formed on the surface layer portion of the well region. The contact regionis formed adjacently to a side of the source regionopposite to the drain region. The contact regionis doped with a P-type impurity in a higher concentration than in the well region, to exhibit a Pconductivity type.

487 484 485 487 484 485 484 485 487 487 487 487 487 487 2 x y x y 2 2 2 A gate insulating filmis formed on a region (channel region) between the source regionand the drain region. More specifically, the gate insulating filmis opposed to the region between the source regionand the drain region, and extends over a peripheral edge portion of the source regionand a peripheral edge portion of the drain region. The gate insulating filmhas an AlON/SiO/SiONmultilayer structure including an SiON filmA made of SiON, an SiOfilmB made of SiOand formed on the SiON filmA, and an AlON filmC made of AlON which is a high dielectric constant insulating material and formed on the SiOfilmB.

487 487 487 487 487 2 2 The thickness of the SiON filmA is 1 to 5 nm. The thickness of the SiOfilmB is 1 to 5 nm. The total thickness of the SiON filmA and the SiOfilmB is 2 to 10 nm. The thickness of the AlON filmC is 10 to 200 nm. Each range includes the lower limit and the upper limit thereof.

488 487 487 488 A gate electrodehaving the same shape as the gate insulating filmin plan view is formed on the gate insulating film. The gate electrodeis made of a metallic material containing Al.

489 484 486 489 484 486 489 A source electrodeis formed on the source regionand the contact region. The source regionis in contact with the surfaces of the source regionand the contact regionwhile extending over the same. The source electrodeis made of a metallic material containing Al.

490 485 490 485 490 A drain electrodeis formed on the drain region. The drain electrodeis in contact with the surface of the drain region. The drain electrodeis made of a metallic material containing Al.

488 489 490 483 487 490 489 Voltage of not less than a threshold is applied to the gate electrodein a state where the source electrodeis grounded and positive voltage is applied to the drain electrode, whereby a channel is formed in the channel region of the well regionin the vicinity of the interface between the same and the gate insulating film, and current flows from the drain electrodetoward the source electrode.

481 401 39 FIG. Also in the semiconductor device, functions/effects similar to those of the semiconductor deviceshown incan be attained.

403 463 402 462 403 463 404 465 405 469 402 462 While the structures in which the semiconductor layersandare stacked on the semiconductor substrates (SiC substrates)andhave been adopted, the semiconductor layersandmay be omitted, and the well regionsandand the source regionsandetc. may be formed on the surface layer portions of the SiC substratesand.

401 451 461 481 Further, the conductivity type of each portion of the semiconductor devices,,andmay be inverted. In other words, while the case where the first conductivity type is the N type and the second conductivity type is the P type has been adopted, the first conductivity type may be the P type, and the second conductivity type may be the N type.

408 468 488 The materials for the gate electrodes,andare not restricted to the metallic materials containing Al, but may be polysilicon doped with an N-type impurity or a P-type impurity.

407 467 487 2 3 While the AlON filmC, the AlON filmC and the AlON filmC have been illustrated as high dielectric constant insulating films, the material for the high dielectric constant insulating films is not restricted to AlON, but may be a high dielectric constant material such as AlO(aluminum oxide), ZrO (zirconium oxide), HfO (hafnium oxide) or AlN (aluminum nitride).

A fifth embodiment provides a semiconductor device capable of approximating a movement path of carriers in a channel region to a straight line thereby reducing channel resistance.

49 FIG. 50 FIG. 49 FIG. 50 FIG. is a schematic plan view of a semiconductor device according to the fifth embodiment of the present invention.is a schematic sectional view of the semiconductor device taken along a cutting plane line C-C shown in. Referring to, only portions consisting of conductors are hatched, while hatching on the remaining portions is omitted.

601 49 FIG. A semiconductor devicehas a quadrangular (generally square) outer shape in plan view, as shown in.

601 602 602 603 602 603 50 FIG. The semiconductor deviceincludes a semiconductor substrate, as shown in. The semiconductor substrateis made of SiC (N-type SiC) doped with an N-type impurity. A semiconductor layeris formed on the semiconductor substrateby epitaxy. In other words, the semiconductor layeris an epitaxial layer made of N-type SiC.

604 603 604 604 604 16 19 −3 A plurality of P-type well regionsare formed on a surface layer portion of the semiconductor layer. The plurality of well regionsare quadrangular (generally square) in plan view, and arrayed in the form of a matrix. The depth of the well regionsis 0.5 to 2 μm, for example. The well regionshave such an impurity concentration profile that the P-type impurity concentration in portions whose depth from the upper surfaces thereof is not more than 0.5 μm is 1×10to 1×10cm, for example.

604 605 604 605 On a surface layer portion of each well region, an N-type source regionis formed at an interval from a peripheral edge of the well region. The depth of the source regionis 0.2 to 1 μm, for example.

605 605 605 605 605 605 605 605 605 605 + − 17 19 −3 19 20 −3 In the source region, the N-type impurity concentration in a first regionA of a prescribed width (0.2 μm, for example) from a peripheral edge thereof in plan view is lower by one to three digits than the N-type impurity concentration in a remaining second region (region inside the first regionA)B. In other words, the source regionhas the N-type second regionB whose N-type impurity concentration is relatively high and the N-type first regionA, in the form of an annulus surrounding the second regionB, whose N-type impurity concentration is relatively low. The first regionA has such an impurity concentration profile that the N-type impurity concentration in a portion whose depth from the upper surface thereof is not more than 0.2 μm is 5×10to 5×10cm, for example. The second regionB has such an impurity concentration profile that the N-type impurity concentration in a portion whose depth from the upper surface thereof is not more than 0.2 μm is 5×10to 5×10cm, for example.

605 605 605 605 605 604 A step S where the upper surface of the second regionB is lower by one stage than the upper surface of the first regionA is formed between the upper surface of the first regionA and the upper surface of the second regionB. The magnitude of the step S is 0.2 μm, for example. No large step is formed between the upper surface of the first regionA and the upper surface of the well region(channel region C), but the upper surfaces are generally flush with each other.

+ 606 604 605 605 606 605 604 605 A P-type contact regiondoped with a P-type impurity in a higher concentration than in the well regionis formed at the center of the second regionB of each source region. Each contact regionis formed to pass through the second regionB in the depth direction, and the deepest portion reaches the well regionpresent under the source region.

607 603 607 2 A gate insulating filmis formed on the semiconductor layer. The gate insulating filmis made of silicon oxide (SiO), for example.

608 607 608 603 604 604 605 605 605 607 608 601 608 49 FIG. A gate electrodeis formed on the gate insulating film. The gate electrodeis opposed to the semiconductor layerbetween the well regions, the channel region C between the peripheral edge of each well regionand a peripheral edge of the source regioninside the same and part of the first regionA of the source regionthrough the gate insulating film. The gate electrodeis provided in the form of a lattice in plan view as a whole, as shown in. Thus, the semiconductor devicehas a planar gate MIS structure. The gate electrodeis made of polysilicon doped with an N-type impurity or a P-type impurity.

49 FIG. 608 609 611 In, the gate electrodeis shown through an interlayer dielectric filmand a source metaldescribed later.

609 603 603 609 608 609 50 FIG. The interlayer dielectric filmis formed on the semiconductor layer, as shown in. The upper surface of the semiconductor layeris covered with the interlayer dielectric film, along with the gate electrode. The interlayer dielectric filmis made of silicon oxide, for example.

609 610 606 610 607 606 605 606 610 In the interlayer dielectric film, a contact holeis formed on a position opposed to each contact region. Each contact holepasses through the gate insulating film, and the whole area of the contact regionand a portion of the source regionaround the contact regionface the inner portion of each contact hole.

611 609 611 610 609 605 606 611 The source metalis formed on the interlayer dielectric film. The source metalenters each contact holeformed in the interlayer dielectric film, and is connected to the source regionand the contact region. The source metalis made of a metallic material containing aluminum (Al) as a main component, for example.

609 611 601 608 612 49 FIG. The interlayer dielectric filmand the source metalare selectively removed at the centers of portions along one side edge of the semiconductor device, whereby an opening exposing part of the gate electrodeas a gate padfor connection with an external portion is formed, as shown in.

602 613 614 602 50 FIG. On the back surface of the semiconductor substrate, an ohmic metalmade of nickel (Ni) or the like and a drain metalmade of a metallic material containing aluminum as a main component are formed on the whole surface thereof in this order from the side of the semiconductor substrate, as shown in.

608 611 614 604 607 611 614 The potential (gate voltage) of the gate electrodeis controlled in a state where the source metalis grounded and proper positive voltage is applied to the drain metal, whereby a channel is formed in the channel region C of the well regionin the vicinity of the interface between the same and the gate insulating film, and current flows between the source metaland the drain metal.

51 FIG. 50 FIG. is a schematic enlarged sectional view in the vicinity of the first region of the source region and the channel region shown in.

605 605 601 605 604 The N-type impurity concentration in the first regionA of the source regionadjacent to the channel region C is lowered in the semiconductor device, whereby no large step is formed between the upper surface of the first regionA and the upper surface of the channel region C (the well region).

611 614 605 605 601 30 FIG. Therefore, electrons (e) flowing between the source metaland the drain metalmove from the source regionto the channel region C along the upper surface of the first regionA, and move in the channel region C along the upper surface thereof. In other words, the path of the electrons in the channel region C becomes a linear path along the upper surface of the channel region C. Therefore, channel resistance of the semiconductor deviceis lower than the channel resistance of the semiconductor device ofin which the movement path of the electrons in the channel region becomes a bent path.

52 52 FIGS.A toK 52 52 FIGS.A toK are schematic sectional views successively showing manufacturing steps for the semiconductor device. Referring to, only portions consisting of conductors are hatched, while hatching on the remaining portions is omitted.

601 603 603 604 641 603 603 641 52 FIG.A In the manufacturing steps for the semiconductor device, a deposition layer of polysilicon is first formed on the semiconductor layerby CVD (Chemical Vapor Deposition). Then, the deposition layer (not shown) of polysilicon is selectively removed from a portion of the semiconductor layerto become the well regionby photolithography and etching. Thus, a maskmade of polysilicon is formed on the semiconductor layer, as shown in. Thereafter a portion of the semiconductor layerexposed from the maskis doped with a P-type impurity (aluminum, for example) by ion implantation.

603 641 641 642 641 642 643 603 606 603 641 642 643 52 FIG.B Then, an oxide film (not shown) made of silicon oxide is formed to collectively cover the semiconductor layerand the mask. Thereafter a deposition layer (not shown) of polysilicon is formed on the oxide film. Then, the deposition layer of polysilicon is etched back through the oxide film serving as an etching stopper and only prescribed portions of the deposition layer in contact with the side surfaces of the maskare left, whereby a maskintegrated with the maskis formed, as shown in. Then, the oxide film exposed from the maskis removed. Then, a resist patternis formed on a portion of the semiconductor layerto become the contact regionby photolithography. Thereafter portions of the semiconductor layerexposed from the masksandand the resist patternare doped with an N-type impurity (phosphorus (P), for example) by ion implantation.

643 603 641 642 642 644 641 642 644 645 603 606 603 641 642 644 645 641 642 644 645 52 FIG.C After the resist patternis removed, an oxide film (not shown) made of silicon oxide is formed again, to collectively cover the semiconductor layerand the masksand. Thereafter a deposition layer (not shown) of polysilicon is formed on the oxide film. Then, the deposition layer of polysilicon is etched back through the oxide film serving as an etching stopper and only prescribed portions of the deposition layer in contact with the side surfaces of the maskare left, whereby a maskintegrated with the masksandis formed, as shown in. Then, the oxide film exposed from the maskis removed. Then, a resist patternis formed on the portion of the semiconductor layerto become the contact regionby photolithography. Thereafter portions of the semiconductor layerexposed from the masks,andand the resist patternare additionally doped with the N-type impurity by ion implantation. After the doping of the N-type impurity, the masks,andand the resist patternare removed.

52 52 FIGS.B andC 643 645 603 606 643 645 601 In the steps shown in, the formation of the resist patternsandmay be omitted, and the portion of the semiconductor layerto become the contact regionmay be doped with the N-type impurity. Thus, photomasks necessary for the formation of the resist patternsandcan be omitted, and the manufacturing steps for the semiconductor devicecan be simplified.

646 603 646 603 606 603 646 52 FIG.D Then, a resist patternis formed on the semiconductor layer, as shown in. The resist patternexposes only the portion of the semiconductor layerto become the contact region. Then, the portion of the semiconductor layerexposed from the resist patternis doped with a P-type impurity by ion implantation.

603 604 605 605 605 606 603 603 647 605 605 606 603 604 605 605 647 605 606 52 FIG.E Thereafter annealing for activating the P-type impurity and the N-type impurity doped into the semiconductor layeris performed, and the well region, the source region(the first regionA and the second regionB) and the contact regionare formed on the surface layer portion of the semiconductor layer, as shown in. At the annealing, the upper surface of the semiconductor layeris thermally oxidized, whereby an oxide filmis formed. The second regionB of the source regionand the contact regionhave higher impurity concentrations as compared with the semiconductor layer, the well regionand the first regionA of the source region, whereby the oxide filmrelatively thickly grows on the second regionB and the contact region.

647 605 606 603 604 605 605 605 605 52 FIG.F After the oxide filmis removed, therefore, the upper surfaces of the second regionB and the contact regionenter states lower by one stage than the upper surfaces of the semiconductor layer, the well regionand the first regionA of the source region, and the step S is formed between the first regionA and the second regionB, as shown in.

647 603 604 605 606 603 604 605 606 605 605 After the removal of the oxide film, the states of the upper surfaces of the semiconductor layer, the well region, the source regionand the contact regionmay be improved by forming a sacrificial oxide film on the upper surfaces of the semiconductor layer, the well region, the source regionand the contact regionby thermal oxidation and removing the sacrificial oxide film. In this case, a larger step S is formed between the first regionA and the second regionB after the removal of the sacrificial oxide film.

607 603 604 605 606 52 FIG.G Thereafter the gate insulating filmis formed on the upper surfaces of the semiconductor layer, the well region, the source regionand the contact regionby thermal oxidation, as shown in.

648 607 52 FIG.H Then, a deposition layerof polysilicon is formed on the gate insulating filmby CVD, as shown in.

648 608 607 52 FIG.I Then, the deposition layeris selectively removed by photolithography and etching, and the gate electrodemade of polysilicon is formed on the gate insulating film, as shown in.

609 607 608 52 FIG.J Then, the interlayer dielectric filmis formed on the gate insulating filmand the gate electrodeby CVD, as shown in.

610 609 607 52 FIG.K Then, the contact holepassing through the interlayer dielectric filmand the gate insulating filmis formed by photolithography and etching, as shown in.

611 609 612 613 614 602 601 50 FIG. Thereafter the source metalis formed on the interlayer dielectric filmby sputtering. Then, the gate padis formed by photolithography and etching. Further, the ohmic metaland the drain metalare formed on the back surface of the semiconductor substrateby sputtering. Thus, the semiconductor deviceshown inis obtained.

647 605 605 605 605 604 647 605 As hereinabove described, the rate (rate of oxidation) of growth of the oxide filmon the upper surface of the first regionA can be suppressed low by lowering the impurity concentration in the first regionA of the source regionadjacent to the channel region C. Therefore, formation of a large step between the upper surface of the first regionA and the upper surface of the channel region C (the well region) can be prevented after the removal of the oxide film. Consequently, the path (movement path) of the electrons moving from the source regionin the channel region C can be approximated to a straight line, whereby reduction of channel resistance can be attained.

605 605 605 605 605 605 605 605 605 605 605 605 605 The impurity concentration in the second regionB of the source regionother than the first regionA is higher than the impurity concentration in the first regionA, whereby the step S where the upper surface of the second regionB is lower by one stage than the upper surface of the first regionA is formed between the upper surface of the first regionA and the upper surface of the second regionB. Even if the step S is formed between the upper surface of the first regionA and the upper surface of the second regionB, the step S does not influence the flow of the electrons in the channel region C. Therefore, the channel resistance can be reduced without reducing the carrier concentration in the source regionby relatively lowering the impurity concentration in the first regionA and relatively raising the impurity concentration in the second regionB.

53 FIG. 53 FIG. 50 FIG. 50 FIG. 53 FIG. 53 FIG. is a schematic sectional view of a semiconductor device according to a modification. Referring to, portions corresponding to the respective portions shown inare denoted by the same reference numerals as the reference numerals assigned to the respective portions. In the following, only a point different from the structure shown inis described as to the structure shown in, and description of the respective portions denoted by the same reference numerals is omitted. Referring to, only portions consisting of conductors are hatched, while hatching on the remaining portions is omitted.

605 605 605 601 605 605 605 651 605 605 651 601 50 FIG. 53 FIG. 50 FIG. While the depth of the first regionA of the source regionand the depth of the second regionB are generally identical to each other in the semiconductor deviceshown in, the depth of a first regionA of a source regionis smaller than the depth of a second regionB in a semiconductor deviceshown in. Also when the depth of the first regionA is smaller than the depth of the second regionB as in the semiconductor device, effects similar to those of the semiconductor deviceshown incan be attained.

54 FIG. 54 FIG. is a schematic sectional view of a semiconductor device according to another modification. Referring to, only portions consisting of conductors are hatched, while hatching on the remaining portions is omitted.

601 651 661 50 FIG. 53 FIG. 54 FIG. While the semiconductor deviceshown inand the semiconductor deviceshown inhave planar gate MIS structures, a semiconductor deviceshown inhas a trench gate MIS structure.

661 662 662 663 662 663 The semiconductor deviceincludes a semiconductor substrate. The semiconductor substrateis made of SiC (N-type SiC) doped with an N-type impurity. A semiconductor layeris formed on the semiconductor substrateby epitaxy. In other words, the semiconductor layeris an epitaxial layer made of N-type SiC.

663 664 663 665 − A base layer portion of the semiconductor layermaintains the state after the epitaxy, and forms an N-type drain region. A surface layer portion of the semiconductor layeris doped with a P-type impurity, to be converted to a P-type well region.

663 666 666 608 666 665 664 49 FIG. In the semiconductor layer, a gate trenchis formed to be dug down from the surface thereof. The gate trenchis provided in the form of a lattice in plan view, similarly to the gate electrodeshown in, for example. The gate trenchpasses through the well region, and the deepest portion thereof reaches the drain region.

667 666 667 A gate insulating filmis formed on the inner surface of the gate trench. The gate insulating filmis made of silicon oxide, for example.

667 668 666 The inner side of the gate insulating filmis filled up with polysilicon doped with an N-type impurity or a P-type impurity, whereby a gate electrodemade of the doped polysilicon is embedded in the gate trench.

669 665 669 669 669 An N-type source regionis formed on a surface layer portion of the well region. The depth of the source region(the total depth of a first regionA and a second regionB described later) is 0.5 to 2 μm, for example.

669 669 669 669 669 669 669 669 669 669 + − 17 19 −3 19 20 −3 In the source region, the N-type impurity concentration in the first regionA of a prescribed depth (0.2 μm, for example) on the bottom portion thereof is lower by one to three digits than the N-type impurity concentration in the remaining second region (region on the first regionA)B. In other words, the source regionhas the N-type second regionB whose N-type impurity concentration is relatively high and the N-type first regionA, formed under the second regionB, whose N-type impurity concentration is relatively low. The N-type impurity concentration in the first regionA is 5×10to 5×10cm, for example, and the N-type impurity concentration in the second regionB is 5×10to 5×10cm, for example.

669 668 669 669 669 669 669 669 665 667 669 669 669 A step S where the side surface of the second regionB more separates from the gate electrodethan the side surface of the first regionA is formed between the side surface of the first regionA and the side surface of the second regionB, due to the difference between the N-type impurity concentrations in the first regionA and the second regionB. The magnitude of the step S is 0.1 μm, for example. No large step is formed between the side surface of the first regionA and the side surface of the well region(channel region C), but the side surfaces are generally flush with each other. The gate insulating filmhas a relatively large thickness on the side surface of the second regionB, due to the difference between the N-type impurity concentrations in the first regionA and the second regionB.

665 670 669 666 666 + On the surface layer portion of the well region, a P-type contact regionis formed to pass through the source regionin the thickness direction on a position at an interval from the gate trenchin each region surrounded by the gate trench.

671 663 671 An interlayer dielectric filmis stacked on the semiconductor layer. The interlayer dielectric filmis made of silicon oxide, for example.

671 672 670 670 669 670 672 In the interlayer dielectric film, a contact holeis penetratingly formed on a position opposed to each contact region. The whole area of the contact regionand a portion of the source regionaround the contact regionface the inner portion of each contact hole.

673 671 673 672 669 670 673 A source metalis formed on the interlayer dielectric film. The source metalenters each contact hole, and is connected to the source regionand the contact region. The source metalis made of a metallic material containing Al as a main component, for example.

662 674 675 662 On the back surface of the semiconductor substrate, an ohmic metalmade of nickel (Ni) or the like and a drain metalmade of a metallic material containing aluminum as a main component are formed on the whole surface thereof in this order from the side of the semiconductor substrate.

668 673 675 665 667 673 675 The potential (gate voltage) of the gate electrodeis controlled in a state where the source metalis grounded and proper positive voltage is applied to the drain metal, whereby a channel is formed in the channel region C of the well regionin the vicinity of the interface between the same and the gate insulating film, and current flows between the source metaland the drain metal.

55 FIG. 54 FIG. is a schematic enlarged sectional view in the vicinity of the first region of the source region and the channel region shown in.

669 669 661 669 665 The N-type impurity concentration in the first regionA of the source regionadjacent to the channel region C is lowered in the semiconductor device, whereby no large step is formed between the side surface of the first regionA and the side surface of the channel region C (the well region).

− 673 675 669 669 666 661 601 651 661 30 FIG. Therefore, electrons (e) flowing between the source metaland the drain metalmove from the source regionto the channel region C along the side surface of the first regionA (the inner surface of the gate trench), and move in the channel region C along the side surface thereof. In other words, the path of the electrons in the channel region C becomes a linear path along the side surface of the channel region C. Also according to the structure of the semiconductor device, therefore, functions/effects similar to those of the semiconductor devicesandcan be exhibited, and channel resistance of the semiconductor deviceis lower than the channel resistance of the semiconductor device ofin which the movement path of the electrons in the channel region becomes a bent path.

603 663 602 662 603 663 604 665 605 669 602 662 While such structures that the semiconductor layersandare stacked on the semiconductor substratesandhave been adopted in the aforementioned embodiment, the semiconductor layersandmay be omitted, and the well regionsandand the source regionsandetc. may be formed on the surface layer portions of the semiconductor substratesand.

Further, the conductivity type of each portion may be inverted. In other words, while the case where the first conductivity type is the N type and the second conductivity type is the P type has been adopted, the first conductivity type may be the P type, and the second conductivity type may be the N type.

While the present invention has been described in detail by way of the embodiments thereof, it should be understood that these embodiments are merely illustrative of the technical principles of the present invention but not limitative of the invention. The spirit and scope of the present invention are to be limited only by the appended claims.

1 semiconductor device 2 SiC substrate (silicon carbide substrate) 8 2 SiOfilm (silicon oxide film) 9 AlON film (aluminum oxynitride film) 10 gate electrode 14 2 SiOfilm (silicon oxide film) 15 AlON film (aluminum oxynitride film) 16 capacitor electrode 101 semiconductor device 102 semiconductor substrate (semiconductor layer, silicon carbide substrate) 103 semiconductor layer (semiconductor layer) 104 well region 105 source region 105 A first region 105 B second region 107 gate insulating film 107 2 A SiOfilm (silicon oxide film) 107 B AlON film (aluminum oxynitride film) 108 gate electrode 151 semiconductor device 161 semiconductor device 162 semiconductor substrate (semiconductor layer) 163 semiconductor layer (semiconductor layer) 165 well region 166 gate trench 167 gate insulating film 168 gate electrode 169 source region 169 A first region 169 B second region 301 semiconductor device 303 SiC layer (silicon carbide layer) 307 gate insulating film 307 A SiON film (silicon oxynitride film) 307 2 B SiOfilm (silicon oxide film) 307 C AlON film (high dielectric constant insulating film) 308 gate electrode 351 semiconductor device 353 SiC layer (silicon carbide layer) 357 gate insulating film 357 A SiON film (silicon oxynitride film) 357 2 B SiOfilm (silicon oxide film) 357 C AlON film (high dielectric constant insulating film) 358 gate electrode 381 semiconductor device 382 SiC substrate (silicon carbide layer) 387 gate insulating film 387 A SiON film (silicon oxynitride film) 387 2 B SiOfilm (silicon oxide film) 387 C AlON film (high dielectric constant insulating film) 388 gate electrode 401 semiconductor device 402 semiconductor substrate (semiconductor layer) 403 semiconductor layer (semiconductor layer, silicon carbide layer) 404 well region 405 source region 405 A first region 405 B second region 407 gate insulating film 408 gate electrode 451 semiconductor device 453 SiC layer (silicon carbide layer) 457 gate insulating film 457 A SiON film (silicon oxynitride film) 457 2 B SiOfilm (silicon oxide film) 457 C AlON film (high dielectric constant insulating film) 458 gate electrode 461 semiconductor device 462 semiconductor substrate (semiconductor layer) 463 semiconductor layer (semiconductor layer) 465 well region 466 gate trench 467 gate insulating film 468 gate electrode 469 source region 469 A first region 469 B second region 471 SiON film (silicon oxynitride film) 472 2 SiOfilm (silicon oxide film) 473 AlON film (high dielectric constant insulating film) 481 semiconductor device 482 SiC substrate (silicon carbide layer) 487 gate insulating film 487 A SiON film (silicon oxynitride film) 487 2 B SiOfilm (silicon oxide film) 487 C AlON film (high dielectric constant insulating film) 488 gate electrode 601 semiconductor device 602 semiconductor substrate (semiconductor layer) 603 semiconductor layer (semiconductor layer) 604 well region 605 source region 605 A first region 605 B second region 607 gate insulating film 608 gate electrode 651 semiconductor device 661 semiconductor device 662 semiconductor substrate (semiconductor layer) 663 semiconductor layer (semiconductor layer) 665 well region 666 gate trench 667 gate insulating film 668 gate electrode 669 source region 669 A first region 669 B second region C channel region S step 1 2 SSiOfilm formation step 2 Snitrogen plasma application step 3 SFGA step 4 SAlON film formation step 5 SPDA step