Integrated Circuit Device

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0089118, filed on Jul. 5, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

The inventive concept relates to an integrated circuit (IC) device, and more particularly, to an IC device including a field-effect transistor (FET).

As the downscaling of IC devices is rapidly progressing, IC devices require having not only a high operating speed but also high operating accuracy. Accordingly, various studies are being conducted on developing an IC device having a structure that may provide optimum performance and may improve reliability.

The inventive concept provides an integrated circuit (IC) device having a structure capable of improving the electrical performance and reliability of a field-effect transistor (FET).

According to an aspect of the inventive concept, there is provided an IC device including a channel region, a gate line surrounding the channel region, the gate line having a first top surface extending in a first direction, wherein the first top surface of the gate line is a first distance apart from an uppermost surface of the channel region in a second direction perpendicular to the first direction, a source/drain region contacting the channel region, a source/drain contact located on the source/drain region and connected to the source/drain region, the source/drain contact having a second top surface coplanar with the first top surface of the gate line and extending in the first direction, and an etch stop insulating film extending from the first top surface of the gate line toward the second top surface of the source/drain contact in the first lateral direction, the etch stop insulating film contacting the first top surface of the gate line.

According to another aspect of the inventive concept, there is provided an IC device including a plurality of channel regions apart from each other in a first direction, a plurality of gate lines at least partially surrounding the plurality of channel regions, each gate line extending perpendicular to the plurality of channel regions, and each gate line having a first top surface extending in the first direction wherein the first top surface of the gate line is a first distance apart from of an uppermost surface of each of the plurality of channel regions in a second direction perpendicular to the first direction, a plurality of source/drain regions, each of the plurality of source/drain regions between two adjacent gate lines of the plurality of gate lines, a plurality of source/drain contacts, each of the plurality of source/drain contacts connected to a source/drain region of the plurality of source/drain regions, and each of the plurality of source/drain contacts having a second top surface coplanar with the first top surface of the gate line and extending in the first direction, and an etch stop insulating film extending in the first direction from the first top surface of each of the plurality of gate lines toward the second top surface of a source/drain contact, from among the plurality of source/drain contacts, the etch stop insulating film contacting the first top surface of each of the plurality of gate lines.

According to another aspect of the inventive concept, there is provided an IC device including a nanosheet stack comprising a plurality of nanosheets extending in a first direction and stacked in a second direction perpendicular to the first direction, a plurality of gate lines at least partially surrounding the plurality of nanosheets and extending lengthwise in a third direction perpendicular to the first direction and the second direction, a plurality of gate insulating spacers at least partially covering both sidewalls of each of the plurality of gate lines, a source/drain region between two adjacent ones of the plurality of gate lines, the source/drain region contacting the plurality of nanosheets, a source/drain contact on the source/drain region and connected to the source/drain region, an etch stop insulating film contacting a first top surface of each of the plurality of gate lines and a spacer top surface of each of the plurality of gate insulating spacers, a capping insulating film on a top surface of the etch stop insulating film, the capping insulating film including a different material from a constituent material of the etch stop insulating film, a plurality of gate contacts passing through the capping insulating film and the etch stop insulating film in the second direction, each gate contact contacting the first top surface of a corresponding one of the plurality of gate lines, and a via contact passing through the capping insulating film and the etch stop insulating film in the second direction and contacting a second top surface of the source/drain contact, wherein the first top surface of each of the plurality of gate lines and the second top surface of the source/drain contact are coplanar and extend in the first direction and the third direction, wherein the first top surface of each of the plurality of gate lines is a first distance apart from a an uppermost surface of the nanosheet stack in the second direction, and a third top surface of each of the plurality of gate contacts and a fourth top surface of the via contact are coplanar in the first direction, and are a second distance apart from the uppermost surface of the nanosheet stack in the second direction, and the second distance is greater than the first distance.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used to denote the same elements in the drawings, and repeated descriptions thereof will be omitted.

The terms “first,” “second,” etc., may be used herein merely to distinguish one component, layer, direction, etc. from another. The terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated elements, but do not preclude the presence of additional elements. The term “and/or” includes any and all combinations of one or more of the associated listed items. The term “connected” may be used herein to refer to a physical and/or electrical connection. When components or layers are referred to herein as “directly” on, or “in direct contact” or “directly connected,” no intervening components or layers are present. Likewise, when components are “immediately” adjacent to one another, no intervening components may be present.

Components or layers described with reference to “overlap” in a particular direction may be at least partially obstructed by one another when viewed along a line extending in the particular direction or in a plane perpendicular to the particular direction. The term “surrounding” or “covering” or “filling” as may be used herein may not require completely surrounding or covering or filling the described elements or layers, but may, for example, refer to partially surrounding or covering or filling the described elements or layers, for example, with voids or other spaces throughout. The term “exposed,” may be used to describe relationships between elements and/or certain intermediate processes in fabricating a completed semiconductor device but may not necessarily require exposure of the particular region, layer, structure or other element in the context of the completed device.

It will be understood that spatially relative terms such as ‘on,’ ‘upper,’ ‘upper portion,’ ‘upper surface,’ ‘below,’ ‘lower,’ ‘lower portion,’ ‘lower surface,’ ‘side surface,’ and the like may be denoted by reference numerals and refer to the drawings, except where otherwise indicated. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

1 FIG. 12 10 is a schematic plan view of a cell blockof an integrated circuit (IC) deviceaccording to embodiments.

1 FIG. 1 FIG. 1 FIG. 12 10 12 Referring to, the cell blockof the IC devicemay include a plurality of cells LC, which include circuit patterns configured to constitute various circuits. The plurality of cells LC may be arranged in a matrix form in a widthwise direction (X direction in) and a height direction (Y direction in) in the cell block.

Each of the plurality of cells LC may include a circuit pattern having a layout designed according to a place-and-route (PnR) technique to perform at least one logic function. The plurality of cells LC may perform various logic functions. In embodiments, the plurality of cells LC may include a plurality of standard cells. In embodiments, at least some of the plurality of cells LC may perform the same logic function. In other embodiments, at least some of the plurality of cells LC may perform different logic functions.

The plurality of cells LC may include various kinds of logic cells including a plurality of circuit elements. For example, each of the plurality of logic cells LC may include an AND, a NAND, an OR, a NOR, an exclusive OR (XOR), an exclusive NOR (XNOR), an inverter (INV), an adder (ADD), a buffer (BUF), a delay (DLY), a filter (FIL), a multiplexer (MXT/MXIT), an OR/AND/INVERTER (OAI), an AND/OR (AO), an AND/OR/INVERTER (AOI), a D-flip-flop, a reset flip-flop, a master-slave flip-flop, a latch, or a combination thereof, without being limited thereto.

12 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 FIG. 1 FIG. In the cell block, at least some of the plurality of cells LC that form one row RW, RW, RW, RW, RW, or RWin the widthwise direction (X direction in) may have the same width as each other. Also, at least some of the plurality of cells LC that form one row RW, RW, RW, RW, RW, or RWmay have the same height as each other. However, the inventive concept is not limited to those illustrated in, and at least some of the plurality of cells LC that form one row RW, RW, RW, RW, RW, or RWmay have different widths and heights from each other.

12 10 1 FIG. 1 FIG. An area of each of the plurality of cells LC included in the cell blockof the IC devicemay be defined by a cell boundary CBD. A cell boundary contact portion CBC where respective cell boundaries CBD of two cells LC that are adjacent to each other in the widthwise direction (X direction in) or the height direction (Y direction in), from among the plurality of cells LC, meet each other may be between the two adjacent cells LC.

1 2 3 4 5 6 1 2 3 4 5 6 In embodiments, from among the plurality of cells LC that form one row RW, RW, RW, RW, RW, or RW, two cells LC that are adjacent to each other in the widthwise direction may contact each other at the cell boundary contact portion CBC without a distance therebetween. In other embodiments, from among the plurality of cells LC that form one row RW, RW, RW, RW, RW, or RW, two cells LC that are adjacent to each other in the widthwise direction may be a predetermined distance apart from each other.

1 2 3 4 5 6 1 2 3 4 5 6 In embodiments, from among the plurality of cells LC that form one row RW, RW, RW, RW, RW, or RW, two adjacent cells LC may perform the same function as each other. In this case, the two adjacent cells LC may have the same structure as each other. In other embodiments, from among the plurality of cells LC that form one row RW, RW, RW, RW, RW, or RW, two adjacent cells may perform different functions from each other.

12 10 3 2 3 4 12 1 2 6 12 1 FIG. 1 FIG. In embodiments, one cell LC, which is selected from the plurality of cells LC included in the cell blockof the IC device, may have a symmetrical structure to another cell LC, which is adjacent to the selected cell LC in the height direction (Y direction in), about the cell boundary contact portion CBC therebetween. For example, a reference cell LC_R in a third row RWmay have a symmetrical structure to a lower cell LC_L in a second row RWabout the cell boundary contact portion CBC therebetween. Also, the reference cell LC_R in the third row RWmay have a symmetrical structure to an upper cell LC_H in a fourth row RWabout the cell boundary contact portion CBC therebetween. Althoughillustrates an example in which the cell blockincludes six rows RW, RW, . . . , and RW, the inventive concept is not limited thereto. The cell blockmay include various numbers of rows, which are selected as needed, and one row may include various numbers of cells, which are selected as needed.

1 2 3 4 5 6 1 FIG. A selected one of a plurality of ground lines VSS and a plurality of power lines VDD may be between a plurality of rows (e.g., RW, RW, RW, RW, RW, and RW), each of which includes a plurality of cells LC arranged in a line in the widthwise direction (X direction in). The plurality of ground lines VSS and the plurality of power lines VDD may each extend in the widthwise direction (X direction) and may be alternately arranged apart from each other in the height direction (Y direction). The second lateral direction (Y direction) may be perpendicular to the first lateral direction (X direction). Accordingly, the plurality of ground lines VSS and the plurality of power lines VDD may each overlap the cell boundary CBD of the cell LC in the second lateral direction (Y direction).

2 FIG. 3 FIG. 2 FIG. 4 FIG. 2 FIG. 5 FIG. 2 FIG. 6 FIG. 3 FIG. 2 6 FIGS.to 2 6 FIGS.to 1 FIG. 100 100 1 1 100 1 1 100 2 2 1 100 100 is a plan layout diagram of an IC deviceaccording to embodiments.is a cross-sectional view of the IC devicetaken along line X-X′ of.is a cross-sectional view of the IC devicetaken along line Y-Y′ of.is a cross-sectional view of the IC devicetaken along line Y-Y′ of.is an enlarged cross-sectional view of a region indicated by “EX” of. The IC deviceincluding a field-effect transistor (FET) having a gate-all-around structure including a channel region of a nanowire or nanosheet type and a gate surrounding the channel region is described with reference to. Components of the IC device, which are described with reference to, may constitute some of the plurality of cells LC shown in.

2 6 FIGS.to 100 1 160 130 1 102 1 1 160 130 160 160 152 160 130 Referring to, the IC devicemay include a fin-type active region F, a plurality of nanosheet stacks NSS, a plurality of gate lines, and a plurality of source/drain regions. The fin-type active region Fmay protrude from a substrateand extend lengthwise in a first lateral direction (X direction). The plurality of nanosheet stacks NSS may be apart upward from the fin-type active region Fin a vertical direction (Z direction) and face a fin top surface FF of the fin-type active region F. The plurality of gate linesmay surround the plurality of nanosheet stacks NSS. Each of the plurality of source/drain regionsmay be between two adjacent ones of the plurality of gate lines. Each of the plurality of gate linesmay be surrounded by a gate dielectric film. The plurality of gate lines, the plurality of nanosheet stacks NSS, and the plurality of source/drain regionsmay constitute a plurality of FETs TR.

102 102 As used herein, the term “nanosheet” refers to a conductive structure having a cross-section that is substantially perpendicular to a direction in which current flows. The nanosheet may be interpreted as including a nanowire. The substratemay include an element semiconductor, such as silicon (Si) or germanium (Ge), or a compound semiconductor, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), or indium phosphide (InP). As used herein, each of the terms “SiGe,” “SiC,” “GaAs,” “InAs,” “InGaAs,” and “InP” refers to a material including elements included therein, without referring to a chemical formula representing a stoichiometric relationship. The substratemay include a conductive region, for example, a doped well or a doped structure.

1 1 102 1 112 112 160 1 160 1 1 160 6 1 2 3 4 1 1 2 3 4 1 2 3 4 3 4 FIGS., A trench Tdefining the fin-type active region Fmay be formed in the substrate. The trench Tmay be filled by a field insulating film. The field insulating filmmay include a silicon oxide film. A plurality of gate linesmay be on the fin-type active region F. Each of the plurality of gate linesmay extend lengthwise in a second lateral direction (Y direction), which is perpendicular to the first lateral direction (X direction). The plurality of nanosheet stacks NSS may be respectively on fin top surfaces FF of the plurality of fin-type active regions Fin regions where the plurality of fin-type active regions Fintersect the plurality of gate lines. Each of the plurality of nanosheet stacks NSS may include at least one nanosheet. As shown in, and, each of the plurality of nanosheet stacks NSS may include first to fourth nanosheets N, N, N, and N, which overlap each other in the vertical direction (Z direction) on the fin-type active region F. Each of the first to fourth nanosheets N, N, N, and Nincluded in the nanosheet stack NSS may provide a channel region. As used herein, the nanosheet stacks NSS, each of which includes the first to fourth nanosheets N, N, N, and N, may be each referred to as a channel region.

1 2 3 4 1 2 3 4 In embodiments, each of the first to fourth nanosheets N, N, N, and Nincluded in the nanosheet stack NSS may include a Si layer, a SiGe layer, or a combination thereof. For example, each of the first to fourth nanosheets N, N, N, and Nmay include a Si layer.

1 2 3 4 1 160 1 2 3 4 The first to fourth nanosheets N, N, N, and Nmay be at different vertical distances (Z-direction distances) from the fin top surface FF of the fin-type active region F. Each of the plurality of gate linesmay surround the first to fourth nanosheets N, N, N, and N, which are included in the nanosheet stack NSS and overlap each other in the vertical direction (Z direction).

2 FIG. 3 4 6 FIGS.,, and 1 160 160 1 1 160 1 1 2 3 4 Althoughillustrates a case in which the nanosheet stack NSS has a substantially rectangular planar shape, the inventive concept is not limited thereto. The nanosheet stack NSS may have various planar shapes according to a planar shape of each of the fin-type active region Fand the gate line. The present embodiment pertains to a configuration in which the plurality of nanosheet stacks NSS and the plurality of gate linesare formed on one fin-type active region F, and the plurality of nanosheet stacks NSS are arranged in a line in the first lateral direction (X direction) on one fin-type active region F. However, the number of nanosheet stacks NSS and the number of gate lineson one fin-type active region Fare not specifically limited and may be variously changed as needed.illustrate an example in which each of the plurality of nanosheet stacks NSS includes the first to fourth nanosheets N, N, N, and N, but the inventive concept is not limited thereto. For example, the nanosheet stack NSS may include at least one nanosheet, and the number of nanosheets in the nanosheet stack NSS is not specifically limited.

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 In embodiments, each of the first to fourth nanosheets N, N, N, and Nmay have a thickness selected in a range of about 4 nm to about 6 nm, without being limited thereto. Here, the thickness of each of the first to fourth nanosheets N, N, N, and Nrefers to a size of each of the first to third nanosheets N, N, N, and Nin the vertical direction (Z direction). In embodiments, the first to fourth nanosheets N, N, N, and Nmay have substantially the same thickness in the vertical direction (Z direction). In other embodiments, at least some of the first to fourth nanosheets N, N, N, and Nmay have different thicknesses in the vertical direction (Z direction).

3 6 FIGS.and 3 6 FIGS.and 1 2 3 4 1 2 3 4 As shown in, the first to third nanosheets N, N, N, and Nincluded in one nanosheet stack NSS may have the same size or similar sizes in the first lateral direction (X direction). In other embodiments, differently from that shown in, at least some of the first to third nanosheets N, N, N, and Nincluded in one nanosheet stack NSS may have different sizes in the first lateral direction (X direction).

3 4 6 FIGS.,, and 160 160 160 160 160 160 1 2 3 4 1 1 160 160 As shown in, each of the plurality of gate linesmay include a main gate portionM and a plurality of sub-gate portionsS. The main gate portionM may cover a top surface of the nanosheet stack NSS and extend lengthwise in the second lateral direction (Y direction). The plurality of sub-gate portionsS may be integrally connected to the main gate portionM and respectively one-by-one arranged between the first to fourth nanosheets N, N, N, and Nand between the first nanosheet Nand a fin top surface FF of the fin-type active region F. In the vertical direction (Z direction), a thickness of each of the plurality of sub-gate portionsS may be less than a thickness of the main gate portionM.

160 160 The plurality of gate linesmay include a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from molybdenum (Mo), ruthenium (Ru), copper (Cu), and tungsten (W). The metal nitride may be selected from titanium nitride (TiN), tantalum nitride (TaN), and titanium aluminum nitride (TiAIN), or a combination thereof. The metal carbide may include titanium aluminum carbide (TiAIC). However, a material included in the plurality of gate linesis not limited to the examples described above.

4 FIG. 112 102 160 112 1 As shown in, the field insulating filmmay be between the substrateand the gate linein the vertical direction (Z direction). The field insulating filmmay cover a sidewall of the fin-type active region Fin the second lateral direction (Y direction).

3 5 FIGS.and 1 1 1 1 As shown in, a plurality of recesses Rmay be formed in the fin-type active region F. A lowermost surface of each of the plurality of recesses Rmay be at a lower vertical level than the fin top surface FF of the fin-type active region F.

130 1 130 160 160 130 1 2 3 4 A plurality of source/drain regionsmay be inside the plurality of recesses R. Each of the plurality of source/drain regionsmay be adjacent to at least one gate lineselected from the plurality of gate lines. Each of the plurality of source/drain regionsmay have surfaces in contact with the first to fourth nanosheets N, N, N, and Nincluded in the nanosheet stack NSS adjacent thereto.

130 130 130 130 130 130 Each of the plurality of source/drain regionsmay include an epitaxially grown semiconductor layer. In embodiments, each of the plurality of source/drain regionsmay include an epitaxially grown Si layer, an epitaxially grown SiC layer, or a plurality of epitaxially grown SiGe layers. When the source/drain regionconstitutes an NMOS transistor, the source/drain regionmay include a Si layer doped with an n-type dopant or a SiC layer doped with an n-type dopant. The n-type dopant may be selected from phosphorus (P), arsenic (As), and antimony (Sb). When the source/drain regionconstitutes a PMOS transistor, the source/drain regionmay include a SiGe layer doped with a p-type dopant. The p-type dopant may be selected from boron (B) and gallium (Ga).

160 160 1 1 0 0 0 1 4 3 6 FIGS.to Each of the plurality of gate linesmay have a first top surfaceT, which extends at a first vertical level LVin a lateral direction (e.g., the first lateral direction (X direction) and the second lateral direction (Y direction)). The first vertical level LVmay be a first distance apart from a reference vertical level LVin the vertical direction (Z direction), and the reference vertical level LVmay be a vertical level of an uppermost surface of the nanosheet stack NSS. The first distance may be a shortest distance between the reference vertical level LVand the first vertical level LV. In, the uppermost surface of the nanosheet stack NSS may correspond to a top surface of the fourth nanosheet N.

3 6 FIGS.and 160 118 118 100 160 112 118 160 118 160 152 118 As shown in, both sidewalls of each of the plurality of gate linesin the first lateral direction (X direction) may be covered by gate insulating spacers. Each of a plurality of gate insulating spacersincluded in the IC devicemay extend lengthwise along with the gate linein the second lateral direction (Y direction) on the nanosheet stack NSS and the field insulating film. The gate insulating spacersmay cover both sidewalls of the main gate portionM on the top surface of each of the plurality of nanosheet stacks NSS. The gate insulating spacermay be apart from the gate linewith the gate dielectric filmtherebetween. The gate insulating spacersmay each include silicon nitride, silicon oxide, silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon oxycarbide (SiOC), or a combination thereof. As used herein, each of the terms “SiCN,” “SiBN,” “SiON,” “SiOCN,” “SiBCN,” and “SiOC” refers to a material including elements included therein, without referring to a chemical formula representing a stoichiometric relationship.

152 160 152 A gate dielectric filmmay be between the nanosheet stack NSS and the gate line. The gate dielectric filmmay have a stack structure of an interface dielectric film and a high-k dielectric film. The interface dielectric film may include a low-k dielectric material film (e.g., a silicon oxide film, a silicon oxynitride film, or a combination thereof), which has a dielectric constant of about 9 or less. In embodiments, the interface dielectric film may be omitted. The high-k dielectric film may include a material having a higher dielectric constant than a silicon oxide film. For example, the high-k dielectric film may have a dielectric constant of about 10 to 25. The high-k dielectric film may include hafnium oxide, without being limited thereto.

160 160 130 152 152 160 160 1 2 3 4 160 160 130 1 160 1 160 160 Both sidewalls of each of the plurality of sub-gate portionsS included in the plurality of gate linesmay be apart from the source/drain regionwith the gate dielectric filmtherebetween. The gate dielectric filmmay include respective portions between the sub-gate portionS included in the gate lineand the first to fourth nanosheets N, N, N, and N, portions between the sub-gate portionS included in the gate lineand the source/drain region, and a portion between the fin top surface FF of the fin-type active region Fand the sub-gate portionS that is closest to the fin top surface FF of the fin-type active region F, from among the plurality of sub-gate portionsS included in the gate line.

172 130 172 172 A metal silicide filmmay be formed on a top surface of each of the plurality of source/drain regions. The metal silicide filmmay include a metal, which includes titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), or palladium (Pd). For example, the metal silicide filmmay include titanium silicide, without being limited thereto.

5 FIG. 142 144 130 142 144 130 142 142 144 As shown in, an insulating linerand an inter-gate dielectric filmmay be sequentially located on the plurality of source/drain regions. The insulating linerand the inter-gate dielectric filmmay constitute an inter-gate insulating structure. The plurality of source/drain regionsmay be covered by the insulating liner. In embodiments, the insulating linermay include silicon nitride (SiN), SiCN, SiBN, SION, SiOCN, SiBCN, or a combination thereof, without being limited thereto. The inter-gate dielectric filmmay include a silicon oxide film, without being limited thereto.

5 FIG. 112 142 119 112 130 119 130 1 119 130 119 142 119 118 119 As shown in, the field insulating filmmay have a top surface contacting the insulating liner. A plurality of side insulating spacersmay be on the field insulating filmon both sides of the source/drain regionin the second lateral direction (Y direction). Each of the plurality of side insulating spacersmay cover a sidewall of a partial region of the source/drain region, which is adjacent to the fin-type active region F. Each of the plurality of side insulating spacersmay be in contact with a sidewall of the source/drain region. The plurality of side insulating spacersmay be covered by the insulating liner. Each of the plurality of side insulating spacersmay include the same material as a constituent material of the gate insulating spacer. In other embodiments, at least some of the plurality of side insulating spacersmay be omitted.

3 5 6 FIGS.,, and 130 144 142 130 130 172 130 172 130 As shown in, a plurality of source/drain contacts CA may be on the plurality of source/drain regions. Each of the plurality of source/drain contacts CA may pass through an inter-gate dielectric structure including the inter-gate dielectric filmand the insulating linerin the vertical direction (Z direction) and be electrically connected to one source/drain regionselected from the plurality of source/drain regions. A bottom surface of each of the plurality of source/drain contacts CA may be in contact with a metal silicide filmformed on the source/drain region. The metal silicide filmmay be between the source/drain regionand the source/drain contact CA.

130 172 160 160 118 Each of the plurality of source/drain contacts CA may be electrically connectable to the source/drain regionthrough the metal silicide film. Each of the plurality of source/drain contacts CA may be apart from the main gate portionM of the gate linewith the gate insulating spacertherebetween in the first lateral direction (X direction).

In embodiments, each of the plurality of source/drain contact CA may include a metal plug and a conductive barrier film surrounding the metal plug. The metal plug may include molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (AI), copper (Cu), a combination thereof, or an alloy thereof, without being limited thereto. The conductive barrier film may include a metal or a conductive metal nitride. For example, the conductive barrier film may include titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), or a combination thereof, without being limited thereto. In other embodiments, the conductive barrier film may be omitted in each of the plurality of source/drain contacts CA.

1 118 118 1 160 160 118 118 Each of the plurality of source/drain contacts CA may have a second top surface CAT, which extends at the first vertical level LVin a lateral direction (e.g., the first lateral direction (X direction) and the second lateral direction (Y direction)). In addition, each of the plurality of gate insulating spacersmay have a spacer top surfaceT, which extends at the first vertical level LVin a lateral direction (e.g., the first lateral direction (X direction) and the second lateral direction (Y direction)). That is, the first top surfaceT of each of the plurality of gate lines, the second top surface CAT of each of the plurality of source/drain contacts CA, and the spacer top surfaceT of each of the plurality of gate insulating spacersmay extend at the same vertical level in a lateral direction (e.g., the first lateral direction (X direction) and the second lateral direction (Y direction)).

160 160 152 118 118 174 160 160 152 118 118 174 The first top surfaceT of each of the plurality of gate lines, an uppermost surface of the gate dielectric film, the second top surface CAT of each of the plurality of source/drain contacts CA, and the spacer top surfaceT of each of the plurality of gate insulating spacersmay be covered by an etch stop insulating film. The first top surfaceT of each of the plurality of gate lines, the uppermost surface of the gate dielectric film, the second top surface CAT of each of the plurality of source/drain contacts CA, and the spacer top surfaceT of each of the plurality of gate insulating spacersmay be in contact with a bottom surface of the etch stop insulating film.

174 160 160 174 The etch stop insulating filmmay extend in the first lateral direction (X direction) from the first top surfaceT of each of the plurality of gate linestoward the second top surface CAT of the source/drain contact CA adjacent to the etch stop insulating film, from among the plurality of source/drain contacts CA.

5 FIG. 144 130 144 144 1 144 144 174 As shown in, in the second lateral direction (Y direction), the inter-gate dielectric filmmay cover a sidewall of each of the source/drain regionand the source/drain contact CA. An insulating top surfaceT of the inter-gate dielectric filmmay extend at the first vertical level LVin a lateral direction (e.g., the first lateral direction (X direction) and the second lateral direction (Y direction)). The insulating top surfaceT of the inter-gate dielectric filmmay be in contact with the bottom surface of the etch stop insulating film.

175 174 175 174 A capping insulating filmmay be on the etch stop insulating film. A bottom surface of the capping insulating filmmay be in contact with a top surface of the etch stop insulating film.

174 175 174 175 174 The etch stop insulating filmand the capping insulating filmmay include different insulating materials from each other. For example, the etch stop insulating filmmay include a silicon oxide film or an aluminum oxide film, and the capping insulating filmmay include a silicon nitride film. In embodiments, the etch stop insulating filmmay include a single film including a single material, which is selected from a silicon oxide film and an aluminum oxide film.

100 160 160 The IC devicemay further include a plurality of gate contacts CB contacting the first top surfacesT of the plurality of gate linesand a plurality of via contacts VA contacting the second top surfaces CAT of the plurality of source/drain contacts CA.

175 174 175 174 Each of the plurality of gate contacts CB and the plurality of via contacts VA may pass through the capping insulating filmand the etch stop insulating filmin the vertical direction (Z direction). The capping insulating filmand the etch stop insulating filmmay surround a sidewall of each of the plurality of gate contacts CB and the plurality of via contacts VA.

2 2 0 0 2 0 1 Each of the plurality of gate contacts CB may have a third top surface CBT, and each of the plurality of via contacts VA may have a fourth top surface VAT. The third top surface CBT of each of the plurality of gate contacts CB and the fourth top surface VAT of each of the plurality of via contacts VA may extend at a second vertical level LVin a lateral direction (e.g., the first lateral direction (X direction) and the second lateral direction (Y direction)). The second vertical level LVmay be a second distance apart from the reference vertical level LVin the vertical direction (Z direction). The second distance may be a shortest distance between the reference vertical level LVand the second vertical level LV. The second distance may be greater than the first distance, which is the shortest distance between the reference vertical level LVand the first vertical level LV.

Each of the plurality of gate contacts CB and the plurality of via contacts VA may include a metal plug and a conductive barrier film surrounding the metal plug. The meal plug included in each of the plurality of gate contacts CB may include molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (AI), copper (Cu), a combination thereof, or an alloy thereof, without being limited thereto. The conductive barrier film included in each of the plurality of gate contacts CB and the plurality of via contacts VA may include a metal or a conductive metal nitride. For example, the conductive barrier film may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, without being limited thereto. In other embodiments, the conductive barrier film may be omitted in each of the plurality of gate contacts CB and the plurality of via contacts VA.

175 175 2 175 175 The capping insulating filmmay have a capping top surfaceT, which extends at the second vertical level LVin a lateral direction (e.g., the first lateral direction (X direction) and the second lateral direction (Y direction)). The capping top surfaceT of the capping insulating film, the third top surface CBT of each of the plurality of gate contacts CB, and the fourth top surface VAT of each of the plurality of via contacts VA may extend at the same vertical level in a lateral direction (e.g., the first lateral direction (X direction) and the second lateral direction (Y direction)).

3 FIG. 1 130 130 130 102 102 1 174 130 As shown in, the fin-type active region Fmay be in contact with a bottom surface of each of the plurality of source/drain regions. The bottom surface of each of the plurality of source/drain regionsmay be a surface of each of the plurality of source/drain regions, which is closest to a backside surfaceB of the substrate. The fin-type active region Fmay be apart from the etch stop insulating filmwith the plurality of source/drain regionstherebetween in the vertical direction (Z direction).

175 175 180 180 182 184 175 182 184 184 The third top surface CBT of each of the plurality of gate contacts CB, the fourth top surface VAT of each of the plurality of via contacts VA, and the capping top surfaceT of the capping insulating filmmay be covered by an upper insulating structure. The upper insulating structuremay include an etch stop filmand an upper insulating film, which are sequentially stacked on each of the plurality of gate contacts CB, the plurality of via contacts VA, and the capping insulating film. The etch stop filmmay include silicon carbide (SiC), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), aluminum oxycarbide (AlOC), or a combination thereof. The upper insulating filmmay include an oxide film, a nitride film, an ultralow-k (ULK) film having an ultralow dielectric constant of about 2.2 to about 2.4, or a combination thereof. For example, the upper insulating filmmay include a tetraethylorthosilicate (TEOS) film, a high-density plasma (HDP) film, a boro-phospho-silicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a silicon oxynitride (SiON) film, a silicon nitride (SiN) film, a silicon oxycarbide (SiOC) film, a SiCOH film, or a combination thereof, without being limited thereto.

1 180 1 1 The plurality of upper wiring layers Mmay pass through the upper insulating structure. Each of the plurality of upper wiring layers Mmay be connected to the plurality of via contacts VA or the gate contact CB. The plurality of upper wiring layers Mmay include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (AI), a combination thereof, or an alloy thereof, without being limited thereto.

100 180 1 When necessary, the IC devicemay further include a back-end-of-line (BEOL) structure including a plurality of wirings on the upper insulating structureand the plurality of upper wiring layers M.

100 160 160 160 160 118 118 160 174 174 160 160 160 160 100 2 6 FIGS.to To improve electrical properties of the FET TR, the IC devicedescribed with reference tomay have a structure in which the top surface of the source/drain contact CA and the top surface of the gate lineextend at the same vertical level in the lateral direction. In addition, the third top surface CBT of the gate contact CB connected to the gate lineand the fourth top surface VAT of the via contact VA connected to the source/drain contact CA may extend at the same vertical level in the lateral direction (e.g., the first lateral direction (X direction) and the second lateral direction (Y direction)). Furthermore, portions of the first top surfaceT of the gate line, except for a portion connected to the gate contact CB, and the spacer top surfacesT of the gate insulating spacerscovering both sidewalls of the gate linemay extend at the same vertical level and each contact the etch stop insulating film. The etch stop insulating filmmay have a structure extending in the first lateral direction (X direction) from the first top surfaceT of the gate linetoward the second top surface CAT of the source/drain contact CA. Accordingly, a length of the gate linein the vertical direction (Z direction) may be reduced, and thus, a capacitance of the gate linemay be reduced. Also, a length of each of the source/drain contact CA, the via contact VA, and the gate contact CB in the vertical direction (Z direction) may be reduced, and thus, a contact resistance of each contact structure including the source/drain contact CA, the via contact VA, and the gate contact CB may be reduced. Also, an insulating margin may be ensured to prevent the occurrence of short circuits between the contact structure and conductive structures adjacent thereto. Therefore, the IC deviceaccording to the inventive concept may improve the electrical performance and reliability of the FETs TR.

7 FIG. 7 FIG. 2 FIG. 7 FIG. 2 6 FIGS.to 7 FIG. 1 FIG. 200 1 1 200 200 is a cross-sectional view of an IC deviceaccording to embodiments.illustrates a cross-sectional configuration of a portion corresponding to a cross-section taken along line X-X′ of, in the IC device. In, the same reference numerals are used to denote the same elements as in, and detailed descriptions thereof are omitted. Components of the IC devicedescribed with reference tomay constitute some of the plurality of cells LC shown in.

7 FIG. 2 6 FIGS.to 7 FIG. 200 100 200 274 Referring to, the IC devicemay substantially have the same configuration as the IC devicedescribed with reference to. However, the IC deviceshown inmay include an etch stop insulating film.

274 174 274 274 274 160 160 152 118 118 274 160 160 152 118 118 3 6 FIGS.to The etch stop insulating filmmay substantially have the same configuration as the etch stop insulating filmdescribed with reference to. However, the etch stop insulating filmmay have a double layer structure including a first etch stop insulating filmA and a second etch stop insulating filmB, which are sequentially stacked on a first top surfaceT of each of the plurality of gate lines, an uppermost surface of a gate dielectric film, a second top surface CAT of each of the plurality of source/drain contacts CA, and a spacer top surfaceT of each of the plurality of gate insulating spacers. A bottom surface of the first etch stop insulating filmA may be in contact with each of the first top surfaceT of each of the plurality of gate lines, the uppermost surface of the gate dielectric film, the second top surface CAT of each of the plurality of source/drain contacts CA, and the spacer top surfaceT of each of the plurality of gate insulating spacers.

274 274 274 274 274 274 274 The etch stop insulating filmmay include a combination of a silicon oxide film and an aluminum oxide film, and the first etch stop insulating filmA and the second etch stop insulating filmB may include different films, each of which is selected from a silicon oxide film and an aluminum oxide film. In embodiments, the first etch stop insulating filmA may include a silicon oxide film, and the second etch stop insulating filmB may include an aluminum oxide film. In other embodiments, the first etch stop insulating filmA may include an aluminum oxide film, and the second etch stop insulating filmB may include a silicon oxide film.

8 8 FIGS.A andB 8 FIG.A 2 FIG. 8 FIG.B 2 FIG. 8 8 FIGS.A andB 2 6 FIGS.to 8 8 FIGS.A andB 1 FIG. 300 1 1 300 1 1 300 300 are cross-sectional views of an IC deviceaccording to embodiments.illustrates a cross-sectional configuration of a portion corresponding to a cross-section taken along line X-X′ of, in the IC device, andillustrates a cross-sectional configuration of a portion corresponding to a cross-section taken along line Y-Y′ of, in the IC device. In, the same reference numerals are used to denote the same elements as in, and detailed descriptions thereof are omitted. Components of the IC devicedescribed with reference tomay constitute some of the plurality of cells LC shown in.

8 8 FIGS.A andB 2 6 FIGS.to 200 100 300 Referring to, the IC devicemay substantially have the same configuration as the IC devicedescribed with reference to. However, the IC devicemay include a backside source/drain contact BCA and a backside power rail MPR connected to the backside source/drain contact BCA.

130 130 130 130 130 The backside source/drain contact BCA may be configured to be connected to one source/drain region(which may be referred to as a first source/drain region) selected from the plurality of source/drain regionsat a backside surface of the selected source/drain region(or the first source/drain region). The backside source/drain contact BCA may pass through a lower portion of the source/drain regioncorresponding thereto in a vertical direction (Z direction) from a backside of the source/drain region.

198 130 130 130 198 198 172 3 5 6 FIGS.,, and A backside metal silicide filmmay be between the backside source/drain contact BCA and the source/drain regionconnected to the backside source/drain contact BCA, from among the plurality of source/drain regions. The backside source/drain contact BCA may be connected to the source/drain regioncorresponding thereto through the backside metal silicide film. A constituent material of the backside metal silicide filmmay substantially be the same as that of the metal silicide film, which has been described above with reference to.

8 FIG.A 8 FIG.A 130 130 130 130 130 130 130 130 174 Althoughillustrates a configuration in which a source/drain contact CA is connected to a frontside surface of the source/drain regionconnected to the backside source/drain contact BCA, the inventive concept is not limited thereto. Unlike shown in, the source/drain contact CA may not be connected to the source/drain regionthat is connected to the backside source/drain contact BCA. As used herein, the backside surface and the frontside surface of the source/drain regionrefer to surfaces of the source/drain region, which are opposite to each other in the vertical direction (Z direction). The backside surface of the source/drain regionmay be a surface of the source/drain region, which faces the backside power rail MPR, and the frontside surface of the source/drain regionmay be a surface of the source/drain region, which faces an etch stop insulating film.

174 130 300 300 8 FIG.A The backside power rail MPR may be apart from the etch stop insulating filmin the vertical direction (Z direction) with the source/drain regiontherebetween. As shown in, the IC devicemay include a plurality of backside bulk insulating films BBI, which are arranged in a line in a first lateral direction (X direction) and each extend lengthwise in a second lateral direction (Y direction). A plurality of backside power rails MPR may be separated from each other by the plurality of backside bulk insulating films BBI in a plurality of backside power rails MPR in the first lateral direction (X direction). Each of the plurality of backside power rails MPR may be between two adjacent ones of the plurality of backside bulk insulating films BBI in the first lateral direction (X direction). The backside source/drain contact BCA may be integrally connected to one backside power rail MPR selected from the plurality of backside power rails MPR. In the IC device, the plurality of nanosheet stacks NSS may be apart from the plurality of backside bulk insulating films BBI in the vertical direction (Z direction).

160 Each of the plurality of backside bulk insulating films BBI may be in contact with a pair of backside power rails MPR, which are selected from the plurality of backside power rails MPR and adjacent to each other. Each of the plurality of backside bulk insulating films BBI may extend lengthwise from a space between a pair of backside power rails MPR, which are adjacent to each other, toward a selected one of the plurality of gate linesin the vertical direction (Z direction). In embodiments, each of the plurality of backside bulk insulating films BBI may include a nitrogen (N)-containing insulating film. For example, each of the plurality of backside bulk insulating films BBI may include silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or a combination thereof, without being limited thereto.

130 The backside source/drain contact BCA may extend lengthwise in the vertical direction (Z direction) between a pair of backside bulk insulating films BBI, which are adjacent to each other, from among the plurality of backside bulk insulating films BBI. From among the plurality of backside power rails MPR, the backside power rail MPR integrally connected to the backside source/drain contact BCA may be apart from the source/drain regionwith the backside source/drain contact BCA therebetween in the vertical direction (Z direction).

In embodiments, the backside source/drain contact BCA and the backside power rail MPR may be simultaneously formed using a single process, and the backside source/drain contact BCA and the backside power rail MPR may include the same material. In other embodiments, the backside source/drain contact BCA and the backside power rail MPR may be formed using separate processes, and an interface may be present between the backside source/drain contact BCA and the backside power rail MPR. In embodiments, the backside source/drain contact BCA and the backside power rail MPR may include a single metal. In other embodiments, the source/drain contact CA may include a metal plug and a conductive barrier film surrounding the metal plug. The metal plug may include molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), a combination thereof, or an alloy thereof, without being limited thereto. The conductive barrier film may include a metal or a conductive metal nitride. For example, the conductive barrier film may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, without being limited thereto.

160 160 152 The plurality of backside bulk insulating films BBI may include a pair of backside bulk insulating films BBI, which are respectively on both sides of the backside source/drain contact BCA with the backside source/drain contact BCA therebetween in the first lateral direction (X direction). Each of the pair of backside bulk insulating films BBI may overlap one gate lineselected from the plurality of gate linesin the vertical direction (Z direction) and extend lengthwise in the vertical direction (Z direction). The pair of backside bulk insulating films BBI may include portions facing the backside source/drain contact BCA in the first lateral direction (X direction). Each of the plurality of backside bulk insulating films BBI may contact a gate dielectric film.

8 FIG.A 300 130 As shown in, the IC devicemay include a plurality of semiconductor blocks SB. From among the plurality of semiconductor blocks SB, some semiconductor blocks SB may cover a sidewall of the backside source/drain contact BCA in the first lateral direction (X direction). From among the plurality of semiconductor blocks SB, some other semiconductor blocks SB may be in contact with a backside surface of the source/drain regionconnected to the source/drain contact CA. Each of the plurality of semiconductor blocks SB may include silicon (Si).

152 160 160 160 From among the plurality of semiconductor blocks SB, at least some semiconductor blocks SB may cover a sidewall of the backside bulk insulating film BBI in the first lateral direction (X direction). The plurality of semiconductor blocks SB may be in contact with the gate dielectric filmcovering a lowermost surface of the gate line. As used herein, the lowermost surface of the gate linemay refer to a surface of the gate line, which is closest to the backside power rail MPR.

8 FIG.B 160 112 130 As shown in, both sidewalls of a portion of the backside bulk insulating film BBI, which are adjacent to the gate linein the second lateral direction (Y direction), may be covered by a field insulating film. At least one of the plurality of semiconductor blocks SB may have a surface contacting the source/drain region.

8 FIG.B 112 160 152 As shown in, the field insulating filmmay have a surface facing the gate linewith the gate dielectric filmtherebetween and a surface contacting the backside bulk insulating film BBI.

8 8 FIGS.A andB 174 160 160 As shown in, the plurality of backside bulk insulating films BBI may overlap the plurality of nanosheet stacks NSS in the vertical direction (Z direction). Each of the plurality of nanosheet stacks NSS may be apart from the backside bulk insulating film BBI in the vertical direction (Z direction). The etch stop insulating filmmay be apart from the gate linethe backside bulk insulating film BBI and the backside power rail MPR with the gate linetherebetween in the vertical direction (Z direction).

300 100 8 8 FIGS.A andB 2 6 FIGS.to The IC devicedescribed with reference tomay have the same effects as those of the IC device, which have been described with reference to.

Next, a method of manufacturing an IC device, according to embodiments, is described in detail.

9 28 FIGS.A to 9 10 11 12 13 14 15 16 17 28 FIGS.A,A,A,A,A,A,A,A, andto 2 FIG. 9 10 11 12 13 14 15 16 FIGS.B,B,B,B,B,B,B, andB 2 FIG. 12 13 FIGS.C andC 2 FIG. 2 6 FIGS.to 9 28 FIGS.A to 9 28 FIGS.A to 2 6 FIGS.to 1 1 1 1 2 2 100 are cross-sectional views showing a process sequence of a method of manufacturing an IC device, according to embodiments. More specifically,are cross-sectional views showing example cross-sectional structures of a portion corresponding to a cross-section taken along line X-X′ of, according to the process sequence.are cross-sectional views showing example cross-sectional structures of a portion corresponding to a cross-section taken along line Y-Y′ of, according to the process sequence.are cross-sectional views showing example cross-sectional structures of a portion corresponding to a cross-section taken along line Y-Y′ of, according to the process sequence. An example of a method of manufacturing the IC devicedescribed with reference tois described with reference to. In, the same reference numerals are used to denote the same elements as in, and detailed descriptions thereof are omitted.

9 9 FIGS.A andB 102 102 102 104 102 102 Referring to, a substratehaving a frontside surfaceF and a backside surfaceB, which are opposite to each other, may be prepared. A plurality of sacrificial semiconductor layersand a plurality of nanosheet semiconductor layers NS may be alternately stacked one-by-one on the frontside surfaceF of the substrateto form a stack structure.

104 104 104 104 In the stack structure, the plurality of sacrificial semiconductor layersand the plurality of nanosheet semiconductor layers NS may include semiconductor materials having different etch selectivities from each other. In embodiments, the plurality of nanosheet semiconductor layers NS may include a Si layer, and the plurality of sacrificial semiconductor layersmay include a SiGe film. The SiGe film included in the sacrificial semiconductor layermay have a constant Ge content, which is selected in a range of about 5 at % to about 50 at %, for example, about 10 at % to about 40 at %. In embodiments, the plurality of sacrificial semiconductor layersmay each include a SiGe film and have the same Ge content.

10 10 FIGS.A andB 9 9 FIGS.A andB 1 1 1 102 Referring to, a mask pattern MPhaving openings exposing a top surface of the stack structure may be formed on the resultant structure of. The mask pattern MPmay have a stack structure of a silicon oxide film pattern and a silicon nitride film pattern. The mask pattern MPmay include portions extending parallel to each other in a first lateral direction (X direction) on the substrate.

104 102 1 1 102 1 1 102 104 1 A portion of each of the plurality of sacrificial semiconductor layers, the plurality of nanosheet semiconductor layers NS, and the substratemay be etched using the mask pattern MPas an etch mask, and thus, a plurality of fin-type active regions Fmay be formed on the substrate. A plurality of trenches Tmay be defined by the plurality of fin-type active regions Fon the substrate. A portion of each of the plurality of sacrificial semiconductor layersand the plurality of nanosheet semiconductor layers NS may remain on a fin top surface FF of each of the plurality of fin-type active regions F.

11 11 FIGS.A andB 10 10 FIGS.A andB 112 112 1 1 Referring to, a field insulating filmmay be formed on the resultant structure of. The field insulating filmmay be formed to fill the plurality of trenches Tand sidewalls of each of the plurality of fin-type active regions F.

112 1 1 1 112 112 104 102 112 10 10 FIGS.A andB The formation of the field insulating filmmay include forming an insulating film having such a sufficient thickness as to fill the plurality of trenches Ton the resultant structure of, planarizing the obtained resultant structure to expose a top surface of the mask pattern MP, removing the exposed mask pattern MP, and performing a recess process of removing a portion of the insulating film. Thus, the field insulating filmincluding the remaining portion of the insulating film may be formed. After the field insulating filmis formed, a stack structure including the plurality of sacrificial semiconductor layersand the plurality of nanosheet semiconductor layers NS, which remain on the substrate, may protrude over a top surface of the field insulating film, and a top surface of an uppermost one of the plurality of nanosheet semiconductor layers NS may be exposed.

12 12 12 FIGS.A,B, andC 11 11 FIGS.A andB 122 124 126 104 124 126 Referring to, a plurality of dummy gate structures DGS may be formed on the resultant structure of. Each of the plurality of dummy gate structures DGS may be formed to extend lengthwise in a second lateral direction (Y direction). Each of the plurality of dummy gate structures DGS may include a dummy oxide film D, a dummy gate layer D, and a capping layer D, which are sequentially stacked on the stack structure including the plurality of sacrificial semiconductor layersand the plurality of nanosheet semiconductor layers NS. In embodiments, the dummy gate layer Dmay include polysilicon, and the capping layer Dmay include a silicon nitride film.

12 FIG.A 118 104 1 118 1 2 3 4 1 1 1 2 3 4 1 As shown in, a plurality of insulating spacersmay be respectively formed on both sidewalls of the plurality of dummy gate structures DGS. A portion of each of the plurality of sacrificial semiconductor layersand the plurality of nanosheet semiconductor layers NS and a portion of the fin-type active region Fmay be etched by using the plurality of dummy gate structures DGS and the plurality of insulating spacersas etch masks. Thus, the plurality of nanosheet semiconductor layers NS may be divided into a plurality of nanosheet stacks NSS including the first to fourth nanosheets N, N, N, and N, and a plurality of recesses Rmay be formed in the fin-type active region F. Widths of the first to fourth nanosheets N, N, N, and Nin the first lateral direction (X direction) may be defined by the plurality of recesses R.

1 118 1 119 1 112 1 12 FIG.C The plurality of recesses Rmay be formed by using a dry etching process, a wet etching process, or a combination thereof. During the formation of the plurality of insulating spacersand the plurality of recesses R, as shown in, a plurality of side insulating spacersmay be formed adjacent to the plurality of recesses Ron the field insulating filmon both sides of each of the fin-type active region Fin the second lateral direction (Y direction).

13 13 13 FIGS.A,B, andC 12 12 12 FIGS.A,B, andC 130 1 130 1 2 3 4 1 1 Referring to, in the resultant structure of, a plurality of source/drain regionsmay be formed to fill the plurality of recesses R. To form the plurality of source/drain regions, a semiconductor material may be epitaxially grown from a sidewall of each of the first to fourth nanosheets N, N, N, and Nand a surface of the fin-type active region F, which are exposed at the plurality of recesses R.

130 In embodiments, to form the plurality of source/drain regions, a low-pressure chemical vapor deposition (LPCVD) process, a selective epitaxial growth (SEG) process, or a cyclic deposition and etching (CDE) process may be performed by using source materials including an element semiconductor precursor. The element semiconductor precursor may include an element, such as silicon (Si) and germanium (Ge).

130 130 102 4 2 6 3 8 2 2 4 2 6 3 8 4 10 2 2 2 2 6 In embodiments, the source/drain regionmay include a SiGe layer doped with boron (B). In this case, to form the plurality of source/drain regions, boron (B) ions may be doped in-situ while supplying a Si source and a Ge source onto the substrate. Silane (SiH), disilane (SiH), trisilane (SiH), and/or dichlorosilane (SiHCl) may be used as the Si source, without being limited thereto. Germane (GeH), digermane (GeH), trigermane (GeH), tetragermane (GeH), and/or dichlorogermane (GeHCl) may be used as the Ge source, without being limited thereto. Diborane (BH), triborane, tetraborane, and/or pentaborane may be used as the B source, without being limited thereto.

130 130 102 3 In other embodiments, the plurality of source/drain regionsmay include a Si layer doped with phosphorus (P). In this case, to form the plurality of source/drain regions, phosphorus (P) ions may be doped in-situ while supplying a Si source onto the substrate. The Si source may be selected from the materials described above. Phosphine (PH) gas may be used as the phosphorus (P) ion source, without being limited thereto.

142 130 144 142 142 144 126 126 124 142 144 144 124 12 12 FIGS.A andB Afterwards, an insulating linermay be formed to cover the resultant structure in which a plurality of source/drain regionsare formed, and an inter-gate dielectric filmmay be formed on the insulating liner. A portion of each of the insulating linerand the inter-gate dielectric filmmay be etched to expose top surfaces of a plurality of capping layers (refer to Din). Thereafter, the plurality of capping layers Dmay be removed to expose the dummy gate layer D, and the insulating linerand the inter-gate dielectric filmmay be partially removed such that a top surface of the inter-gate dielectric filmbecomes at substantially the same level as a top surface of the dummy gate layer D.

14 14 FIGS.A andB 13 13 13 FIGS.A,B, andC 124 122 Referring to, the dummy gate layer Dand the dummy oxide film Dmay be removed from the resultant structure ofto prepare a gate space GS.

15 15 FIGS.A andB 14 14 FIGS.A andB 104 102 1 2 3 4 1 1 Referring to, in the resultant structure of, the plurality of sacrificial semiconductor layersremaining on the substratemay be selectively removed through the gate space GS. Thus, the gate space GS may extend to respective spaces between the first to fourth nanosheets N, N, N, and Nand a space between the first nanosheet Nand the fin top surface FF of the fin-type active region F.

104 1 2 3 4 1 104 104 104 3 3 3 3 2 2 In embodiments, to selectively remove the plurality of sacrificial semiconductor layers, etch selectivities of each of the first to fourth nanosheets N, N, N, and Nand fin-type active region Fwith respect to the plurality of sacrificial semiconductor layersmay be used. A liquid or gaseous etchant may be used to selectively remove the plurality of sacrificial semiconductor layers. In embodiments, to selectively remove the plurality of sacrificial semiconductor layers, a CHCOOH-based etchant, for example, an etchant including a mixture of CHCOOH, HNO, and HF or an etchant including a mixture of CHCOOH, HO, and HF may be used, without being limited thereto.

16 16 FIGS.A andB 15 15 FIGS.A andB 152 1 2 3 4 1 152 Referring to, in the resultant structure of, a gate dielectric filmmay be formed to cover respective exposed surfaces of the first to fourth nanosheets N, N, N, and Nand the fin-type active region F. The gate dielectric filmmay be formed using an atomic layer deposition (ALD) process.

160 152 160 152 118 160 152 118 168 160 152 118 15 15 FIGS.A andB Afterwards, a gate linefilling the gate space (refer to GS in) may be formed on the gate dielectric film. Thereafter, a height of each of the gate line, the gate dielectric film, and the gate insulating spacermay be reduced by removing a portion of each of the gate line, the gate dielectric film, and the gate insulating spacerfrom a top surface of each thereof, and a plurality of capping insulating patternsmay be formed to cover the top surface of each of the gate line, the gate dielectric film, and the gate insulating spacer.

17 FIG. 16 16 FIGS.A andB 142 144 130 130 Referring to, in the resultant structure of, a portion of each of the insulating linerand the inter-gate dielectric filmmay be removed to form a plurality of source/drain contact holes CAH exposing the source/drain region. After the plurality of source/drain contact holes CAH are formed, a portion of a frontside surface of the source/drain regionexposed through the plurality of source/drain contact holes CAH may be removed.

18 FIG. 17 FIG. 3 5 6 FIGS.,, and 3 5 6 FIGS.,, and 172 130 1 172 1 1 Referring to, in the resultant structure of, a metal silicide filmmay be formed to cover the frontside surface of the source/drain regionexposed through the plurality of source/drain contact holes CAH, and a metal-containing layer MLfilling the plurality of source/drain contact holes CAH may be formed on the metal silicide film. The metal-containing layer MLmay include materials required to form a plurality of source/drain contacts (refer to CA in). For example, the formation of the metal-containing layer MLmay include first forming a conductive barrier film and forming a metal plug on the conductive barrier film. Detailed configurations of the conductive barrier film and the metal plug are the same as those of the plurality of source/drain contacts CA, which have been described with reference to.

19 FIG. 18 FIG. 1 168 1 160 152 118 Referring to, in the resultant structure of, a portion of the metal-containing layer MLand the plurality of capping insulating patternsmay be removed, and thus, the plurality of source/drain contacts CA may be formed from the metal-containing layer ML. The obtained resultant structure may be planarized to reduce a height of each of the plurality of gate linesand the plurality of source/drain contacts CA in a vertical direction (Z direction). During the planarization of the obtained resultant structure as described above, a height of each of a plurality of gate dielectric filmsand the plurality of gate insulating spacersin the vertical direction (Z direction) may also be reduced.

20 FIG. 19 FIG. 174 175 176 177 1 176 177 Referring to, an etch stop insulating film, a capping insulating film, a first hardmask film, a second hardmask film, and a first photoresist pattern PRmay be sequentially formed on a planarized top surface of the resultant structure of. In embodiments, the first hardmask filmmay include a carbon-containing film, such as a spin-on-hardmask (SOH) film, and the second hardmask filmmay include a silicon oxynitride (SiON) film, without being limited thereto.

21 FIG. 20 FIG. 177 176 1 175 174 1 177 Referring to, in the resultant structure of, the second hardmask filmand the first hardmask filmmay be sequentially etched by using the first photoresist pattern PRas an etch mask. The capping insulating filmmay be etched using the obtained etching resultant structure as an etch mask and using the etch stop insulating filmas an etch stop layer to form a plurality of via contact holes VAH. During or after the formation of the plurality of via contact holes VAH, the first photoresist pattern PRand the second hardmask filmthat remain in the resultant structure may be removed.

22 FIG. 21 FIG. 176 175 176 176 Referring to, the first hardmask filmthat remains in the resultant structure ofmay be removed to expose a top surface of the capping insulating film. When the first hardmask filmincludes an SOH film, the remaining first hardmask filmmay be removed using ashing and strip processes.

23 FIG. 22 FIG. 178 175 179 2 178 178 179 Referring to, in the resultant structure of, a third hardmask filmmay be formed to fill the plurality of via contact holes VAH and cover the top surface of the capping insulating film, and a fourth hardmask filmand a second photoresist pattern PRmay be sequentially formed on the third hardmask film. In embodiments, the third hardmask filmmay include a carbon-containing film, such as an SOH film, and the fourth hardmask filmmay include a SiON film, without being limited thereto.

24 FIG. 23 FIG. 179 178 2 175 174 2 179 Referring to, in the resultant structure of, the fourth hardmask filmand the third hardmask filmmay be sequentially etched by using the second photoresist pattern PRas an etch mask. The capping insulating filmmay be etched using the obtained etching resultant structure as an etch mask and using the etch stop insulating filmas an etch stop layer to form a plurality of gate contact holes CBH. During or after the formation of the plurality of gate contact holes CBH, the second photoresist pattern PRand the fourth hardmask filmthat remain in the resultant structure may be removed.

25 FIG. 24 FIG. 178 175 178 178 Referring to, the third hardmask filmthat remains in the resultant structure ofmay be removed to expose the top surface of the capping insulating film. When the third hardmask filmincludes an SOH film, the remaining third hardmask filmmay be removed using ashing and strip processes.

26 FIG. 174 160 Referring to, portions of the etch stop insulating film, which are exposed through the plurality of via contact holes VAH and the plurality of gate contact holes CBH, may be removed. Thus, top surfaces of the source/drain contacts CA may be respectively exposed through the plurality of via contact holes VAH, and the top surfaces of the gate linesmay be respectively exposed through the plurality of gate contact holes CBH.

27 FIG. 26 FIG. 3 6 FIGS.to 3 6 FIGS.to 3 6 FIGS.to 2 160 2 2 Referring to, in the resultant structure of, a metal-containing layer MLmay be formed to fill the plurality of via contact holes VAH and the plurality of gate contact holes CBH and contact the top surface of each of the plurality of source/drain contacts CA and the top surface of each of the plurality of gate lines. The metal-containing layer MLmay include materials required to form a plurality of gate contacts (refer to CB in) and a plurality of via contacts (refer to VA in). For example, the formation of the metal-containing layer MLmay include first forming a conductive barrier film and forming a metal plug on the conductive barrier film. Detailed configurations of the conductive barrier film and the metal plug are the same as those of the plurality of gate contacts CB and the plurality of via contacts VA, which have been described with reference to.

28 FIG. 27 FIG. 2 175 2 Referring to, in the resultant structure of, a portion of the metal-containing layer MLmay be removed to expose the top surface of the capping insulating film, and the plurality of gate contacts CB and the plurality of via contacts VA, which include the remaining portions of the metal-containing layer ML, may be formed.

3 6 FIGS.to 28 FIG. 182 184 180 1 180 180 1 Thereafter, as illustrated in, an etch stop filmand an upper insulating filmmay be sequentially formed on the resultant structure ofto form an upper insulating structure, and a plurality of upper wiring layers Mmay be formed to pass through the upper insulating structurein the vertical direction (Z direction). Afterwards, when necessary, a BEOL structure including a plurality of wirings may be formed on the upper insulating structureand the plurality of upper wiring layers M.

29 35 FIGS.to 29 35 FIGS.to 2 FIG. 2 6 FIGS.to 29 35 FIGS.to 29 35 FIGS.to 2 28 FIGS.to 1 1 100 are cross-sectional views showing a process sequence of a method of manufacturing an IC device, according to embodiments.each illustrate a cross-sectional structure of a portion corresponding to a cross-section taken along line X-X′ of, according to the process sequence. Another example of a method of manufacturing the IC deviceshown inis described with reference to. In, the same reference numerals are used to denote the same elements as in, and detailed descriptions thereof are omitted.

29 FIG. 9 21 FIGS.A to 21 FIG. 1 1 1 Referring to, the processes described with reference tomay be performed. Afterwards, a first pillar layer PLhaving such a sufficient thickness as to fill a plurality of via contact holes VAH may be formed on the resultant structure of. In embodiments, the first pillar layer PLmay include a silicon oxide film, without being limited thereto. The first pillar layer PLmay be formed using an ALD process.

30 FIG. 29 FIG. 29 FIG. 1 1 1 1 176 176 175 1 176 176 Referring to, in the resultant structure of, a portion of the first pillar layer PLmay be etched back from a top surface of the first pillar layer PL, and thus, a plurality of first pillars PPmay be formed from the first pillar layer PLand a first hardmask film (refer toin) may be exposed. Thereafter, the remaining first hardmask filmmay be removed to expose a top surface of the capping insulating filmaround each of the plurality of first pillars PP. When the first hardmask filmincludes an SOH film, the first hardmask filmmay be removed using ashing and strip processes.

31 FIG. 30 FIG. 278 1 1 279 22 178 278 279 Referring to, in the resultant structure of, a third hardmask filmmay be formed to fill respective spaces between the plurality of first pillars PPand cover a top surface of each of the plurality of first pillars PP, and a fourth hardmask filmand a second photoresist pattern PRmay be sequentially formed on the third hardmask film. In embodiments, the third hardmask filmmay include a carbon-containing film, such as an SOH film, and the fourth hardmask filmmay include a SiON film, without being limited thereto.

32 FIG. 31 FIG. 279 278 22 175 174 22 279 Referring to, in the resultant structure of, the fourth hardmask filmand the third hardmask filmmay be sequentially etched by using the second photoresist pattern PRas an etch mask. The capping insulating filmmay be etched using the obtained etching resultant structure as an etch mask and using the etch stop insulating filmas an etch stop layer to form a plurality of gate contact holes CBH. During or after the formation of the plurality of gate contact holes CBH, the second photoresist pattern PRand the fourth hardmask filmthat remain in the resultant structure may be removed.

33 FIG. 32 FIG. 2 2 2 Referring to, a second pillar layer PLhaving such a sufficient thickness as to fill the plurality of contact holes CBH may be formed on the resultant structure of. In embodiments, the second pillar layer PLmay include a silicon oxide film, without being limited thereto. The second pillar layer PLmay be formed using an ALD process.

34 FIG. 33 FIG. 33 FIG. 2 2 2 2 278 278 175 1 2 278 278 Referring to, in the resultant structure of, a portion of the second pillar layer PLmay be etched back from a top surface of the second pillar layer PL, and thus, a plurality of second pillars PRmay be formed from the second pillar layer PLand the third hardmask film (refer toin) may be exposed. Thereafter, the remaining third hardmask filmmay be removed to expose the top surface of the capping insulating filmaround each of the plurality of first pillars PPand the plurality of second pillars PR. When the third hardmask filmincludes an SOH film, the third hardmask filmmay be removed using ashing and strip processes.

35 FIG. 34 FIG. 1 2 174 Referring to, in the resultant structure of, the plurality of first pillars PPand the plurality of second pillars PRmay be removed such that the inside of each of the plurality of gate contact holes CBH and the plurality of via contact holes VAH is emptied and the etch stop insulating filmis exposed at the bottom of each of the plurality of gate contact holes CBH and the plurality of via contact holes VAH.

26 28 FIGS.to 2 6 FIGS.to 100 Afterwards, the processes described with reference tomay be performed, and thus, the IC deviceshown inmay be manufactured.

36 42 FIGS.A to 36 37 38 39 42 FIGS.A,A,A, andto 2 FIG. 36 37 38 FIGS.B,B, andB 2 FIG. 8 8 FIGS.A andB 36 42 FIGS.A to 36 42 FIGS.A to 2 35 FIGS.to 1 1 1 1 300 are cross-sectional views showing a process sequence of a method of manufacturing an IC device, according to embodiments. More specifically,are cross-sectional views showing example cross-sectional structures of a portion corresponding to a cross-section taken along line X-X′ of, according to the process sequence.are cross-sectional views showing example cross-sectional structures of a portion corresponding to a cross-section taken along line Y-Y′ of, according to the process sequence. An example of a method of manufacturing the IC devicedescribed with reference tois described with reference to. In, the same reference numerals are used to denote the same elements as in, and detailed descriptions thereof are omitted.

36 36 FIGS.A andB 3 6 FIGS.to 102 102 102 1 112 1 112 1 112 Referring to, in the resultant structure described with reference to, the substratemay be removed from the backside surfaceB of the substrateto expose the plurality of fin-type active regions Fand the field insulating film. A portion of each of the plurality of fin-type active regions Fand the field insulating filmthat are exposed may be further removed to reduce a thickness of each of the plurality of fin-type active regions Fand the field insulating filmin a vertical direction (Z direction).

102 1 112 In embodiments, the process of removing the substrateand the process of removing the portion of each of the plurality of fin-type active regions Fand the field insulating filmmay be performed using at least one process selected from a mechanical grinding process, a chemical mechanical polishing (CMP) process, a wet etching process, and a combination thereof.

37 37 FIGS.A andB 36 36 FIGS.A andB 1 1 112 1 1 1 112 1 1 1 Referring to, in the resultant structure of, a first backside mask pattern BMPmay be formed on the backside surface at which the plurality of fin-type active regions Fand the field insulating filmare exposed. The first backside mask pattern BMPmay have a plurality of line-shaped openings BH, which extend lengthwise in a second lateral direction (Y direction). A portion of each of the plurality of fin-type active regions Fand the field insulating filmmay be exposed through the plurality of line-shaped openings BHof the first backside mask pattern BMP. In embodiments, the first backside mask pattern BMPmay include an SOH material, without being limited thereto.

38 38 FIGS.A andB 37 37 FIGS.A andB 1 1 152 1 Referring to, in the resultant structure of, the plurality of fin-type active regions Fmay be selectively etched using the first backside mask pattern BMPas an etch mask, and thus, a plurality of vertical holes SH may be formed to expose the gate dielectric film. When the plurality of vertical holes SH are formed, each of the plurality of fin-type active regions Fmay be divided into a plurality of semiconductor blocks SB.

1 1 Thereafter, a plurality of backside bulk insulating films BBmay be formed to fill the plurality of vertical holes SH and the plurality of line-shaped openings BH. In embodiments, the plurality of backside bulk insulating films BBI may be formed using an ALD process or a chemical vapor deposition (CVD) process, without being limited thereto.

39 FIG. 38 38 FIGS.A andB 1 1 1 Referring to, the first backside mask pattern BMPmay be removed from the resultant structure of. When the first backside mask pattern BMPincludes an SOH material, the first backside mask pattern BMPmay be removed using ashing and strip processes.

40 FIG. 39 FIG. 2 2 130 130 130 Referring to, the resultant structure of the process described with reference tomay be coated with an SOH material to form a planarized hardmask film. The hardmask film may be planarized to form a second backside mask pattern BMPhaving a hole exposing the semiconductor block SB. Afterwards, the semiconductor block SB may be etched by using the second backside mask pattern BMPas an etch mask to form a via hole VH exposing a backside surface of the source/drain region. A portion of the source/drain regionmay be etched during the formation of the via hole VH, and thus, the via hole VH may extend into the source/drain region.

41 FIG. 40 FIG. 2 2 2 Referring to, the second backside mask pattern BMPmay be removed from the resultant structure of. When the second backside mask pattern BMPincludes an SOH material, the second backside mask pattern BMPmay be removed using ashing and strip processes.

42 FIG. 41 FIG. 8 FIG.A 8 8 FIGS.A andB 300 Referring to, in the resultant structure of, respective spaces between the via holes VH and the backside bulk insulating films BBI may be filled by a conductive material to form the backside source/drain contact BCA and the backside power rail MPR, which are shown in. Thus, the IC deviceshown inmay be manufactured.

100 300 200 100 200 300 2 6 FIGS.to 8 8 FIGS.A andB 9 42 FIGS.A to 7 FIG. 2 8 FIGS.toB 9 42 FIGS.A to Although the IC deviceshown inand the methods of manufacturing the IC deviceshown inhave been described with reference to, it will be understood that the IC deviceshown inand variously modified ones of the IC devices,, andshown inmay be manufactured by applying various modifications and changes to the processes described with reference towithin the scope of the inventive concept.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.