Semiconductor Devices and Methods of Manufacturing the Same

The present disclosure relates to semiconductor devices and methods of manufacturing the same.

A semiconductor device may include a plurality of vertically stacked metal structures and vias to electrically connect the metal structures.

Meanwhile, as a semiconductor device is highly integrated, more devices are needed to be formed per unit area, and thus a gap between adjacent conductive patterns in a horizontal direction may become narrow. As a result, a via connected to a conductive pattern may unintentionally come into contact to adjacent conductive pattern, and thus a short circuit may occur.

Some embodiments of the inventive concept provide methods of manufacturing semiconductor devices capable of reducing or preventing electrical contact between a via, which is connected to a conductive pattern, and an adjacent conductive pattern, which is adjacent to the conductive pattern.

Some embodiments of the inventive concept provide semiconductor devices manufactured by the methods.

A method of manufacturing a semiconductor device may comprise: forming a first layer in which first conductive patterns and first dielectric patterns are alternately arranged; forming passivation layers on the first conductive patterns, respectively; and forming second dielectric patterns on the first dielectric patterns, respectively, by an area-selective atomic layer deposition at a first temperature, wherein the first temperature may be 350° C. or less, wherein the area-selective atomic layer deposition may include: pulsing a metal catalyst; performing a primary purge by a purge gas; sub-pulsing a reaction precursor at least once; and performing a secondary purge by the purge gas after each of the sub-pulsing.

The purge gas may be continuously supplied with a constant flow rate and a constant pressure during the area-selective atomic layer deposition.

The constant pressure of the purge gas may be 1 Torr or less.

The area-selective atomic layer deposition may further include pumping the purge gas between the sub-pulsing the reaction precursor and the secondary purge.

The purge gas of the performing the primary purge may have a first flow rate and a first pressure, the purge gas of the pumping the purge gas may have a second flow rate and a second pressure, and the purge gas of the performing the second purge may have a third flow rate and a third pressure.

The first flow rate may be greater than the second flow rate, the third flow rate may be greater than the second flow rate, the first pressure may be greater than the second pressure, and the third pressure may be greater than the second pressure.

The second flow rate may be zero (0) standard cubic centimeters per minute (sccm), and the second pressure may be 0.1 Torr or less.

The first temperature may be 150° C. to 350° C.

The metal catalyst may include trimethylaluminum, triethylaluminum, dimethylaluminum iso-propoxide, and/or a combination thereof.

The reaction precursor may be a silanol precursor, and the second dielectric patterns may include silicon oxide.

The silanol precursor may include tris(t-pentoxy)silanol, bis(t-pentoxy)(t-butoxy)silanol, and/or a combination thereof.

The forming the passivation layers may include supplying a self-assembled molecule that includes a thiol group material, an amine group material, and/or a carboxylic group material.

The supplying the self-assembled molecule may be performed at a second temperature of 100° C. to 350° C.

The forming the passivation layers may further include performing additional purge after the supplying the self-assembled molecule.

The method may further include repeating the area-selective atomic layer deposition until the second dielectric patterns reach to a desired thickness, and performing a tertiary purge before the repeating the area-selective atomic layer deposition.

The second dielectric patterns may include a dielectric material that has a dielectric constant of 2.5 to 6.0.

−7 2 The second dielectric patterns may include a dielectric material that has a leakage current of 3×10A/cmor less at 5 MV/cm.

The first dielectric patterns and the second dielectric patterns each may include silicon oxide.

The method may further include forming vias electrically connected to the first conductive patterns, and forming second conductive patterns electrically connected to the first conductive patterns through the vias.

−7 2 According to some embodiments, a semiconductor device may include a first layer including first conductive patterns and first dielectric patterns; second dielectric patterns on the first dielectric patterns, wherein the second dielectric patterns may have same planar shapes as the first dielectric patterns, respectively, and may include a dielectric material that has a dielectric constant of 2.5 to 6.0 and a leakage current of 3×10A/cmor less at 5 MV/cm; a second layer electrically connected to the first conductive patterns, wherein the second layer may include vias that are in contact with the second dielectric patterns; and a third layer including second conductive patterns that are electrically connected to the first conductive patterns through the vias, wherein the semiconductor device may be manufactured by a method comprising: forming the first layer in which the first conductive patterns and the first dielectric patterns are alternately arranged; forming passivation layers on the first conductive patterns, respectively; and forming the second dielectric patterns on the first dielectric patterns, respectively, by an area-selective atomic layer deposition at a first temperature, wherein the first temperature may be 350° C. or less, and wherein the area-selective atomic layer deposition may include: pulsing a metal catalyst; performing a primary purge by a purge gas; sub-pulsing a reaction precursor at least once; and performing a secondary purge by the purge gas after each of the sub-pulsing.

By selectively forming dielectric patterns with good film quality at a relatively low temperature, (unintended) electrical contact between a via connected to one conductive pattern and adjacent conductive pattern may be reduced or prevented without deterioration of electrical characteristics.

The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the disclosure are shown.

As those skilled in the art would realize, the described embodiments may be modified in various ways, all without departing from the scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Uke reference numerals designate like elements throughout the specification unless clearly indicated otherwise.

In the flowchart described with reference to the drawings, an order of operations may be changed, various operations may be merged, a certain operation may be divided, and a certain operation may not be performed (e.g., may be omitted).

In addition, a singular form may be intended to include a plural form as well, unless the explicit expression such as “one” or “single” is used. Terms including ordinal numbers such as first, second, and the like will be used only to describe various constituent elements, and are not to be interpreted as limiting these constituent elements. These terms may be used for a purpose of distinguishing one constituent element from other constituent elements. Hereinafter, a semiconductor device according to some embodiments is described.

1 FIG. 2 FIG. 1 FIG. 100 130 100 is a schematic diagram of a semiconductor deviceaccording to some embodiments, andis a cross-sectional view showing some embodiments of a metal connection portionof the semiconductor deviceof.

100 100 110 120 110 130 120 The semiconductor device, according to some embodiments, may be an integrated circuit device, including, for example, a memory semiconductor and/or a logic semiconductor. The semiconductor devicemay include a substrate, such as a silicon wafer, a logic circuit portion(on the substrate), and the metal connection portion(on the logic circuit portion). As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

120 The logic circuit portionmay include logic circuit elements such as a transistor, a capacitor, and/or a resistor, and may be formed by a front end of line (FEOL) process and/or middle end of line (MEOL) process.

130 131 135 120 132 133 134 130 110 110 The metal connection portionmay include conductive patterns (e.g., first conductive patternsand/or second conductive patterns) (electrically) connected to a logic circuit element of the logic circuit portion, a dielectric (e.g., first dielectric patternsand/or second dielectric patterns) that (electrically) separates the conductive patterns in a vertical and/or a horizontal direction (e.g., a first horizontal direction and/or a second horizontal direction), and vias (e.g., vias) for (electrically) connecting the conductive patterns in the vertical direction. The metal connection portionmay be formed by back end of line (BEOL) process. The first horizontal direction and a second horizontal direction may be parallel with an upper surface and/or a lower surface of the substrate, and the vertical direction may be perpendicular to the upper surface and/or the lower surface of the substrate. The first horizontal direction and the second horizontal direction may intersect each other. For example, the first horizontal direction and the second horizontal direction may be perpendicular to each other. It will be understood that when an element or layer is referred to as being “connected to”, or “coupled to”, another element or layer, it may be directly on, connected to, or coupled to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element is referred to as being “directly coupled,” “directly connected,” or “directly responsive” to, or “directly on,” another element, there are no intervening elements present. In addition, “electrical connection” conceptually includes a physical connection and a physical disconnection.

2 FIG. 130 1 2 3 1 2 3 130 Referring to, the metal connection portionmay include a first layer L, a second layer L, and a third layer Lstacked in the vertical direction. In the drawing, for convenience of explanation, a structure including the first layer L, the second layer L, and the third layer Lis illustrated, but the metal connection portionmay include more layers stacked in two or three dimensions.

1 131 132 1 131 131 The first layer Lmay include first conductive patternsand first dielectric patternsarranged alternately (in the first horizontal direction). The first layer Lmay be an interlayer dielectric layer, and the first conductive patternsmay be (embedded) in the interlayer dielectric layer. The first conductive patternsmay be formed by a damascene process, but is not limited thereto.

131 131 131 The first conductive patternsmay include metal or metal alloy, for example, copper (e.g., Cu), titanium (e.g., Ti), tantalum (e.g., Ta), aluminum (e.g., Al), tungsten (e.g., W), cobalt (e.g., Co), molybdenum (e.g., Mo), ruthenium (e.g., Ru), an alloy thereof, and/or combinations thereof, but is not limited thereto. The width of at least one of the first conductive patterns(in the first horizontal direction) may be, for example, (about) 30 nm or less. For example, the width of at least one of the first conductive patternsin the first horizontal direction may be (about) 1 nm to 30 nm, (about) 1 nm to 25 nm, (about) 1 nm to 20 nm, (about) 1 nm to 15 nm, (about) 1 nm to 10 nm, (about) 1 nm to 7 nm, or (about) 1 nm to 5 nm.

132 131 1 132 131 131 131 132 132 132 The first dielectric patternsmay be the remaining portions excluding the first conductive patternsof the interlayer dielectric layer of the first layer L. For example, one of the first dielectric patternsmay be positioned between adjacent first conductive patternsamong the first conductive patternsto (electrically) separate the adjacent first conductive patternsfrom each other. The first dielectric patternsmay include, for example, a dielectric material having a dielectric constant of (about) 2.5 to (about) 6.0. For example, the first dielectric patternsmay include a dielectric material having a dielectric constant of (about) 2.5 to (about) 5.0, (about) 2.7 to (about) 5.0, or (about) 3.0 to (about) 5.0. The first dielectric patternsmay include, for example, a silicon oxide.

133 132 133 132 132 133 132 133 133 132 133 132 134 2 131 131 134 134 131 The second dielectric patternsmay be selectively formed on the first dielectric patterns. The planar shape of each of the second dielectric patternsmay be (substantially) the same as the planar shape of each of the first dielectric patterns, and each of them may be linear extending in one direction. For example, the first dielectric patternsand the second dielectric patternsmay be aligned in the vertical direction, respectively. For example, the first dielectric patternsand the second dielectric patternsmay extend in the second horizontal direction. Each of the second dielectric patternsmay be selectively formed on each of the first dielectric patternsby, for example, an area-selective atomic layer deposition process, as described later, without a patterning process. The second dielectric patternsmay be positioned on the first dielectric patterns, and thus one of the viasof the second layer L, which will be described later, may be prevented from being short-circuited by contacting an adjacent first conductive patternother than the first conductive patternto which the one of the viasis electrically connected. For example, one of the viasmay be in contact (e.g., may overlap in the vertical direction) with only one of the first conductive patterns. As used herein, “an element A overlapping an element B in a direction X” (or similar language) means that there is at least one line that extends in the direction X and intersects both the elements A and B.

133 132 133 133 133 −7 2 −12 2 −7 2 The second dielectric patternsmay include a dielectric material that is the same as or different from that included in the first dielectric patterns, for example, the dielectric material included in the second dielectric patternsmay have or exhibit a dielectric constant of (about) 2.5 to (about) 6.0 and a leakage current of (about) 3×10A/cmor less at 5 MV/cm. For example, the dielectric material included in the second dielectric patternsmay have a dielectric constant of (about) 2.5 to (about) 5.0, (about) 2.7 to (about) 5.0, or (about) 3.0 to (about) 5.0 and a leakage current of (about) 1×10A/cmto (about) 3×10A/cmat 5 MV/cm. The second dielectric patternmay include, for example, a silicon oxide.

2 134 131 134 131 135 3 134 131 134 133 The second layer Lmay be an interlayer dielectric layer and may include vias(electrically) connected to the first conductive patterns, respectively. Each of the viasmay (electrically) connect one of the first conductive patternsand one of the second conductive patternsof the third layer L. A width of the via(in the first horizontal direction) may be equal to or wider than that of the first conductive pattern, and for example, the viamay be in contact with a side surface and an upper surface of the second dielectric pattern.

3 135 135 131 134 135 131 135 The third layer Lmay include the second conductive patterns, and the second conductive patternsmay be electrically connected to the first conductive patternsthrough vias. The second conductive patternsmay include the same metal as or different metal from the metal included in the first conductive patterns. For example, the second conductive patternsmay include Cu, Ti, Ta, Al, W, Co, Mo, Ru, an alloy thereof, and/or a combination thereof, but is not limited thereto.

130 2 FIG. Hereinafter, some embodiments of a method of manufacturing the metal connection portionshown inwill be described.

3 8 FIGS.to 2 FIG. 130 are cross-sectional views showing some embodiments of a method of manufacturing the metal connection portionof.

3 FIG. 131 132 1 Referring to, the first conductive patternsand the first dielectric patternsmay be alternately arranged (in the first horizontal direction) to form the first layer L.

1 131 1 131 132 To form the first layer L, an interlayer dielectric layer may be first deposited and photoetched to remove a predetermined area. The predetermined area may be an area where (at least one of) the first conductive patternswill be positioned, and may be, for example, linearly extending in one direction (e.g., in the second horizontal direction). Next, a metal or a metal alloy may be deposited on (in) the removed area to form a conductive layer (e.g., a metal layer), and the interlayer dielectric layer and the conductive layer may be planarized using, for example, chemical mechanical polishing (CMP). Accordingly, the first layer Lhaving a cross section in which the first conductive patternsand the first dielectric patternsare alternately arranged may be formed.

4 FIG. 131 1 131 131 1 131 131 1 131 131 1 131 133 132 133 Referring to, a passivation layer-may be selectively formed on (at least one of) the first conductive patterns. For example, the passivation layer-may overlap with one of the first conductive patternsin the vertical direction. Each of the passivation layers-may be on one of the first conductive patterns, respectively. The passivation layer-may be a blocking layer to shield the surfaces (e.g., upper surfaces) of the first conductive patternsso that the metal catalyst for the second dielectric patternsis selectively formed only on the first dielectric patternsin the forming the second dielectric patterns, which will be described later and may provide an inactive area during the area-selective atomic layer deposition, which will be described later.

131 1 131 133 The passivation layer-may be, for example, a self-assembled monolayer (SAM). The self-assembled monolayer may include a mono-molecule with different surface properties, for example, including a hydrophilic functional group on one end and a hydrophobic portion on the other end. Accordingly, the hydrophilic functional group may be selectively self-assembled on the surfaces (e.g., the upper surfaces) of the first conductive patterns, and the hydrophobic portion may serve to block the adsorption of the metal catalyst in the forming the second dielectric patterns, which will be described later. For example, the self-assembled monolayer may be formed using a self-assembled mono-molecule selected from C3 to C30 hydrocarbon compounds including a thiol group, an amine group, and/or a carboxyl group, such as 1-dodecanethiol (DDT), 1-tetradecanethiol (TDT), and/or a combination thereof, but is not limited thereto.

The forming the self-assembled monolayer may include, for example, providing the self-assembled mono-molecule in a vapor state at a temperature of (about) 100 to 350° C. for (about) 1 to 20 minutes, and may further include an additional purge. The additional purge may use inert gas supplied at a predetermined flow rate, for example, nitrogen gas, argon gas, and/or a combination thereof may be supplied for (about) 30 to 300 seconds.

5 FIG. 133 132 133 132 133 131 1 131 1 Referring to, the second dielectric patternsmay be selectively formed on the first dielectric patterns. Each of the second dielectric patternsmay be on one of the first dielectric patterns, respectively. The second dielectric patternsmay include, for example, an oxide film formed by an area-selective atomic layer deposition. The area-selective atomic layer deposition may selectively form a film or a layer with several to tens of nanometers thick in a specific area without a patterning process, for example, an oxide film may be selectively formed only in areas excluding the inactive area covered with the passivation layer-. The area-selective atomic layer deposition may not require plasma, unlike plasma enhanced chemical vapor deposition (PECVD), so it may effectively reduce or prevent damage to the underlying film including the self-assembled monolayer described above (e.g., the passivation layer-).

The area-selective atomic layer deposition may use a metal catalyst and a reaction precursor.

131 1 132 131 1 The metal catalyst may provide high selectivity to the surface of the passivation layer-, which is the self-assembled monolayer described above, and accordingly, the metal catalyst may induce that the reaction precursor is selectively adsorbed on the surface of the first dielectric patternson which the passivation layer-is not formed. The metal catalyst may be, for example, an aluminum catalyst, and/or may include, for example, trimethylaluminum (TMA), triethylaluminum (TEA), dimethylaluminum iso-propoxide (DMAI), and/or a combination thereof, but is not limited thereto.

The reaction precursor may react with the metal catalyst (e.g., by a condensation reaction) to form an oxide film. The reaction precursor may be, for example, a silanol precursor, such as tris(t-pentoxy)silanol (TTPS), bis(t-pentoxy)(t-butoxy)silanol (BTPTBS), and/or a combination thereof, but is not limited thereto.

In this way, the oxide film formed by the area-selective atomic layer deposition using the metal catalyst and the reaction precursor may have an advantage capable of being selectively formed in a specific area without a patterning process. On the other hand, the film properties and electrical properties of the oxide film formed by the area-selective atomic layer deposition using the metal catalyst and the reaction precursor may be strongly temperature-dependent, so in order to obtain desired (good) film properties and electrical properties, the area-selective atomic layer deposition may be performed at a relatively high temperature of higher than 350° C. and/or may need a post-deposition annealing at a temperature of (about) 400° C. or higher.

133 According to embodiments of the inventive concept, the detailed process of the area-selective atomic layer deposition may be effectively controlled to obtain the second dielectric patternswith desired (good) film properties and electrical properties without a high-temperature deposition process or an additional post-deposition annealing. For example, the area-selective atomic layer deposition may be performed at a temperature of (about) 350° C. or less (lower). For example, the area-selective atomic layer deposition may be performed at a temperature of (about) 300° C. or less (lower), (about) 250° C. or less (lower), (about) 100° C. to 350° C., (about) 100° C. to 300° C., (about) 100° C. to 250° C., or (about) 150° C. to 250° C., and the temperature may be maintained throughout the area-selective atomic layer deposition process.

132 133 Specifically, the area-selective atomic layer deposition may include pulsing (pulse feeding or pulse supply of) the metal catalyst on the surface of the first dielectric patterns, performing a primary purge, sub-pulsing (sub-pulse feeding or sub-pulse supply of) the reaction precursor for the second dielectric patternsonce or multiple times, and performing a secondary purge after each of the sub-pulsing.

9 FIG. As an example embodiment, referring to, the area-selective atomic layer deposition may be performed by a continuous flow process. The continuous flow process may provide a purge gas with a constant flow rate and a constant pressure.

For example, first, the metal catalyst (e.g., aluminum catalyst) may be pulsed (A) (may be supplied by the pulse feeding) while a purge gas is supplied with a first flow rate and a first pressure.

Next, the primary purge may be performed while the purge gas is supplied with the first flow rate and the first pressure (maintain the first flow rate and the first pressure). The purge gas may be, for example, an inert gas such as nitrogen gas, argon gas, and/or a combination thereof.

Next, the reaction precursor (e.g., silanol) may be sub-pulsed once (B1) or several times (B1, B2, and B3) (may be supplied by the sub-pulse feeding once or several times). The reaction precursor may be prepared by heating to (about) 50° C. or higher, within the above range (e.g., lower than 350° C.). For example, the reaction precursor may be prepared by heating to (about) 50 to 120° C. or (about) 70 to 100° C. The sub-pulse feeding of the reaction precursor may be performed 1 to 20 times, but is not limited thereto. The sub-pulse feeding of the reaction precursor may be performed while the purge gas is supplied with the first flow rate and the first pressure (maintain the first flow rate and the first pressure).

After each sub-pulse feeding, the secondary purge may be performed while the purge gas is supplied with the first flow rate and the first pressure (maintain the first flow rate and the first pressure).

10 FIG. As another example embodiment, referring to, the area-selective atomic layer deposition may be performed by a pump-purge process. The pump-purge process may include supplying the purge gas, reducing the purge gas supply for a predetermined period of time, and increasing the purge gas supply again. For example, the purge gas supply may be reduced to 0 standard cubic centimeters per minute (sccm) for the predetermined period of time (e.g., gradually reducing it until the lowest pressure and/or the lowest flow rate is reached) and increased again to a certain flow rate and/or a certain pressure, which may be, for example, the initial flow rate and/or the initial pressure, respectively, before the reduction of the purge gas supply. The purge gas may be provided with a variable flow rate and a variable pressure.

For example, first, the metal catalyst (e.g., aluminum catalyst) may be pulsed (A) (may be supplied by the pulse feeding). The pressure of the purge gas supply may vary before and/or after pulsing the metal catalyst.

Next, the primary purge may be performed while the purge gas is supplied. The purge gas may be an inert gas such as nitrogen gas, argon gas, and/or a combination thereof. The primary purge may supply the purge gas for (about) 5 to 30 seconds with a pressure of (about) 1 Torr or less. For example, the pressure of the purge gas supply during the primary purge may be (about) 0.01 Torr to 1 Torr or (about) 0.1 Torr to 0.8 Torr.

Next, the reaction precursor (e.g., silanol) may be sub-pulsed once (B1) or multiple times (B1, B2, and B3) (may be supplied by the sub-pulse feeding once or multiple times). The reaction precursor may be prepared by heating to (about) 50° C. or higher, within the above range (e.g., lower than 350° C.). For example, the reaction precursor may be prepared by heating to (about) 50 to 120° C. or (about) 70 to 100° C. The sub-pulse feeding of the reaction precursor may be performed 1 to 20 times, but is not limited thereto.

After each sub-pulse, pumping and a secondary purge may be performed. For example, the pumping may be performed between each sub-pulse and the secondary purge.

The pumping may cease supplying the purge gas (flow rate: 0 sccm) or supply the purge gas with a reduced flow rate than the flow rate of the purge gas in the primary purge until the purge gas pressure reaches a low pressure of less than (about) 0.1 Torr.

In some embodiments, the secondary purge may be performed while supplying the purge gas with the same flow rate and the same pressure as the primary purge, and may be performed for (about) 2 to 30 seconds.

133 133 The above-described pulsing the metal catalyst, the primary purge, and the sub-pulsing the reaction precursor for the second dielectric patterns(including the secondary purge) may form one cycle, and this cycle may be repeated one or more times, for example, until the second dielectric patternswith a desired thickness are formed. For example, the above-described cycle may be repeated for 2 to 10 cycles, and a tertiary purge may be further included before of the repeating (before each cycle). The tertiary purge may, for example, supply a purge gas for (about) 5 to 30 seconds with a pressure of (about) 1 Torr or less, but is not limited thereto.

133 In this way, the area-selective atomic layer deposition may add the performing the purges between the pulsing of the metal catalyst and the sub-pulsing of the reaction precursor and/or between the sub-pulses of the reaction precursor in a continuous flow process or a pump-purge process, and in the performing the purges, by effectively controlling various factors such as flow rate, pressure, and/or time, the quality of the oxide film formed therefrom may be effectively controlled. It may be expected that this is due to the fact that trapped water (e.g., by-products from a condensation reaction of the metal catalyst and the reaction precursor) and organic reaction by-products inevitably generated during the process are effectively reduced or removed by the above process (the performing the purges). Therefore, the electrical characteristics of the second dielectric patternsmay be improved without a high temperature process or an additional post-deposition annealing.

133 −7 2 For example, the second dielectric patternsmay include a silicon oxide formed according to the above-described process using silanol precursor as a reaction precursor, so that the obtained silicon oxide may satisfy a dielectric constant of (about) 2.5 to (about) 6.0, a leakage current of (about) 3×10A/cmor less at 5 MV/cm, and a breakdown field of (about) 8 to 11 MV/cm without a high temperature process of (about) higher than 350° C. or an additional post-deposition annealing.

131 1 Subsequently, the passivation layer-may be removed.

6 FIG. 7 FIG. 8 FIG. 2 FIG. 140 131 133 140 131 134 135 140 134 Referring to, an interlayer dielectric layermay be formed on the first conductive patternsand the second dielectric patterns. Next, referring to, the interlayer dielectric layermay be photoetched to form via holes 141 and expose the first conductive patterns. Next, referring to, the via holes 141 may be (at least partially) filled with a conductor (e.g., conductive material) to form the vias. Next, referring to, the second conductive patternsmay be formed on the interlayer dielectric layerand the vias.

Hereinafter, the embodiments are illustrated in more detail with reference to examples. However, these examples are not restrictive, and the scope of claims is not limited thereto.

2 Tris(t-pentoxy)silanol (TTPS) precursor is heated to 95° C., and trimethylaluminum (TMA) catalyst is unheated at room temperature of (about) 24° C. Atomic layer deposition (ALD) (the area-selective atomic layer deposition) of silicon oxide film is carried out at 200° C. in a 200 mm-diameter cross-flow reactor using the continuous flow process, wherein Npurge gas is supplied with 0.17 Torr pressure and 20 sccm flow rate. For each cycle of the ALD, TMA catalyst is pulsed for 0.015 second, purged for 15 seconds, followed by 10 sub-pulses of TTPS precursor delivered by vapor draw for 2 seconds per sub-pulse followed by a 5 second purge after each sub-pulse, and finally purged for another 10 seconds before the next cycle. This process is repeated for a total of 6 cycles until (about) 250 Å of silicon oxide film is deposited on a 45 mm×45 mm silicon substrate with native oxide.

2 TTPS precursor is heated to 95° C. and TMA catalyst is unheated at room temperature of (about) 24° C. ALD of silicon oxide film is carried out at 175° C. in a 200 mm-diameter cross flow reactor using the continuous flow process, wherein Npurge gas is supplied with 0.17 Torr pressure and 20 sccm flow rate. For each cycle of ALD, TMA catalyst is pulsed for 0.015 second, purged for 15 seconds, followed by 10 sub-pulses of TTPS precursor delivered by vapor draw for 2 seconds per sub-pulse followed by a 10 second purge after each sub-pulse, and finally purged for another 10 seconds before the next cycle. This process is repeated for a total of 4 cycles until (about) 300 Å of silicon oxide film is deposited on a 45 mm×45 mm silicon substrate with native oxide.

2 TTPS precursor is heated to 90° C. and TMA catalyst is unheated at room temperature of (about) 24° C. ALD of silicon oxide film is carried out at 175° C. in a 200 mm-diameter cross flow reactor using the continuous flow process, wherein Npurge gas is supplied with 0.11 Torr pressure and 10 sccm flow rate. For each cycle of ALD, TMA catalyst is pulsed for 0.015 second, purged for 15 seconds, followed by 15 sub-pulses of TTPS precursor delivered by vapor draw for 2 seconds per sub-pulse followed by a 10 second purge after each sub-pulse, and finally purged for another 10 seconds before the next cycle. This process is repeated for a total of 4 cycles until (about) 260 Å of silicon oxide film is deposited on a 45 mm×45 mm silicon substrate with native oxide.

2 TTPS precursor is heated to 95° C. and TMA catalyst is unheated at room temperature of (about) 24° C. ALD of silicon oxide film is carried out at 150° C. in a 200 mm-diameter cross flow reactor using the continuous flow process, wherein Npurge gas is supplied with 0.17 Torr pressure and 20 sccm flow rate. For each cycle of ALD, TMA catalyst is pulsed for 0.015 second, purged for 15 seconds, followed by 10 sub-pulses of TTPS precursor delivered by vapor draw for 2 seconds per sub-pulse followed by a 15 second purge after each sub-pulse, and finally purged for another 10 seconds before the next cycle. This process is repeated for a total of 3 cycles until (about) 325 Å of silicon oxide film is deposited on a 45 mm×45 mm silicon substrate with native oxide.

2 TTPS precursor is heated to 90° C. and TMA catalyst is unheated at room temperature of (about) 24° C. ALD of silicon oxide film is carried out at 150° C. in a 200 mm-diameter cross flow reactor using the continuous flow process, wherein Npurge gas is supplied with 0.11 Torr pressure and 10 sccm flow rate. For each cycle of ALD, TMA catalyst is pulsed for 0.015 second, purged for 15 seconds, followed by 15 sub-pulses of TTPS precursor delivered by vapor draw for 2 seconds per sub-pulse followed by a 15 second purge after each sub-pulse, and finally purged for another 10 seconds before the next cycle. This process is repeated for a total of 4 cycles until (about) 265 Å of silicon oxide film is deposited on a 45 mm×45 mm silicon substrate with native oxide.

2 2 2 2 TTPS precursor is heated to 88° C. and TMA catalyst is unheated at room temperature of (about) 24° C. ALD of silicon oxide film is carried out at 150° C. in a 200 mm-diameter cross flow reactor using the pump-purge process. For each cycle of ALD, TMA catalyst is pulsed for 0.015 second and purged for 15 seconds while Npurge gas is supplied with 0.11 Torr pressure and 10 sccm flow rate, followed by 8 sub-pulses of TTPS precursor as follows: each sub-pulse of TTPS precursor is delivered by vapor draw for 2 seconds with 10 sccm Npurge gas flow, pumped for 30 seconds with 0 sccm of Npurge gas flow down to base pressure of (about) 0.034 Torr, and purged for 15 seconds with 10 sccm Npurge gas flow, and finally purged for another 10 seconds before the next cycle. This process is repeated for a total of 4 cycles until (about) 230 Å of silicon oxide film is deposited on a 45 mm×45 mm silicon substrate with native oxide.

2 2 2 2 Mixed-ligand precursor, bis(tert-pentoxy)(tert-butoxy)silanol (BTPTBS) precursor, is heated to 80° C. and TMA catalyst is unheated at room temperature of (about) 24° C. ALD of silicon oxide film is carried out at 150° C. using the pump-purge process. For each cycle of ALD, TMA catalyst is pulsed for 0.015 second and purged for 15 seconds while Npurge gas is supplied with 0.11 Torr pressure and 10 sccm flow rate, followed by 10 sub-pulses of BTPTBS precursor as follows: each sub-pulse of BTPTBS precursor is delivered by vapor draw for 2 seconds with 10 sccm Npurge gas flow, pumped for 30 seconds with 0 sccm of Npurge gas flow down to base pressure of (about) 0.034 Torr, purged for 15 seconds with 10 sccm Npurge gas flow, and finally purged for another 10 seconds before the next cycle. This process is repeated for a total of 4 cycles until (about) 218 Å of silicon oxide film is deposited on a 45 mm×45 mm silicon substrate with native oxide.

The silicon oxide films according to Examples are analyzed by Fourier Transform Infrared Spectroscopy (FTIR).

FTIR is analyzed using a Nicolet IS50 FT-IR system (Thermo Fisher Scientific Inc.).

11 FIG. The results are as shown in.

11 FIG. is a FTIR analysis graph of the silicon oxide films obtained in Examples.

11 FIG. 2 −1 −1 Referring to, although Example 6 (150° C./pump-purge) and Example 4 (150° C., 0.17 Torr purge) are performed at the same temperature (150° C.), it is confirmed that the silicon oxide film according to Example 6 using the pump-purge process has reduced HO (3400 cm) and Si—OH (900 cm) compared to the silicon oxide film according to Example 4.

2 −1 −1 Additionally, although Example 2 (175° C./0.17 Torr purge) and Example 3 (175° C./0.11 Torr purge) are performed at the same temperature (175° C.), it is confirmed that the silicon oxide film according to Example 3 performed at a lower purge pressure (0.11 Torr) has reduced HO (3400 cm) and Si—OH (900 cm) compared to the silicon oxide film according to Example 2.

2 −1 −1 Additionally, although Example 1 (200° C./0.17 Torr purge), Example 2 (175° C./0.17 Torr purge) and Example 4 (150° C./0.17 Torr purge) are performed under the same pressure (0.17 Torr), it is confirmed that the silicon oxide film according to Example 1 performed at a higher temperature (200° C.) has reduced HO (3400 cm) and Si—OH (900 cm) compared to the silicon oxide films according to Examples 2 and 4.

The MISCAP (metal-insulator-semiconductor capacitor) devices including the silicon oxide films according to Examples are manufactured and its electrical properties are evaluated.

2 The MISCAP device has a stacked structure of p-type silicon substrate (45 mm×45 mm)/native oxide (with thickness of 12˜15 Å)/SiOlayer (formed by ALD)/TiN electrode.

2 Here, the SiOlayers are silicon oxide films according to Examples 1 to 7, and the TiN electrode is formed to have a thickness of (about) 200 Å by sputtering at (about) 250° C. and patterned through a general photoetching process.

The electric characteristics are evaluated using Keysight B1500A Semiconductor Device Parameter Analyzer equipped with HRSMU (high resolution source/monitor unit) module for evaluating leakage current and MFCMU (multi-frequency capacitance measurement unit) module for evaluating capacitance.

12 13 FIGS.and The results are as shown in Table 1 and.

12 FIG. 13 FIG. is a graph showing the change in leakage current at 5 MV/cm according to deposition temperature and purge gas pressure during the formation of a silicon oxide film, andis a graph showing the change in breakdown field according to deposition temperature and purge gas pressure during the formation of a silicon oxide film.

TABLE 1 Dielectric Leakage Current Breakdown Field Constant 2 (A/cm, @ 5 MV/cm) (MV/cm) Example 1 4.3 −8 1.0 × 10 10.8 Example 2 4.6 −8 5.0 × 10 10.6 Example 3 — −8 1.0 × 10 10.2 Example 4 4.9 −7 2.0 × 10 9 Example 5 — −7 2.0 × 10 8.7 Example 6 4.6 −8 3.0 × 10 10.7 Example 7 4.4 −8 3.0 × 10 10.3

12 13 FIGS.and Referring to Table 1 and, it is confirmed that the devices including the silicon oxide films according to Examples have desired (good) electrical characteristics using a continuous flow process at 200 to 250° C. with 0.17 Torr pressure (e.g., Example 1), a continuous flow process at 175° C. with 0.11 Torr pressure (e.g., Example 3), and a pump-purge process at 150° C. (e.g., Example 6). Examples II

A 25 mm×25 mm silicon substrate with a copper film on an upper surface thereof and a 25 mm×25 mm silicon substrate with native oxide are each etched in an aqueous solution containing 2 wt % of citric acid for 2.5 to 3 minutes, then rinsed with distilled water 3 times for 1 minute each. The substrates are blown dry with nitrogen gas, immediately loaded to the center (the central area) of a 200 mm-diameter cross flow reactor heated to 80° C., pumped down to base pressure (e.g., 0.034 Torr), then heated up gradually to 150° C. with 10 sccm of nitrogen purge gas flow. 1-dodecanethiol (DDT) liquid in a stainless ampule is heated to 100° C., delivered by vapor draw into the 200 mm-diameter cross flow reactor at 150° C. for 5 minutes continuously without carrier or purge gas to selectively form a SAM passivation layer on the copper film, purged with 20 sccm of nitrogen purge gas flow for 90 seconds, then deposited in-situ at the same temperature of 150° C. without vacuum break for 2 cycles of ALD of silicon oxide using the process described in Example 6. The substrates are cooled down to 80° C. before exposing (opening) to air for unloading.

A 25 mm×25 mm silicon substrate with a copper film on an upper surface thereof and a 25 mm×25 mm silicon substrate with native oxide are each etched in an aqueous solution containing 2 wt % of citric acid for 2.5 to 3 minutes, then rinsed with distilled water 3 times for 1 minute each. The substrates are blown dry with nitrogen gas, immediately loaded to the center (the central area) of a 200 mm-diameter cross flow reactor heated to 80° C., pumped down to base pressure (e.g., 0.034 Torr), then heated up gradually to 175° C. with 20 sccm of nitrogen purge gas flow. 1-tetradecanethiol (TDT) in a stainless ampule is heated to 110° C., vapor draw delivered into the 200 mm-diameter cross flow reactor at 175° C. for 5 minutes continuously without carrier or purge gas to selectively form a SAM passivation layer on the copper film, purged with 20 sccm of nitrogen purge gas flow for 60 seconds, then deposited in-situ at the same temperature of 175° C. without vacuum break for 2 cycles of ALD of silicon oxide using the process described in Example 2. The substrates are cooled down to 80° C. before exposing (opening) to air for unloading.

A 25 mm×25 mm silicon substrate with a copper film on an upper surface thereof and a 25 mm×25 mm silicon substrate with native oxide are each etched in an aqueous solution containing 2 wt % of citric acid for 2.5 to 3 minutes, then rinsed with distilled water 3 times for 1 minute each. The substrates are blown dry with nitrogen gas, immediately loaded to the center (the central area) of a 200 mm-diameter cross flow reactor heated to 80° C., pumped down to base pressure (e.g., 0.034 Torr), then heated up gradually to 200° C. with 20 sccm of nitrogen purge gas flow. 1-dodecanethiol (DDT) in a stainless ampule is heated to 100° C., vapor draw delivered into the 200 mm-diameter cross flow reactor at 200° C. continuously for 2 minutes without carrier or purge gas to selectively form a SAM passivation layer on the copper film, purged with 20 sccm of nitrogen purge gas flow for 30 seconds, then deposited in-situ at the same temperature of 200° C. without vacuum break for 2 cycles of ALD of silicon oxide using the process described in Example 1. The substrates are cooled down to 80° C. before exposing (opening) to air for unloading.

A 25 mm×25 mm silicon substrate with a copper film on an upper surface thereof and a 25 mm×25 mm silicon substrate with native oxide are each etched in an aqueous solution containing 2 wt % of citric acid for 2.5 to 3 minutes, then rinsed with distilled water 3 times for 1 minute each. The substrates are blown dry with nitrogen gas, immediately loaded to the center (the central area) of a 200 mm-diameter cross flow reactor heated to 80° C., pumped down to base pressure (e.g., 0.034 Torr), then heated up gradually to 250° C. with 20 sccm of nitrogen purge gas flow. 1-dodecanethiol (DDT) in a stainless ampule is heated to 110° C., vapor draw delivered into the 200 mm-diameter cross flow reactor at 250° C. continuously for 2 minutes without carrier or purge gas to selectively form a SAM passivation layer on the copper film, purged with 20 sccm of nitrogen purge gas flow and 0.17 Torr of purge gas pressure for 15 seconds, followed by 2 cycles of in-situ ALD deposition of silicon oxide at the same pressure of 0.17 Torr and same temperature of 250° C. without vacuum break using a single-pulse continuous flow process as follows: TMA pulse 0.015 second, purge 15 seconds, 15 second pulse of TTPS, and finally 15 second purge at the same pressure for each cycle. The substrates are cooled down to 80° C. before exposing (opening) to air for unloading.

Selectivity according to the area-selective atomic layer deposition (also referred to as ALD herein) of silicon oxide films according to Examples are evaluated.

Selectivity is evaluated by measuring the thicknesses of the silicon oxide film on the copper non-grown surface and the silicon oxide film on the native oxide surface.

2 The thickness of the silicon oxide film on the copper non-grown surface is calculated from Si(at %) values measured using XPS analysis (Thermo Scientific K-Alpha+ XPS Spectrometer) based on samples with known SiOthickness.

The thickness of the silicon oxide film on the native oxide surface is measured using a Woollam Alpha-SE Ellipsometer. Selectivity is calculated according to Equation below.

The results are as shown in Table 2.

TABLE 2 Deposition Selectivity Temperature(° C.) 1 T(Å) 2 T(Å) (%) Example 8 150 195 2.4 98.8 Example 9 175 140 9.5 93.2 Example 10 200 108 11.6 89.3 Example 11 250 32.5 1.8 94.5 1 * T: thickness on native oxide growth surface 2 * T: thickness on Cu non-growth surface

Referring to Table 2, it is confirmed that the selectivity of the silicon oxide films according to Examples is determined depending on the deposition temperature and the thickness of the silicon oxide film on the native oxide growth surface.

While this disclosure has been described in connection with what is presently considered to be practical example embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.