Microelectronic Devices Including Heat Sinks, and Associated Devices and Methods

This application claims the benefit under 35 U.S.C. § 119 (e) of U.S. Provisional Patent Application Ser. No. 63/669,626, filed Jul. 10, 2024, the disclosure of which is hereby incorporated herein in its entirety by this reference.

Embodiments of the disclosure generally relate to microelectronic devices. In particular, embodiments of the disclosure relate to microelectronic devices including heat sinks, and associated devices and methods.

Microelectronic device designers often desire to increase the level of integration or density of features within a microelectronic device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, microelectronic device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified, easier and less expensive to fabricate designs.

One example of a microelectronic device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many types of memory devices including, but not limited to, non-volatile memory devices (e.g., NAND Flash memory devices) and volatile memory devices (e.g., dynamic random access memory (DRAM) devices).

Control logic devices within a base control logic structure underlying a memory array of a memory device have been used to control operations on the memory cells of the memory device. Control logic devices of the base control logic structure can be provided in electrical communication with conductive lines (e.g., digit lines, word lines) coupled to the memory cells by way of routing and contact structures. Unfortunately, processing conditions (e.g., temperatures, pressures, materials) for the formation of the memory array over the base control logic structure can limit the configurations and performance of the control logic devices within the base control logic structure. In addition, the quantities, dimensions, and arrangements of the different control logic devices employed within the base control logic structure can also undesirably impede reductions to the size (e.g., horizontal footprint) of a memory device, and/or improvements in the performance (e.g., faster memory cell ON/OFF speed, lower threshold switching voltage requirements, faster data transfer rates, lower power consumption) of the memory device.

The following description provides specific details, such as material compositions, shapes, and sizes, in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art would understand that the embodiments of the disclosure may be practiced without employing these specific details. Indeed, the embodiments of the disclosure may be practiced in conjunction with conventional microelectronic device fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a microelectronic device (e.g., a memory device). The structures described below do not form a complete microelectronic device. Only those process acts and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional acts to form a complete microelectronic device from the structures may be performed by conventional fabrication techniques.

Drawings presented herein are for illustrative purposes only, and are not meant to be actual views of any particular material, component, structure, device, or system. Variations from the shapes depicted in the drawings as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes or regions as illustrated, but include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as box-shaped may have rough and/or nonlinear features, and a region illustrated or described as round may include some rough and/or linear features. Moreover, sharp angles that are illustrated may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of a region and do not limit the scope of the present claims. The drawings are not necessarily to scale. Additionally, elements common between figures may retain the same numerical designation.

As used herein, a “memory device” means and includes microelectronic devices exhibiting memory functionality, but not necessarily limited to memory functionality. Stated another way, and by way of non-limiting example only, the term “memory device” includes not only conventional memory (e.g., conventional non-volatile memory; conventional volatile memory), but also includes an application specific integrated circuit (ASIC) (e.g., a system on a chip (SoC)), a microelectronic device combining logic and memory, and a graphics processing unit (GPU) incorporating memory.

As used herein, the term “configured” refers to a size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one apparatus facilitating operation of one or more of the structure and the apparatus in a pre-determined way.

As used herein, the phrase “coupled to” refers to structures operatively connected with each other, such as electrically connected through a direct Ohmic connection or through an indirect connection (e.g., by way of another structure).

As used herein, the term “substantially” in reference to a given parameter means and includes to a degree that one skilled in the art would understand that the given parameter, property, or condition is met with a small degree of variance, such as within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0 percent met, at least 95.0 percent met, at least 99.0 percent met, at least 99.9 percent met, or even 100.0 percent met.

As used herein, “about” or “approximately” in reference to a numerical value for a particular parameter is inclusive of the numerical value and a degree of variance from the numerical value that one of ordinary skill in the art would understand is within acceptable tolerances for the particular parameter. For example, “about” or “approximately” in reference to a numerical value may include additional numerical values within a range of from 90.0 percent to 110.0 percent of the numerical value, such as within a range of from 95.0 percent to 105.0 percent of the numerical value, within a range of from 97.5 percent to 102.5 percent of the numerical value, within a range of from 99.0 percent to 101.0 percent of the numerical value, within a range of from 99.5 percent to 100.5 percent of the numerical value, or within a range of from 99.9 percent to 100.1 percent of the numerical value.

As used herein, relational terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for case of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the drawings. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if materials in the figures are inverted, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used herein, the term “and/or” means and includes any and all combinations of one or more of the associated listed items.

As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are in reference to a major plane of a structure and are not necessarily defined by earth's gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the major plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of the structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. With reference to the drawings, a “horizontal” or “lateral” direction may be perpendicular to an indicated “Z” axis, and may be parallel to an indicated “X” axis and/or parallel to an indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to an indicated “Z” axis, may be perpendicular to an indicated “X” axis, and may be perpendicular to an indicated “Y” axis.

As used herein, features (e.g., structures, materials, regions, devices) described as “neighboring” one another means and includes features of the disclosed identity (or identities) that are located most proximate (e.g., closest to) one another. Additional features (e.g., additional regions, additional structures, additional devices) not matching the disclosed identity (or identities) of the “neighboring” features may be disposed between the “neighboring” features. Put another way, the “neighboring” features may be positioned directly adjacent one another, such that no other feature intervenes between the “neighboring” features; or the “neighboring” features may be positioned indirectly adjacent one another, such that at least one feature having an identity other than that associated with at least one of the “neighboring” features is positioned between the “neighboring” features. Accordingly, features described as “vertically neighboring” one another means and includes features of the disclosed identity (or identities) that are located most vertically proximate (e.g., vertically closest to) one another. Moreover, features described as “horizontally neighboring” one another means and includes features of the disclosed identity (or identities) that are located most horizontally proximate (e.g., horizontally closest to) one another.

As used herein, “conductive material” means and includes thermally conductive material such as one or more of a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), an alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe- and Ni-based alloy, a Co- and Ni-based alloy, an Fe- and Co-based alloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide), and a conductively-doped semiconductor material (e.g., conductively-doped polysilicon, conductively-doped germanium (Ge), conductively-doped silicon germanium (SiGe)). In addition, a “conductive structure” means and includes a structure formed of and including conductive material.

x x x x x x x x y x y x y x y z x z y As used herein, “insulative material” means and includes thermally insulative material, such one or more of at least one dielectric oxide material (e.g., one or more of a silicon oxide (SiO), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlO), a hafnium oxide (HfO), a niobium oxide (NbO), a titanium oxide (TiO), a zirconium oxide (ZrO), a tantalum oxide (TaO), and a magnesium oxide (MgO)), at least one dielectric nitride material (e.g., a silicon nitride (SiN)), at least one dielectric oxynitride material (e.g., a silicon oxynitride (SiON)), at least one dielectric oxycarbide material (e.g., silicon oxycarbide (SiOC)), at least one hydrogenated dielectric oxycarbide material (e.g., hydrogenated silicon oxycarbide (SiCOH)), and at least one dielectric carboxynitride material (e.g., a silicon carboxynitride (SiOCN)). In addition, an “insulative structure” means and includes a structure formed of and including insulative material.

−8 4 6 X 1-X X 1-X Y 1-Y x y x y x x y z x y z x y x x x x z x y x y z x y z x y z x y z a x y z x y z x y z x y z As used herein, the term “semiconductor material” refers to a material having an electrical conductivity between those of insulative materials and conductive materials. For example, a semiconductor material may have an electrical conductivity of between about 10Siemens per centimeter (S/cm) and about 10S/cm (10S/m) at room temperature. Examples of semiconductor materials include elements found in column IV of the periodic table of elements such as silicon (Si), germanium (Ge), and carbon (C). Other examples of semiconductor materials include compound semiconductor materials such as binary compound semiconductor materials (e.g., gallium arsenide (GaAs)), ternary compound semiconductor materials (e.g., AlGaAs), and quaternary compound semiconductor materials (e.g., GaInAsP), without limitation. Compound semiconductor materials may include combinations of elements from columns III and V of the periodic table of elements (III-V semiconductor materials) or from columns II and VI of the periodic table of elements (II-VI semiconductor materials), without limitation. Further examples of semiconductor materials include oxide semiconductor materials such as zinc tin oxide (ZnSnO, commonly referred to as “ZTO”), indium zinc oxide (InZnO, commonly referred to as “IZO”), zinc oxide (ZnO), indium gallium zinc oxide (InGaZnO, commonly referred to as “IGZO”), indium gallium silicon oxide (InGaSiO, commonly referred to as “IGSO”), indium tungsten oxide (InWO, commonly referred to as “IWO”), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxide nitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and other similar materials. In addition, each of a “semiconductor structure” and a “semiconductive structure” means and includes a structure formed of and including semiconductor material.

x x x x x y x y x y x y z x z y Formulae including one or more of “x,” “y,” and “z” herein (e.g., SiO, AlO, HfO, NbO, TiO, SiN, SiON, SiOC, SiCOH, SiOCN) represent a material that contains an average ratio of “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if any) for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As the formulae are representative of relative atomic ratios and not strict chemical structure, an insulative material may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and values of “x,” “y,” and “z” (if any) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions.

Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. In addition, unless the context indicates otherwise, removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization (e.g., chemical-mechanical planarization (CMP)), or other known methods.

Control logic devices (e.g., complementary metal-oxide semiconductor (CMOS devices)) within a base control logic structure underlying a memory array structure of a memory device (e.g., DRAM device, a NAND device) may be used to control operations of the memory device. Processing conditions (e.g., temperatures, pressures, materials) conventionally employed for the formation of a conventional memory array structure over a conventional base control logic structure can limit the configurations and performance of the control logic devices within the base control logic structure and/or the configurations and performance of memory cells within the memory array structure. In addition, the quantities, dimensions, and arrangements of the different control logic devices employed within the base control logic structure can also undesirably impede reductions to the size of a memory device, and/or improvements in the performance of the memory device.

Bonding techniques, such as wafer-to-wafer bonding may facilitate forming the control logic structure (including the control logic circuitry and devices thereof) separately from a memory array structure (including the arrays of memory cells thereof). Forming the control logic structure and the memory array structure separately may facilitate reductions in size and/or performance enhancements for a memory device subsequently formed using wafer-to-wafer bonding relative to conventional memory device configuration. After the control logic structure and the memory array structure are separately formed, they may be bonded to one another in a desired arrangement (e.g., a face-to-back (F2B) configuration, where a back of the control logic structure is bonded to a face of the memory array structure; a face-to-face (F2F) configuration, a back-to-face (B2F) configuration; a back-to-back (B2B) configuration). For example, the control logic structure may be bonded to the memory array structure through wafer-to-wafer bonding by at least forming dielectric-to-dielectric (e.g., oxide-to-oxide) bonds between the dielectric material (e.g., dielectric oxide material) of the control logic structure and additional dielectric material (e.g., additional dielectric oxide material) of the memory array structure. For example, oxide-to-oxide bonds may be formed between the control logic structure and the memory array structure to form a relatively larger assembly by bringing the dielectric oxide materials of the control logic structure and the memory array structure in physical contact and applying a temperature greater than or equal to about 400° C. (e.g., within a range of from about 400° C. to about 800° C., greater than about 800° C.) to form the oxide-to-oxide bonds. In some embodiments, the dielectric oxide materials are exposed to at least one temperature greater than about 800° C. to form the oxide-to-oxide bonds between the control logic structure and the memory array structure.

The reductions in size facilitated by the aforementioned wafer-on-wafer bonding techniques may result in a reduction in the ability of the resulting microelectronic device (e.g., memory device) to dissipate heat. For example, base semiconductor materials (e.g., silicon) of the control logic structure and/or the memory array structure operatively associated therewith may act as a heat sink for some control logic devices of the control logic structure. Wafer-on-wafer may permit reducing a vertical thickness of such one or more base semiconductor materials, but may correspondingly result in a reduction of the heat sink functionality facilitated by the base semiconductor materials. Thus, absent the configuration of the disclosure described hereinbelow, relatively high powered circuits and devices of a control logic structure, such as electrostatic discharge (ESD) protection circuitry and devices, may suffer from insufficient heat dissipation. Such issues with heat dissipation may otherwise result in less desirable (e.g., relatively larger) microelectronic device dimensions, and/or a reduction in performance (e.g., speed, memory cell ON/OFF speed, threshold switching voltage, data transfer rates, power consumption) of the microelectronic device.

Embodiments of the disclosure include heat sink structures embedded in one or more of the control logic structure and the memory array structure to facilitate the dissipation of heat from control logic circuitry and devices (e.g., relatively high power devices, such as ESD devices) of the control logic structure. The heat sink structures may facilitate reductions in a size of a microelectronic device (e.g., memory devices) including the control logic structure and the memory array structure, as compared to conventional microelectronic device configurations, without effectuating undesirable overheating the microelectronic device during use and operation of the microelectronic device.

1 FIG. 100 100 102 104 106 102 108 104 102 110 110 110 illustrates a simplified, partial vertical cross-sectional view of a microelectronic device(e.g., memory device), in accordance with embodiments of the disclosure. The microelectronic deviceincluding a control logic structure(e.g., a control logic die) is bonded to a memory array structure(e.g., a memory array die). A back sideof the control logic structureis bonded (e.g., dielectric-to-dielectric bonded) to a faceof the memory array structureat an interface. The control logic structureincludes a high-power component. The high-power componentmay be a device or circuit configured to receive relatively high voltages and/or to handle relatively high currents. By way of non-limiting example, the high-power componentmay be an electrostatic discharge (ESD) protection device (e.g., an ESD diode, an ESD suppressor), transistor logic circuits, charge pumps, regulators, on-die termination (ODT) devices, amplifier circuitry, or a resistor.

1 FIG. 110 112 114 112 114 112 114 112 114 113 102 113 112 114 112 114 112 114 100 In the embodiment illustrated in, the high-power componentis an ESD diode including electrodes,. One of the electrodes,may be an anode (e.g., a positive electrode) and the other of the electrodes,may be a cathode (e.g., a negative electrode). The electrodes,are separated from one another by semiconductor material(e.g., silicon) of the control logic structureto form the ESD diode. The semiconductor materialinterposed between the electrodes,may permit electrical current to pass (e.g., flow) from the electrodeto the electrode, or vice versa, when a voltage between the electrodeand the electrodeis above a threshold value to discharge electrostatic energy and substantially prevent damage to other components of the microelectronic device.

112 114 113 112 114 113 102 112 114 113 113 116 110 102 116 112 114 113 102 116 Passing electrical current between the electrodeand the electrodemay generate heat at least due to the resistance of the semiconductor materialinterposed between the electrodeand the electrode. The semiconductor material, as a whole of the control logic structure, may dissipate thermal energy (e.g., heat) generated by the current passing between the electrodeand the electrode. However, as a vertical thickness (e.g., in the Z-direction) of the semiconductor materialis decreased, the capability of the semiconductor material, as a whole, to dissipate generated thermal energy is correspondingly reduced. Accordingly, in accordance with embodiments of the disclosure, a heat sink structureis provided to vertically underlie (e.g., in the Z-direction) and horizontally overlap (e.g., in the X-direction, in the Y-direction) the high-power componentof the control logic structure. The heat sink structuremay be configured to dissipate thermal energy generated by the current passing between the electrodeand the electrodethat is not dissipated by the semiconductor materialof the control logic structure. The heat sink structuremay be formed of and include material having relatively high thermal conductivity, such as one more of tungsten, aluminum, and copper.

116 104 108 104 116 102 106 102 116 110 116 110 110 102 104 116 104 104 1 FIG. In some embodiments, the heat sink structureis positioned in an upper portion of the memory array structurenear the faceof the memory array structure, as illustrated in. In other embodiments, the heat sink structureis positioned in a lower portion of the control logic structurenear the back sideof the control logic structure, as discussed in further detail below. The heat sink structuremay be arranged to horizontally extend (e.g., in the X-direction, in the Y-direction) beyond a horizontal area of the high-power component. For example, the heat sink structuremay horizontally span a distance, in the X-direction, which is greater than a width, in the X-direction, of the high-power component. The high-power componentmay be positioned in the control logic structurein a region that is not positioned over auxiliary contact structures of the memory array structure, such that the heat sink structuremay extend through the memory array structurewithout contacting the auxiliary contact structures of the memory array structure.

116 100 116 118 100 116 118 100 100 112 114 116 102 104 118 102 In some embodiments, the heat sink structureserves as a ground bus within the microelectronic device. For example, the heat sink structuremay be coupled to one or more contact structuresthat may be connected to a ground for the microelectronic device. In other embodiments, the heat sink structureand the contact structurescombine to form a larger heat sink for the microelectronic devicewithout being electrically connected to other features of the microelectronic device. For example, thermal energy generated by the current passing between the electrodeand the electrodemay be transferred vertically (e.g., in a Z-direction) to the heat sink structurethrough the control logic structureand the memory array structure, and the heat may also be transferred horizontally (e.g., in the X-direction) to the contact structurethrough the control logic structure.

2 FIG. 2 FIG. 102 118 116 118 116 202 118 202 118 116 202 118 116 202 116 118 illustrates an enlarged, vertical cross-sectional view of the control logic structureand the interface between the contact structureand the heat sink structure. As illustrated in, the contact structureprovides a connection between the heat sink structureand a secondary structure. The contact structureand the secondary structuremay each be formed from a material having a high thermal conductivity, such as one or more of tungsten, aluminum, and copper. Thus, the contact structuremay provide a thermal connection between the heat sink structureand the secondary structure. In some embodiments, the contact structureis also configured to provide an electrical connection between the heat sink structureand the secondary structure, such as when the heat sink structureand the contact structureare operating as a ground bus.

202 202 100 116 118 116 118 202 In some embodiments, the secondary structureis an electrical contact, such as a contact pad, a via, a post, a pin, or a solder bump. In other embodiments, the secondary structureis a second heat sink structure. For example, multiple microelectronic devicesmay be vertically stacked in the Z-direction and the heat sink structuresof the stacked microelectronic devices may be thermally connected to one another through the contact structure, such that the heat sink structure, the contact structure, and the secondary structurecombine to form a relatively larger heat sink structure having greater heat dissipation capabilities.

102 204 113 102 118 204 118 102 204 x 2 y 3 4 The control logic structuremay include an insulative structurepositioned between one or more additional materials (e.g., the semiconductor material) of the control logic structureand the contact structure. The insulative structuremay be configured to substantially electrically isolate the contact structurefrom the additional materials of control logic structure. For example, the insulative structuremay be formed of and include dielectric oxide materials, such as SiO(e.g., SiO) or SiN(e.g., SiN).

3 3 FIGS.A-C 3 FIG.A 3 FIG.B 3 FIG.C 3 FIG.A 3 FIG.B 3 FIG.C 3 3 FIGS.A-C 300 300 300 310 310 310 300 300 300 310 310 310 318 318 318 310 310 310 318 318 318 318 318 318 310 310 310 a b c a b c a b c a b c a b c a b c a b c a b c a b c illustrate simplified, partial vertical cross-sectional views of different microelectronic devices(),(),() with heat sink structures(),(),() positioned at different vertical arrangements (e.g., in the Z-direction) therein. With collective reference to, in the microelectronic devices,,the heat sink structure,,vertically underlies and horizontally overlaps a high-power component,,, respectively. The heat sink structures,,also horizontally span (e.g., in the X-direction) a distance that is greater than a width (e.g., in the X-direction) of the high-power component,,, respectively. A horizontal area of the high-power component,,may at least partially (e.g., substantially) horizontally overlap (e.g., in the X-direction, in the Y-direction) a horizontal area of the heat sink structure,,, respectively.

3 3 FIGS.A-C 4 7 FIGS.-F 3 7 FIGS.A-F 1 2 FIGS.and To avoid repetition, not all features (e.g., structures, materials, regions, devices) shown inand subsequentare described in detail herein. Rather, unless described otherwise below, in, a feature designated by a reference numeral that is a 100 increment of the reference numeral of a feature previously described with reference to one or more ofwill be understood to be substantially similar to the previously described feature.

3 FIG.A 310 302 318 306 302 302 304 306 302 308 304 a a a a a a a a a a a. In the embodiment illustrated in, the heat sink structureis positioned in the control logic structureat a vertical position between the high-power componentand the back sideof the control logic structure. The control logic structuremay be bonded to the memory array structurethrough dielectric-to-dielectric bonds (e.g., oxide-to-oxide bonds) between dielectric material at the back sideof the control logic structureand additional dielectric material at the faceof the memory array structure

310 318 302 310 306 302 a a a a a a. To form the heat sink structure, a material having high thermal conductivity may be formed and optionally patterned so as to be vertically offset from and horizontally overlap the high-power componentof the control logic structure. Thereafter, dielectric material (e.g., silicon oxide, silicon nitride) may be formed on or over the heat sink structure. The dielectric material may at least partially form the back sideof the control logic structure

302 304 306 302 308 304 a a a a a a The control logic structuremay then be bonded to the memory array structure. For example, the back sideof the control logic structuremay be provided in physical contact with the faceof the memory array structure, and then an annealing temperature greater than or equal to about 400° C. (e.g., within a range of from about 400° C. to about 800° C., greater than about 800° C.) may be applied to form the dielectric-to-dielectric bonds.

3 FIG.B 310 304 306 302 304 308 304 302 304 308 304 306 302 b b b b b b b b b b b b b. In the embodiment illustrated in, the heat sink structureis positioned at a vertical position in the memory array structurevertically beneath the back sideof the control logic structure. The dielectric material of the memory array structureforms the faceof the memory array structure. The control logic structureis bonded to the memory array structurethrough dielectric-to-dielectric bonds between the dielectric material at the faceof the memory array structureand additional dielectric material at the back sideof the control logic structure

310 304 318 302 310 308 304 b b b b b b b. To form the heat sink structure, a material having high thermal conductivity is formed at a horizontal location within the memory array structuresubstantially corresponding to a horizontal location of the high-power componentof the control logic structure. Thereafter, dielectric material (e.g., silicon oxide, silicon nitride) may be formed on or over the heat sink structure. The dielectric material may at least partially form the faceof the memory array structure

302 304 306 302 308 304 b b b b b b The control logic structuremay then be bonded to the memory array structure. For example, the back sideof the control logic structuremay be provided in physical contact with the faceof the memory array structure, and then an annealing temperature greater than or equal to about 400° C. (e.g., within a range of from about 400° C. to about 800° C., greater than about 800° C.) may be applied to form the dielectric-to-dielectric bonds.

3 FIG.C 3 FIG.C 310 320 302 304 318 302 314 310 306 302 316 310 308 304 302 304 308 304 306 302 314 316 310 c c c c c c c c c c c c c c c c c c. In the embodiment illustrated in, the heat sink structureis vertically positioned at an interfacebetween the control logic structureand the memory array structurevertically beneath the high-power componentof the control logic structure. An upper portionof the heat sink structureforms a portion of the back sideof the control logic structure, and a lower portionof the heat sink structureforms a portion of the faceof the memory array structure. In the embodiment of, the control logic structureis bonded to the memory array structurethrough combination of dielectric-to-dielectric bonds between the dielectric material at the faceof the memory array structureand additional dielectric material at the back sideof the control logic structure, and metal-to-metal bonds between the upper portionand the lower portionof the heat sink structure

310 304 318 302 302 318 302 302 304 300 310 306 302 308 304 308 304 306 302 314 302 316 304 310 c c c c c c c c c c c c c c c c c c c c c c. To form the heat sink structure, a material having high thermal conductivity is formed at a horizontal location within the memory array structuresubstantially corresponding to a horizontal location of the high-power componentof the control logic structure; and additional material having high thermal conductivity formed at a horizontal location within the control logic structuresubstantially corresponding to the horizontal location of the high-power componentof the control logic structure. Thereafter, the control logic structuremay then be bonded to the memory array structureto form microelectronic deviceand simultaneously form the heat sink structure. For example, the back sideof the control logic structuremay be provided in physical contact with the faceof the memory array structure, and then an annealing temperature greater than or equal to about 400° C. (e.g., within a range of from about 400° C. to about 800° C., greater than about 800° C.) may be applied to form the dielectric-to-dielectric bonds between the dielectric material at the faceof the memory array structureand additional dielectric material at the back sideof the control logic structure, while also forming metal-to-metal bonds between the additional material (corresponding to the upper portion) of the control logic structureand the material (corresponding to the lower portion) of the memory array structureto form the heat sink structure

4 FIG. 4 FIG. 400 400 416 418 416 418 410 416 404 402 404 408 404 402 404 408 404 406 402 illustrates a simplified, partial vertical cross-sectional view of a microelectronic device, in accordance with embodiments of the disclosure. The microelectronic deviceincludes a heat sink structurehorizontally extending (e.g., in the X-direction) between two contact structures, such that the heat sink structureand the contact structuresform a cup-like shape around a high-power component. In the embodiment illustrated in, the heat sink structureis vertically positioned in the memory array structurevertically below the control logic structure. Dielectric material of the memory array structureat least partially forms the faceof the memory array structure. The control logic structureis bonded to the memory array structurethrough dielectric-to-dielectric bonds between the faceof the memory array structureand the back sideof the control logic structure.

416 420 416 The heat sink structurehas a thicknesssufficient to dissipate a similar amount of heat to a control logic structure having a greater volume of semiconductor material. For example, the heat sink structuremay have a thickness in a range from about 5 nanometers (nm) to about 20 micrometers (μm), such as in a range from about 25 nm to about 10 μm or from about 2 μm to about 5 μm.

4 FIG. 3 FIG.A 3 FIG.C 416 404 404 416 406 402 404 422 416 406 402 422 416 406 402 402 416 416 422 416 406 402 416 402 422 416 402 416 402 300 416 406 402 300 a c In the embodiment illustrated in, the heat sink structureis positioned in the memory array structurewith a portion of semiconductor material of the memory array structurebetween the heat sink structureand the back sideof the control logic structure. The portion of the semiconductor material plus dielectric material of the memory array structuredefines a distancebetween the heat sink structureand the back sideof the control logic structure. As the distancebetween the heat sink structureand the back sideof the control logic structuredecreases, the heat transfer between the semiconductor material of the control logic structureand the heat sink structuremay increase, which may improve the heat dissipation provided by the heat sink structure. The distancebetween the heat sink structureand the back sideof the control logic structuremay be less than about 5 μm, such as less than about 2 μm or less than about 1 μm. As discussed above, in some embodiments, the heat sink structureis in direct contact with semiconductor material of the control logic structure, such that there is no distancebetween the heat sink structureand the control logic structure. For example, the heat sink structuremay be at least partially (e.g., substantially) disposed within the semiconductor material of the control logic structure, as illustrated in the microelectronic deviceof, or the heat sink structuremay form a portion of the back sideof the control logic structure, as illustrated in the microelectronic deviceof.

4 FIG. 416 418 400 410 418 416 416 418 418 424 416 418 424 418 424 420 416 418 424 420 416 In the embodiment illustrated in, the heat sink structureis coupled to the contact structuresextending vertically, in the Z-direction, through portions of the microelectronic devicehorizontally neighboring, in the X-direction, sides of the high-power component. The contact structuresmay be respectively formed of and include thermally conductive material similar to that of the heat sink structure, such that the heat sink structureand the contact structureseffectively combine to form a relatively larger heat sink structure. The contact structuresmay have a horizontal thickness(e.g., in the X-direction) similar to the vertical thickness (e.g., in the Z-direction) of the heat sink structure. For example, the contact structuresmay have a horizontal thicknesswithin a range from about 5 nm to about 20 micrometers (μm), such as from about 25 nm to about 10 μm, or from about 2 μm to about 5 μm. In some embodiments, the contact structuresrespectively have a horizontal thicknessthat is the same as the vertical thicknessof the heat sink structure. In other embodiments, one or more (e.g., each) of the contact structureshave a horizontal thicknessgreater than the vertical thicknessof the heat sink structure.

418 426 412 414 410 402 402 The contact structuresmay be respectively spaced a horizontal distancefrom a nearest electrode,of the high-power componentby semiconductor material of the control logic structure. For example, the semiconductor material of the control logic structuremay define a horizontal spacing distance within a range from about 0.1 μm to about 10 μm, such as within a range from about 1 μm to about 5 μm, or from about 1 μm to about 2 μm.

5 5 FIGS.A-C 5 FIG.A 5 FIG.B 5 FIG.C 5 FIG.A 5 FIG.B 5 FIG.C 4 FIG. 5 FIG.A 5 FIG.B 5 FIG.C 5 FIG.A 5 FIG.B 5 FIG.C 5 FIG.A 5 FIG.B 5 FIG.C 5 5 FIGS.A-C 5 FIG.A 5 FIG.B 5 FIG.C 5 FIG.A 5 FIG.B 5 FIG.C 500 500 500 500 500 500 400 510 510 510 516 516 516 518 510 518 510 510 510 510 510 510 a b c a b c a b c a b c a b c a b c a b c illustrate simplified, partial vertical cross-sectional views of different microelectronic devices(),(),(), in accordance with embodiments of the disclosure. The microelectronic devices(),(),() may have similar configurations to the microelectronic device(), within different high-power components(),(),() positioned within the cup-like structure formed by the combination of the heat sink structures(),(),() and the contact structures(),(),(). In the embodiments illustrated in, the high-power components(),(),() may comprise different types of electrostatic discharge (ESD) diodes than one another. In the embodiment illustrated in, the high-power componentincludes an n-well ESD diode. In the embodiment illustrated in, the high-power componentincludes a p-well ESD diode. In the embodiment illustrated in, the high-power componentincludes an ESD silicon-controlled rectifier (SCR).

5 FIG.A 5 FIG.A 500 510 510 512 514 512 514 512 514 520 502 520 512 514 516 518 518 520 520 516 a a a a a a a a a a a a a a a a. Referring to, the microelectronic devicehas a high-power componentincluding an n-well ESD diode. The high-power componentincludes two types of electrodes,that are configured as anodes and cathodes. The electrodesmay be configured as anodes, and the electrodesmay be configured as cathodes. The electrodes,are substantially surrounded by an n-wellincluding n-type doped semiconductor material of the control logic structure. The n-wellis interposed between the electrodes,and each of the heat sink structuresand the contact structures. As illustrated in, the contact structuresare positioned laterally outside the n-wellin the X-direction. Similarly, a horizontal area of the n-wellis within a horizontal area of the heat sink structure

5 FIG.A 520 510 502 502 520 506 502 502 520 518 510 a a a a a a a a. As illustrated in, the n-wellof the high-power componentis vertically positioned within the control logic structure. Additional semiconductor material and dielectric material of the control logic structureis positioned between the n-welland the back sideof the control logic structure. Additional semiconductor material of the control logic structurealso is positioned horizontally between the n-welland the contact structureshorizontally neighboring the high-power component

5 FIG.A 516 504 516 502 502 504 510 516 a a a a a a a a. In the embodiment illustrated in, the heat sink structureis vertically positioned within the memory array structure. In other embodiments, the heat sink structureis vertically positioned within the control logic structure, or is vertically positioned within both the control logic structureand the memory array structure. A horizontal area of the high-power componentis at least partially (e.g., substantially) contained within a horizontal area of the heat sink structure

5 FIG.B 5 FIG.B 500 510 510 512 514 512 514 b b b b b b b Referring next to, the microelectronic devicehas a high-power componentincluding a p-well ESD diode. The high-power componentincludes two types of electrodes,that are configured as anodes and cathodes. In the embodiment illustrated in, the electrodesare configured as anodes, and the electrodesare configured as cathodes.

512 514 502 502 512 514 516 518 512 514 516 b b b b b b b b b b b. The electrodes,are at least partially surrounded by semiconductor material of the control logic structure. The semiconductor material of the control logic structureis interposed between the electrodes,and each of the heat sink structuresand the contact structures. Each of the electrodes,may be positioned within a horizonal area of the heat sink structure

5 FIG.B 516 504 516 502 502 504 510 516 b b b b b b b b. In the embodiment illustrated in, the heat sink structureis vertically positioned within the memory array structure. In additional embodiments, the heat sink structureis vertically positioned within the control logic structure, or is vertically positioned within both the control logic structureand the memory array structure. A horizontal area of the high-power componentis at least partially (e.g., substantially) contained within a horizontal area of the heat sink structure

5 FIG.C 5 FIG.C 500 510 510 512 514 512 514 510 524 526 524 524 526 526 514 524 522 522 502 c c c c c c c c c c. Referring next to, the microelectronic devicehas a high-power componentincluding an ESD SCR. The high-power componentincludes two electrodes,individually configured as an anode or a cathode. In the embodiment illustrated in, the electrodeis configured as a cathode, and the electrodeis configured as an anode. The high-power componentalso includes two gates,. The gateis configured as an anode gate, and the gateis configured as a cathode gate. The electrodeand the anode gateare substantially surrounded by an n-well. The n-wellcomprises an n-type doped semiconductor material of the control logic structure

512 526 502 502 522 502 512 514 516 518 502 524 526 516 518 502 522 516 518 512 514 524 526 522 516 c c c c c c c c c c c c c c c c c. The electrodeand the cathode gateare at least partially surrounded by additional semiconductor material of the control logic structure. The additional semiconductor material of the control logic structurealso partially surrounds the n-well. The additional semiconductor material of the control logic structureis interposed between the electrodes,and each of the heat sink structuresand the contact structures. The additional semiconductor material of the control logic structureis also interposed between the gates,and each of the heat sink structuresand the contact structures. The additional semiconductor material of the control logic structureis further interposed between the n-welland each of the heat sink structuresand the contact structures. The electrodes,, the gates,, and the n-wellare respectively positioned within a horizontal area of the heat sink structure

5 FIG.C 516 504 516 502 502 504 510 516 c c c c c c c c. In the embodiment illustrated in, the heat sink structureis vertically positioned within the memory array structure. In other embodiments, the heat sink structureis vertically positioned within the control logic structure, or is vertically positioned within both the control logic structureand the memory array structure. A horizontal area of the high-power componentis at least partially (e.g., substantially) contained within a horizontal area of the heat sink structure

5 FIG.D 5 FIG.B 5 FIG.D 5 FIG.D 5 FIG.B 5 FIG.A 5 FIG.C 500 502 504 516 518 512 514 510 500 500 500 b b b b b b b b b a c illustrates a simplified, partial top down view of the microelectronic deviceof. In, the control logic structureand the memory array structureare not shown, so as to more clearly illustrate horizontal arrangements, in both the X-direction and the Y-direction, of the heat sink structure, the contact structures, and the electrodes,of the high-power component. Whileillustrates the microelectronic deviceof, it will be understood that a similar configuration may be included in the microelectronic devices() and().

5 FIG.D 516 528 530 532 530 512 514 530 512 514 510 532 512 514 532 512 514 b b b b b b b b b b. In the embodiment illustrated in, the heat sink structureincludes a mesh structurehaving lateral bandsand longitudinal bands. The lateral bandsextend in the X-direction and run perpendicular to the electrodes,. The lateral bandsindividually vertically underlie (e.g., in the Z-direction) and horizontally extend (e.g., in the X-direction) across multiple electrodes,of the high-power component. The longitudinal bandsextend in the Y-direction, and run parallel to the electrodes,. Individual longitudinal bandsmay not horizontally extend, in X-direction, across more than one of the electrodes,

5 FIG.D 5 FIG.D 530 532 534 516 516 534 530 532 516 500 516 534 516 b b b b b b As shown in, the lateral bandsand the longitudinal bandsmay define filled openingswithin the heat sink structure. A relationship between a horizontal area of the heat sink structureand cumulative horizontal areas of the filled openingsbetween the lateral bandsand the longitudinal bandsmay define a total horizontal coverage percentage of the heat sink structurerelative to the horizontal area of the microelectronic deviceoccupied by the combination of the heat sink structureand the filled openings. For example, in the embodiment illustrated in, the heat sink structurehas a horizontal coverage percentage of about 50 percent (%).

534 504 502 516 504 534 530 532 302 302 310 310 302 302 b b b b a b a c a c 5 FIG.B 3 3 FIGS.A andC 3 3 FIGS.A andC 3 3 FIGS.A andC The filled openingsmay be occupied with semiconductor material of the memory array structureor the control logic structure, depending on where the heat sink structureis vertically positioned. For example, in the embodiment illustrated in, semiconductor material of the memory array structureoccupies the filled openingsbetween the lateral bandsand the longitudinal bands. In other embodiments, semiconductor material of associated control logic structures (e.g., the control logic structures,previously described with reference to) may occupy filled openings defined by associated heat sink structures (e.g., the heat sink structures,previously described with reference to) vertically positioned within an associated control logic structure (e.g., the control logic structures,previously described with reference to).

518 516 518 530 516 532 516 518 500 b b b b b b b. 5 FIG.D The contact structuresmay form columns vertically extending (e.g., in the Z-direction) from intersection points about the perimeter of the heat sink structure. In the embodiment illustrated in, a contact structurevertically extends from each intersection between the lateral bandsand the perimeter of the heat sink structureand from each intersection between the longitudinal bandsand the perimeter of the heat sink structure. As discussed above, the contact structuresvertically extend in the Z-direction through the microelectronic device

6 6 FIGS.A andB 6 FIG.A 6 FIG.B 4 FIG. 6 FIG.A 6 FIG.B 6 FIG.A 6 FIG.B 6 FIG.A 6 FIG.B 6 6 FIGS.A andB 6 FIG.A 6 FIG.B 6 FIG.A 6 FIG.B 600 600 600 600 400 610 610 616 616 618 618 610 610 610 610 a b a b a b a b a b a b a b illustrate simplified, partial vertical cross-sections of different microelectronic devices(),(), in accordance with embodiments of the disclosure. The microelectronic devices,may have similar configurations to the microelectronic device(), but with different high-power components(),() positioned within a horizontal area of the cup-like structure formed by the combination of the heat sink structures(),() and the contact structures(),(). In the embodiments illustrated in, the high-power components(),() may be different types of ESD power clamps. In the embodiment illustrated in, the high-power componentis an ESD NMOS power clamp. In the embodiment illustrated in, the high-power componentis an ESD PMOS power clamp.

6 FIG.A 6 FIG.A 600 610 610 612 614 612 602 602 612 612 616 618 616 604 604 616 612 a a a a a a a a a a a a a a a a a. Referring to, the microelectronic devicehas a high-power componentincluding an ESD NMOS power clamp. The high-power componentincludes a string of diodesjoined together by connectors. The string of diodesis at least partially surrounded by semiconductor material of the control logic structure, such that the semiconductor material of the control logic structureis interposed between each of the diodesin the string of diodesand a heat sink effectively formed by the heat sink structureand the contact structures. In the embodiment illustrated in, the heat sink structureis vertically positioned within the memory array structure, such that semiconductor material of the memory array structureis interposed between the heat sink structureand the string of diodes

612 618 602 612 612 618 612 616 a a a a a a a a. The entire string of diodesmay be horizontally positioned, in the X-direction, between the contact structureshorizontally neighboring one another in the X-direction. The semiconductor material of the control logic structuremay be horizontally positioned, in the X-direction, between end diodesof the string of diodesand the contact structures. The string of diodesmay be at least partially (e.g., substantially) contained within a horizontal area of the heat sink structure

6 FIG.B 6 FIG.B 600 610 610 612 614 612 602 602 612 612 616 618 616 604 604 616 612 b b b b b b b b b b b b b b b b b. Referring next to, the microelectronic devicehas a high-power componentincluding an ESD PMOS power clamp. The high-power componentincludes a string of diodesjoined together by connectors. The string of diodesmay be at least partially surrounded by semiconductor material of the control logic structure, such that the semiconductor material of the control logic structureis interposed between each of the diodesin the string of diodesand a heat sink effectively formed by the heat sink structureand the contact structures. In the embodiment illustrated in, the heat sink structureis vertically positioned within the memory array structure, such that semiconductor material of the memory array structureis interposed between the heat sink structureand the string of diodes

610 600 620 612 620 602 620 612 616 618 618 620 620 616 b b b b b b b b b. 6 FIG.B The high-power componentof the microelectronic deviceincludes an n-wellat least partially surrounding the string of diodes. The n-wellcomprises n-type doped semiconductor material of the control logic structure. The n-wellis interposed between the string of diodesand each of the heat sink structuresand the contact structures. As illustrated in, the contact structuresare horizontally positioned outside the n-well. A horizontal area of the n-wellmay be at least partially (e.g., substantially) within a horizontal area of the heat sink structure

6 FIG.B 620 610 602 602 620 606 602 602 620 618 b b b b b b b As illustrated in, the n-wellof the high-power componentis vertically positioned within the control logic structure, such that semiconductor material of the control logic structureis interposed between the n-welland the back sideof the control logic structure. Semiconductor material of the control logic structuremay be positioned between the n-welland the contact structuresin the X-direction.

6 FIG.C 6 FIG.A 6 FIG.C 6 FIG.C 6 FIG.A 6 FIG.B 600 602 604 616 618 612 614 610 600 600 a a a a a a a a a b illustrates a simplified, partial top down view of the microelectronic deviceof. In, the control logic structureand the memory array structureare not shown so as to more clearly illustrate the horizontal arrangements, in both the X-direction and the Z-direction, of the heat sink structure, the contact structures, the diodes, and the connectorsof the high-power component. Whileillustrates the microelectronic deviceof, it will be understood that a similar configuration may be included in the microelectronic deviceillustrated in.

6 FIG.C 616 622 624 626 624 612 614 624 612 614 610 626 612 614 626 612 614 a a a a a a a a a a. Referring to, the heat sink structureincludes a mesh structurehaving lateral bandsand longitudinal bands. The lateral bandsextend in the X-direction and run perpendicular to the diodesand connectors. The lateral bandsmay respectively vertically underlie (e.g., in the Z-direction) and horizontally extend (e.g., in the X-direction) across multiple diodesand connectorsof the high-power component. The longitudinal bandsmay horizontally extend in the Y-direction and may run parallel to the diodesand the connectors. The longitudinal bandsmay respectively vertically underlie (e.g., in the Z-direction) and horizontally extend (e.g., in the Y-direction) through a horizontal area of the individual diodeand/or individual connectors

624 626 622 628 616 628 624 626 616 600 616 628 616 a a a a a 6 FIG.C The lateral bandsand the longitudinal bandsof the mesh structuredefine filled openings. A relationship between a horizontal area of the heat sink structureand cumulative horizontal areas of the filled openingsbetween the lateral bandsand the longitudinal bandsmay define a total horizontal coverage percentage of the heat sink structurerelative to the horizontal area of the microelectronic deviceoccupied by the combination of the heat sink structureand the filled openings. For example, in the embodiment illustrated in, the heat sink structurehas a horizontal coverage percentage of about 50 percent (%).

628 604 602 616 604 628 624 626 302 302 310 310 302 302 a a a a a b a c a c 6 FIG.A 3 3 FIGS.A andC 3 3 FIGS.A andC 3 3 FIGS.A andC The filled openingsmay be occupied by semiconductor material of the memory array structureor the control logic structure, depending on where the heat sink structureis vertically positioned. For example, in the embodiment illustrated in, the semiconductor material of the memory array structureoccupies the filled openingsbetween the lateral bandsand the longitudinal bands. In other embodiments, semiconductor material of an associated control logic structure (e.g., the control logic structures,previously described with reference to) may occupy filled openings defined by associated heat sink structures (e.g., the heat sink structures,previously described with reference to) vertically positioned within an associated control logic structure (e.g., the control logic structures,previously described with reference to).

618 616 618 624 616 626 616 618 600 a a a a a a a. 6 FIG.C The contact structuresmay form columns vertically extending (e.g., in the Z-direction) from intersection points about the perimeter of the heat sink structure. In the embodiment illustrated in, a contact structurevertically extends from each intersection between the lateral bandsand the perimeter of the heat sink structure, and from each intersection between the longitudinal bandsand the perimeter of the heat sink structure. As discussed above, the contact structuresrespectively vertically extend in the Z-direction through the microelectronic device

7 7 FIGS.A-F 7 7 FIGS.A-F 7 7 FIGS.A-F 7 7 FIGS.A-F 716 700 700 716 718 712 714 710 700 710 712 714 100 300 300 300 400 500 500 500 600 600 a b c a b c a b illustrate simplified, partial top-down views of a different configurations for microelectronic device, in accordance with embodiments of the disclosure.shown different arrangements of a heat sink structurewithin the microelectronic device. In each of, the microelectronic deviceis illustrated without a control logic structure or memory logic structure to more clearly illustrate the lateral arrangements, in both the X-direction and the Y-direction, of the heat sink structure, the contact structures, and the electrodes,of the high-power component. Whileillustrate a microelectronic deviceincluding a high-power componentincluding the electrodesand, it will be understood that similar features can be included in any of the microelectronic devices,,,,,,,,,previously described herein.

7 FIG.A 716 710 716 720 710 710 720 718 720 716 722 720 722 710 a a Referring to, the heat sink structureis positioned vertically beneath a high-power component. The heat sink structureincludes a perimeter structureextending around the high-power component, such that the high-power componentis horizontally surrounded by the perimeter structureboth in the X-direction and in the Y-direction. The contact structuresextend vertically in the Z-direction from several points along the perimeter structure. The heat sink structurealso includes bandsthat horizontally extend in parallel in the Y-direction between horizontal ends of the perimeter structure. The bandsvertically underlie the high-power componentin the Z-direction.

722 712 714 722 712 714 722 712 714 722 712 714 722 712 714 422 722 712 714 700 722 712 714 722 712 714 a a a a a a a a 7 FIG.A 7 FIG.A 4 FIG. The bandshorizontally extend parallel to the electrodes,. In the embodiment illustrated in, the bandshave a 0% horizontal offset relative to the electrodes,in the X-direction, such that the bandsare substantially horizontally aligned with the electrodes,in the X-direction. In embodiments where the offset between the bandsand the electrodes,is 0%, such as the embodiment of, a distance between the bandsand the electrodes,is the vertical distance(). In some embodiments, the bandsare horizontally offset from the electrodes,in the X-direction, so as to accommodate other structures in the microelectronic deviceor to resolve other design-specific requirements. As the horizontal offset between the bandsand the electrodes,in the X-direction increases, the total distance between the bandsand the electrodes,also increases.

7 FIG.B 7 FIG.A 7 FIG.A 7 FIG.B 716 722 712 714 722 720 722 722 712 714 722 722 712 714 722 712 714 722 712 714 722 712 714 b b a b a b b b b Referring next to, the heat sink structureincludes bandshaving a 50% horizontal offset relative to the electrodes,in the X-direction. The bandshorizontal extend in parallel in the Y-direction between the horizontal ends of the perimeter structure, similar to the bandspreviously described with reference to. The bandsalso horizontally extend parallel to the electrodes,, similar to the bandspreviously described with reference to. However, due to the 50% horizontal offset, the bandsare not substantially horizontally aligned with the electrodes,in the X-direction. Rather, the bandshave substantially no horizontal overlap with the electrodes,in the X-direction. The bandsinare positioned within horizontal areas of gaps between the electrodes,. The total distance between the bandsand the electrodes,may be found in the following formula:

722 712 714 722 712 714 722 712 714 722 712 714 b b b b where D is the total distance between the bandsand the electrodes,; V is the vertical offset between the bandsand the electrodes,; and L is the horizontal offset between the bandsand the electrodes,. In embodiments wherein a horizontal offset in the X-direction is utilized to accommodate other features, the vertical offset in the Z-direction may be decreased to maintain an effective total distance between the bandsand the electrodes,.

3 FIG.C 7 FIG.C 7 FIG.C 7 FIG.A 7 FIG.C 722 720 722 712 714 722 712 714 712 714 722 712 714 722 712 714 722 712 714 712 714 722 712 714 716 722 712 714 712 714 722 712 714 c c c c c c c a c Referring to, in some embodiments, bandshorizontally extend in parallel in the X-direction between ends of the perimeter structure. The bandsillustrated inhorizontally extend substantially perpendicular to the electrodes,. The bandspass beneath multiple of the electrodes,in the X-direction, and respectively are not substantially aligned with an individual one of the electrodes,in the X-direction. In other embodiments, the bandsmay horizontally extend at an angle (e.g., an acute angle, an obtuse angle) relative to the electrodes,. In the embodiment illustrated in, the bandshorizontally extend at a 90° angle relative to the electrodes,. In other embodiments, the bandsmay extend at an angle between 90° and 1°, relative to the electrodes,, such as at a 45° angle relative to the electrodes,. As the angle between the bandsand the electrodes,changes, the effective coverage of the heat sink structuremay also change. For example, the bandsofthat horizontally extend at an angle of 0° relative to the electrodes,and that have substantially 0% horizontal offset relative to the electrodes,may have a greater effective coverage than the bandsofthat horizontally extend at an angle of 90° relative to the electrodes,.

716 720 716 722 722 722 722 722 722 716 7 7 FIGS.A-C 7 7 FIGS.D-E a b c a b c Another aspect of the heat sink structurethat may influence effective coverage is a coverage percentage, which is the percentage of the horizontal area having horizontal boundaries defined by the perimeter structurecovered by the heat sink structure. In the embodiments illustrated in, the horizontal area defined by the spaces between the bands,,is larger than the horizontal area defined by the bands,,. Therefore, the coverage percentage is less than about 50%, such as within a range from about 20% to about 50%.illustrate configurations having different coverage percentages that are equal to or greater than about 50%. Thus, different embodiments of the heat sink structuremay define a coverage percentage within a range from about 20% to about 100%, such as within a range from about 25% to about 100%, from about 50% to about 100%, or from about 50% to about 75%.

7 FIG.D 7 FIG.D 716 724 710 724 710 712 714 712 714 710 724 Referring to, the heat sink structureincludes a plateproviding 100% coverage of the high-power component. The platefully covers the horizontal area of the high-power component, including both the total horizontal area of the electrodes,and the total horizontal area of the gaps between the electrodes,. As illustrated in, the high-power componentis substantially contained within the horizontal area of the plate.

718 724 718 724 718 724 724 718 724 718 718 7 FIG.D The contact structuresextend vertically from the perimeter of the plate. In the embodiment illustrated in, the contact structuresare slot structures. Slot structures are plate structures or wall structures having an elongated rectangular horizonal cross-section and extending vertically from the plate. In additional embodiments, one or more of the contact structuresare column structures (e.g., circular column structures, square column structures) vertically extending from the perimeter region of the plate. For example, one or more sides of the platemay include contact structuresthat are columns, and other sides of the platemay include contact structures that are slot structures. In another example, the contact structuresmay include multiple slot structures with gaps horizontally between the horizontally neighboring contact structures.

7 FIG.E 7 FIG.E 716 726 728 730 728 730 732 726 720 716 726 716 726 720 716 a a a a a Referring next to, the heat sink structureincludes a mesh structureformed from first bandsand second bands. The first bandsand the second bandsmay define openingsin the mesh structure. The coverage percentage is the ratio of the total horizontal area within the perimeter structureof the heat sink structureto the total horizontal area of the mesh structureof the heat sink structure. In the embodiment illustrated in, the mesh structurecovers about 75% of the horizontal area bounded by the perimeter structureof the heat sink structure.

7 FIG.F 7 FIG.F 716 726 728 730 728 730 732 726 726 720 716 b b b b b Referring to, the heat sink structureincludes a mesh structureformed from first bandsand second bands. The first bandsand the second bandsdefine openingsin the mesh structure. In the embodiment illustrated in, the mesh structurecovers about 50% of the horizontal area bounded by the perimeter structureof the heat sink structure.

7 7 FIGS.E andF 7 FIG.E 7 FIG.F 7 FIG.E 7 FIG.F 7 FIG.E 7 FIG.F 7 FIG.E 7 FIG.F 7 FIG.E 7 FIG.F 7 FIG.E 7 FIG.F 7 FIG.E 7 FIG.F 7 FIG.E 7 FIG.F 7 FIG.E 7 FIG.F 728 728 730 730 728 730 728 730 728 730 728 728 730 730 716 728 728 730 730 716 728 728 730 730 a b a b a a b b a a a b a b a b a b a b a b In the embodiments illustrated in, the difference in the coverage percentages is created by a different number of first bands(),() and second bands(),(). In the embodiment illustrated in, there are a greater number of first bandsand second bandsthan the number of first bandsand second bandsin the embodiment of. The greater number of first bandsand second bandsresult in a greater amount of coverage. In other embodiments, horizontal dimensions of the first bands(),() and the second bands(),() may be changed between embodiments to create different coverages. For example, two heat sink structuresmay have a same number of first bands(),() and/or second bands(),(), with one of the heat sink structureshaving a greater coverage percentage because of the differences in the horizontal widths in the Y-direction of the first bands() and the first bands() relative to one another, and/or differences in the horizontal widths in the X-direction the second bands() and the second bands() relative to one another.

100 300 300 300 400 500 500 500 600 600 700 800 800 800 802 802 100 300 300 300 400 500 500 500 600 600 700 a b c a b c a b a b c a b c a b 8 FIG. 1 7 FIGS.throughF Microelectronic devices (e.g., the microelectronic devices,,,,,,,,,, and) according to embodiments of the disclosure may be included in embodiments of electronic systems of the disclosure. For example,is a block diagram of an electronic system, in accordance with embodiments of the disclosure. The electronic systemmay comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an iPAD® or SURFACE® tablet, an electronic book, a navigation device, etc. The electronic systemincludes at least one memory device. The memory devicemay include, for example, an embodiment of a semiconductor device package including one or more of the microelectronic devices previously described herein (e.g., the microelectronic devices,,,,,,,,,, andpreviously described with reference to).

800 804 804 800 806 800 800 808 806 808 800 806 808 802 804 The electronic systemmay further include at least one electronic signal processor device(often referred to as a “microprocessor”). The electronic signal processor devicemay, optionally, include an embodiment of one or more of a microelectronic device and a microelectronic device structure previously described herein. The electronic systemmay further include one or more input devicesfor inputting information into the electronic systemby a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic systemmay further include one or more output devicesfor outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input deviceand the output devicemay comprise a single touchscreen device that can be used both to input information to the electronic systemand to output visual information to a user. The input deviceand the output devicemay communicate electrically with one or more of the memory deviceand the electronic signal processor device.

Thus, embodiments of the disclosure include a microelectronic device. The microelectronic device includes a control logic structure including a high-power component. The microelectronic device also includes a memory array structure vertically offset from and attached to the control logic structure, the memory array structure comprising an array of memory cells. The microelectronic device further includes a heat sink structure vertically underlying and horizontally overlapping the high-power component, the heat sink structure comprising a material having higher thermal conductivity than semiconductor material of the control logic structure.

Another embodiment of the disclosure includes an electronic system. The electronic system includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device includes a control logic structure including a high-power component. The memory device also includes a memory array structure vertically underlying and bonded to control logic structure. The memory device further includes a heat sink structure vertically interposed between the high-power component of the control logic structure and a memory array of the memory array structure, the heat sink structure at least partially within a horizontal area of the high-power component of the control logic structure. The memory device also includes contact structures extending vertically through the control logic structure and the memory array structure, the contact structures respectively in physical contact with a perimeter section of the heat sink structure.

Other embodiments of the disclosure include a memory device. The memory device includes a control logic structure including an electrostatic discharge (ESD) protection device. The memory device further includes a memory array structure vertical offset from and dielectric-to-dielectric bonded coupled to the control logic structure, the memory array structure comprising non-volatile memory cells. The memory device also includes a heat sink structure within a horizontal area of the ESD protection device of the control logic structure and vertically interposed between the ESD protection device of the control logic structure and at least a portion of the memory array structure, the heat sink structure comprising bands horizontally extending in parallel in a first direction ad horizontal overlapping electrodes of the ESD protection device in a second direction orthogonal to the second direction.

The structures and devices of the disclosure may facilitate enhanced heat dissipation for high-power components relative to conventional structures and devices. Dissipating the heat from the high-power components may facilitate reductions in volumes of semiconductor material employed in devices of the disclosure relative to conventional devices. Reducing the volume of semiconductor material may facilitate the production of relatively thin devices and/or the inclusion of higher power components and/or a greater number of high-power components. In addition, reductions in space requirements and the inclusion of more high-power components may facilitate reductions in space requirements within the associated devices and/or the inclusion of more functional components with the associated devices.

The embodiments of the disclosure described above and illustrated in the accompanying drawing figures do not limit the scope of the invention, since these embodiments are merely examples of embodiments of the invention, which are defined by the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of this disclosure. Indeed, various modifications of the present disclosure, in addition to those shown and described herein, such as alternative useful combinations of the elements described, may become apparent to those skilled in the art from the description. Such modifications and embodiments are also intended to fall within the scope of the appended claims and their legal equivalents.