Power Amplifier Circuit and Power Amplification Method

This application is a continuation of International Application No. PCT/JP2024/004769, filed Feb. 13, 2024, which claims priority to Japanese Patent Application No. Application No. 2023-057511, filed Mar. 31, 2023, the contents of each of which are hereby incorporated by reference in their entireties.

The present disclosure relates to a power amplifier circuit and a power amplification method.

In recent years, power-added efficiency has been improved by applying tracking technologies to power amplifier circuits. U.S. Pat. No. 8,829,993 discloses a tracker circuit for digital envelope tracking (D-ET) in which a power amplifier circuit is supplied with a power supply voltage whose level changes discretely over time based on an envelope signal (hereinafter simply referred to as “multiple discrete voltages”). Moreover, U.S. Patent No. 10, 686, 407 discloses a tracker circuit for symbol power tracking (SPT) in which a power amplifier circuit is supplied with multiple discrete voltages based on symbols.

In the technologies described in the above-noted patent documents, digital pre-distortion (DPD) is sometimes used to reduce nonlinear distortion caused by a power amplifier circuit operating in a nonlinear region. In DPD, the input signal of the power amplifier circuit is distorted in advance in order to cancel out the nonlinear distortion caused by the power amplifier circuit.

However, when multiple discrete voltages are supplied to the power amplifier circuit, the reduction of nonlinear distortion achieved by DPD may be limited.

Accordingly, the exemplary aspects of the present disclosure provide a power amplifier circuit and a power amplification method that reduces nonlinear distortion.

According to an exemplary aspect, a power amplifier circuit is provided that includes a first power amplifier configured to amplify a radio frequency signal using multiple discrete voltages that includes a first power supply voltage and a second power supply voltage higher than the first power supply voltage; a second power amplifier configured to amplify the radio frequency signal amplified by the first power amplifier using multiple discrete voltages; a first bias circuit configured to supply a first bias voltage to the first power amplifier when the first power supply voltage is supplied to the first power amplifier, and to supply a second bias voltage lower than the first bias voltage to the first power amplifier when the second power supply voltage is supplied to the first power amplifier; and a second bias circuit configured to supply a third bias voltage to the second power amplifier when the first power supply voltage is supplied to the second power amplifier, and to supply a fourth bias voltage higher than the third bias voltage to the second power amplifier when the second power supply voltage is supplied to the second power amplifier.

According to another exemplary aspect, a power amplifier circuit is provided that includes a first power amplifier configured to amplify a radio frequency signal using multiple discrete voltages including a first power supply voltage and a second power supply voltage higher than the first power supply voltage; a second power amplifier configured to amplify the radio frequency signal amplified by the first power amplifier using multiple discrete voltages; a first bias circuit configured to supply a bias voltage to the first power amplifier; a second bias circuit configured to supply a first bias voltage to the second power amplifier when the first power supply voltage is supplied to the second power amplifier and to supply a second bias voltage higher than the first bias voltage to the second power amplifier when the second power supply voltage is supplied to the second power amplifier; and a variable attenuation circuit connected to an input terminal of the first power amplifier or connected between an output terminal of the first power amplifier and an input terminal of the second power amplifier. The variable attenuation circuit is adjusted to a first attenuation when the first power supply voltage is supplied to the first power amplifier and is adjusted to a second attenuation greater than the first attenuation when the second power supply voltage is supplied to the first power amplifier.

Moreover, in another exemplary aspect, a power amplification method for amplifying a radio frequency signal using multiple discrete voltages is provided that includes receiving a first power supply voltage included in the multiple discrete voltages; supplying a first bias voltage to a first power amplifier based on the first power supply voltage; amplifying a first radio frequency signal in the first power amplifier using the first power supply voltage and the first bias voltage; supplying a third bias voltage to a second power amplifier based on the first power supply voltage; amplifying the first radio frequency signal amplified in the first power amplifier in the second power amplifier using the first power supply voltage and the third bias voltage; receiving a second power supply voltage that is included in the multiple discrete voltages and is higher than the first power supply voltage; supplying a second bias voltage, which is lower than the first bias voltage, to the first power amplifier based on the second power supply voltage; amplifying a second radio frequency signal in the first power amplifier using the second power supply voltage and the second bias voltage; supplying a fourth bias voltage, which is higher than the third bias voltage, to the second power amplifier based on the second power supply voltage; and amplifying the second radio frequency signal amplified in the first power amplifier in the second power amplifier using the second power supply voltage and the fourth bias voltage.

According to the exemplary aspects of the present disclosure, nonlinear distortion is reduced.

Hereafter, exemplary embodiments will be described in detail with reference to the drawings. The embodiments described hereafter each illustrate a comprehensive or specific example of the present disclosure. The numerical values, shapes, materials, components, the arrangement of the components and the way in which the components are connected, steps, and the order of steps illustrated in the following embodiments are merely examples and are not intended to limit the exemplary aspects of the present disclosure.

It is noted that the drawings are schematic diagrams in which certain elements are emphasized or omitted or their proportions are adjusted as appropriate, the drawings are not necessarily illustrated in a strictly accurate manner, and the actual shapes, positional relationships, and proportions may be different. In the drawings, configurations that are substantially the same as each other may be denoted by the same symbols and repeated description thereof may be omitted or simplified.

In the drawings referred to below and for purposes of the present disclosure, an x axis and a y axis are mutually perpendicular axes on a plane that is parallel to main surfaces of a module substrate. Specifically, when the module substrate has a rectangular shape in plan view, the x-axis is parallel to a first edge of the module substrate and the y-axis is parallel to a second edge of the module substrate that is perpendicular to the first edge. In addition, a z axis is an axis that is perpendicular to the main surfaces of the module substrate, and a positive z axis direction indicates an upward direction and a negative z axis direction indicates a downward direction.

In the following description of circuit configurations, the term “connected” includes not only the case where the components are directly connected by connection terminals and/or wiring conductors, but also the case where the components are electrically connected via other circuit elements. The phrase “directly connected” can indicate directly connected by a connection terminal and/or a wiring conductor without the interposition of other circuit elements. The phrase “C is connected between A and B” indicates that one end of C is connected to A and the other end of C is connected to B, and indicates that C is disposed in series on a path connecting A and B. The phrase “path connecting A and B” indicates a path comprising a conductor that electrically connects A to B.

In the following descriptions of circuit configurations, the term “terminal” refers to a point where a conductor in an element ends. Note that, when the impedance of the conductor between elements is sufficiently low, a terminal is interpreted not only as a single point, but also as any point on the conductor between elements or the entire conductor.

In the following descriptions of circuit layouts, the expression “C is disposed closer to A than B” can indicate that the distance between A and C is shorter than the distance between A and B. Here, the expression “the distance between A and B” indicates the shortest distance between A and B. In other words, “the distance between A and B” indicates the length of the shortest line segment among multiple line segments connecting any point on the surface of A and any point on the surface of B.

In addition, terms indicating the relationships between elements, such as “parallel” and “perpendicular”, terms indicating the shape of elements such as “rectangular”, and numerical ranges do not express only a strict meaning, but rather are intended to include substantially equivalent ranges, for example, differences of several percent as would be appreciated to one skilled in the art.

1 1 FIGS.A toC 1 1 FIGS.A toC First, as a technology for amplifying radio frequency signals with high efficiency, a tracking mode will be described in which a power amplifier is supplied with a power supply voltage that is dynamically adjusted over time based on the radio frequency signal. A “tracking mode” is a mode in which a power supply voltage applied to a power amplifier is dynamically adjusted. There are several types of tracking mode, but here, an APT mode, an A-ET mode, and a D-ET mode are described with reference to. In, the horizontal axis represents time and the vertical axis represents voltage. In addition, the thick solid line represents the power supply voltage, and the thin solid line (e.g., waveform) represents the modulated signal.

1 FIG.A is a graph illustrating an example of the transitions of the power supply voltage in the APT mode. The APT mode is a mode in which the power supply voltage is varied to multiple discrete voltage levels in units of one frame based on the average power.

According to an exemplary aspect, a frame refers to a unit forming a radio frequency signal (e.g., a modulated signal). For example, in fifth Generation New Radio (5GNR) and Long Term Evolution (LTE), a frame includes 10 subframes, each subframe includes multiple slots, and each slot includes multiple symbols. The subframe length is 1 ms, and the frame length is 10 ms according to the exemplary aspect.

It is noted that a mode in which the voltage level is changed in units of one frame or units larger than one frame based on the average power is called an APT mode, and is distinguished from a mode in which the voltage level is changed in units smaller than one frame (for example, units of subframe, slot, or symbol).

1 FIG.B is a graph illustrating an example of the transitions of the power supply voltage in the A-ET mode. The A-ET mode is a mode in which the power supply voltage is changed continuously based on an envelope signal. In the A-ET mode, the envelope of the modulated signal is tracked.

2 2 The envelope signal is a signal that indicates the envelope of the modulated signal. The envelope value is expressed, for example, as the square root of (I+Q). Here, (I, Q) represent a constellation point. A constellation point is a point that represents a digitally modulated signal on a constellation diagram. (I, Q) are determined, for example, by a baseband integrated circuit (BBIC) based on transmission information.

1 FIG.C is a graph illustrating an example of the transitions of the power supply voltage in the D-ET mode. The D-ET mode is a mode in which the power supply voltage is changed to multiple discrete voltage levels within a single frame based on an envelope signal. In the D-ET mode, the envelope of the modulated signal is tracked.

Embodiment 1 is described hereafter.

6 6 2 FIG. 2 FIG. First, the circuit configuration of a communication deviceaccording to this embodiment will be described with reference to.is a circuit configuration diagram of the communication deviceaccording to this exemplary embodiment.

2 FIG. 6 6 It is also noted thatdepicts an exemplary circuit configuration, and the communication devicemay be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the communication deviceprovided below is not to be interpreted as limiting.

6 6 6 The communication deviceaccording to this embodiment is implemented as a user terminal (user equipment (UE)) in a cellular network, and is typically a mobile phone, a smartphone, a tablet computer, a wearable device, or the like. Note that the communication devicemay also be implemented as an Internet of Things (IoT) sensor device, a medical/healthcare device, a car, an unmanned aerial vehicle (UAV) (so-called drone), or an automated guided vehicle (AGV). The communication devicemay also be implemented as a base station (BS) in a cellular network or an access point in a wireless local area network (WLAN).

2 FIG. 6 1 2 3 4 5 As illustrated in, the communication deviceincludes a power amplifier circuit, a tracker circuit, a radio frequency integrated circuit (RFIC), a BBIC, and an antenna.

1 3 1 The power amplifier circuitis a multi-stage amplifier circuit and can amplify a radio frequency signal supplied from the RFIC. The circuit configuration of the power amplifier circuitwill be described later.

2 1 1 The tracker circuitcan be configured to supply multiple discrete voltages to the power amplifier circuitas a power supply voltage (Vcc) based on a tracking mode applied to the power amplifier circuit. In this embodiment, the D-ET mode or SPT mode and the APT mode can be switched between and used as the tracking mode, but the tracking modes that can be used are not limited to these modes.

2 2 2 It is noted that, as the tracker circuit, an existing tracker circuitthat operates in the D-ET mode or SPT mode and APT mode can be used, and for example, the tracker circuit described in U.S. Pat. No. 8,829,993 and/or U.S. Pat. No. 10,686,407 can be used. Thus, it is noted that the tracker circuitis not limited to these tracker circuits as would be appreciated to one skilled in the art.

3 3 4 1 The RFICis an example of a signal processing circuit that is configured to process radio frequency signals. The RFICcan receive digital IQ signals from the BBICand supply a radio frequency signal to the power amplifier circuit.

3 4 Specifically, the RFICcan pre-distort the digital IQ signals supplied from the BBICbased on a DPD mathematical model. As the mathematical model, for example, a memoryless polynomial model, a memory polynomial model (MPM), a generalized memory polynomial model (GMP), or the like can be used, but the mathematical model is not limited to these mathematical models.

3 3 31 1 Then, the RFICcan convert the pre-distorted digital IQ signals into pre-distorted analog IQ signals. The RFICcan generate a radio frequency signal by performing quadrature modulation and up-conversion on the analog IQ signals. The generated radio frequency signal is supplied to a radio-frequency input terminalof the power amplifier circuit.

3 14 15 1 3 33 1 3 3 4 1 2 Furthermore, the RFICincludes a control unit that controls bias circuitsandand so forth of the power amplifier circuit. The control unit of the RFICcan supply digital control signals to a control terminalof the power amplifier circuit. It is noted that some or all of the functions of the control unit of the RFICmay be implemented outside the RFIC, for example, in the BBIC, the power amplifier circuit, or the tracker circuitas would be appreciated to one skilled in the art.

4 4 3 4 6 The BBICis a baseband signal processing circuit that is configured to perform signal processing using a frequency band lower than that of the radio frequency signals. The BBICdigitally modulates, for example, an image signal for image display and/or a bit sequence representing an audio signal for communication via a speaker and generates digital IQ signals. The generated digital IQ signals are supplied to the RFIC. It is noted that the BBICmay be omitted from the communication devicein an exemplary aspect.

5 30 1 1 6 5 6 6 5 The antennais connected to an antenna connection terminalof the power amplifier circuit, and can output the radio frequency signal amplified by the power amplifier circuitto the space outside the communication device. The antennamay be omitted from the communication devicein an exemplary aspect. Moreover, the communication devicemay further include one or more antennas in addition to the antenna.

1 1 11 12 14 15 17 19 20 21 2 FIG. Next, the circuit configuration of the power amplifier circuitaccording to this embodiment will be described with reference to. The power amplifier circuitincludes power amplifiersand, bias circuitsand, matching circuits (e.g., matching networks)to, a PA control circuit, and an inductor.

11 31 12 11 31 17 11 12 18 11 14 32 21 11 3 1 14 2 The power amplifieris an example of a “first power amplifier” according to the exemplary aspect, and is connected between the radio-frequency input terminaland the power amplifier. Specifically, an input terminal of the power amplifieris connected to the radio-frequency input terminalvia the matching circuit, and an output terminal of the power amplifieris connected to the input terminal of the power amplifiervia the matching circuit. Furthermore, the power amplifieris connected to the bias circuit, and is connected to a power supply voltage terminalvia the inductor. As a result, the power amplifiercan amplify a radio frequency signal (RFin) supplied from the RFICusing a bias voltage (Vbe) supplied from the bias circuitand the power supply voltage (Vcc) supplied from the tracker circuit.

12 11 30 12 11 18 12 30 19 12 15 32 21 12 11 2 15 2 The power amplifieris an example of a “second power amplifier” according to the exemplary aspect, and is connected between the power amplifierand the antenna connection terminal. Specifically, the input terminal of the power amplifieris connected to the output terminal of the power amplifiervia the matching circuit, and the output terminal of the power amplifieris connected to the antenna connection terminalvia the matching circuit. Furthermore, the power amplifieris connected to the bias circuit, and is connected to the power supply voltage terminalvia the inductor. As a result, the power amplifiercan amplify the radio frequency signal amplified by the power amplifierusing a bias voltage (Vbe) supplied from the bias circuitand the power supply voltage (Vcc) supplied from the tracker circuit.

14 11 14 1 11 14 1 11 14 1 3 FIG.A 3 FIG.B The bias circuitis an example of a “first bias circuit” according to the exemplary aspect, and is connected to the power amplifier. The bias circuitcan supply the bias voltage (Vbe) to the power amplifier. The bias circuitcan change the bias voltage (Vbe) in accordance with the power supply voltage (Vcc) supplied to the power amplifier. Details of the bias circuitand the bias voltage (Vbe) will be described later usingand.

15 12 15 2 12 15 2 12 15 2 4 FIG.A 4 FIG.B The bias circuitis an example of a “second bias circuit” according to the exemplary aspect, and is connected to the power amplifier. The bias circuitcan supply a bias voltage (Vbe) to the power amplifier. The bias circuitcan change the bias voltage (Vbe) in accordance with the power supply voltage (Vcc) supplied to the power amplifier. Details of the bias circuitand the bias voltage (Vbe) will be described later usingand.

17 31 11 17 31 11 17 31 11 17 17 1 The matching circuitis connected between the radio-frequency input terminaland the power amplifier. Alternatively, the matching circuitmay be connected between the path between the radio-frequency input terminaland the power amplifier, and the ground. The matching circuitis an impedance matching circuit and can achieve impedance matching between the radio-frequency input terminaland the input terminal of the power amplifier. The matching circuitmay comprise, for example, an inductor and/or a capacitor, or may comprise of a transformer. It is noted that the matching circuitmay be omitted from the power amplifier circuitin an exemplary aspect.

18 11 12 18 11 12 18 11 12 18 18 1 The matching circuitis connected between the power amplifiersand. Alternatively, the matching circuitmay be connected between the path between the power amplifiersand, and the ground. The matching circuitis an impedance matching circuit and can achieve impedance matching between the output terminal of the power amplifierand the input terminal of the power amplifier. The matching circuitmay comprise, for example, an inductor and/or a capacitor, or may comprise a transformer. The matching circuitmay be omitted from the power amplifier circuitin an exemplary aspect.

19 12 30 19 12 30 19 12 30 19 19 1 The matching circuitis connected between the power amplifierand the antenna connection terminal. Alternatively, the matching circuitmay be connected between the path between the power amplifierand the antenna connection terminal, and the ground. The matching circuitis an impedance matching circuit, and can achieve impedance matching between the output terminal of the power amplifierand the antenna connection terminal. The matching circuitmay comprise, for example, an inductor and/or a capacitor, or may comprise a transformer. The matching circuitmay be omitted from the power amplifier circuitin an exemplary aspect.

20 33 3 33 20 14 15 20 14 15 20 1 The PA control circuitis connected to the control terminal, and can receive digital control signals from the RFICvia the control terminal. The PA control circuitcan control the bias circuitsandbased on the digital control signal. For example, the PA control circuitcan control the bias circuitsandin units of a frame of a radio frequency signal. The PA control circuitmay be omitted from the power amplifier circuitin an exemplary aspect.

As the digital control signals, for example, serial data signals are used. More specifically, as the digital control signals, source synchronous serial data signals (a clock signal (CLK) and a data signal (DATA)) are used. The digital control signals are not limited to source synchronous serial data signals. For example, serial data signals using an embedded clock scheme may be used as the digital control signals.

21 32 11 12 21 1 The inductoris a so-called choke inductor, and is connected between the power supply voltage terminaland the power amplifiersand. The inductormay be omitted from the power amplifier circuitin an exemplary aspect.

14 14 3 FIG.A 3 FIG.A Next, the circuit configuration of the bias circuitaccording to this embodiment will be described with reference to.is a circuit configuration diagram of the bias circuitaccording to this embodiment.

3 FIG.A 14 14 It is noted thatdepicts an exemplary circuit configuration, and the bias circuitcan be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the bias circuitprovided below should not be interpreted as limiting.

14 141 147 141 141 142 141 142 20 141 142 The bias circuitincludes transistors Tto T, a resistor R, a constant current source I, and a reference current source I. The constant current source Iand the reference current source Ican respectively output a constant current (Icont) and a reference current (Iref) in accordance with a control signal from the PA control circuit. In this embodiment, the constant current source Iand the reference current source Ican be controlled in units of a frame of a radio frequency signal or units larger than a frame of a radio frequency signal. In other words, the constant current (Icont) and the reference current (Iref) cannot be controlled in units smaller than a frame (for example, units of an envelope or symbol).

14 141 142 141 1 11 141 142 1 In the bias circuit, the emitter terminals of the transistors Tand Tare connected, via the resistor R, to an output terminal that supplies the bias voltage (Vbe) to the power amplifier. Therefore, when the sum of the emitter currents of the transistors Tand Tincreases, the bias voltage (Vbe) decreases.

141 143 141 143 141 141 11 The emitter current (collector current) of the transistor Tdepends on the collector current of the transistor Tconnected to the constant current source I. The collector current of the transistor Tdepends on the constant current (Icont) output from the constant current source Iand is constant. Therefore, the emitter current of the transistor Tis constant regardless of the power supply voltage (Vcc) of the power amplifier.

142 144 144 144 145 146 145 146 145 11 146 147 147 147 142 142 The emitter current of the transistor Tdepends on the collector current of the transistor Tand increases as the collector current of the transistor Tincreases. The collector current of the transistor Tdepends on the collector currents of the transistors Tand Tand increases as the collector current of the transistor Tincreases and decreases as the collector current of the transistor Tincreases. The collector current of the transistor Tdepends on the power supply voltage (Vcc) of the power amplifier, and increases as the power supply voltage (Vcc) increases. The collector current of the transistor Tdepends on the collector current of the transistor T, and increases as the collector current of the transistor Tincreases. The collector current of the transistor Tdepends on the reference current (Iref) output from the reference current source I, and increases as the reference current (Iref) increases. In summary, the emitter current of the transistor Tincreases as the power supply voltage (Vcc) increases, and decreases as the reference current (Iref) increases.

141 142 14 1 11 From the above description, when the reference current (Iref) is constant, the sum of the emitter currents of the transistors Tand Tincreases as the power supply voltage (Vcc) increases. Therefore, in the bias circuit, the bias voltage (Vbe) supplied to the power amplifierdecreases as the power supply voltage (Vcc) increases.

1 1 14 1 3 FIG.B 3 FIG.B 3 FIG.B The relationship between the bias voltage (Vbe) and the power supply voltage (Vcc) will be described with reference to.is a diagram illustrating the relationship between the bias voltage (Vbe) supplied from the bias circuitaccording to this embodiment and the power supply voltage (Vcc). In, the vertical axis represents the bias voltage (Vbe), and the horizontal axis represents the power supply voltage (Vcc).

14 11 11 1 11 14 12 11 11 2 1 11 The bias circuitcan supply a bias voltage (Vbe) (an example of a first bias voltage) to the power amplifierwhen a power supply voltage (Vcc) (an example of a first power supply voltage) is supplied to the power amplifier. Furthermore, the bias circuitcan supply a bias voltage (Vbe) (an example of a second bias voltage) that is lower than the bias voltage (Vbe) to the power amplifierwhen a power supply voltage (Vcc) (an example of a second power supply voltage) that is higher than the power supply voltage (Vcc) is supplied to the power amplifier.

3 2 11 14 13 12 11 4 3 11 14 14 13 11 Similarly, when a power supply voltage (Vcc) that is higher than the power supply voltage (Vcc) is supplied to the power amplifier, the bias circuitcan supply a bias voltage (Vbe) that is lower than the bias voltage (Vbe) to the power amplifier. Furthermore, when a power supply voltage (Vcc) that is higher than the power supply voltage (Vcc) is supplied to the power amplifier, the bias circuitcan supply a bias voltage (Vbe) that is lower than the bias voltage (Vbe) to the power amplifier.

14 1 11 11 14 1 11 1 As described above, the bias circuitcan supply a lower bias voltage (Vbe) to the power amplifieras the power supply voltage (Vcc) supplied to the power amplifierincreases. In other words, the bias circuitcan supply a bias voltage (Vbe) having a negative proportional relationship to the power supply voltage (Vcc) to the power amplifier. Such a negative proportional relationship can be identified by measuring the bias voltage (Vbe) at least at three different levels of power supply voltage (Vcc).

1 1 1 11 1 It is noted that in this embodiment, the bias voltage (Vbe) is proportional to the power supply voltage (Vcc), but the relationship between the bias voltage (Vbe) and the power supply voltage (Vcc) is not limited to being proportional. For example, the bias voltage (Vbe) may decrease in a stepwise or exponential manner as the power supply voltage (Vcc) increases. Furthermore, in a range of the power supply voltage (Vcc) that is not supplied to the power amplifier, the bias voltage (Vbe) may increase as the power supply voltage (Vcc) increases.

15 15 4 FIG.A 4 FIG.A Next, the circuit configuration of the bias circuitaccording to this embodiment will be described with reference to.is a circuit configuration diagram of the bias circuitaccording to this embodiment.

4 FIG.A 15 15 It is noted thatdepicts an exemplary circuit configuration, and the bias circuitmay be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the bias circuitprovided below should not be interpreted as limiting.

15 151 157 151 1151 152 151 1152 20 151 152 The bias circuitincludes transistors Tto T, a resistor R, a constant current source, and a reference current source I. The constant current source Iand the reference current sourcecan respectively output a constant current (Icont) and a reference current (Iref) in accordance with a control signal from the PA control circuit. In this embodiment, the constant current source Iand the reference current source Ican be controlled in units of a frame of a radio frequency signal or in units larger than a frame of a radio frequency signal. In other words, the constant current (Icont) and the reference current (Iref) cannot be controlled in units smaller than a frame (for example, units of an envelope or symbol).

15 151 152 151 2 12 151 152 2 In the bias circuit, the emitter terminals of the transistors Tand Tare connected, via the resistor R, to an output terminal that supplies the bias voltage (Vbe) to the power amplifier. Therefore, when the sum of the emitter currents of the transistors Tand Tincreases, the bias voltage (Vbe) decreases.

151 153 151 153 1151 151 12 The emitter current (collector current) of the transistor Tdepends on the collector current of the transistor Tconnected to the constant current source I. The collector current of the transistor Tdepends on the constant current (Icont) output from the constant current sourceand is constant. Therefore, the emitter current of the transistor Tis constant regardless of the power supply voltage (Vcc) of the power amplifier.

152 156 156 156 157 154 157 154 157 152 154 155 155 155 12 152 The emitter current of the transistor Tdepends on the collector current of the transistor Tand increases as the collector current of the transistor Tincreases. The collector current of the transistor Tdepends on the collector currents of the transistors Tand Tand increases as the collector current of the transistor Tincreases and decreases as the collector current of the transistor Tincreases. The collector current of the transistor Tdepends on the reference current (Iref) output from the reference current source I, and increases as the reference current (Iref) increases. The collector current of the transistor Tdepends on the collector current of the transistor T, and increases as the collector current of the transistor Tincreases. The collector current of the transistor Tdepends on the power supply voltage (Vcc) of the power amplifier, and increases as the power supply voltage (Vcc) increases. In summary, the emitter current of the transistor Tdecreases as the power supply voltage (Vcc) increases, and increases as the reference current (Iref) increases.

151 152 15 2 12 From the above description, when the reference current (Iref) is constant, the sum of the emitter currents of the transistors Tand Tdecreases as the power supply voltage (Vcc) increases. Therefore, in the bias circuit, the bias voltage (Vbe) supplied to the power amplifierincreases as the power supply voltage (Vcc) increases.

2 2 15 2 4 FIG.B 4 FIG.B 4 FIG.B The relationship between the bias voltage (Vbe) and the power supply voltage (Vcc) will be described with reference to.is a diagram illustrating the relationship between the bias voltage (Vbe) supplied from the bias circuitaccording to this embodiment and the power supply voltage (Vcc). In, the vertical axis represents the bias voltage (Vbe), and the horizontal axis represents the power supply voltage (Vcc).

15 21 12 12 1 15 22 21 12 12 2 1 The bias circuitcan supply a bias voltage (Vbe) (an example of a third bias voltage) to the power amplifierwhen the power amplifieris supplied with the power supply voltage (Vcc). Furthermore, the bias circuitcan supply a bias voltage (Vbe) (an example of a fourth bias voltage) higher than the bias voltage (Vbe) to the power amplifierwhen the power amplifieris supplied with the power supply voltage (Vcc) higher than the power supply voltage (Vcc).

3 2 12 15 23 22 12 4 3 12 15 24 23 12 Similarly, when a power supply voltage (Vcc) higher than the power supply voltage (Vcc) is supplied to the power amplifier, the bias circuitcan supply a bias voltage (Vbe) higher than the bias voltage (Vbe) to the power amplifier. Furthermore, when a power supply voltage (Vcc) higher than the power supply voltage (Vcc) is supplied to the power amplifier, the bias circuitcan supply a bias voltage (Vbe) higher than the bias voltage (Vbe) to the power amplifier.

15 2 12 12 15 2 12 2 As described above, the bias circuitcan supply a higher bias voltage (Vbe) to the power amplifieras the power supply voltage (Vcc) supplied to the power amplifierincreases. In other words, the bias circuitcan supply the bias voltage (Vbe) having a positive proportional relationship to the power supply voltage (Vcc) to the power amplifier. This positive proportional relationship can be determined by measuring the bias voltage (Vbe) at at least three different levels of the power supply voltage (Vcc), as in the case of the negative proportional relationship.

2 2 2 12 2 In this embodiment, the bias voltage (Vbe) is proportional to the power supply voltage (Vcc), but the relationship between the bias voltage (Vbe) and the power supply voltage (Vcc) is not limited to being proportional. For example, the bias voltage (Vbe) may increase in a stepwise or exponential manner as the power supply voltage (Vcc) increases. Furthermore, in a range of the power supply voltage (Vcc) that is not supplied to the power amplifier, the bias voltage (Vbe) may decrease as the power supply voltage (Vcc) increases.

1 1 5 FIG. 5 FIG. 5 FIG. Next, an implementation example of the power amplifier circuitaccording to this embodiment will be described with reference to.is a layout diagram of the power amplifier circuitaccording to this embodiment. In, multiple components are labeled with abbreviations (e.g., “PA”, “BC”, and the like) that indicate the functions of the components so that the layout relationship of the multiple components can be easily understood, but the actual circuit components may not be labeled with such abbreviations.

5 FIG. 1 1 It is noted thatis an exemplary layout diagram, and the power amplifier circuitmay be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the power amplifier circuitprovided below is not to be interpreted as limiting.

1 7 8 9 19 21 7 The power amplifier circuitis mounted on a module substrate. Integrated circuitsand, the matching circuit(MN), and the inductor(L) are disposed on the module substrate.

8 11 12 14 15 17 18 8 8 The integrated circuitincludes the power amplifiersand(PA), the bias circuitsand(BC), and the matching circuitsand(MN). For example, silicon germanium (SiGe) or gallium arsenide (GaAs) can be used as the semiconductor material of the integrated circuit. For example, gallium nitride (GaN) or silicon carbide (SiC) may also be used as the semiconductor material of the integrated circuit.

11 12 11 12 11 12 The power amplifiersandcan be constructed using heterojunction bipolar transistors (HBTs). The amplifying transistors of the power amplifiersandare not limited to HBTs. For example, the power amplifiersand/ormay be constructed using high electron mobility transistors (HEMTs) or metal-semiconductor field effect transistors (MESFETs).

14 11 14 11 15 11 14 12 The bias circuitis disposed close to the power amplifier. That is, the bias circuitis disposed closer to the power amplifierthan the bias circuit. In other words, the power amplifieris disposed closer to the bias circuitthan the power amplifier.

15 12 15 12 14 12 15 11 The bias circuitis disposed close to the power amplifier. That is, the bias circuitis disposed closer to the power amplifierthan the bias circuit. In other words, the power amplifieris disposed closer to the bias circuitthan the power amplifier.

9 20 9 9 8 The integrated circuitincludes the PA control circuit(PAC). As the semiconductor material of the integrated circuit, for example, single crystal silicon, GaN, or SiC can be used. The integrated circuitis disposed next to the integrated circuit.

1 7 1 7 8 9 8 8 9 It is noted that the power amplifier circuitis mounted on one side of the module substrate, but is not limited to this layout. For example, the power amplifier circuitmay be mounted on both sides of the module substratein an alternative aspect. In addition, the integrated circuitmay be divided into multiple integrated circuits. Furthermore, the integrated circuitmay be stacked on the integrated circuit, or conversely, the integrated circuitmay be stacked on the integrated circuit.

6 FIG. 6 FIG. 6 FIG. 1 2 1 Next, a power amplification method according to this embodiment will be described with reference to.is a flowchart illustrating the power amplification method according to this embodiment. It is noted that a case is assumed inin which two discrete levels of power supply voltage (Vccand Vcc) are supplied to the power amplifier circuit.

1 1 1 10 14 15 1 12 First, when the power supply voltage (Vcc) is supplied to the power amplifier circuit(Vccin S), the bias circuitsandreceive the power supply voltage (Vcc) (S).

14 11 1 11 14 11 1 11 16 The bias circuitsupplies the bias voltage (Vbe) based on the power supply voltage (Vcc) to the power amplifier(S). The power amplifieramplifies a radio frequency signal using the power supply voltage (Vcc) and the bias voltage (Vbe) (S).

15 21 1 12 18 12 11 1 21 20 The bias circuitsupplies the bias voltage (Vbe) based on the power supply voltage (Vcc) to the power amplifier(S). The power amplifieramplifies the radio frequency signal amplified by the power amplifierusing the power supply voltage (Vcc) and the bias voltage (Vbe) (S).

1 2 2 10 14 15 2 1 22 When the power amplifier circuitis supplied with the power supply voltage (Vcc) (Vccin S), the bias circuitsandreceive the power supply voltage (Vcc) higher than the power supply voltage (Vcc) (S).

14 11 12 11 2 24 11 2 12 26 The bias circuitsupplies the power amplifierwith the bias voltage (Vbe) lower than the bias voltage (Vbe) based on the power supply voltage (Vcc) (S). The power amplifieramplifies the radio frequency signal using the power supply voltage (Vcc) and the bias voltage (Vbe) (S).

15 12 22 21 2 28 12 11 2 22 30 The bias circuitsupplies the power amplifierwith the bias voltage (Vbe) higher than the bias voltage (Vbe) based on the power supply voltage (Vcc) (S). The power amplifieramplifies the radio frequency signal amplified by the power amplifierusing a power supply voltage (Vcc) and a bias voltage (Vbe) (S).

6 FIG. 6 FIG. 14 18 24 28 It is noted that the steps and the order of steps inare merely examples, and the power amplification method is not limited to the flowchart inas would be appreciated to one skilled in the art. For example, Steps Sand Smay be performed simultaneously, and Steps Sand Smay be performed simultaneously.

1 1 7 FIG.A 7 FIG.B 7 FIG.A 7 FIG.B 7 FIG.A 7 FIG.B Next, the gain of the power amplifier circuitas described above will be described with reference toand.is a diagram illustrating the gain characteristics with respect to the output power of the power amplifier circuitaccording to this embodiment.is a diagram illustrating the gain characteristics with respect to the output power of a power amplifier circuit of the related art. Inand, the vertical axis represents the gain of the power amplifier circuit, and the horizontal axis represents the output power of the power amplifier circuit.

11 12 It is noted that the power amplifier circuit of the related art refers to a power amplifier circuit having a bias circuit that supplies a fixed bias voltage to the power amplifiersandindependent of the power supply voltage (Vcc).

7 FIG.A 61 64 1 1 4 1 1 4 In, gainstorepresent the gains of the power amplifier circuitat the power supply voltages (Vccto Vcc). Gain 60 represents the gain of the power amplifier circuitwhen the power supply voltage (Vccto Vcc) is changed discretely in accordance with the output power.

7 FIG.B 66 69 1 4 1 4 In, gainstorepresent the gains of the power amplifier circuit of the related art at the power supply voltages (Vccto Vcc). Gain 65 represents the gain of the power amplifier circuit of the related art when the power supply voltage (Vccto Vcc) is changed discretely in accordance with the output power.

7 7 FIGS.A andB 1 4 3 As illustrated in, in this embodiment, the difference in gain characteristics (shape of the gain curve) in the saturation region at multiple discrete voltages (Vccto Vcc) can be suppressed more than was previously possible. Furthermore, in this embodiment, discontinuous changes in gain with respect to discrete changes in the power supply voltage (Vcc) can be suppressed more than was previously possible. As a result, the difficulty of DPD in the RFICcan be reduced, and this can contribute to reducing the power consumption for DPD and/or reducing nonlinear distortion due to DPD.

8 10 FIGS.toB Next, the reason why the difference in gain characteristics in the saturation region at multiple discrete voltages and discontinuous changes in gain with respect to discrete changes in the power supply voltage can be suppressed in this embodiment will be described with reference to.

8 FIG. 9 FIG.A 9 FIG.B 8 FIG. 9 FIG.A 9 FIG.B 12 12 12 is a diagram illustrating the operating points of the power amplifiersaccording to Embodiment 1 and the related art.is a diagram illustrating the gain characteristics with respect to the output power of the power amplifierof the related art.is a diagram illustrating the gain characteristics with respect to the output power of the power amplifieraccording to Embodiment 1. In, the vertical axis represents the collector (emitter) current (Ice), and the horizontal axis represents the collector-emitter voltage (Vce). Inand, the vertical axis represents the gain, and the horizontal axis represents the output power.

71 74 12 2 76 79 12 2 Operating pointstorepresent operating points at respective power supply voltages of the power amplifierof the related art in which the bias voltage (Vbe) is fixed. Operating pointstorepresent operating points at respective power supply voltages of the power amplifieraccording to this embodiment in which a higher bias voltage (Vbe) is supplied as the power supply voltage (Vcc) increases.

12 2 23 1 71 1 4 74 4 12 12 1 4 12 9 FIG.A In the power amplifierof the related art, the bias voltage (Vbe) is constant at the voltage (Vbe), and therefore when the power supply voltage (Vcc) changes, the ratio of the collector-emitter voltage (Vce) to the power supply voltage (Vcc) also changes significantly. For example, the ratio of the collector-emitter voltage (Vce) to the power supply voltage (Vcc) at the operating pointat the power supply voltage (Vcc) is lower than the ratio of the collector-emitter voltage (Vce) to the power supply voltage (Vcc) at the operating pointat the power supply voltage (Vcc). Therefore, the operation mode of the power amplifier(e.g., from class AB to class A) also changes with the change in the power supply voltage (Vcc). As a result, as illustrated in, the gain characteristics in the saturation region of the power amplifierchange with the multiple discrete voltages (Vccto Vcc) supplied to the power amplifier.

12 2 76 1 1 79 4 4 12 12 1 4 12 9 FIG.B On the other hand, in the power amplifierof this embodiment, when the power supply voltage (Vcc) is lowered, the bias voltage (Vbe) is also lowered, and therefore even when the power supply voltage (Vcc) changes, the change in the ratio of the collector-emitter voltage (Vce) to the power supply voltage (Vcc) is suppressed. For example, the ratio of the collector-emitter voltage (Vce) at the operating pointat the power supply voltage (Vcc) to the power supply voltage (Vcc) is not significantly different from the ratio of the collector-emitter voltage (Vce) at the operating pointat the power supply voltage (Vcc) to the power supply voltage (Vcc). Therefore, a change in the operation mode of the power amplifierdue to a change in the power supply voltage (Vcc) is suppressed. As a result, as illustrated in, the gain characteristics of the power amplifierin the saturation region do not change with the multiple discrete voltages (Vccto Vcc) supplied to the power amplifier.

12 1 12 1 11 It is noted that, in the power amplifieraccording to this embodiment, changes in the gain characteristics in the saturation region can be suppressed at multiple discrete voltages, but differences in gain in the linear region become large. Therefore, it is difficult to suppress discontinuous changes in the gain of the power amplifier circuitwith respect to discrete changes in the power supply voltage (Vcc) by only controlling the bias voltage of the power amplifier. Therefore, in this embodiment, the bias voltage (Vbe) that decreases with an increase in the power supply voltage (Vcc) is supplied to the power amplifier.

10 FIG.A 10 FIG.B 11 11 is a diagram illustrating the gain characteristics with respect to the output power of the power amplifierof the related art.is a diagram illustrating the gain characteristics with respect to the output power of the power amplifieraccording to Embodiment 1.

10 FIG.A 10 FIG.B 7 FIG.A 11 11 12 11 1 As illustrated in, in the power amplifierof the related art, the gain increases as the power supply voltage (Vcc) increases in the linear region. On the other hand, as illustrated in, in the power amplifierof this embodiment, the gain decreases as the power supply voltage (Vcc) increases in the linear region. This makes it possible to compensate for changes in gain in the linear region of the power amplifierby using changes in gain in the linear region of the power amplifier. As a result, in this embodiment, as illustrated in, it is possible to suppress discontinuous changes in the gain of the power amplifier circuitin response to discrete changes in the power supply voltage (Vcc).

1 11 1 2 12 11 14 11 11 11 12 11 11 15 21 12 12 22 12 12 As described above, the power amplifier circuitaccording to this embodiment includes: the power amplifierconfigured to amplify a radio frequency signal using multiple discrete voltages including a first power supply voltage (e.g., Vcc) and a second power supply voltage (e.g., Vcc) higher than the first power supply voltage; the power amplifierconfigured to amplify the radio frequency signal amplified by the power amplifierusing multiple discrete voltages; the bias circuitconfigured to supply a first bias voltage (e.g., Vbe) to the power amplifierwhen the first power supply voltage is supplied to the power amplifierand to supply a second bias voltage (e.g., Vbe) lower than the first bias voltage to the power amplifierwhen the second power supply voltage is supplied to the power amplifier; and a bias circuitconfigured to supply a third bias voltage (e.g., Vbe) to the power amplifierwhen the first power supply voltage is supplied to the power amplifierand to supply a fourth bias voltage (e.g., Vbe) higher than the third bias voltage to the power amplifierwhen the second power supply voltage is supplied to the power amplifier.

12 11 11 12 1 1 Accordingly, a change in the voltage of the operating point with respect to the power supply voltage caused by a change in the power supply voltage can be suppressed by supplying a higher fourth bias voltage when a higher second power supply voltage is supplied to the power amplifier. Therefore, a change in the operation mode caused by a change in the power supply voltage can be suppressed, and a change in the gain characteristics in the saturation region of the power amplifier can be suppressed. As a result, the difficulty of DPD can be reduced, thereby contributing to reducing power consumption for DPD and/or reducing nonlinear distortion due to DPD. Furthermore, by supplying a lower second bias voltage when a higher second power supply voltage is supplied to the power amplifier, a change in gain in the linear region of the power amplifiercan compensate for a change in gain in the linear region of the power amplifier. Therefore, a change in gain with respect to a change in the power supply voltage in the linear region of the power amplifier circuitcan be suppressed, and a discontinuous change in the gain of the power amplifier circuitwith respect to a discrete change in the power supply voltage can be suppressed. As a result, the difficulty of DPD can be reduced, thereby contributing to reducing power consumption for DPD and/or reducing nonlinear distortion due to DPD.

1 14 1 11 11 15 2 12 12 Furthermore, for example, in the power amplifier circuitaccording to this embodiment, the bias circuitmay be configured to supply a lower bias voltage (Vbe) to the power amplifieras the power supply voltage (Vcc) supplied to the power amplifierincreases, and the bias circuitmay be configured to supply a higher bias voltage (Vbe) to the power amplifieras the power supply voltage (Vcc) supplied to the power amplifierincreases.

1 1 This makes it possible to suppress changes in the voltage of the operating point relative to the power supply voltage due to changes in the power supply voltage even when more discrete voltages are supplied to the power amplifier circuit, and also suppresses discontinuous changes in the gain of the power amplifier circuitrelative to discrete changes in the power supply voltage. This makes it possible to reduce the difficulty of DPD and contribute to reducing power consumption for DPD and/or reducing nonlinear distortion due to DPD.

1 11 12 14 15 8 14 11 15 15 12 14 Furthermore, for example, in the power amplifier circuitaccording to this embodiment, the power amplifier, the power amplifier, the bias circuit, and the bias circuitmay be included in one integrated circuit, the bias circuitmay be disposed closer to the power amplifierthan the bias circuit, and the bias circuitmay be disposed closer to the power amplifierthan the bias circuit.

14 11 15 12 14 11 15 12 1 14 11 2 15 12 1 2 This makes it possible to dispose the bias circuitcloser to the power amplifier, and the bias circuitcloser to the power amplifier. Therefore, the wiring length between the bias circuitand the power amplifierand the wiring length between the bias circuitand the power amplifiercan be shortened. As a result, deterioration of the bias voltage (Vbe) supplied from the bias circuitto the power amplifierand the bias voltage (Vbe) supplied from the bias circuitto the power amplifiercan be suppressed. In particular, since the bias voltages (Vbeand Vbe) change in response to changes in the power supply voltage (Vcc), the effect of the parasitic impedance of the wiring is significant and shortening the wiring length is effective.

1 11 12 14 15 8 11 14 12 12 15 11 Furthermore, for example, in the power amplifier circuitaccording to this embodiment, the power amplifier, the power amplifier, the bias circuit, and the bias circuitmay be included in one integrated circuit, the power amplifiermay be disposed closer to the bias circuitthan the power amplifier, and the power amplifiermay be disposed closer to the bias circuitthan the power amplifier.

11 14 12 15 14 11 15 12 1 14 11 2 15 12 1 2 In this way, the power amplifieris disposed closer to the bias circuit, and the power amplifieris disposed closer to the bias circuit. Therefore, the wiring length between the bias circuitand the power amplifierand the wiring length between the bias circuitand the power amplifiercan be shortened. As a result, deterioration of the bias voltage (Vbe) supplied from the bias circuitto the power amplifierand the bias voltage (Vbe) supplied from the bias circuitto the power amplifiercan be suppressed. In particular, since the bias voltages (Vbeand Vbe) change in response to changes in the power supply voltage (Vcc), the effect of the parasitic impedance of the wiring is significant and shortening the wiring length is effective.

1 12 11 11 14 11 16 21 12 18 11 12 20 2 22 12 11 24 11 26 22 12 28 11 12 30 The power amplification method according to this embodiment is a power amplification method for amplifying a radio frequency signal using multiple discrete voltages. The power amplification method includes: receiving a first power supply voltage (e.g., Vcc) included in the multiple discrete voltages (S); supplying a first bias voltage (e.g., Vbe) to the power amplifierbased on the first power supply voltage (S); amplifying a first radio frequency signal in the power amplifierusing the first power supply voltage and the first bias voltage (S); supplying a third bias voltage (e.g., Vbe) to the power amplifierbased on the first power supply voltage (S); amplifying the first radio frequency signal amplified by the power amplifierin the power amplifierusing the first power supply voltage and the third bias voltage (S); receiving a second power supply voltage (e.g., Vcc) that is included in the multiple discrete voltages and is higher than the first power supply voltage (S); supplying a second bias voltage (e.g., Vbe) that is lower than the first bias voltage to the power amplifierbased on the second power supply voltage (S); amplifying a second radio frequency signal in the power amplifierusing the second power supply voltage and the second bias voltage (S); supplying a fourth bias voltage (e.g., Vbe) that is higher than the third bias voltage to the power amplifierbased on the second power supply voltage (S); and amplifying the second radio frequency signal amplified by the power amplifierin the power amplifierusing the second power supply voltage and the fourth bias voltage (S).

12 11 12 11 1 1 Accordingly, a change in the voltage of the operating point with respect to the power supply voltage caused by a change in the power supply voltage can be suppressed by supplying a higher fourth bias voltage when a higher second power supply voltage is supplied to the power amplifier. Therefore, a change in the operation mode caused by a change in the power supply voltage can be suppressed, and a change in the gain characteristics in the saturation region of the power amplifier can be suppressed. As a result, the difficulty of DPD can be reduced, thereby contributing to reducing power consumption for DPD and/or reducing nonlinear distortion due to DPD. Furthermore, when a higher second power supply voltage is supplied to the power amplifier, a lower second bias voltage is supplied, and thus a change in gain in the linear region of the power amplifiercan be compensated for by a change in gain in the linear region of the power amplifier. Therefore, a change in gain with respect to a change in the power supply voltage in the linear region of the power amplifier circuitcan be suppressed, and a discontinuous change in the gain of the power amplifier circuitwith respect to a discrete change in the power supply voltage can be suppressed. As a result, the difficulty of DPD can be reduced, thereby contributing to reducing power consumption for DPD and/or reducing nonlinear distortion due to DPD.

11 Next, Modification 1 of Embodiment 1 will be described. This modification mainly differs from Embodiment 1 in that the bias voltage supplied to the power amplifiercan be switched depending on the tracking mode. Hereafter, this modification will be described with reference to the drawings, focusing on the differences from Embodiment 1.

2 FIG. 2 FIG. 6 6 6 6 1 1 1 1 1 14 14 is a circuit configuration diagram of a communication deviceA according to this modification. As illustrated in, the communication deviceA according to this modification is substantially the same as the communication deviceaccording to Embodiment 1, except that the communication deviceA includes a power amplifier circuitA instead of the power amplifier circuit, and therefore the description thereof is omitted. The power amplifier circuitA according to this modification is substantially the same as the power amplifier circuitaccording to Embodiment 1, except that the power amplifier circuitA includes a bias circuitA instead of the bias circuit, and therefore the description thereof is omitted.

14 14 11 FIG. 11 FIG. The circuit configuration of the bias circuitA according to this modification will be described with reference to.is a circuit diagram of the bias circuitA according to this modification.

11 FIG. 14 14 It is noted thatdepicts an exemplary circuit configuration, and the bias circuitA can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the bias circuitA provided below should not be interpreted as limiting.

14 14 15 14 141 147 152 154 156 157 141 141 142 152 The bias circuitA has a circuit configuration that is a combination of the bias circuitsand. Specifically, the bias circuitA includes transistors Tto T, T, T, T, and T, a resistor R, a constant current source I, and reference current sources Iand I.

142 152 1 142 152 0 142 1 152 1 142 1152 0 142 1 152 In this modification, the reference current sources Iand Iare controlled according to a tracking mode. Specifically, when the D-ET mode and the SPT mode are applied to the power amplifier circuitA, the reference current source Iis turned on and the reference current source Iis turned off. That is, in the D-ET mode and the SPT mode, a reference current (Iref) is output from the reference current source I, and a reference current (Iref) is not output from the reference current source I. On the other hand, when the APT mode is applied to the power amplifier circuitA, the reference current source Iis turned off, and the reference current sourceis turned on. That is, in the APT mode, the reference current (Iref) is not output from the reference current source I, and the reference current (Iref) is output from the reference current source I.

14 14 12 FIG.A 12 FIG.B This allows the operation of the bias circuitA to be switched between the DET mode or the SPT mode and the APT mode. Next, the operation of the bias circuitA will be described with reference toand.

12 FIG.A 12 FIG.B 12 FIG.A 12 FIG.B 1 14 1 andare diagrams illustrating the relationship between the bias voltage (Vbe) supplied from the bias circuitA according to this modification and the power supply voltage (Vcc). Inand, the vertical axis represents the bias voltage (Vbe), and the horizontal axis represents the power supply voltage (Vcc).

1 14 11 11 1 11 2 1 11 14 12 11 11 12 FIG.A When the D-ET mode or the SPT mode is applied to the power amplifier circuitA, as illustrated in, the bias circuitA can supply a bias voltage (Vbe) (an example of a first bias voltage) to the power amplifierwhen a power supply voltage (Vcc) (an example of a first power supply voltage) is supplied to the power amplifier. When a power supply voltage (Vcc) (an example of a second power supply voltage) higher than the power supply voltage (Vcc) is supplied to the power amplifier, the bias circuitA can supply a bias voltage (Vbe) (an example of a second bias voltage) lower than the bias voltage (Vbe) to the power amplifier.

3 2 11 14 13 12 11 4 3 11 14 14 13 11 Similarly, when a power supply voltage (Vcc) higher than the power supply voltage (Vcc) is supplied to the power amplifier, the bias circuitA can supply a bias voltage (Vbe) lower than the bias voltage (Vbe) to the power amplifier. Furthermore, when a power supply voltage (Vcc) higher than the power supply voltage (Vcc) is supplied to the power amplifier, the bias circuitA can supply a bias voltage (Vbe) lower than the bias voltage (Vbe) to the power amplifier.

1 14 15 11 1 11 14 16 15 11 2 1 11 12 FIG.B On the other hand, when the APT mode is applied to the power amplifier circuitA, as illustrated in, the bias circuitA can supply a bias voltage (Vbe) (an example of a fifth bias voltage) to the power amplifierwhen a power supply voltage (Vcc) is supplied to the power amplifier. Furthermore, the bias circuitA can supply a bias voltage (Vbe) (an example of a sixth bias voltage) higher than the bias voltage (Vbe) to the power amplifierwhen a power supply voltage (Vcc) higher than the power supply voltage (Vcc) is supplied to the power amplifier.

14 17 16 11 3 2 11 4 3 11 14 18 17 11 Similarly, the bias circuitA can supply a bias voltage (Vbe) higher than the bias voltage (Vbe) to the power amplifierwhen a power supply voltage (Vcc) higher than the power supply voltage (Vcc) is supplied to the power amplifier. Furthermore, when a power supply voltage (Vcc) higher than the power supply voltage (Vcc) is supplied to the power amplifier, the bias circuitA can supply a bias voltage (Vbe) higher than the bias voltage (Vbe) to the power amplifier.

11 14 1 11 11 14 1 11 11 14 1 11 11 14 1 11 As described above, when the D-ET mode or SPT mode is applied to the power amplifier, the bias circuitA can supply a lower bias voltage (Vbe) to the power amplifieras the power supply voltage (Vcc) supplied to the power amplifierincreases. That is, in the D-ET mode or SPT mode, the bias circuitA can supply a bias voltage (Vbe) having a negative proportional relationship with the power supply voltage (Vcc) to the power amplifier. On the other hand, when the APT mode is applied to the power amplifier, the bias circuitA can supply a higher bias voltage (Vbe) to the power amplifieras the power supply voltage (Vcc) supplied to the power amplifierincreases. That is, in the APT mode, the bias circuitA can supply a bias voltage (Vbe) having a positive proportional relationship with the power supply voltage (Vcc) to the power amplifier.

1 1 1 11 1 11 1 It is noted that in this modification, the bias voltage (Vbe) has a positive or negative proportional relationship with the power supply voltage (Vcc), but the relationship between the bias voltage (Vbe) and the power supply voltage (Vcc) is not limited to a proportional relationship. For example, the bias voltage (Vbe) may change in a stepwise or exponential manner with respect to changes in the power supply voltage (Vcc). Furthermore, in a range of the power supply voltage (Vcc) not supplied to the power amplifier, the bias voltage (Vbe) may change in the opposite manner to the range of the power supply voltage (Vcc) supplied to the power amplifier. In addition, the bias voltage (Vbe) may be fixed regardless of the power supply voltage (Vcc).

1 14 11 11 11 14 11 11 1 11 12 11 2 11 11 14 15 11 11 16 11 11 As described above, in the power amplifier circuitA according to this modification, the bias circuitA may be configured to switch the bias voltage supplied to the power amplifierdepending on the tracking mode applied to the power amplifier. When the D-ET mode or the SPT mode is applied to the power amplifier, the bias circuitA may be configured to supply a first bias voltage (e.g., Vbe) to the power amplifierwhen a first power supply voltage (e.g., Vcc) is supplied to the power amplifier, and to supply a second bias voltage (e.g., Vbe) lower than the first bias voltage to the power amplifierwhen a second power supply voltage (e.g., Vcc) is supplied to the power amplifier. When the APT mode is applied to the power amplifier, the bias circuitA may be configured to supply a fifth bias voltage (e.g., Vbe) to the power amplifierwhen the first power supply voltage is supplied to the power amplifier, and to supply a sixth bias voltage (e.g., Vbe) higher than the fifth bias voltage to the power amplifierwhen the second power supply voltage is supplied to the power amplifier.

1 2 1 11 12 12 11 Accordingly, in the D-ET mode or SPT mode, bias voltages (Vbeand Vbe), as in the case of the power amplifier circuitaccording to Embodiment 1, are supplied to the power amplifiersand, and therefore the difficulty of DPD can be reduced, thereby contributing to reducing power consumption for DPD and/or reducing nonlinear distortion due to DPD. On the other hand, in the APT mode, when a higher second power supply voltage is supplied to the power amplifier, a higher sixth bias voltage is supplied, and therefore the linearity of the power amplifiercan be improved. In the APT mode, the power supply voltage changes on a frame-by-frame basis, and the changes in the power supply voltage are slower than in the D-ET mode and SPT mode. Therefore, an increase in the difficulty of DPD due to gain fluctuations in the linear region is also suppressed.

1 11 14 1 11 11 11 14 1 11 11 For example, in the power amplifier circuitA according to this modification, when the D-ET mode or the SPT mode is applied to the power amplifier, the bias circuitA may be configured to supply a lower bias voltage (Vbe) to the power amplifieras the power supply voltage (Vcc) supplied to the power amplifierincreases, and when the APT mode is applied to the power amplifier, the bias circuitA may be configured to supply a higher bias voltage (Vbe) to the power amplifieras the power supply voltage (Vcc) supplied to the power amplifierincreases.

1 This makes it possible to reduce the difficulty of DPD even when more discrete voltages are supplied to the power amplifier circuitA, thereby contributing to reducing the power consumption for DPD and/or reducing nonlinear distortion due to DPD.

Next, Modification 2 of Embodiment 1 will be described. This modification mainly differs from Embodiment 1 in that the power amplifier circuit is a Doherty amplifier circuit. Hereafter, this modification will be described with reference to the drawings, focusing on the differences from Embodiment 1.

6 6 1 1 The circuit configuration of a communication deviceB according to this modification is substantially the same as that of the communication deviceaccording to Embodiment 1, except that a power amplifier circuitB is provided instead of the power amplifier circuit, and therefore the description thereof will be omitted.

1 6 13 FIG. 13 FIG. The circuit configuration of the power amplifier circuitB according to this modification will be described with reference to.is a circuit configuration diagram of the communication deviceB according to this modification.

1 1 11 13 14 16 17 19 20 21 22 23 The power amplifier circuitB is a multi-stage amplifier circuit and is a Doherty amplifier circuit. The power amplifier circuitB includes power amplifiersto, bias circuitsto, matching circuits (matching networks)to, a PA control circuit, an inductor, and phase shift circuitsand.

According to an exemplary aspect, the term “Doherty amplifier circuit” refers to an amplifier circuit that achieves high efficiency by using multiple amplifiers as a carrier amplifier and a peak amplifier. Moreover, the term “carrier amplifier” refers to an amplifier, in the Doherty amplifier circuit, that operates regardless of whether the power of the radio frequency signal (input) is low or high. The term “peak amplifier” refers to an amplifier, in the Doherty amplifier circuit, that mainly operates when the power of the radio frequency signal (input) is high. Therefore, when the input power of the radio frequency signal is low, the radio frequency signal is mainly amplified by the carrier amplifier, and when the input power of the radio frequency signal is high, the radio frequency signal is amplified by the carrier amplifier and the peak amplifier and the resulting signals are then combined. With such an operation, in the Doherty amplifier circuit, the load impedance seen from the carrier amplifier at a low output power increases, and the efficiency at a low output power is improved.

11 31 12 11 31 17 11 12 18 13 18 22 11 14 32 21 11 3 1 14 2 The power amplifieris an example of a “first power amplifier” according to the exemplary aspect and is connected between the radio-frequency input terminaland the power amplifier. Specifically, an input terminal of the power amplifieris connected to the radio-frequency input terminalvia the matching circuit. The output terminal of the power amplifieris connected to the input terminal of the power amplifiervia a matching circuitand is connected to the input terminal of the power amplifiervia the matching circuitand the phase shift circuit. Furthermore, the power amplifieris connected to the bias circuit, and is connected to a power supply voltage terminalvia the inductor. As a result, the power amplifiercan amplify a radio frequency signal (RFin) supplied from the RFICusing a bias voltage (Vbe) supplied from the bias circuitand the power supply voltage (Vcc) supplied from the tracker circuit.

12 12 11 30 12 11 18 12 30 23 19 12 15 32 21 12 11 2 15 2 The power amplifieris an example of a “second power amplifier” according to the exemplary aspect and is a carrier amplifier. The power amplifieris connected between the power amplifierand the antenna connection terminal. Specifically, the input terminal of the power amplifieris connected to the output terminal of the power amplifiervia the matching circuit, and the output terminal of the power amplifieris connected to the antenna connection terminalvia the phase shift circuitand the matching circuit. Furthermore, the power amplifieris connected to the bias circuit, and is connected to the power supply voltage terminalvia the inductor. This allows the power amplifierto amplify at least part of the radio frequency signal amplified by the power amplifierusing the bias voltage (Vbe) supplied from the bias circuitand the power supply voltage (Vcc) supplied from the tracker circuit.

13 13 11 30 13 11 22 18 13 30 19 13 16 32 21 13 11 3 16 2 The power amplifieris an example of a “third power amplifier” and is a peak amplifier according to the exemplary aspect. The power amplifieris connected between the power amplifierand the antenna connection terminal. Specifically, the input terminal of the power amplifieris connected to the output terminal of the power amplifiervia the phase shift circuitand the matching circuit, and the output terminal of the power amplifieris connected to the antenna connection terminalvia the matching circuit. Furthermore, the power amplifieris connected to the bias circuitand to the power supply voltage terminalvia the inductor. This allows the power amplifierto amplify part of the radio frequency signal amplified by the power amplifierusing the bias voltage (Vbe) supplied from the bias circuitand the power supply voltage (Vcc) supplied from the tracker circuit.

16 13 16 3 13 16 3 13 16 3 14 FIG.A 14 FIG.B The bias circuitis an example of a “third bias circuit” according to the exemplary aspect and is connected to the power amplifier. The bias circuitcan supply a bias voltage (Vbe) to the power amplifier. The bias circuitcan change the bias voltage (Vbe) in accordance with the power supply voltage (Vcc) supplied to the power amplifier. Details of the bias circuitand the bias voltage (Vbe) will be described later with reference toand.

22 11 13 11 The phase shift circuitis connected between the output terminal of the power amplifierand the input terminal of the power amplifierand can shift the phase of part of the radio frequency signal amplified by the power amplifierby −90 degrees (delay by 90 degrees).

23 12 30 12 The phase shift circuitis connected between the output terminal of the power amplifierand the antenna connection terminaland can shift the phase of the radio frequency signal amplified by the power amplifierby −90 degrees (delay by 90 degrees).

22 23 22 23 22 23 Each of the phase shift circuitsandcan be, for example, a quarter-wave transmission line. The phase shift circuitsand/ormay include an inductor and/or a capacitor. This enables the line lengths to be shortened by the phase shift circuitsand/or.

1 12 13 12 13 23 13 It is noted that in the power amplifier circuitB according to this modification, the output signals of the two power amplifiersandare combined in phase with each other, but this configuration may be varied. For example, the output signals of the two power amplifiersandmay be combined with each other with opposite phases using a transformer. In this case, the phase shift circuitmay be connected between the output terminal of the power amplifierand the transformer.

16 16 14 FIG.A 14 FIG.A The circuit configuration of the bias circuitaccording to this modification will be described with reference to.is a circuit configuration diagram of the bias circuitaccording to this modification.

14 FIG.A 16 16 It is noted thatdepicts an exemplary circuit configuration, and the bias circuitmay be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the bias circuitprovided below should not be interpreted as limiting.

14 FIG.A 16 14 16 As illustrated in, the bias circuithas the same circuit configuration as the bias circuit. Therefore, detailed description of the circuit configuration of the bias circuitis omitted.

14 FIG.B 14 FIG.B 3 16 3 is a diagram illustrating the relationship between the bias voltage (Vbe) supplied from the bias circuitaccording to this modification and the power supply voltage (Vcc). In, the vertical axis represents the bias voltage (Vbe), and the horizontal axis represents the power supply voltage (Vcc).

16 31 13 1 13 2 1 13 16 32 31 13 The bias circuitcan supply a bias voltage (Vbe) (an example of a seventh bias voltage) to the power amplifierwhen a power supply voltage (Vcc) (an example of a first power supply voltage) is supplied to the power amplifier. Furthermore, when a power supply voltage (Vcc) (an example of a second power supply voltage) higher than the power supply voltage (Vcc) is supplied to the power amplifier, the bias circuitcan supply a bias voltage (Vbe) (an example of an eighth bias voltage) lower than the bias voltage (Vbe) to the power amplifier.

3 2 13 16 33 32 13 4 3 13 16 34 33 13 Similarly, when a power supply voltage (Vcc) higher than the power supply voltage (Vcc) is supplied to the power amplifier, the bias circuitcan supply a bias voltage (Vbe) lower than the bias voltage (Vbe) to the power amplifier. Furthermore, when a power supply voltage (Vcc) higher than the power supply voltage (Vcc) is supplied to the power amplifier, the bias circuitcan supply a bias voltage (Vbe) lower than the bias voltage (Vbe) to the power amplifier.

16 13 3 13 16 13 3 As described above, the bias circuitcan supply the power amplifierwith a lower bias voltage (Vbe) as the power supply voltage (Vcc) supplied to the power amplifierincreases. In other words, the bias circuitcan supply the power amplifierwith a bias voltage (Vbe) having a negative proportional relationship with the power supply voltage (Vcc).

3 3 3 13 3 It is noted that in this modification, the bias voltage (Vbe) is proportional to the power supply voltage (Vcc), but the relationship between the bias voltage (Vbe) and the power supply voltage (Vcc) is not limited to being proportional. For example, the bias voltage (Vbe) may decrease in a stepwise or exponential manner as the power supply voltage (Vcc) increases. In addition, in a range of the power supply voltage (Vcc) that is not supplied to the power amplifier, the bias voltage (Vbe) may increase as the power supply voltage (Vcc) increases.

1 13 12 As described above, the power amplifier circuitB according to this modification may be a Doherty amplifier circuit and may further include a power amplifieras a peak amplifier, and the power amplifiermay be a carrier amplifier.

1 In addition to the power-added efficiency being improved by the Doherty amplifier circuit, this can contribute to reducing power consumption for DPD and/or reducing nonlinear distortion due to DPD, similarly to the power amplifier circuitaccording to Embodiment 1.

1 16 31 13 1 13 32 13 2 13 Furthermore, for example, the power amplifier circuitB according to this modification may further include the bias circuitconfigured to supply a seventh bias voltage (e.g., Vbe) to the power amplifierwhen a first power supply voltage (e.g., Vcc) is supplied to the power amplifier, and to supply an eighth bias voltage (e.g., Vbe) lower than the seventh bias voltage to the power amplifierwhen a second power supply voltage (e.g., Vcc) is supplied to the power amplifier.

13 Accordingly, when a higher second power supply voltage is supplied to the power amplifier, a lower eighth bias voltage is supplied, and therefore the rising output of the peak amplifier can be adjusted in accordance with an increase in the saturation output of the carrier amplifier, and the back-off region of the Doherty amplifier circuit can be optimized to improve the power added efficiency.

1 16 3 13 13 Furthermore, for example, in the power amplifier circuitB according to this modification, the bias circuitmay be configured to supply a lower bias voltage (Vbe) to the power amplifieras the power supply voltage (Vcc) supplied to the power amplifierincreases.

1 Accordingly, even when more discrete voltages are supplied to the power amplifier circuitB, the back-off region of the Doherty amplifier circuit can be optimized to improve the power added efficiency.

1 11 Next, Embodiment 2 will be described. In this embodiment, the main difference from Embodiment 1 is that the attenuation of a variable attenuator is changed instead of changing the bias voltage (Vbe) of the power amplifieraccording to the power supply voltage (Vcc). Hereafter, this embodiment is described with reference to the drawings, focusing on the differences from Embodiment 1.

6 6 6 1 1 The circuit configuration of a communication deviceC according to this embodiment is substantially the same as that of the communication deviceaccording to Embodiment 1, except that the communication deviceC includes a power amplifier circuitC instead of the power amplifier circuit, and therefore the description thereof is omitted.

1 6 15 FIG. 15 FIG. The circuit configuration of the power amplifier circuitC according to this embodiment will be described with reference to.is a circuit configuration diagram of the communication deviceC according to this embodiment.

1 11 12 14 15 17 19 20 21 24 The power amplifier circuitC includes power amplifiersand, bias circuitsC and, matching circuits (matching networks)to, a PA control circuit, an inductor, and a variable attenuation circuit.

14 11 14 1 11 The bias circuitC is an example of a “first bias circuit” according to the exemplary aspect and is connected to the power amplifier. The bias circuitC can supply a bias voltage (Vbe) to the power amplifier.

16 FIG.A 14 1 11 14 f Specifically, for example, as illustrated in, the bias circuitC can supply a fixed bias voltage (Vbe) to the power amplifierregardless of the power supply voltage (Vcc). Substantially the same circuit configuration as that of a bias circuit of the related art can be used for the bias circuitC, and therefore illustration and description thereof are omitted.

15 12 15 2 12 15 2 12 15 2 21 22 The bias circuitis an example of a “second bias circuit” according to the exemplary aspect and is connected to the power amplifier. The bias circuitcan supply a bias voltage (Vbe) to the power amplifier. The bias circuitcan change the bias voltage (Vbe) in accordance with the power supply voltage (Vcc) supplied to the power amplifier. Details of the bias circuitand the bias voltage (Vbe) are substantially the same as those in Embodiment 1, except that the bias voltage (Vbe) is an example of the first bias voltage and the bias voltage (Vbe) is an example of the second bias voltage, and therefore description thereof is omitted.

24 31 11 24 31 24 11 17 24 32 21 24 11 12 The variable attenuation circuitis connected between the radio-frequency input terminaland the input terminal of the power amplifier. Specifically, one end of the variable attenuation circuitis connected to the radio-frequency input terminal, and the other end of the variable attenuation circuitis connected to the input terminal of the power amplifiervia the matching circuit. Furthermore, the variable attenuation circuitis connected to the power supply voltage terminalvia the inductor. The variable attenuation circuitmay be connected between the output terminal of the power amplifierand the input terminal of the power amplifier.

24 The variable attenuation circuitcan change the attenuation thereof depending on the power supply voltage (Vcc). Here, the attenuation is expressed as a value obtained by inverting the sign of the common logarithm of the ratio of the output power to the input power. Therefore, the attenuation can be determined by measuring the input power and the output power.

24 24 16 FIG.B 16 FIG.B 16 FIG.B Next, the relationship between the attenuation of the variable attenuation circuitand the power supply voltage (Vcc) will be described with reference to.is a diagram illustrating the relationship between the attenuation of the variable attenuation circuitaccording to this embodiment and the power supply voltage (Vcc). In, the vertical axis represents the attenuation, and the horizontal axis represents the power supply voltage.

24 1 1 1 24 2 1 2 1 1 The variable attenuation circuitcan be adjusted to an attenuation (Att) (an example of a first attenuation) when a power supply voltage (Vcc) is supplied to the power amplifier circuitC. Furthermore, the variable attenuation circuitcan be adjusted to an attenuation (Att) (an example of a second attenuation) greater than the attenuation (Att) when a power supply voltage (Vcc) higher than the power supply voltage (Vcc) is supplied to the power amplifier circuitC.

24 3 2 3 2 1 24 4 3 4 3 1 Similarly, the variable attenuation circuitcan be adjusted to an attenuation (Att) greater than the attenuation (Att) when a power supply voltage (Vcc) higher than the power supply voltage (Vcc) is supplied to the power amplifier circuitC. Furthermore, the variable attenuation circuitcan be adjusted to an attenuation (Att) greater than the attenuation (Att) when a power supply voltage (Vcc) higher than the power supply voltage (Vcc) is supplied to the power amplifier circuitC.

24 1 24 As described above, the variable attenuation circuitcan be adjusted to a greater attenuation as the power supply voltage (Vcc) supplied to the power amplifier circuitC increases. In other words, the variable attenuation circuitcan be adjusted to an attenuation having a positive proportional relationship with the power supply voltage (Vcc).

24 1 24 It is noted that, in this embodiment, the attenuation of the variable attenuation circuitis proportional to the power supply voltage (Vcc), but the relationship between the attenuation and the power supply voltage (Vcc) is not limited to being proportional. For example, the attenuation may increase in a stepwise or exponential manner as the power supply voltage (Vcc) increases. In addition, in a range of the power supply voltage (Vcc) not supplied to the power amplifier circuitC, the attenuation of the variable attenuation circuitmay decrease as the power supply voltage (Vcc) increases.

1 1 17 FIG. 17 FIG. 17 FIG. Next, an implementation example of the power amplifier circuitC according to this embodiment will be described with reference to.is a layout diagram of the power amplifier circuitC according to this embodiment. In, multiple components are labeled with abbreviations (e.g., “PA”, “BC”, and the like) that indicate the functions of the components so that the layout relationship of the multiple components can be easily understood, but the actual circuit components do not need to be labeled with such abbreviations.

17 FIG. 1 1 It is noted thatis an exemplary layout diagram, and the power amplifier circuitC can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the power amplifier circuitC provided below is not to be interpreted as limiting.

1 7 8 9 19 21 7 The power amplifier circuitC is mounted on a module substrate. Integrated circuitsC and, the matching circuit(MN), and the inductor(L) are disposed on the module substrate.

8 11 12 14 15 17 18 24 8 8 The integrated circuitC includes the power amplifiersand(PA), the bias circuitsC and(BC), the matching circuitsand(MN), and the variable attenuation circuit(ATT). The semiconductor material of the integrated circuitC may be the same as or similar to that of the integrated circuitof Embodiment 1.

14 11 14 11 15 11 14 12 The bias circuitC is disposed near the power amplifier. That is, the bias circuitC is disposed closer to the power amplifierthan the bias circuit. In other words, the power amplifieris disposed closer to the bias circuitC than the power amplifier.

15 12 15 12 14 12 15 11 The bias circuitis disposed close to the power amplifier. That is, the bias circuitis disposed closer to the power amplifierthan the bias circuitC. In other words, the power amplifieris disposed closer to the bias circuitthan the power amplifier.

1 7 1 7 8 9 8 8 9 It is noted that the power amplifier circuitC is mounted on one side of the module substratebut is not limited to this layout. For example, the power amplifier circuitC may be mounted on both sides of the module substrate. In addition, the integrated circuitC may be divided into multiple integrated circuits. Furthermore, the integrated circuitmay be stacked on the integrated circuitC, or conversely, the integrated circuitC may be stacked on the integrated circuit.

1 11 1 2 12 11 14 1 11 15 21 12 12 22 12 12 24 11 11 12 24 1 11 2 11 As described above, the power amplifier circuitC according to this embodiment includes: the power amplifierconfigured to amplify a radio frequency signal using multiple discrete voltages including a first power supply voltage (e.g., Vcc) and a second power supply voltage (e.g., Vcc) higher than the first power supply voltage; the power amplifierconfigured to amplify the radio frequency signal amplified by the power amplifierusing multiple discrete voltages; the bias circuitC configured to supply a bias voltage (Vbe) to the power amplifier; the bias circuitconfigured to supply a first bias voltage (e.g., Vbe) to the power amplifierwhen the first power supply voltage is supplied to the power amplifier, and to supply a second bias voltage (e.g., Vbe) higher than the first bias voltage to the power amplifierwhen the second power supply voltage is supplied to the power amplifier; and the variable attenuation circuitconnected to the input terminal of the power amplifieror connected between the output terminal of the power amplifierand the input terminal of the power amplifier. The variable attenuation circuitis adjusted to a first attenuation (e.g., Att) when the first power supply voltage is supplied to the power amplifier, and is adjusted to a second attenuation (e.g., Att) larger than the first attenuation when the second power supply voltage is supplied to the power amplifier.

12 11 24 12 11 1 1 Accordingly, when a higher second power supply voltage is supplied to the power amplifier, a higher second bias voltage is also supplied, and therefore a change in the voltage of the operating point relative to the power supply voltage due to a change in the power supply voltage can be suppressed. Therefore, a change in the operation mode caused by a change in the power supply voltage can be suppressed, and a change in the gain characteristics in the saturation region of the power amplifier can be suppressed. As a result, the difficulty of DPD can be reduced, thereby contributing to reducing power consumption for DPD and/or reducing nonlinear distortion due to DPD. Furthermore, when a higher second power supply voltage is supplied to the power amplifier, the variable attenuation circuitis adjusted to a larger attenuation, and a change in the gain in the linear region of the power amplifiercan be compensated for by a change in the attenuation of the output signal of the power amplifier. Therefore, a change in the gain with respect to a change in the power supply voltage in the linear region of the power amplifier circuitC can be suppressed, and a discontinuous change in the gain of the power amplifier circuitC with respect to the discrete change in the power supply voltage can be suppressed. As a result, the difficulty of DPD can be reduced, thereby contributing to reducing power consumption for DPD and/or reducing nonlinear distortion due to DPD.

A power amplifier circuit and a power amplification method according to exemplary aspects of the present disclosure have been described above based on embodiments, but a power amplifier circuit and a power amplification method according to the present disclosure are not limited to the above embodiments. Other embodiments realized by combining any of the components in the above-described embodiments, modifications obtained by modifying the above-described embodiments in various ways as conceived of by one skilled in the art without departing from the spirit of the exemplary aspects, and various devices incorporating the above-described power amplifier circuit are also included in the present disclosure.

21 11 21 12 For example, in the circuit configurations of the various circuits according to the above-described embodiments, other circuit elements, wiring lines, and the like may be inserted midway along paths connecting the circuit elements and signal paths disclosed in the drawings. For example, a capacitor may be inserted between the path between the inductorand the power amplifierand the ground. Similarly, a capacitor may be inserted between the path between the inductorand the power amplifierand the ground.

1 14 14 Furthermore, for example, Modification 1 and Modification 2 of Embodiment 1 may be combined with each other. For example, the power amplifier circuitB may include the bias circuitA instead of the bias circuit.

In addition, for example, Modification 1 of Embodiment 1 may be applied to Embodiment 2. That is, the variable attenuation circuit may switch the attenuation depending on the tracking mode. Specifically, the variable attenuation circuit may be adjusted to a greater attenuation as the power supply voltage increases in the D-ET mode or SPT mode and be adjusted to a smaller attenuation as the power supply voltage decreases in the APT mode.

It is noted that in the above-described embodiments, the number of discrete voltages that can be supplied from the tracker circuit to the power amplifier circuit is four but is not limited to this number. The number of discrete voltages may be more than four or less than four as would be appreciated to one skilled in the art.

The present disclosure can be widely used in communication devices such as mobile phones as a power amplifier circuit for amplifying radio frequency signals.

1 1 1 1 ,A,B,C power amplifier circuit 2 tracker circuit 3 RFIC 4 BBIC 5 antenna 6 6 6 6 ,A,B,C communication device 7 module substrate 8 8 9 ,C,integrated circuit 11 12 13 ,,power amplifier 14 14 14 15 16 ,A,C,,bias circuit 17 18 19 ,,matching circuit 20 PA control circuit 21 inductor 22 23 ,phase shift circuit 24 variable attenuation circuit 30 antenna connection terminal 31 radio-frequency input terminal 32 power supply voltage terminal 33 control terminal