Phase Adjustment Circuit

This application is a national phase entry of PCT Application No. PCT/JP2022/027567, filed on Jul. 13, 2022, which application is hereby incorporated herein by reference.

The present invention relates to a phase adjustment circuit of a sine wave.

At present, the sine wave plays an important role. In communication, the sine wave may be used for generating a carrier wave, or the sine wave may be used as a clock. In the communication, the clock is used not only as the carrier wave, but also as a timing reference for determining data.

When the clock is used as the timing reference for such data determination, it is necessary to adjust the phase of the clock and perform data determination at an appropriate timing. As a method for performing the data determination at an appropriate timing, there is clock data recovery. As means for realizing clock data recovery, a configuration using a phase comparator and a phase adjustment circuit is known. In this configuration, phases are compared by some means, and a desired phase is generated on the basis of the comparison result.

14 FIG. 14 FIG. 203 201 202 In the related art, as the phase adjustment circuit, a configuration disclosed in NPL 1 is known. A configuration of the phase adjustment circuit of the related art is shown in. In the configuration shown in, by adding a sine wave sin ωt as a reference and a sine wave cos ωt having a fixed phase difference of π/2 with respect to the sine wave sin ωt by an adder, an arbitrary intermediate phase waveform is generated. The sine waves sin ωt and cos ωt are multiplied by constants A and B by multipliersand, respectively. The following Equation is established from equation of trigonometric function synthesis.

α in Equation (1) is as follows:

14 FIG. 200 200 2 In the configuration of, sine waves sin ωt and cos ωt are generated, using a Quadrature-Voltage Controlled Oscillator (VCO). However, since the Quadrature-VCOhas a lower oscillation frequency in terms of structure, there is a problem that it is difficult to use in a limit region of a device. In addition, although a method of using a 90 degree hybrid is known as a method of producing a sine wave having a fixed phase difference of x/from the sine wave, there is a problem that it operates only at a specific frequency when using the 90 degree hybrid.

[NPL 1] Arun Goyal, et al., “A High-Resolution Digital Phase Interpolator Based CDR with a Half-Rate Hybrid Phase Detector”, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), May 2019

Embodiments of the present invention is made to solve above problem, and an object thereof is to provide a phase adjustment circuit that can be used in a wide range of frequencies.

A phase adjustment circuit according to embodiments of the present invention include a sine wave output unit configured to output two sine wave signals of a fixed phase difference; a first multiplying unit configured to output a signal obtained by multiplying an amplitude of a first sine wave signal output from the sine wave output unit by a first variable; a second multiplying unit configured to output a signal obtained by multiplying an amplitude of a second sine wave signal output from the sine wave output unit by a second variable; an adding unit configured to add the signal output from the first multiplying unit and the signal output from the second multiplying unit; an amplitude detecting unit configured to detect an amplitude of an output signal of the adding unit; a differential amplifying unit configured to subtract and amplify the amplitude detected by the amplitude detecting unit from a target amplitude; a first low-pass filter configured to flatten an output result of the differential amplifying unit; a third multiplying unit configured to apply a signal obtained by multiplying an amplitude of the signal output from the first low-pass filter by a first constant, to the first multiplying unit as a control signal for determining the first variable; and a fourth multiplying unit configured to apply a signal obtained by multiplying the amplitude of the signal output from the first low-pass filter by a second constant, to the second multiplying unit as a control signal for determining the second variable.

According to embodiments of the present invention, by providing a sine wave output unit, first and second multiplying units, and an adding unit, it is not necessary to use a conventional Quadrature-VCO as a clock generation unit which is a base of the since wave signal, and an LC-VCO made up of a general LC oscillator can be used as the clock generation unit. In addition, embodiments of the present invention can be used in a wide range of frequencies, unlike a configuration in which a 90-degree hybrid is used as the clock generation unit. Further, in embodiments of the present invention, by providing an amplitude detecting unit, a differential amplifying unit, a first low-pass filter, and third and fourth multiplying units, an output amplitude of the adding unit can be made constant.

1 FIG. First, a configuration of a phase adjustment circuit according to embodiments of the present invention will be explained using. Embodiments of the present invention realize a function of adjusting the phase to an arbitrary phase by adding two sine waves having an arbitrary phase difference at an arbitrary ratio.

1 FIG. 1 2 3 1 4 3 5 2 6 4 7 5 6 8 7 The phase adjustment circuit ofincludes a clock generation unitwhich generates a sinusoidal clock signal, buffer unitsandwhich receive a signal output from the clock generation unitas an input, a delay unitwhich delays the signal output from the buffer unit, a multiplying unitwhich outputs a signal obtained by multiplying an amplitude of the signal output from the buffer unitby A, a multiplying unitwhich outputs a signal obtained by multiplying an amplitude of the signal output from the delay unitby B, an adding unitwhich adds the signal output from the multiplying unitand the signal output from the multiplying unit, and an automatic gain control (AGC) unitwhich keeps the amplitude of the output signal of the adding unitconstant.

1 FIG. 1 FIG. 1 1 7 In the configuration shown in, it is possible to generate an arbitrary waveform by adding a reference sine wave sin ωt and a sine wave sin (ωt+φ), which differs in phase by φ, at an arbitrary magnification. The clock generation unitdoes not need to use a conventional Quadrature-VCO, and can use an LC-VCO made up of a general LC oscillator. In addition, the configuration shown incan be used at a wide range of frequencies, unlike a configuration that uses a 90-degree hybrid like the clock generation unit. An output signal OUT of the adding unitis expressed by the following Equation.

In Equation (3), ejωt represents a reference sin wave. It can be seen from Equation (3) that the sin wave having the phase different by p from the reference phase can be generated, by adding the sin wave having the reference frequency and the sin wave having a phase different by an arbitrary phase q. Here, the phase angle ρ is given by Equation (4).

1 FIG. 7 8 8 7 8 8 In the configuration shown in, there is a problem that it is difficult to keep the amplitude of the output signal OUT of the adding unitconstant. Therefore, an AGC unitis added as a solution. The AGC unitdetects the amplitude of the output signal OUT of the adding unitand adjusts the output amplitude by automatically controlling the amplification factor. However, when the AGC unitis inserted into a main signal path, there is a problem that distortion caused by nonlinearity of the AGC unitis generated in the signal. Further, there is a problem that noise increases and signal quality deteriorates.

1 FIG. In embodiments of the present invention, output amplitude adjustment without using AGC is realized on the basis of the configuration shown in.

2 FIG. 1 2 3 1 4 3 5 2 6 4 7 5 6 9 7 10 9 11 10 12 11 1 5 13 11 2 6 Embodiments of the present invention will be described hereinafter with reference to the drawings.is a block diagram showing a configuration of a phase adjustment circuit according to a first embodiment of the present invention. The phase adjustment circuit includes a clock generation unitwhich generates a sinusoidal clock signal, buffer unitsandwhich receive a signal output from the clock generation unitas an input, a delay unitwhich delays the signal output from the buffer unit, a multiplying unitwhich outputs a signal obtained by multiplying an amplitude of the signal output from the buffer unitby A (first variable), a multiplying unitwhich outputs a signal obtained by multiplying an amplitude of the signal output from the delay unitby B (second variable), an adding unitwhich adds the signal output from the multiplying unitand the signal output from the multiplying unit, an amplitude detecting unitwhich detects the amplitude of the output signal of the adding unit, a differential amplifying unitwhich subtracts the amplitude detected by the amplitude detecting unitfrom a target amplitude Vref and amplifies it, a low-pass filter (LPF)which flattens the output result from the differential amplifying unit, a multiplying unitwhich applies a signal obtained by multiplying the amplitude of the signal output from the LPFby Vratio(first constant) to the multiplying unitas a control signal for determining the first variable, and a multiplying unitthat supplies a signal obtained by multiplying the amplitude of the signal output from the LPFby Vratio(second constant) to the multiplying unitas a control signal for determining the second variable.

1 2 3 4 16 16 2 FIG. The clock generation unit, the buffer unitsand, and the delay unitconstitute a sine wave output unitthat outputs two sine wave signals having a fixed phase difference. The phase difference between the two sine wave signals is not limited to 90 degrees, but may be an arbitrary phase difference. In embodiments of the present invention, the sine wave output unitmay have a configuration different from that shown in.

1 2 12 13 Vratioand Vratioare arbitrary real numbers set in advance. A and B are real numbers determined by the control signals output from the multiplying unitsand.

1 1 2 It is apparent from Equations (3) and (4) that the phase difference given to the reference phase (phase of sine wave sin ωt output from the clock generation unit) is determined by the ratio of A to B. In this embodiment, the same phase difference as that when A=Vratioand B=Vratioare set.

5 6 7 9 10 11 12 13 3 FIG. The configuration of this embodiment includes a feedback circuit for controlling the signal amplitude. The feedback circuit is made up of the multiplying unitsand, an adding unit, the amplitude detecting unit, a differential amplifying unit, the LPF, and the multiplying unitsand. The feedback circuit is equivalent to the control model of the signal amplitude as shown in.

7 7 1 2 100 101 100 102 101 103 102 Y indicates the amplitude of the signal output from the adding unit, and P indicates a fixed amplitude which is the result of amplitude adjustment based on the signal output from the adding unitwhen A=Vratioand B=Vratioare satisfied. The control model is made up of a subtracting unitwhich subtracts the amplitude Y from the target amplitude Vref, an amplifying unitwhich amplifies the subtraction result from the subtracting unit, an LPFwhich allows only a low frequency component out of the output of the amplifying unitto pass, and a multiplying unitwhich multiplies the constant amplitude P by the output of the LPF.

1 2 1 2 As described above, the phase difference given to the reference phase is determined from the ratio of A to B. The ratio is determined as A:B=Vratio:Vratio, and set to a constant value by Vratioand Vratio.

3 FIG. The control model shown inshows a general feedback system. On the assumption that the entire system is stable, by applying a low-pass characteristic as the frequency characteristic H(ω), the amplitude Y can be brought close to the target amplitude Vref.

3 FIG. 4 FIG. Next, the stability of the control model will be considered. In order to stabilize the control model, it is necessary that the signal at the output terminal be stable even when noise is input to each node shown in.shows a block diagram of a control model when it is assumed that noise is input to each node. Here, the block diagram is rewritten with Vref as an input and Y as an output.

101 102 103 100 101 4 FIG. ΔE is a noise which is input to the amplifying unit, ΔKo is a noise which is input to the LPF, ΔX is a noise which is input to the multiplying unit, and ΔY is a noise which is input to the subtracting unit. When the transfer characteristic of the amplifying unitis represented by K and the transfer characteristic of the structure shown inis calculated, Equation (5) is obtained.

(I) PHK/(1+PHK) is stable. (II) P/(1+PHK) is stable. (III) PH/(1+PHK) is stable. When the influence on the output amplitude Y from each noise component is calculated, a term of PHK/(1+PHK)×(ΔE−ΔY), a term of P/(1+PHK)×(ΔX), and a term of PH/(1+PHK)×(ΔKo) overlap. Therefore, in order to stabilize the control model, it is necessary to satisfy the following three conditions (I) to (III).

(a) The transfer characteristic K of the amplifier is stable. (b) The characteristic H of the LPF is stable. (c) 1/(1+PHK) is stable. Since the amplitude P is a constant, the condition (II) may be stated as “1/(1+PHK) is stable,” the condition (III) may be stated as “H is stable” under the condition (II), and similarly, the condition (I) may be stated as “K is stable.” Thus, when the conditions for stabilizing the control model are reorganized, it is necessary to satisfy the following three conditions (a) to (c). Therefore, the feedback circuit may be designed to satisfy the conditions (a) to (c).

5 FIG. 1 FIG. 6 FIG. 1 52 FIG., and 50 1 51 7 shows the results of confirming by a circuit simulation that the phase of the sine wave changes by the phase adjustment circuit shown in, andshows the results of confirming by the circuit simulation that the phase of the sine wave changes by the phase adjustment circuit of this embodiment. Reference numeraldenotes a sine wave output from the clock generation unit,denotes a sine wave (output of the adding unit) whose phase is changed by the phase adjustment circuit shown indenotes a sine wave whose phase is changed by the phase adjustment circuit of this embodiment.

1 FIG. In the case of the phase adjustment circuit shown in, the output amplitude fluctuates greatly with respect to the input without adding the AGC unit, but it is understood that the output amplitude can be made constant in this embodiment.

4 4 4 Although there are many methods for realizing the delay unit, the delay unitmay be realized by, for example, propagation delay of wiring. In particular, a transmission line may be used as a wiring for realizing the delay unitto cope with a high frequency. The type and structure of the transmission line are not limited. A coplanar line or a microstrip line may be used as the transmission line.

4 4 4 Further, as the delay unit, an arbitrary number of amplifiers may be cascade-connected. Further, the delay unitmay be realized by a lumped constant element. For example, the delay unitcan be realized by an LCR resonance circuit.

4 Further, the delay unitmay be realized by combining the wiring, the amplifier, and the lumped constant element.

5 6 12 13 5 6 12 13 5 1 1 1 2 1 1 3 1 1 4 1 1 5 2 2 1 2 6 2 2 3 4 7 1 1 4 2 2 3 3 5 7 4 6 7 5 7 7 FIG. n p p n n n p p p n In this embodiment, specific embodiments of the multiplying units,,andof the first embodiment will be described. Gilbert cells, which are variable amplifiers, can be used as the multiplying units,,, and. As shown in, the multiplying unitincludes an NPN bipolar transistor Qin which a control signal IN(first control signal or third control signal) is input to a base and an output signal OUTon a positive phase side is output from a collector; an NPN bipolar transistor Qin which a control signal IN(second control signal or fourth control signal) is input to a base and an output signal OUTof a negative phase side is output from a collector; an NPN bipolar transistor Qin which a control signal INis input to a base and an output signal OUTof the negative phase side is output from a collector; an NPN bipolar transistor Qin which a control signal INis input to a base and an output signal OUTof the positive phase side is output from a collector; an NPN bipolar transistor Qin which a signal INof the positive phase side of the differential signal output from the buffer unitis input to a base and a collector is connected to emitters of the transistors Qand Q; an NPN bipolar transistor Qin which a signal INof the negative phase side of the differential signal output from the buffer unitis input to a base and a collector is connected to emitters of the transistors Qand Q; an NPN bipolar transistor Qin which a bias voltage VB is applied to a base, a resistor Rwhich has one end connected to a power supply voltage VCC and the other end connected to the collectors of the transistors Qand Q; a resistor Rwhich has one end connected to the power supply voltage VCC and the other end connected to the collectors of the transistors Qand Q; a resistor Rwhich has one end connected to the emitter of the transistor Qand the other end connected to the collector of the transistor Q; a resistor Rwhich has one end connected to the emitter of the transistor Qand the other end connected to the collector of the transistor Q; and a resistor Rwhich has one end connected to the emitter of the transistor Qand the other end connected to the ground.

5 1 1 p n. An amplification factor (the amplitude A) of the multiplying unitcan be controlled by a voltage difference between the control signals INand IN

6 5 6 2 2 4 5 6 6 1 1 p n p n. The configuration of the multiplying unitis the same as that of the multiplying unit. In the case of the multiplying unit, differential signals INand INoutput from the delay unitare input to transistors Qand Q. The amplification factor (the amplitude B) of the multiplying unitcan be controlled by the voltage difference between the control signals INand IN

12 5 12 2 2 11 5 6 1 12 1 1 p n p n. The configuration of the multiplying unitis the same as that of the multiplying unit. In the case of the multiplying unit, differential signals INand INoutput from the LPFare input to transistors Qand Q. An amplification factor (the constant Vratio) of the multiplying unitcan be set to a constant value by a voltage difference between the control signals INand IN

13 5 13 2 2 11 5 6 13 2 1 1 p n p n. The configuration of the multiplying unitis the same as that of the multiplying unit. In the case of the multiplying unit, differential signals INand INoutput from the LPFare input to the transistors Qand Q. The amplification factor of the multiplying unit(the above constant Vratio) can be set to a constant value by the voltage difference between the control signals INand IN

1 1 2 2 1 1 2 2 1 1 2 4 11 1 1 2 2 p n p n p n p n p n p n p n In the Gilbert cell, (IN−IN)×(IN−IN) obtained by multiplying (IN−IN) and (IN−IN) becomes an output (OUT-OUT) in terms of the structure. Therefore, the differential signals output from the buffer unit, delay unit, and LPFmay be assigned to INand IN, and INand INmay be used as control signals.

7 FIG. 7 FIG. 5 6 12 13 2 3 4 In the configuration shown in, multiplying units,,, andhave a differential input and differential output type configuration. In order to correspond to the configurations of, the buffer unitsandmay be a differential output type buffer unit. Further, the delay unitmay be a differential transmission line including two transmission lines, or may have a configuration in which differential input and differential output type amplifiers [Third Embodiment]

7 7 7 8 5 5 2 9 5 5 2 10 6 6 2 11 6 6 2 12 13 6 8 11 7 9 10 8 8 12 9 9 12 10 10 13 11 11 13 12 12 13 13 8 FIG. n p p n p n n p In this embodiment, a specific embodiment of the adding unitof the first embodiment will be explained. As the adding unit, a current mode logic (CML) block of a current addition base can be used. As shown in, the adding unitincludes an NPN bipolar transistor Qin which a signal INon a negative phase side of the differential signal output from the multiplying unitis input to a base and an output signal OUTof a positive phase side is output from a collector; an NPN bipolar transistor Qin which a signal INof the positive phase side of the differential signal output from the multiplying unitis input to a base and an output signal OUTof the negative phase side is output from a collector; an NPN bipolar transistor Qin which a signal INof the positive phase side of the differential signal output from the multiplying unitis input to a base and an output signal OUTof the negative phase side is output from a collector; an NPN bipolar transistor Qin which a signal INof the negative phase side of the differential signal output from the multiplying unitis input to a base, and an output signal OUTof the positive phase side is output from a collector; NPN bipolar transistors Qand Qin which a bias voltage Vb is applied to a base; a resistor Rwhich has one end connected to a power supply voltage VCC and the other end connected to the collectors of the transistors Qand Q; a resistor Rwhich has one end connected to the power supply voltage VCC and the other end connected to the collectors of the transistors Qand Q; a resistor Rwhich has one end connected to an emitter of the transistor Qand the other end connected to the collector of the transistor Q; a resistor Rwhich has one end connected to an emitter of the transistor Qand the other end connected to the collector of the transistor Q; a resistor Rwhich has one end connected to an emitter of the transistor Qand the other end connected to the collector of the transistor Q; a resistor Rwhich has one end connected to an emitter of the transistor Qand the other end connected to the collector of the transistor Q; a resistor Rwhich has one end connected to an emitter of the transistor Qand the other end connected to the ground; and a resistor Rwhich has one end connected to an emitter of the transistor Qand the other end connected to the ground.

8 FIG. 8 FIG. 7 FIG. 7 5 6 In the configuration of, the adding unithas a differential input and differential output type configuration. In order to correspond to the configuration shown in, the multiplying unitsandmay be of differential output type as shown in.

8 FIG. 8 FIG. 8 FIG. 8 FIG. 10 10 6 6 9 5 9 5 p n p n The configuration ofmay be used as the differential amplifying unit. In the case of applying to the differential amplifying unit, a signal on the positive phase side of the differential signal indicating the target amplitude Vref may be input as INof, and a signal on the negative phase side of the differential signal indicating the target amplitude Vref may be input as IN. The signal on the negative phase side of the differential signal output from the amplitude detecting unitmay be input as INof, and the signal on the positive phase side of the differential signal output from the amplitude detecting unitmay be input as IN. It is possible to provide a gain depending on how to obtain a circuit constant. In order to achieve both high speed and gain, an amplifying circuit may be provided at a subsequent stage of the configuration ofto form a multi-stage configuration.

9 9 9 14 7 7 15 7 7 16 17 18 16 19 17 20 7 7 21 7 7 22 7 7 23 7 7 24 16 20 21 25 17 22 23 26 14 14 15 15 16 14 16 17 15 17 18 18 19 19 20 20 23 21 21 22 22 24 26 23 25 26 24 26 25 20 23 3 26 21 22 3 1 20 9 FIG. n p n p n p p n In this embodiment, a specific embodiment of the amplitude detecting unitof the first embodiment will be described. A circuit based on a Gilbert cell can be used as the amplitude detecting unit. As shown in, the amplitude detecting unitincludes an NPN bipolar transistor Qin which a signal INon the negative phase side of the differential signal output from the adding unitis input to a base; an NPN bipolar transistor Qin which a signal INon the positive phase side of the differential signal output from the adding unitis input to a base; an NPN bipolar transistor Qto which a base and a collector are connected; an NPN bipolar transistor Qto which a base and a collector are connected; an NPN bipolar transistor Qin which a bias voltage VB is applied to a base and a collector is connected to an emitter of the transistor Q; an NPN bipolar transistor Qin which the bias voltage VB is applied to a base and a collector is connected to an emitter of the transistor Q; an NPN bipolar transistor Qin which a signal INon the negative phase side of the differential signal output from the adding unitis input to a base; an NPN bipolar transistor Qin which a signal INon the positive phase side of the differential signal output from the adding unitis input to a base; an NPN bipolar transistor Qin which the signal INon the negative phase side of the differential signal output from the adding unitis input to a base; an NPN bipolar transistor Qin which a signal INon the positive phase side of the differential signal output from the adding unitis input to a base; an NPN bipolar transistor Qin which a base is connected to the base and the collector of the transistor Qand a collector is connected to emitters of transistors Qand Q; an NPN bipolar transistor Qin which a base is connected to the base and the collector of the transistor Qand a collector is connected to emitters of the transistors Qand Q; an NPN bipolar transistor Qin which a bias voltage VB is applied to a base; a resistor Rwhose one end is connected to the power supply voltage VCC and the other end is connected to a collector of the transistor Q; a resistor Rwhose one end is connected to the power supply voltage VCC and the other end is connected to a collector of the transistor Q; a resistor Rwhose one end is connected to an emitter of the transistor Qand the other end is connected to the base and collector of the transistor Q; a resistor Rwhose one end is connected to an emitter of the transistor Qand the other end is connected to the base and collector of the transistor Q; a resistor Rwhose one end is connected to an emitter of the transistor Qand the other end is connected to the ground; a resistor Rwhose one end is connected to an emitter of the transistor Qand the other end is connected to the ground; a resistor Rwhose one end is connected to the power supply voltage VCC and the other end is connected to collectors of transistors Qand Q; a resistor Rwhose one end is connected to the power supply voltage VCC and the other end is connected to collectors of the transistors Qand Q; a resistor Rwhose one end is connected to an emitter of transistor Qand the other end is connected to a collector of transistor Q; a resistor Rwhose one end is connected to an emitter of the transistor Qand the other end is connected to a collector of the transistor Q; a resistor Rwhose one end is connected to an emitter of the transistor Qand the other end is connected to ground; a resistor Rin which one end is connected to collectors of transistors Qand Qand an output signal OUTof the positive phase side is output from the other end; a resistor Rin which one end is connected to collectors of the transistors Qand Q, and an output signal OUTon the negative phase side is output from the other end; a capacitor Cwhose one end is connected to collectors of the transistors Qand

23 2 21 22 3 25 4 26 Qand the other end is connected to the ground; a capacitor Cwhose one end is connected to collectors of the transistors Qand Qand the other end is connected to the ground; a capacitor Cwhose one end is connected to the other end of the resistor Rand the other end is connected to the ground; and a capacitor Cwhose one end is connected to the other end of the resistor Rand the other end is connected to the ground.

9 FIG. 7 14 26 14 24 25 26 1 4 20 23 24 25 14 19 14 19 16 17 In the circuit of, the output amplitude of the adding unitis squared by a squarer made up of transistors Qto Qand resistors Rto R, and the squared amplitude is flattened by an LPF made up of resistors Rand Rand capacitors Cto Cto detect the amplitude. In order to realize the square of the amplitude by the Gilbert cell, it is necessary to absorb the difference of the in-phase signal level between the signals input to the transistors Qto Qand the signals input to the transistors Qand Q, and an emitter follower made up of transistors Qto Qand resistors Rto Ris inserted in the first stage to adjust the In-phase level of the input signal. It is also possible to replace the diode-connected transistors Qand Qwith resistors or diodes.

9 FIG. 9 FIG. 8 FIG. 9 7 In the configurations of, the amplitude detecting unithas a differential input and differential output type configuration. In order to correspond to the configuration of, the adding unitmay be of a differential output type as shown in.

11 11 27 10 11 5 11 27 10 FIG. In this embodiment, a specific embodiment of the LPFof the first embodiment will be explained. As shown in, the LPFincludes a resistor Rin which a signal output from the differential amplifying unitis input to one end, and the other end is connected to an output terminal of the LPF; and a capacitor Cwhose one end is connected to an output terminal of LPFand the other end is connected to the ground. An inductor may be used instead of the resistor R, or the resistor and the inductor may be used in combination.

10 FIG. Althoughshows the configuration of a passive LPF, an active filter may be used. A digital filter may be used instead of the analogue filter. That is, the signal may be analogue-to-digital (AD) converted, the signal may be digitally processed, and the digital signal may be returned to the analogue signal by digital-to-analog (DA) conversion.

9 9 1 7 9 6 9 11 FIG. 11 FIG. The amplitude detecting unitmay be constituted by the squarer and the LPF as described in the fourth embodiment, but may be constituted by a peak detector as shown in. In the embodiment shown in, the amplitude detecting unitincludes a diode Din which a signal output from the adding unitis input to an anode and a cathode is connected to an output terminal of the amplitude detecting unit, and a capacitor Cwhose one end is connected to the output terminal of the amplitude detecting unitand the other end is connected to the ground.

12 FIG. 9 2 7 7 3 7 4 7 7 2 5 7 3 14 2 4 15 3 5 2 5 p p n n Further, as shown in, the amplitude detecting unitis made up of a diode Din which a signal INon the positive phase side of the differential signal output from the adding unitis input to a cathode, a diode Din which the signal INis input to an anode, a diode Din which a signal INon the negative phase side of the differential signal output from the adding unitis input to a cathode and an anode is connected to an anode of a diode D, a diode Din which the signal INis input to an anode and a cathode is connected to a cathode of a diode D, an LPFwhich flattens the signal at the connecting point between the anode of the diode Dand the anode of the diode D, and an LPFwhich flattens a signal at a connecting point between the cathode of the diode Dand the cathode of the diode D. The diodes Dto Dconstitute an asynchronous detecting circuit.

5 6 7 27 1 2 28 1 2 29 1 2 30 1 2 31 2 2 27 28 32 2 2 29 30 33 34 3 2 35 3 2 36 3 13 FIG. n p p n n n p p p n n p p n n Further, by combining the Gilbert cell and the CML, a configuration in which the multiplying unitsandand the adding unitare integrated may be realized. This configuration includes, as shown in, an NPN bipolar transistor Qin which a control signal IN(first control signal) is input to a base, and an output signal OUTof a positive phase side is output from a collector; an NPN bipolar transistor Qin which a control signal IN(second control signal) is input to a base, and an output signal OUTof the negative phase side is output from a collector; an NPN bipolar transistor Qin which a control signal INis input to a base and the output signal OUTof the negative phase side is output from a collector; an NPN bipolar transistor Qin which a control signal INis input to a base and an output signal OUTof the positive phase side is output from a collector; an NPN bipolar transistor Qin which a signal INof the positive phase side of the differential signal output from the buffer unitis input to a base, and a collector is connected to emitters of the transistors Qand Q; an NPN bipolar transistor Qin which a signal INof the negative phase side of the differential signal output from the buffer unitis input to a base, and a collector is connected to emitters of the transistors Qand Q; an NPN bipolar transistor Qin which a bias voltage VB is applied to a base; an NPN bipolar transistor Qin which a control signal IN(third control signal) is input to a base and an output signal OUTof the positive phase side is output from a collector; an NPN bipolar transistor Qin which a control signal IN(fourth control signal) is input to a base, and an output signal OUTof the negative phase side is output from a collector; an NPN bipolar transistor Qin which a control signal INis input to a base and an output signal

2 37 3 2 38 4 4 34 35 39 4 4 36 37 40 28 27 30 34 37 29 28 29 35 36 30 31 33 31 32 33 32 33 33 38 40 34 39 40 35 40 n p p p n OUTof the negative phase side is output from a collector; an NPN bipolar transistor Qin which a control signal INis input to a base, and an output signal OUTof the positive phase side is output from a collector; an NPN bipolar transistor Qin which a signal INof the positive phase side of the differential signal output from the delay unitis input to a base, and a collector is connected to emitters of the transistors Qand Q; an NPN bipolar transistor Qin which a signal INof the negative phase side of the differential signal output from the delay unitis input to a base, and a collector is connected to emitters of the transistors Qand Q; an NPN bipolar transistor Qin which a bias voltage VB is applied to a base; a resistor Rwhich has one end connected to a power supply voltage VCC, and the other end connected to collectors of the transistors Q, Q, Qand Q; a resistor Rwhich has one end connected to the power supply voltage VCC and the other end connected to collectors of the transistors Q, Q, Qand Q; a resistor Rwhich has one end connected to an emitter of the transistor Qand the other end connected to a collector of the transistor Q; a resistor Rwhich has one end connected to an emitter of the transistor Q, and the other end connected to the collector of the transistor Q; a resistor Rwhich has one end connected to an emitter of the transistor Q, and the other end connected to the ground; a resistor Rwhich has one end connected to an emitter of the transistor Q, and the other end connected to the collector of the transistor Q; a resistor Rwhich has one end connected to an emitter of the transistor Q, and the other end connected to the collector of the transistor Q; and a resistor Rwhich has one end connected to an emitter of the transistor Q, and the other end connected to the ground.

5 1 1 6 3 3 2 1 1 4 3 3 2 2 4 4 p n p n p n p p n p n 7 FIG. The amplification factor (the amplitude A) of the multiplying unitcan be controlled by the voltage difference between the control signals INand IN, and the amplification factor (the amplitude B) of the multiplying unitcan be controlled by the voltage difference between the control signals INand IN. Further, as described in, the differential signals output from the buffer unitmay be allocated to INand IN, the differential signals output from the delay unitmay be allocated to INand IN, and IN, IN, INand INmay be used as control signals.

13 FIG. 1 1 2 2 3 3 4 4 1 1 2 2 3 3 4 4 2 2 p n p n p n p n p n p n p n p n p n With the configuration shown in, an output {(IN−IN)×(IN−IN)}+{(IN−IN)×(IN−IN)} obtained by adding the result of multiplying (IN−IN) and (IN−IN) and the result of multiplying (IN−IN) and (IN−IN) becomes (OUT−OUT).

1 40 7 9 13 FIGS.toand Although an embodiment in which a bipolar transistor is used as the transistors Qto Qis shown in, a MOS transistor may be used. When the MOS transistor is used, in the above description, the base may be replaced with the gate, the collector may be replaced with the drain, and the emitter may be replaced with the source.

Further, a resistor or a capacitor for gain adjustment and frequency response adjustment may be inserted into the emitter or the source of the transistor, or both of the resistor and the capacitor may be inserted into the emitter or the source of the transistor. In addition, an arbitrary amplification circuit such as an emitter follower may be provided as necessary for level adjustment, driving force adjustment, and the like.

(Appendix 1) A phase adjustment circuit according to embodiments of the present invention include a sine wave output unit configured to output two sine wave signals of a fixed phase difference; a first multiplying unit configured to output a signal obtained by multiplying an amplitude of a first sine wave signal output from the sine wave output unit by a first variable; a second multiplying unit configured to output a signal obtained by multiplying an amplitude of a second sine wave signal output from the sine wave output unit by a second variable; an adding unit configured to add the signal output from the first multiplying unit and the signal output from the second multiplying unit; an amplitude detecting unit configured to detect an amplitude of an output signal of the adding unit; a differential amplifying unit configured to subtract and amplify the amplitude detected by the amplitude detecting unit from a target amplitude; a first low-pass filter configured to flatten an output result of the differential amplifying unit; a third multiplying unit configured to apply a signal obtained by multiplying an amplitude of the signal output from the first low-pass filter by a first constant, to the first multiplying unit as a control signal for determining the first variable; and a fourth multiplying unit configured to apply a signal obtained by multiplying the amplitude of the signal output from the first low-pass filter by a second constant, to the second multiplying unit as a control signal for determining the second variable. (Appendix 2) In the phase adjustment circuit set forth in Appendix 1, the first multiplying unit includes a first transistor in which a first control signal or a signal on a negative phase side of the first sine wave signal of a differential form is input to a base or a gate, and a signal on a positive phase side is output from a collector or a drain; a second transistor in which a second control signal or a signal on a positive phase side of the first sine wave signal is input to a base or a gate, and a signal on the negative phase side is output from a collector or a drain; a third transistor in which the first control signal or the signal on the negative phase side of the first sine wave signal is input to a base or a gate, and the signal on the negative phase side is output from a collector or a drain; a fourth transistor in which the second control signal or the signal on the positive phase side of the first sine wave signal is input to a base or a gate, and the signal on the positive phase side is output from a collector or a drain; a fifth transistor in which the signal on the positive phase side of the first sine wave signal or the second control signal is input to a base or a gate, and a collector or a drain is connected to emitters or sources of the first and second transistors; a sixth transistor in which the signal on the negative phase side of the first sine wave signal or the first control signal is input to a base or a gate, and a collector or a drain is connected to emitters or sources of the third and fourth transistors; a seventh transistor in which a bias voltage is applied to a base or a gate; a first resistor in which one end is connected to a power supply voltage and the other end is connected to collectors or drains of the first and fourth transistors; a second resistor in which one end is connected to the power supply voltage and the other end is connected to collectors or drains of the second and third transistors; a third resistor in which one end is connected to an emitter or a source of the fifth transistor and the other end is connected to a collector or a drain of the seventh transistor; a fourth resistor in which one end is connected to an emitter or a source of the sixth transistor and the other end is connected to the collector or drain of the seventh transistor; and a fifth resistor in which one end is connected to the emitter or source of the seventh transistor and the other end is connected to ground, in which the second multiplying unit includes an eighth transistor in which a third control signal or a signal on the negative phase side of the second sine wave signal of the differential type is input to a base or a gate, and a signal on the positive phase side is output from a collector or a drain; a ninth transistor in which a fourth control signal or a signal on the positive phase side of the second sine wave signal is input to a base or a gate, and a signal on the negative phase side is output from a collector or a drain; a tenth transistor in which the third control signal or the signal on the negative phase side of the second sine wave signal is input to a base or a gate, and the signal on the negative phase side is output from a collector or a drain; an eleventh transistor in which the fourth control signal or the signal on the positive phase side of the second sine wave signal is input to a base or a gate, and the signal on the positive phase side is output from a collector or a drain; a twelfth transistor in which the signal on the positive phase side of the second sine wave signal or the fourth control signal is input to a base or a gate, and a collector or drain is connected to emitters or sources of the eighth and ninth transistors; a thirteenth transistor in which the signal on the negative phase side of the second sine wave signal or the third control signal is input to a base or a gate, and a collector or a drain is connected to emitters or sources of the tenth or eleventh transistor; a fourteenth transistor in which a bias voltage is applied to a base or a gate; a sixth resistor in which one end is connected to the power supply voltage and the other end is connected to the collector or drain of the eighth and eleventh transistors; a seventh resistor in which one end is connected to the power supply voltage and the other end is connected to the collector or drain of the ninth and tenth transistor; an eighth resistor in which one end is connected to the emitter or source of the twelfth transistor and the other end is connected to the collector or drain of the fourteenth transistor; a ninth resistor in which one end is connected to the emitter or source of the thirteenth transistor and the other end is connected to the collector or drain of the fourteenth transistor; and a tenth resistor in which one end is connected to the emitter or source of the fourteenth transistor and the other end is connected to ground. (Appendix 3) In the phase adjustment circuit set forth in Appendix 1, the adding unit includes a first transistor in which a signal on the negative phase side of the differential signal output from the first multiplying unit is input to a base or a gate, and a signal on the positive phase side is output from a collector or a drain; a second transistor in which a signal on the positive phase side of the differential signal output from the first multiplying unit is input to a base or a gate, and a signal on the negative phase side is output from a collector or a drain; a third transistor in which the signal on the positive phase side of the differential signal output from the second multiplying unit is input to a base or a gate, and a signal on the negative phase side is output from a collector or a drain; a fourth transistor in which the signal on the negative phase side of the differential signal output from the second multiplying unit is input to a base or a gate to, and the signal on the positive phase side is output from a collector or a drain; fifth and sixth transistors in which a bias voltage is applied to bases or gates; a first resistor which has one end connected to a power supply voltage, and the other end connected to the collectors or drains of the first and fourth transistors; a second resistor which has one end connected to the power supply voltage, and the other end connected to the collectors or drains of the second and third transistors; a third resistor which has one end connected to the emitter or source of the first transistor, and the other end connected to the collector or drain of the fifth transistor; a fourth resistor which has one end connected to the emitter or source of the second transistor, and the other end connected to the collector or drain of the fifth transistor; a fifth resistor which has one end connected to the emitter or source of the third transistor, and the other end connected to the collector or drain of the sixth transistor; a sixth resistor which has one end connected to the emitter or source of the fourth transistor, and the other end connected to the collector or drain of the sixth transistor; a seventh resistor which has one end connected to the emitter or source of the fifth transistor, and the other end connected to ground; and an eighth resistor which has one end connected to the emitter or source of the sixth transistor, and the other end connected to ground. (Appendix 4) In the phase adjustment circuit set forth in Appendix 1, the amplitude detecting unit includes a squarer configured to square the output amplitude of the adding unit, and a second low-pass filter configured to flatten the amplitude squared by the squarer. (Appendix 5) In the phase adjustment circuit set forth in Appendix 4, the second squarer includes a first transistor in which the signal on the negative phase side of the differential signal output from the adding unit is input to a base; a second transistor in which the signal on the positive phase side of the differential signal output from the adding unit is input to a base; a third transistor whose base and collector are connected; a fourth transistor whose base and collector are connected; a fifth transistor in which the bias voltage is applied to a base and a collector is connected to the emitter of the third transistor; a sixth transistor in which the bias voltage is applied to a base and a collector is connected to the emitter of the fourth transistor; a seventh transistor in which the signal on the negative phase side of the differential signal output from the adding unit is input to a base; an eighth transistor in which the signal on the positive phase side of the differential signal output from the adding unit is input to a base; a ninth transistor in which the signal on the negative phase side of the differential signal output from the adding unit is input to a base; a tenth transistor in which the signal on the positive phase side of the differential signal output from the adding unit is input to a base; an eleventh transistor in which a base is connected to the base and collector of the third transistor, and a collector is connected to the emitters of the seventh and eighth transistors; a twelfth transistor in which a base is connected to the base and collector of the fourth transistor, and a collector is connected to the emitters of the ninth and tenth transistors; a thirteenth transistor in which the bias voltage is applied to a base; a first resistor which has one end connected to the power supply voltage, and the other end connected to the collector of the first transistor; a second resistor which has one end connected to the power supply voltage, and the other end connected to the collector of the second transistor; a third resistor which has one end connected to the emitter of the first transistor, and the other end connected to the base and collector of the third transistor; a fourth resistor which has one end connected to the emitter of the second transistor, and the other end connected to the base and collector of the fourth transistor; a fifth resistor which has one end connected to the emitter of the fifth transistor, and the other end connected to ground; a sixth resistor which has one end connected to the emitter of the sixth transistor and the other end connected to ground; a seventh resistor which has one end connected to the power supply voltage, and the other end connected to the collectors of the seventh and tenth transistors; an eighth resistor which has one end connected to the power supply voltage, and the other end connected to the collectors of the eighth and ninth transistors; a ninth resistor which has one end connected to the emitter of the eleventh transistor, and the other end connected to the collector of the thirteenth transistor; a tenth resistor which has one end connected to the emitter of the twelfth transistor, and the other end connected to the collector of the thirteenth transistor, and an eleventh resistor which has one end connected to the emitter of the thirteenth transistor, and the other end connected to ground, and the second low-pass filter includes a twelfth resistor which has one end connected to the collectors of the seventh and tenth transistors, and outputs a output signal on the positive phase side from the other end; a thirteenth resistor which has one end connected to the collectors of the eighth and ninth transistors, and outputs the output signal on the negative phase side from the other end; a first capacitor which has one end connected to the collectors of the seventh and tenth transistors, and the other end connected to ground; a second capacitor which has one end connected to the collectors of the eighth and ninth transistors, and the other end connected to ground; a third capacitor which has one end connected to the other end of the twelfth resistor, and the other end connected to ground; and a fourth capacitor which has one end connected to the other end of the thirteenth resistor, and the other end connected to ground. (Appendix 6) In the phase adjustment circuit set forth in Appendix 1, the amplitude detecting unit includes a first diode in which the signal on the positive phase side of the differential signal output from the adding unit is input to a cathode; a second diode in which the signal on the positive phase side of the differential signal output from the adding unit is input to an anode; a third diode in which the signal on the negative phase side of the differential signal output from the adding unit is input to a cathode, and an anode is connected to an anode of the first diode; a fourth diode in which the signal on the negative phase side of the differential signal output from the adding unit is input to an anode, and a cathode is connected to a cathode of the second diode; a second low-pass filter configured to flatten a signal at a connecting point between the anode of the first diode and the anode of the third diode; and a third low-pass filter configured to flatten a signal at a connecting point between the cathode of the second diode and the cathode of the fourth diode. (Appendix 7) In the phase adjustment circuit set forth in Appendix 1, the differential amplifying includes a first transistor in which the signal on the positive phase side of the differential signal output from the amplitude detecting unit is input to a base or a gate, and the signal on the positive phase side is output from a collector or a drain; a second transistor in which the signal on the negative phase side of the differential signal output from the amplitude detecting unit is input to a base or a gate, and a signal on the negative phase side is output from a collector or a drain; a third transistor in which the signal on the positive phase side of the differential signal indicating the target amplitude is input to a base or a gate, and the signal on the negative phase side is output from a collector or a drain; a fourth transistor in which the signal on the negative phase side of the differential signal indicating the target amplitude is input to a base or a gate, and the signal on the positive phase side is output from a collector or a drain; fifth and sixth transistors in which the bias voltage is applied to bases or gates; a first resistor in which one end is connected to the power supply voltage, and the other end is connected to the collectors or drains of the first and fourth transistors; a second resistor in which one end is connected to the power supply voltage, and the other end is connected to the collectors or drains of the second and third transistors; a third resistor in which one end is connected to the emitter or source of the first transistor, and the other end is connected to the collector or drain of the fifth transistor; a fourth resistor in which one end is connected to the emitter or source of the second transistor, and the other end is connected to the collector or drain of the fifth transistor; a fifth resistor in which one end is connected to the emitter or source of the third transistor, and the other end is connected to the collector or drain of the sixth transistor; a sixth resistor in which one end is connected to the emitter or source of the fourth transistor, and the other end is connected to the collector or drain of the sixth transistor; a seventh resistor in which one end is connected to the emitter or source of the fifth transistor, and the other end is connected to ground; and an eighth resistor in which one end is connected to the emitter or source of the sixth transistor, and the other end is connected to ground. (Appendix 8) In the phase adjustment circuit set forth in Appendix 1, the first and second multiplying units and the adding unit include a first transistor in which a first control signal or a signal on the negative phase side of the first sine wave signal of the differential form is input to a base or a gate, and a signal on the positive phase side is output from a collector or a drain; a second transistor in which a second control signal or a signal on the positive phase side of the first sine wave signal is input to a base or a gate, and a signal on the negative phase side is output from a collector or a drain; a third transistor in which the first control signal or the signal on the negative phase side of the first sine wave signal is input to a base or a gate, and the signal on the negative phase side is output from a collector or a drain; a fourth transistor in which the second control signal or the signal on the positive phase side of the first sine wave signal is input to a base or a gate, and the signal on the positive phase side is output from a collector or a drain; a fifth transistor in which the signal on the positive phase side of the first sine wave signal or the second control signal is input to a base or a gate, and a collector or a drain is connected to the emitters or sources of the first and second transistors; a sixth transistor in which the signal on the negative phase side of the first sine wave signal or the first control signal is input to a base or a gate, and a collector or a drain is connected to the emitters or sources of the third and fourth transistors; a seventh transistor in which the bias voltage is applied to a base or a gate; an eighth transistor in which a third control signal or the signal on the negative phase side of the second sine wave signal of the differential type is input to a base or gate, and the signal on the positive phase side is output from a collector or a drain; a ninth transistor in which a fourth control signal or the signal on the positive phase side of the second sine wave signal is input to a base or gate, and the signal on the negative phase side is output from a collector or a drain; a tenth transistor in which the third control signal or the signal on the negative phase side of the second sine wave signal is input to a base or gate, and the signal on the negative phase side is output from a collector or a drain; an eleventh transistor in which the fourth control signal or the signal on the positive phase side of the second sine wave signal is input to a base or a gate, and the signal on the positive phase side is output from a collector or a drain; a twelfth transistor in which the signal on the positive phase side of the second sine wave signal or the fourth control signal is input a base or a gate, and a collector or a drain is connected to the emitters or sources of the eighth and ninth transistors; a thirteenth transistor in which the signal on the negative phase side of the second sine wave signal or the third control signal is input to a base or a gate, and a collector or a drain is connected to the emitters or sources of the tenth or eleventh transistor; a fourteenth transistor in which the bias voltage is applied to a base or a gate; a first resistor in which one end is connected to the power supply voltage, and the other end is connected to the collectors or drains of the first, fourth, eighth, and eleventh transistors; a second resistor in which one end is connected to the power supply voltage, and the other end is connected to the collectors or drains of the second, third, ninth, and tenth transistor; a third resistor in which one end is connected to the emitter or source of the fifth transistor, and the other end is connected to the collector or drain of the seventh transistor; a fourth resistor in which one end is connected to the emitter or source of the sixth transistor, and the other end is connected to the collector or drain of the seventh transistor; a fifth resistor in which one end is connected to the emitter or source of the seventh transistor, and the other end is connected to ground; a sixth resistor in which one end is connected to the emitter or source of the twelfth transistor, and the other end is connected to the collector or drain of the fourteenth transistor; a seventh resistor in which one end is connected to the emitter or source of the thirteenth transistor, and the other end is connected to the collector or drain of the fourteenth transistor; and an eighth resistor in which one end is connected to the emitter or source of the fourteenth transistor, and the other end is connected to ground. Some or all of the embodiments are also described in the following appendices, but are not limited to the following.

The embodiments of present invention can be applied to the technique of adjusting the phase of a sine wave.

1 Clock generation unit 2 3 ,Buffer unit 4 Delay unit 5 6 12 13 ,,,Multiplying unit 7 Adding unit 9 Amplitude detecting unit 10 Differential amplifying unit 11 14 15 ,,Low pass filter 16 Sine wave output unit 1 40 Qto QTransistor 1 5 Dto DDiode 1 35 Rto RResistor 1 6 Cto CCapacitor