Bandwidth Averaging Using Credit Counters

This application is a divisional of co-pending U.S. patent application Ser. No. 18/489,555, filed Oct. 18, 2023, which is herein incorporated by reference.

Embodiments of the present disclosure generally relate to improving bandwidth accuracy for any window of time.

In Embedded Systems Software (ESS) devices, one of the strict parameters is to have a known steady (average) bandwidth. For example the bandwidth is measured as an average over a 100 mSec, and at accuracy of 5%. However, there is no synchronization between the host and the device on when the 100 mSec window starts. The Solid State Drive (SSD) controller is built to support maximum possible bandwidth. The problem is seen when trying to slow the device down to a fixed (non-max) bandwidth.

In a Firmware (FW) based approach, write commands are not going directly to the read Direct Memory Access (DMA) but go to the FW first. In this mode, both read commands and write commands can be scheduled by the FW to meet the required average performance. In this approach the bandwidth is limited because the FW gets overloaded with the write commands.

In a write throttling based approach, the queue adds a delay before sending commands to the Remote Direct Memory Access (RDMA). This in turn will slow down the device. However, this is not enough for average, possibly during 10 mSec (out of 100 mSec) there are no commands at all. So, there is nothing “to slow” down. However, in this case, the user would want the device to provide more than the average for the other 90 mSec to compensate.

In a credit based approach, when the user does not send data, credit is accumulated. With the accumulation of credit later data can be sent faster. However, this approach is good only the time of when the 100 mSec window is measured is known.

Therefore, there is a need in the art for improving the accuracy of the bandwidth at any time when the bandwidth is measured.

Instead of maximizing the possible bandwidth of device, utilize time slice credits (TSC), to ensure bandwidth average over a sliding window. When the average is ensured over a sliding window, the device should not care when the host decides to sample a 100 mSec for example, as the average will always be correct. By utilizing set percentage of predetermined allotment for the average bandwidth requirement, the system can give out credit on a predetermined interval. The credit is given out based on usage and once credit is depleted, data cannot be sent until more credit is accumulated. When data is not sent, the system is given a chance to accumulate credit to increase the amount of data sent. Once credit is at a level high enough to send data the device will send the data, but not at a speed that will surpass the average bandwidth requirement.

In one embodiment, a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: receive an average bandwidth accuracy requirement; determine a number of credits to issue to meet the average bandwidth accuracy requirement; start a timer; determine that there is any data to send; determine whether there are sufficient credits available to send the data; and either: send the data if the determination is that there are sufficient credits; or wait for sufficient credits and then send the data.

In another embodiment, a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: initialize a plurality of counters; fill a first counters of the plurality of counters with credit; fill a remainder of counters of the plurality of counters with 0 credits; start a timer; determine that there is data to send; determine that the credit is insufficient to send data; accumulate additional credits in the remainder of counters; determine that there is sufficient credit to send the data, wherein the credit is found in the plurality of counters; send the data; and reduce credit from one or more counters of the plurality of counters.

In another embodiment, a data storage device comprises: means to store data; and a controller coupled to the means to store data, wherein the controller is configured to: write data to the means to store data; fetch commands from a host device; parse the fetched commands; add credits to a plurality of counters; subtract credits from the plurality of counters; and maintain a timer for coordinating the adding and subtracting of credits.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.

In the following, reference is made to embodiments of the disclosure. However, it should be understood that the disclosure is not limited to specifically described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the disclosure. Furthermore, although embodiments of the disclosure may achieve advantages over other possible solutions and/or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the disclosure. Thus, the following aspects, features, embodiments, and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the disclosure” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).

Instead of maximizing the possible bandwidth of device, utilize time slice credits (TSC), to ensure bandwidth average over a sliding window. When the average is ensured over a sliding window, the device should not care when the host decides to sample a 100 mSec for example, as the average will always be correct. By utilizing set percentage of predetermined allotment for the average bandwidth requirement, the system can give out credit on a predetermined interval. The credit is given out based on usage and once credit is depleted, data cannot be sent until more credit is accumulated. When data is not sent, the system is given a chance to accumulate credit to increase the amount of data sent. Once credit is at a level high enough to send data the device will send the data, but not at a speed that will surpass the average bandwidth requirement.

1 FIG. 100 106 104 104 110 106 104 138 100 106 100 106 104 is a schematic block diagram illustrating a storage systemhaving a data storage devicethat may function as a storage device for a host device, according to certain embodiments. For instance, the host devicemay utilize a non-volatile memory (NVM)included in data storage deviceto store and retrieve data. The host devicecomprises a host dynamic random access memory (DRAM). In some examples, the storage systemmay include a plurality of storage devices, such as the data storage device, which may operate as a storage array. For instance, the storage systemmay include a plurality of data storage devicesconfigured as a redundant array of inexpensive/independent disks (RAID) that collectively function as a mass storage device for the host device.

104 106 104 106 114 104 1 FIG. The host devicemay store and/or retrieve data to and/or from one or more storage devices, such as the data storage device. As illustrated in, the host devicemay communicate with the data storage devicevia an interface. The host devicemay comprise any of a wide range of devices, including computer servers, network-attached storage (NAS) units, desktop computers, notebook (i.e., laptop) computers, tablet computers, set-top boxes, telephone handsets such as so-called “smart” phones, so-called “smart” pads, televisions, cameras, display devices, digital media players, video gaming consoles, video streaming device, or other devices capable of sending or receiving data from a data storage device.

138 150 150 138 106 108 106 108 150 150 108 112 116 108 106 118 108 150 106 The host DRAMmay optionally include a host memory buffer (HMB). The HMBis a portion of the host DRAMthat is allocated to the data storage devicefor exclusive use by a controllerof the data storage device. For example, the controllermay store mapping data, buffered commands, logical to physical (L2P) tables, metadata, and the like in the HMB. In other words, the HMBmay be used by the controllerto store data that would normally be stored in a volatile memory, a buffer, an internal memory of the controller, such as static random access memory (SRAM), and the like. In examples where the data storage devicedoes not include a DRAM (i.e., optional DRAM), the controllermay utilize the HMBas the DRAM of the data storage device.

106 108 110 111 112 114 116 118 106 106 106 106 106 106 104 1 FIG. The data storage deviceincludes the controller, NVM, a power supply, volatile memory, the interface, a write buffer, and an optional DRAM. In some examples, the data storage devicemay include additional components not shown infor the sake of clarity. For example, the data storage devicemay include a printed circuit board (PCB) to which components of the data storage deviceare mechanically attached and which includes electrically conductive traces that electrically interconnect components of the data storage deviceor the like. In some examples, the physical dimensions and connector configurations of the data storage devicemay conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5″ data storage device (e.g., an HDD or SSD), 2.5″ data storage device, 1.8″ data storage device, peripheral component interconnect (PCI), PCI-extended (PCI-X), PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, MiniPCI, etc.). In some examples, the data storage devicemay be directly coupled (e.g., directly soldered or plugged into a connector) to a motherboard of the host device.

114 104 104 114 114 114 108 104 108 104 108 114 106 104 111 104 114 1 FIG. Interfacemay include one or both of a data bus for exchanging data with the host deviceand a control bus for exchanging commands with the host device. Interfacemay operate in accordance with any suitable protocol. For example, the interfacemay operate in accordance with one or more of the following protocols: advanced technology attachment (ATA) (e.g., serial-ATA (SATA) and parallel-ATA (PATA)), Fibre Channel Protocol (FCP), small computer system interface (SCSI), serially attached SCSI (SAS), PCI, and PCIe, non-volatile memory express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), or the like. Interface(e.g., the data bus, the control bus, or both) is electrically connected to the controller, providing an electrical connection between the host deviceand the controller, allowing data to be exchanged between the host deviceand the controller. In some examples, the electrical connection of interfacemay also permit the data storage deviceto receive power from the host device. For example, as illustrated in, the power supplymay receive power from the host devicevia interface.

110 110 110 108 108 110 The NVMmay include a plurality of memory devices or memory units. NVMmay be configured to store and/or retrieve data. For instance, a memory unit of NVMmay receive data and a message from controllerthat instructs the memory unit to store the data. Similarly, the memory unit may receive a message from controllerthat instructs the memory unit to retrieve data. In some examples, each of the memory units may be referred to as a die. In some examples, the NVMmay include a plurality of dies (i.e., a plurality of memory units). In some examples, each memory unit may be configured to store relatively large amounts of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

In some examples, each memory unit may include any type of non-volatile memory devices, such as flash memory devices, phase-change memory (PCM) devices, resistive random-access memory (ReRAM) devices, magneto-resistive random-access memory (MRAM) devices, ferroelectric random-access memory (F-RAM), holographic memory devices, and any other type of non-volatile memory devices.

110 108 The NVMmay comprise a plurality of flash memory devices or memory units. NVM Flash memory devices may include NAND or NOR-based flash memory devices and may store data based on a charge contained in a floating gate of a transistor for each flash memory cell. In NVM flash memory devices, the flash memory device may be divided into a plurality of dies, where each die of the plurality of dies includes a plurality of physical or logical blocks, which may be further divided into a plurality of pages. Each block of the plurality of blocks within a particular memory device may include a plurality of NVM cells. Rows of NVM cells may be electrically connected using a word line to define a page of a plurality of pages. Respective cells in each of the plurality of pages may be electrically connected to respective bit lines. Furthermore, NVM flash memory devices may be 2D or 3D devices and may be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). The controllermay write data to and read data from NVM flash memory devices at the page level and erase data from NVM flash memory devices at the block level.

111 106 111 104 111 104 114 111 111 The power supplymay provide power to one or more components of the data storage device. When operating in a standard mode, the power supplymay provide power to one or more components using power provided by an external device, such as the host device. For instance, the power supplymay provide power to the one or more components using power received from the host devicevia interface. In some examples, the power supplymay include one or more power storage components configured to provide power to the one or more components when operating in a shutdown mode, such as where power ceases to be received from the external device. In this way, the power supplymay function as an onboard backup power source. Some examples of the one or more power storage components include, but are not limited to, capacitors, super-capacitors, batteries, and the like. In some examples, the amount of power that may be stored by the one or more power storage components may be a function of the cost and/or the size (e.g., area/volume) of the one or more power storage components. In other words, as the amount of power stored by the one or more power storage components increases, the cost and/or the size of the one or more power storage components also increases.

112 108 112 108 112 108 112 110 112 111 112 118 118 106 118 106 106 118 1 FIG. The volatile memorymay be used by controllerto store information. Volatile memorymay include one or more volatile memory devices. In some examples, controllermay use volatile memoryas a cache. For instance, controllermay store cached information in volatile memoryuntil the cached information is written to the NVM. As illustrated in, volatile memorymay consume power received from the power supply. Examples of volatile memoryinclude, but are not limited to, random-access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, and the like)). Likewise, the optional DRAMmay be utilized to store mapping data, buffered commands, logical to physical (L2P) tables, metadata, cached data, and the like in the optional DRAM. In some examples, the data storage devicedoes not include the optional DRAM, such that the data storage deviceis DRAM-less. In other examples, the data storage deviceincludes the optional DRAM.

108 106 108 110 106 104 108 110 108 100 110 106 104 108 116 110 Controllermay manage one or more operations of the data storage device. For instance, controllermay manage the reading of data from and/or the writing of data to the NVM. In some embodiments, when the data storage devicereceives a write command from the host device, the controllermay initiate a data storage command to store data to the NVMand monitor the progress of the data storage command. Controllermay determine at least one operational characteristic of the storage systemand store at least one operational characteristic in the NVM. In some embodiments, when the data storage devicereceives a write command from the host device, the controllertemporarily stores the data associated with the write command in the internal memory or write bufferbefore sending the data to the NVM.

108 120 120 112 120 108 104 122 122 104 104 104 122 104 104 122 108 122 The controllermay include an optional second volatile memory. The optional second volatile memorymay be similar to the volatile memory. For example, the optional second volatile memorymay be SRAM. The controllermay allocate a portion of the optional second volatile memory to the host deviceas controller memory buffer (CMB). The CMBmay be accessed directly by the host device. For example, rather than maintaining one or more submission queues in the host device, the host devicemay utilize the CMBto store the one or more submission queues normally maintained in the host device. In other words, the host devicemay generate commands and store the generated commands, with or without the associated data, in the CMB, where the controlleraccesses the CMBin order to retrieve the stored generated commands and/or associated data.

2 FIG. 200 200 204 208 210 208 212 214 216 218 220 208 222 232 230 228 226 224 208 222 212 is a block diagram illustrating a SSD systemwithout averaging modules, according to one embodiment. The SSD systemcomprises a host, a controller, and a plurality of memory devices (e.g., NANDs)A-D. The controllercomprises a command modulecomprised of a fetch module, parse module, queues, and FW. The controllerfurther comprises a data enginecomprised of a RDMA, a Write Aggregation (WA) module, a Write Direct Memory Access (WDMA), an Error Correction Code (ECC) module, and a flash interface module (FIM). Of the two main components of the controller, the data enginehandles data transfers and the command modulehandles the commands.

214 216 218 220 220 220 218 220 210 222 224 210 226 210 228 204 The read path operates by the fetch modulefetching the commands. Once the commands are fetched, the parse modulewill parse the commands. The parsed commands are then held in the queueuntil the FWis ready. Once the FWis ready, the FWpulls commands from the queues. The FWwill determine the location of the data in the NANDA-D (logical to physical (L2P)) and trigger the data engine. The FIMwill read the data from the NANDA-D. The ECC modulewill fix any bit flips found in the NANDA-D. The WDMAis used to send (write) the data to the host.

214 216 218 232 232 232 232 204 204 230 220 220 226 224 210 The write path operates by the fetch modulefetching the commands. Once the commands are fetched the parse modulewill parse the commands. The parsed commands are then pushed by the queueto the RDMAwhen the RDMAis ready. Once the RDMAis ready, the RDMAbrings (reads) data from the host. As data arrives from the host, the WAaccumulates into NAND-page-size parts and triggers the FW. The FWdecides where to write the data to, and triggers the ECCand prepares the FIMto push the data to the NANDA-D.

208 204 210 220 The differences between the read and write paths emerge from the fact that the controllercan read the data from the host(write command) before deciding where to put the data in the NANDA-D. While for read commands, the FWneeds to first locate the demanded data.

204 208 220 While the problem of averaging exists for both reads and writes, the focus herein is on the write path. As the data transfers between hostand the controllerthe data does not go through the FWfirst, hence the problem is less manageable. Though, the same solution is valid for the read path as well. As will be discussed herein, the bandwidth can be limited to ensure an average within a predetermined window. More particularly, the disclosure discusses the idea of using time slide credits to ensure bandwidth average over a sliding window. When the average is ensured over a sliding window, the device should not care when the host decides to sample a, for example, 100 ms, as the host device will always be correct or rather within about a 5 percent correctness requirement.

3 FIG. 300 300 304 308 310 308 312 314 216 318 320 308 322 334 332 330 328 326 324 308 322 312 is a block diagram illustrating a SSD systemwith time sliced credit (TSC), according to one embodiment. The SSD systemcomprises a host, a controller, and a plurality of memory devices (e.g., NANDs)A-D. The controllercomprises a command moduleincluding a fetch module, parse module, queues, and FW. The controllerfurther comprises a data engineincluding a TSC module, a RDMA module, a WA module, WDMA module, an ECC module, and a FIM. Of the two main components of the controller, the data enginehandles data transfers and the command modulehandles the commands.

314 316 318 334 334 334 334 332 332 304 304 330 320 320 326 324 310 The write path consists of the fetch modulefetching the commands. Once the commands are fetched, the parse modulewill parse the commands. The parsed commands are then pushed by the queueto the TSC modulewhen the TSC moduleis ready. Once the TSC moduleis ready, the TSCensures the write command (data read) can occur without violating the average bandwidth accuracy requirement, and forward the command to the RDMA. The RDMA modulebrings (read) data from the host. As data arrives from the host, the WA moduleaccumulates into NAND-page-size parts and triggers the FW. The FWdecides where to write the data to, and triggers the ECC moduleand prepares the FIMto push the data to the NANDA-D.

4 FIG. 3 FIG. 400 334 is a diagram illustrating a simple credit, according to one embodiment. To better understand the TSC, such as the TSC moduleof, a description of the simple credit-based solution is shown. In this case, every 1 uSec (as example) some credits are provided (FW configured value) e.g., 8 KB. This in turn means that over 100 mSec, 0.8 GB worth of credit (this matches 8 GB/sec bandwidth) is added. Whenever data is sent, the credit is decreased by the size of sent data. When there are not enough credits to send the next transaction, the next transaction will not get sent. The limit in this approach is that the limit does not meet averaging on any 100 mSec window.

5 FIG. 500 500 500 500 500 500 500 500 500 500 is a diagram illustrating a graph showing a stochastic system, according to one embodiment. The stochastic systemis supporting 16 GB/sec rate, with an average bandwidth accuracy requirement of 50% bandwidth limit (8 GB/average). At the beginning of the stochastic system, there is no command for the first 50 mSec. For those first 50 mSec there is a credit given to the stochastic systemof 400 MB. After the completion of the 50 mSec there is another 400 MB of credit given to the stochastic system. At that time there is a total of 800 MB of credit, so the stochastic systemis able to send data at the full speed of 16 GB/sec for the next 50 mSec. At the completion of sending that data at 16 GB/sec for 50 mSec the credit will depleted. At the start of the next 50 mSecs, a new credit of 400 MB is given to the stochastic system. With the 400 MB credit the stochastic systemcan send data at max 8 GB/see for the next 50 mSec. At the completion of sending the data at 8 BGPs for 50 mSec the credit is depleted. At the start of the next 50 mSecs a new credit of 400 MB is given to the stochastic system. With the 400 MB credit the stochastic systemcan send data at max 4 GB/sec for the next 50 mSec.

500 500 500 For the averages of data sent, at the interval “A” the stochastic systemsent data at an average of 8 GB/sec for 100 mSec. At the interval “C” the stochastic systemsent data at an average of 6 GB/sec for 100 mSec. At the interval “B” the stochastic systemsent data at an average of 12 GB/sec for 100 mSec which violates the average bandwidth accuracy requirement. To meet the average bandwidth requirement of a “sliding window measurement” at 5% error, 20 credit counters are used (5%*20=100%). Each such credit counter is responsible for 5% of the 100 mSec (5 mSec). At each point of time, the decision to allow sending data, depends on having available credits in any of the previous 20 counters. When 5 mSec passes, the oldest credit counter is dropped, and a new credit counter is generated. Whenever sending data, the oldest counter containing credit, gets decremented.

6 FIG. 3 FIG. 600 600 602 600 604 604 334 606 608 600 610 610 600 608 600 612 612 600 606 is a flowchart illustrating a methodfor TSC, according to certain embodiments. The methodbegins at blockand the methodproceeds to block. At block, the TSC, such as the TSC moduleof, generates 19 counters filled with zero credits, and one more with “X” credits. For example, “X” is dependent upon the average bandwidth accuracy requirement (5%), therefore 8 GB/sec average bandwidth accuracy requirement, and this value will be 400 MB the 5 mSec. At block, the TSC starts a 5 mSec timer. The timer is 5 mSecs because that is 5% of the 100 mSec average bandwidth accuracy requirement. At block, the TSC determines whether there is data to send. If the TSC determines that there is no data to send, then the methodproceeds to block. At block, the TSC determines if the 5 mSec has expired. If the TSC determines that the 5 mSec has not expired, then the methodreturns to block. If the TSC determines that the 5 mSec has expired, then the methodproceeds to block. At block, the TSC removes the oldest credit counter and generates a new counter with “X” credits and the methodreturns to block.

600 614 614 600 616 600 616 616 600 612 600 618 618 600 620 620 608 If the TSC determines that there is data to send, then the methodproceeds to block. At block, the TSC determines whether there is enough credits in the 20 counters. If the TSC determines that there is not enough credits in the 20 counters, then the methodproceeds to block. It should be noted, if there is not enough credits in one bucket, the TSC will continue removing more credits from the next oldest credit counter. Credits will be removed until all demanded credits are removed and the methodwill proceeds to block. At block, the TSC waits for the 5 mSec timer to expire and the methodreturns to block. If the TSC determines that there is enough credits in the 20 counters, then the methodproceeds to block. At block, the TSC sends the data and the methodproceeds to block. At block, the TSC decreases the credit from the oldest (non-zero) credit counter and the method returns to block.

5 FIG. This last action (removing any remains from oldest credit counter) ensures that the device does not reach the case where there “over credit” to allow the device to reach a higher than average bandwidth, such as interval “B” of, on any measured 100 mSec. The device can overshoot by 5% (which is allowed) of the average.

By splitting the measured length into bins (number depends on the average bandwidth accuracy requirement) we allow the bandwidth measurement to be correct at any measured time, as with a sliding-time window. The TSC improves the predictability of the average bandwidth without complex FW involvement.

In one embodiment, a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: receive an average bandwidth accuracy requirement; determine a number of credits to issue to meet the average bandwidth accuracy requirement; start a timer; determine that there is any data to send; determine whether there are sufficient credits available to send the data; and either: send the data if the determination is that there are sufficient credits; or wait for sufficient credits and then send the data. The controller is configured to set the timer for an increment equal to a percentage of a sample size set by a host device, wherein the percentage is equal to the average bandwidth accuracy requirement. The controller is configured to remove credit after sending the data. The credit is removed from an oldest non zero credit counter. The controller is configured to determine which credit counter is an oldest credit counter. The controller is configured to add credit to a counter after the timer is incremented for a first segment. The waiting comprises waiting for the timer to expire. The controller is configured to remove all credits from a credit counter when the timer has expired, wherein restart the timer when the timer has expired. The credit counter is an oldest credit counter of a plurality of credit counters. The controller is configured to generate a new counter after removing the oldest credit. The controller is configured to add credit to the new counter. A total number of credits is insufficient to exceed a higher than average bandwidth on any measured period of time set by a host device.

In another embodiment, a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: initialize a plurality of counters; fill a first counters of the plurality of counters with credit; fill a remainder of counters of the plurality of counters with 0 credits; start a timer; determine that there is data to send; determine that the credit is insufficient to send data; accumulate additional credits in the remainder of counters; determine that there is sufficient credit to send the data, wherein the credit is found in the plurality of counters; send the data; and reduce credit from one or more counters of the plurality of counters. A number of the plurality of counters is equal to 1 divided by a correctness requirement. The sample time period is set by a host device. A correctness requirement is set by the host device. The controller includes a time slide credit module.

In another embodiment, a data storage device comprises: means to store data; and a controller coupled to the means to store data, wherein the controller is configured to: write data to the means to store data; fetch commands from a host device; parse the fetched commands; add credits to a plurality of counters; subtract credits from the plurality of counters; and maintain a timer for coordinating the adding and subtracting of credits. The controller is configured to subtract credits from an oldest counter of the plurality of counters when the timer has expired. The controller is configured to generate a new counter with credits when the timer expires, wherein the controller is further configured to restart a counter from the plurality of counters when the counter has expired.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.