Delayed Execution of a Multiple-Read Operation

This application claims the benefit of U.S. Provisional Application No. 63/674,004, titled “Delayed Execution of a Multiple-Read Operation”, filed Jul. 22, 2024, which is hereby incorporated herein by reference in its entirety.

Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to delaying execution of a multiple-read operation in a memory device of a memory sub-system.

A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices.

1 1 FIGS.A-B Aspects of the present disclosure are directed to delaying execution of a multiple-read operation in a memory device of a memory sub-system. A memory sub-system can be a storage device, a memory module, or a combination of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored in the memory sub-system and can request data to be retrieved from the memory sub-system.

1 1 FIGS.A-B A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. One example of non-volatile memory devices is a negative-and (NAND) memory device. Other examples of non-volatile memory devices are described below in conjunction with. A non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells. A memory cell is an electronic circuit that stores information. Depending on the memory cell type, a memory cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1”, or combinations of such values.

A memory device can include multiple memory cells arranged in a two-dimensional or three-dimensional grid. The memory cells are formed onto a silicon wafer in an array of columns (also hereinafter referred to as bitlines) and rows (also hereinafter referred to as wordlines). A wordline can refer to one or more conductive lines of a memory device that are used with one or more bitlines to generate the address of each of the memory cells. The intersection of a bitline and wordline constitutes the address of the memory cell. A block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a wordline group, a wordline, or individual memory cells. One or more blocks can be grouped together to form a plane of the memory device in order to allow concurrent operations to take place on each plane. The memory device can include circuitry that performs concurrent memory page accesses of two or more memory planes. For example, the memory device can include a respective access line driver circuit and power circuit for each plane of the memory device to facilitate concurrent access of pages of two or more memory planes, including different page types. For ease of description, these circuits can be generally referred to as independent plane driver circuits. Control logic on the memory device includes a number of separate processing threads to perform concurrent memory access operations (e.g., read operations, program operations, and erase operations). For example, each processing thread corresponds to a respective one of the memory planes and utilizes the associated independent plane driver circuits to perform the memory access operations on the respective memory plane. As these processing threads operate independently, the power usage and requirements associated with each processing thread also varies.

A memory device can be a three-dimensional (3D) memory device. For example, a 3D memory device can be a three-dimensional (3D) replacement gate memory device (e.g., 3D replacement gate NAND), which is a memory device with a replacement gate structure using wordline stacking. For example, a 3D replacement gate memory device can include wordlines, select gates, etc. located between sets of layers including a pillar (e.g., polysilicon pillar), a tunnel oxide layer, a charge trap (CT) layer, and a dielectric (e.g., oxide) layer. A 3D replacement gate memory device can have a “top deck” corresponding to a first side and a “bottom deck” corresponding to a second side. For example, the first side can be a drain side and the second side can be a source side. Data in a 3D replacement gate memory device can be stored as 1 bit/memory cell (SLC), 2 bits/memory cell (MLC), 3 bits/memory cell (TLC), etc.

In some memory sub-systems, a read operation is performed to read the data stored for each memory page in a selected block. Each read operation requires execution of multiple stages or sequences including a setup (or prologue) sequence, a sense sequence, and a discharge sequence. Accordingly, multiple individual read operations (including the multiple sequences) are executed to read multiple different memory pages, resulting the execution of multiple instances of the setup and discharge sequences.

To reduce the latency associated with the above approach, some systems employ a “seamless read operation” (also referred to as a “multiple-read operation”). A multiple-read operation includes a read operation (e.g., a single read operation) that is performed to read data from a set of multiple pages, where the setup and discharge sequences are “shared” during the reading of those multiple memory pages. As compared to performing an individual read operation for each page, the multiple-read operation includes a single setup sequence, followed by multiple sense sequences (i.e., a sense sequence for each of the pages being read), followed by a single discharge sequence. Accordingly, execution of a multiple-read operation reduces the read time associated with reading multiple pages by “skipping” the setup sequence and discharge sequence between two consecutive read operations associated with a same wordline or block.

Execution of a multiple-read operation can, however, result in memory cells can experiencing read disturb. Read disturb is the result of continually reading from one memory cell without intervening erase operations, causing other nearby memory cells to change over time (e.g., become programmed). If too many read operations are performed on a memory cell, data stored at adjacent memory cells of the memory component can become corrupted or incorrectly stored at the memory cell. This can result in a higher error rate of the data stored at the memory cell. This can increase the use of an error detection and correction operation (e.g., an error control operation) for subsequent operations (e.g., read and/or write) performed on the memory cell. The increased use of the error control operation can result in a reduction of the performance of a conventional memory sub-system. In addition, as the error rate for a memory cell or block continues to increase, it may even surpass the error correction capabilities of the memory sub-system, leading to an irreparable loss of the data. Furthermore, as more resources of the memory sub-system are used to perform the error control operation, fewer resources are available to perform other read operations or write operations.

Additional read disturb associated with the multiple-read operation can result due to limitations in the speed of the associated physical host interface (e.g., ONFI bus) that is used to transmit the data that is sensed or read from the multiple pages. In this regard, speed limitations associated with the physical host interface can result in a bottleneck which results in undesirable wait time during the in-progress multiple-read operation and additional read disturb caused by the memory array remaining polarized at the read voltage level (i.e., read stress) while waiting for the next command and for latch availability. Accordingly, the multiple-read operation can result in significant waiting time and additional read stress, particularly at the beginning of a new sequence of the multiple-read operation (e.g., prior to a sense sequence associated with a target page).

Aspects of the present disclosure address the above and other deficiencies by executing one or more multiple-read operations (e.g., one or mor seamless read operations) including multiple sense or sense sequences (e.g., a first sense sequence to read data from a first page, a second sense sequence to read data from a second page, etc.) to read data from multiple pages, where a delay period (herein referred to as a “multiple-read delay”) from a time of the multiple-read operation request is caused prior to a start of an initial sense sequence or initial read of the multiple pages. Advantageously, delaying the start of the initial sense sequence (i.e., the initial read) of the multiple-read operation by the multiple-read delay enables realignment of a completion or end of the first read of the multiple-read operation with a completion of the transfer of data read of a previous page (herein “previous page data”) by the communication interface to a host system. By employing the multiple-read delay to realign the completion of the first read of the multiple-read operation to coincide with the completion of the transfer of the previous page data, wait time of an in-progress multiple-read operation is eliminated or reduced, which eliminates or reduces the additional read disturb and read stress that can result from communication interface bottleneck.

Advantages of the present disclosure include, but are not limited to, improved memory sub-system performance and quality of service (QOS). For example, employing the multiple-read delay reduces the occurrence of polarizing the portion of the memory of a page at a read voltage as the array waits for a next read command. This results in the reduction or elimination of read disturb due to the unavailability of internal resources that are being used to store data associated with an operation (e.g., latches storing data for a read operation N), while data associated with a next operation (e.g., read operation N−1) is being transferred via the communication interface. In such cases, the data being transferred can be corrupted by a subsequent operation (e.g., N+1 read operation), if that operation starts prior to the completion of the data transfer via the communication interface data and prior to movement of the data associated with the N−1 operation from the internal latches. Accordingly, when the communication interface is slow, the availability of the internal resources (e.g., latches) is negatively impacted.

1 FIG.A 100 110 110 140 130 illustrates an example computing systemthat includes a memory sub-systemin accordance with some embodiments of the present disclosure. The memory sub-systemcan include media, such as one or more volatile memory devices (e.g., memory device), one or more non-volatile memory devices (e.g., memory device), or a combination of such.

110 A memory sub-systemcan be a storage device, a memory module, or a combination of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory modules (NVDIMMs).

100 The computing systemcan be a computing device such as a desktop computer, laptop computer, network server, mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), Internet of Things (IoT) enabled device, embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes memory and a processing device.

100 120 110 120 110 120 110 1 FIG.A The computing systemcan include a host systemthat is coupled to one or more memory sub-systems. In some embodiments, the host systemis coupled to multiple memory sub-systemsof different types.illustrates one example of a host systemcoupled to a memory sub-system. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

120 120 110 110 110 The host systemcan include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller, compute express link (CXL) controller). The host systemuses the memory sub-system, for example, to write data to the memory sub-systemand read data from the memory sub-system.

120 110 120 110 120 130 110 120 110 120 110 120 1 FIG.A The host systemcan be coupled to the memory sub-systemvia a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a CXL interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Pillar, Serial Attached SCSI (SAS), a double data rate (DDR) memory bus, Small Computer System Interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., DIMM socket interface that supports Double Data Rate (DDR)), etc. The physical host interface can be used to transmit data between the host systemand the memory sub-system. The host systemcan further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices) when the memory sub-systemis coupled with the host systemby the physical host interface (e.g., PCIe or CXL bus). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-systemand the host system.illustrates a memory sub-systemas an example. In general, the host systemcan access multiple memory sub-systems via a same communication connection, multiple separate communication connections, and/or a combination of communication connections.

130 140 140 The memory devices,can include any combination of the different types of non-volatile memory devices and/or volatile memory devices. The volatile memory devices (e.g., memory device) can be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

130 Some examples of non-volatile memory devices (e.g., memory device) include a negative-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory cells can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

130 130 130 Each of the memory devicescan include one or more arrays of memory cells. One type of memory cell, for example, single level memory cells (SLC) can store one bit per memory cell. Other types of memory cells, such as multi-level memory cells (MLCs), triple level memory cells (TLCs), quad-level memory cells (QLCs), and penta-level memory cells (PLCs) can store multiple bits per memory cell. In some embodiments, each of the memory devicescan include one or more arrays of memory cells such as SLCs, MLCs, TLCs, QLCs, PLCs or any combination of such. In some embodiments, a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory devicescan be grouped as pages that can refer to a logical unit of the memory device used to store data. With some types of memory (e.g., NAND), pages can be grouped to form blocks.

130 Although non-volatile memory components such as a 3D cross-point array of non-volatile memory cells and NAND type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory devicecan be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide based memories, ferroelectric transistor random-access memory (FeTRAM), ferroelectric random access memory (FeRAM), magneto random access memory (MRAM), Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), negative-or (NOR) flash memory, or electrically erasable programmable read-only memory (EEPROM).

115 115 130 130 115 115 A memory sub-system controller(or controllerfor simplicity) can communicate with the memory devicesto perform operations such as reading data, writing data, or erasing data at the memory devicesand other such operations. The memory sub-system controllercan include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The hardware can include a digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controllercan be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

115 117 119 119 115 110 110 120 The memory sub-system controllercan include a processing device, which includes one or more processors (e.g., processor), configured to execute instructions stored in a local memory. In the illustrated example, the local memoryof the memory sub-system controllerincludes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system, including handling communications between the memory sub-systemand the host system.

119 119 110 115 110 115 1 FIG.A In some embodiments, the local memorycan include memory registers storing memory pointers, fetched data, etc. The local memorycan also include read-only memory (ROM) for storing micro-code. While the example memory sub-systeminhas been illustrated as including the memory sub-system controller, in another embodiment of the present disclosure, a memory sub-systemdoes not include a memory sub-system controller, and can instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

115 120 130 115 130 115 120 130 130 120 In general, the memory sub-system controllercan receive commands or operations from the host systemand can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices. The memory sub-system controllercan be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., a logical block address (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices. The memory sub-system controllercan further include host interface circuitry to communicate with the host systemvia the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devicesas well as convert responses associated with the memory devicesinto information for the host system.

110 110 115 130 The memory sub-systemcan also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-systemcan include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the memory sub-system controllerand decode the address to access the memory devices.

130 135 115 130 115 130 130 110 130 132 115 In some embodiments, the memory devicesinclude local media controllersthat operate in conjunction with memory sub-system controllerto execute operations on one or more memory cells of the memory devices. An external controller (e.g., memory sub-system controller) can externally manage the memory device(e.g., perform media management operations on the memory device). In some embodiments, memory sub-systemis a managed memory device, which is a raw memory devicehaving control logic (e.g., local controller) on the die and a controller (e.g., memory sub-system controller) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

135 137 137 130 137 137 130 120 1 6 FIGS.B- According to embodiments, the local media controllerincludes a read managerconfigured to implement a multiple-read operation (e.g., a single read operation which includes shared setup and discharge sequences and multiple read or sense sequences to read data from multiple pages associated with one or more wordlines) including a multiple-read delay (e.g., a preset time period) prior to a first read sub-operation of the multiple-read operation. According to embodiments, the read managerreceive a request to execute a multiple-read operation to read a set of multiple pages of the memory device. In response to the request, the read managercauses a delay of a predetermined time period (referred to as the multiple-read delay) prior to initiating execution of the requested multiple-read operation. For example, in response to a request for a multiple-read operation to read page X and page Y in a single read operation, the read managerdelays the start of the first sense or sense sequence in the set of requested reads (e.g., the sense sequence associated with page X) by the time period of the multiple-read delay. According to embodiments, delaying the start of the initial sense sequence of the multiple-read operation by the multiple-read delay enables realignment of a completion or end of the first read of the multiple-read operation with a completion of the transfer of data read of a previous page (herein “previous page data”) by a communication interface between the memory deviceand the host system. Advantageously, employing the multiple-read delay to realign the completion of the first read of the multiple-read operation to coincide with the completion of the transfer of the previous page data eliminates or reduces a wait time of the in-progress multiple-read operation since the communication interface is made available upon the transfer completion. This further eliminates or reduces the additional read disturb and read stress that can result when a typical multiple-read operation (i.e., without a delayed start) is forced to wait for the communication interface to become available. Further details regarding the execution of one or more multiple-read operations including a multiple-read delay prior to a first read sub-operation are described below with reference to.

1 FIG.B 1 FIG.A 130 115 110 115 130 is a simplified block diagram of a first apparatus, in the form of a memory device, in communication with a second apparatus, in the form of a memory sub-system controllerof a memory sub-system (e.g., memory sub-systemof), according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and the like. The memory sub-system controller(e.g., a controller external to the memory device), may be a memory controller or other external host device.

130 104 104 1 FIG.B Memory deviceincludes an array of memory cellslogically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., a wordline) while memory cells of a logical column are typically selectively connected to the same data line (e.g., a bitline). A single access line may be associated with more than one logical row of memory cells and a single data line may be associated with more than one logical column. Memory cells (not shown in) of at least a portion of array of memory cellsare capable of being programmed to one of at least two target data states.

108 112 104 130 160 130 130 114 160 108 112 124 160 135 Row decode circuitryand column decode circuitryare provided to decode address signals. Address signals are received and decoded to access the array of memory cells. Memory devicealso includes input/output (I/O) control circuitryto manage input of commands, addresses and data to the memory deviceas well as output of data and status information from the memory device. An address registeris in communication with I/O control circuitryand row decode circuitryand column decode circuitryto latch the address signals prior to decoding. A command registeris in communication with I/O control circuitryand local media controllerto latch incoming commands.

135 130 104 115 135 104 135 108 112 108 112 135 137 130 A controller (e.g., the local media controllerinternal to the memory device) controls access to the array of memory cellsin response to the commands and generates status information for the external memory sub-system controller, i.e., the local media controlleris configured to perform access operations (e.g., read operations, programming operations and/or erase operations) on the array of memory cells. The local media controlleris in communication with row decode circuitryand column decode circuitryto control the row decode circuitryand column decode circuitryin response to the addresses. In one embodiment, local media controllerincludes the read manager, which can execute a multiple-read operation including a delayed start prior to reading multiple pages of the memory device.

135 118 118 135 104 118 170 104 118 160 118 160 115 170 118 118 170 130 204 122 160 135 115 1 FIG.B The local media controlleris also in communication with a cache register. Cache registerlatches data, either incoming or outgoing, as directed by the local media controllerto temporarily store data while the array of memory cellsis busy writing or reading, respectively, other data. During a program operation (e.g., write operation), data may be passed from the cache registerto the data registerfor transfer to the array of memory cells; then new data may be latched in the cache registerfrom the I/O control circuitry. During a read operation, data may be passed from the cache registerto the I/O control circuitryfor output to the memory sub-system controller; then new data may be passed from the data registerto the cache register. The cache registerand/or the data registermay form (e.g., may form a portion of) a page buffer of the memory device. A page buffer may further include sensing devices (not shown in) to sense a data state of a memory cell of the array of memory cells, e.g., by sensing a state of a data line connected to that memory cell. A status registermay be in communication with I/O control circuitryand the local memory controllerto latch the status information for output to the memory sub-system controller.

130 115 135 132 132 130 130 115 136 115 136 Memory devicereceives control signals at the memory sub-system controllerfrom the local media controllerover a control link. For example, the control signals can include a chip enable signal CE #, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE #, a read enable signal RE #, and a write protect signal WP #. Additional or alternative control signals (not shown) may be further received over control linkdepending upon the nature of the memory device. In one embodiment, memory devicereceives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory sub-system controllerover a multiplexed input/output (I/O) busand outputs data to the memory sub-system controllerover I/O bus.

136 160 124 136 160 114 160 118 170 104 For example, the commands may be received over input/output (I/O) pins [7:0] of I/O busat I/O control circuitryand may then be written into command register. The addresses may be received over input/output (I/O) pins [7:0] of I/O busat I/O control circuitryand may then be written into address register. The data may be received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitryand then may be written into cache register. The data may be subsequently written into data registerfor programming the array of memory cells.

118 170 130 115 In an embodiment, cache registermay be omitted, and the data may be written directly into data register. Data may also be output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device. Although reference may be made to I/O pins, they may include any conductive node providing for electrical connection to the memory deviceby an external device (e.g., the memory sub-system controller), such as conductive pads or conductive bumps as are commonly used.

130 1 1 FIGS.A-B 1 1 FIGS.A-B 1 1 FIGS.A-B 1 1 FIGS.A-B It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory deviceofhas been simplified. It should be recognized that the functionality of the various block components described with reference tomay not necessarily be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device could be adapted to perform the functionality of more than one block component of. Alternatively, one or more components or component portions of an integrated circuit device could be combined to perform the functionality of a single block component of. Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins (or other I/O node structures) may be used in the various embodiments.

2 2 FIGS.A-C 2 FIG.A 2 FIG.A 200 104 200 202 202 204 202 200 0 N are diagrams of portions of an example array of memory cells included in a memory device, in accordance with some embodiments of the present disclosure. For example,is a schematic of a portion of an array of memory cellsA as could be used in a memory device (e.g., as a portion of array of memory cells). Memory arrayA includes access lines, such as wordlinesto, and a data line, such as bitline. The wordlinesmay be connected to global access lines (e.g., global wordlines), not shown in, in a many-to-one relationship. For some embodiments, memory arrayA may be formed over a semiconductor that, for example, may be conductively doped to have a conductivity type, such as a p-type conductivity, e.g., to form a p-well, or an n-type conductivity, e.g., to form an n-well.

200 202 204 208 208 208 208 202 208 202 204 204 204 204 208 208 202 204 204 204 204 208 204 204 204 200 204 204 208 202 208 202 202 206 202 N 0 2 4 N 1 3 5 3 5 0 M 0 N 2 FIG.A Memory arrayA can be arranged in rows each corresponding to a respective wordlineand columns each corresponding to a respective bitline. Rows of memory cellscan be divided into one or more groups of physical pages of memory cells, and physical pages of memory cellscan include every other memory cellcommonly connected to a given wordline. For example, memory cellscommonly connected to wordlineand selectively connected to even bitlines(e.g., bitlines,,, etc.) may be one physical page of memory cells(e.g., even memory cells) while memory cellscommonly connected to wordlineand selectively connected to odd bitlines(e.g., bitlines,,, etc.) may be another physical page of memory cells(e.g., odd memory cells). Although bitlines-are not explicitly depicted in, it is apparent from the figure that the bitlinesof the array of memory cellsA may be numbered consecutively from bitlineto bitline. Other groupings of memory cellscommonly connected to a given wordlinemay also define a physical page of memory cells. For certain memory devices, all memory cells commonly connected to a given wordline might be deemed a physical page of memory cells. The portion of a physical page of memory cells (which, in some embodiments, could still be the entire row) that is read during a single read operation or programmed during a single programming operation (e.g., an upper or lower page of memory cells) might be deemed a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as all memory cells connected to wordlines-(e.g., all stringssharing common wordlines). Unless expressly distinguished, a reference to a page of memory cells herein refers to the memory cells of a logical page of memory cells.

2060 206 206 216 208 208 208 206 210 210 210 212 212 212 210 210 212 212 210 210 214 212 212 215 210 212 210 216 210 208 206 210 206 216 210 214 212 204 206 212 208 206 212 206 204 212 215 0 N 0 M 0 M 0 M 0 M 0 M 0 M 0 N Each column can include a string of series-connected memory cells (e.g., non-volatile memory cells), such as one of stringsto. Each stringcan be connected (e.g., selectively connected) to a source line(SRC) and can include memory cellsto. The memory cellsof each stringcan be connected in series between a select gate, such as one of the select gatesto, and a select gate, such as one of the select gatesto. In some embodiments, the select gatestoare source-side select gates (SGS) and the select gatestoare drain-side select gates. Select gatestocan be connected to a select line(e.g., source-side select line) and select gatestocan be connected to a select line(e.g., drain-side select line). The select gatesandmight represent a plurality of select gates connected in series, with each select gate in series configured to receive a same or independent control signal. A source of each select gatecan be connected to SRC, and a drain of each select gatecan be connected to a memory cellof the corresponding string. Therefore, each select gatecan be configured to selectively connect a corresponding stringto SRC. A control gate of each select gatecan be connected to select line. The drain of each select gatecan be connected to the bitlinefor the corresponding string. The source of each select gatecan be connected to a memory cellof the corresponding string. Therefore, each select gatemight be configured to selectively connect a corresponding stringto the bitline. A control gate of each select gatecan be connected to select line.

2 FIG.B 2 FIG.A 206 216 204 216 In some embodiments, and as will be described in further detail below with reference to, the memory array inis a three-dimensional memory array, in which the stringsextend substantially perpendicular to a plane containing SRCand to a plane containing a plurality of bitlinesthat can be substantially parallel to the plane containing SRC.

2 FIG.B 200 104 200 206 206 204 204 212 216 210 206 204 206 204 215 215 212 206 204 210 214 202 200 202 0 M 0 L is another schematic of a portion of an array of memory cellsB (e.g., a portion of the array of memory cells) arranged in a three-dimensional memory array structure. The three-dimensional memory arrayB may incorporate vertical structures which may include semiconductor pillars where a portion of a pillar may act as a channel region of the memory cells of strings. The stringsmay be each selectively connected to a bit line-by a select gateand to the SRCby a select gate. Multiple stringscan be selectively connected to the same bitline. Subsets of stringscan be connected to their respective bitlinesby biasing the select lines-to selectively activate particular select gateseach between a stringand a bitline. The select gatescan be activated by biasing the select line. Each wordlinemay be connected to multiple rows of memory cells of the memory arrayB. Rows of memory cells that are commonly connected to each other by a particular wordlinemay collectively be referred to as tiers.

2 FIG.C 2 2 FIGS.A-B 2 2 FIGS.A-B 2 FIG.C 2 2 FIGS.A-B 200 104 238 238 206 204 238 238 206 204 202 238 238 206 0 1 0 10 11 1 is a diagram of a portion of an array of memory cellsC (e.g., a portion of the array of memory cells). Channel regions (e.g., semiconductor pillars)andrepresent the channel regions of different strings of series-connected memory cells (e.g., stringsof) selectively connected to the bitline. Similarly, channel regionsandrepresent the channel regions of different strings of series-connected memory cells (e.g., NAND stringsof) selectively connected to the bitline. A memory cell (not depicted in) may be formed at each intersection of a wordlineand a channel region, and the memory cells corresponding to a single channel regionmay collectively form a string of series-connected memory cells (e.g., a stringof). Additional features might be common in such structures, such as dummy wordlines, segmented channel regions with interposed conductive regions, etc.

3 FIG. 1 FIG.A 3 FIG. 301 110 302 illustrates an example timeline associated with activities performed by a communication interfaceof a memory sub-system (e.g., memory sub-systemof) and one or more wordlinesassociated with a set of pages to be read by executing a multiple-read operation including a multiple-read delay, according to one or more embodiments of the present disclosure. In the example shown in, each multiple-read operation (e.g., multiple-read operation N−1, multiple-read operation N, and multiple-read operation N+1) includes two read or sense sequences (i.e., each multiple-read operation includes reading two pages in a single operation having shared setup and discharge sequences).

3 FIG. n−1 Read P0 302 As shown in, at a time (t), multiple-read operation N−1 is executed during which page 0 (P0) and page 1 (P1) associated with one or more wordlinesare read. As illustrated, multiple-read operation N−1 includes a first time period or duration (TRead P0) during which data associated with P0 is sensed or read, a second time period or duration (TRead P1) during which data associated with P1 is sensed or read, and a third time period or duration (TD) during which a shared discharge associated with the reading of both P0 and P1 is performed. Although not shown, a portion of the Tperiod may include execution of a setup sequence associated with the multiple-read operation N−1.

3 FIG. 1 1 FIGS.A andB 1 1 FIGS.A andB 1 1 FIGS.A andB 3 FIG. Read P0 n 301 137 135 130 302 As shown in, following completion of T, the communication interface(e.g., an ONFI interface providing communication with the host system) is used to transfer the read data associated with P0 to the host system (i.e., the P0 data transfer). As illustrated, at a time (t), a request to perform multiple-read operation N is identified by control logic (e.g., read managerof) of a local media controller (e.g., local media controllerof) of a memory device (e.g., memory deviceof). In the example shown in, multiple-read operation N includes reading page 2 (P2) and page 3 (P3) associated with one or more wordlines.

3 FIG. 1 1 FIGS.A andB n MD 301 137 As illustrated in, at the time the request for multiple-read operation N is received (i.e., t), communication interfaceis busy transferring data (e.g., the P1 data transfer) associated with the previous operation (e.g., multiple-read operation N−1). According to embodiments, in response to the request to execute multiple-read operation N, the control logic (e.g., read managerof) causes a start of multiple-read operation N to be delayed by a time period (i.e., the multiple-read delay T).

303 303 301 MD According to embodiments, as shown by dashed line, an end or completion of a first sense sequence (e.g., reading of P2) of multiple-read operation N aligns with an end or completion of the transfer of data (e.g., the P1 data transfer) associated with the previous operation (e.g., multiple-read operation N−1). According to embodiments, causing the start of the first sense sequence (e.g., the P2 sense sequence) of multiple-read operation N to be delayed by the multiple-read delay Tenables the alignment, such that a next sense sequence (e.g., the P3 sense sequence) can be executed without undesirable waiting time associated with the communication interface. Advantageously, the alignment and corresponding elimination or reduction in such waiting time enables the elimination or reduction in extra read stress that results when a typical multiple-read operation (i.e., a multiple-read operation that does not include a multiple-read delay) is executed.

n+1 n+1 MD 137 302 301 137 1 1 FIGS.A andB 3 FIG. 3 FIG. 1 1 FIGS.A andB As illustrated, at a time (t), a request to perform multiple-read operation N+1 is identified by control logic (e.g., read managerof). In the example shown in, multiple-read operation N+1 includes reading page 4 (P4) and page 5 (P5) associated with one or more wordlines. As illustrated in, at the time the request for multiple-read operation N+1 is received (i.e., t), communication interfaceis busy transferring data (e.g., the P3 data transfer) associated with the previous operation (e.g., multiple-read operation N+1). According to embodiments, in response to the request to execute multiple-read operation N+1, the control logic (e.g., read managerof) causes a start of multiple-read operation N+1 to be delayed by the multiple-read delay T.

304 304 301 As described above, as shown by dashed line, an end or completion of a first sense sequence (e.g., reading of P2) of multiple-read operation N+1 aligns with an end or completion of the transfer of data (e.g., the P3 data transfer) associated with the previous operation (e.g., multiple-read operation N). According to embodiments, alignmenteliminates or reduces a wait time associated with executing the next sense sequence (e.g., the reading of P5), since communication interfaceis in a ready state and available.

4 FIG. 1 FIG.A 4 FIG. 401 110 402 illustrates an example timeline associated with activities performed by a communication interfaceof a memory sub-system (e.g., memory sub-systemof) and one or more wordlinesassociated with a set of pages to be read by executing a multiple-read operation including a multiple-read delay, according to one or more embodiments of the present disclosure. In the example shown in, each multiple-read operation (e.g., multiple-read operation N−1, multiple-read operation N, and multiple-read operation N+1) includes three read or sense sequences (i.e., each multiple-read operation includes reading a set of three pages in a single operation having shared setup and discharge sequences).

4 FIG. n−1 D 402 Like the example described above, as shown in, at a time (t), multiple-read operation N−1 is executed during which page 0 (P0), page 1 (P1), and page 2 (P2) associated with one or more wordlinesare read. As illustrated, multiple-read operation N−1 includes a first time period or duration (TRead P0) during which data associated with P0 is sensed or read, a second time period or duration (TRead P1) during which data associated with P1 is sensed or read, a third time period or duration (TRead P2) and a fourth time period or duration (T) during which a shared discharge associated with the reading of both P0 and P1 is performed. Although not shown, a portion of the TRead P0 period may include execution of a setup sequence associated with the multiple-read operation N−1.

4 FIG. 401 401 401 wait As illustrated in, following completion of the sense sequence associated with P0, a sense sequence associated with P1 of multiple-read operation N−1 is performed during TRead P1 and the communication interfaceis used to transfer the read data associated with P0 to the host system (i.e., the P0 data transfer). Following completion of the sense sequence associated with P1, a sense sequence associated with P2 of multiple-read operation N−1 is performed during TRead P2 and the communication interfaceis used to transfer the read data associated with P1 to the host system (i.e., the P1 data transfer). It is noted that there may be waiting time (T; as denoted by dashed lines) prior to starting the P2 sense sequence of the multiple-read operation N−1 as a result of the communication interfacebeing busy with the P0 data transfer.

n 137 130 402 1 1 FIGS.A andB 1 1 FIGS.A andB 4 FIG. As illustrated, at a time (t), a request to perform multiple-read operation N is identified by control logic (e.g., read managerof) of a memory device (e.g., memory deviceof). In the example shown in, multiple-read operation N includes reading page 3 (P3), page 4 (P4), and page 5 (P5) associated with one or more wordlines.

4 FIG. 1 1 FIGS.A andB n MD 401 137 As illustrated in, at the time the request for multiple-read operation N is received (i.e., t), communication interfaceis busy transferring data (e.g., the P2 data transfer) associated with the previous operation (e.g., multiple-read operation N−1). According to embodiments, in response to the request to execute multiple-read operation N, the control logic (e.g., read managerof) causes a start of multiple-read operation N to be delayed by a time period (i.e., the multiple-read delay T).

403 403 401 401 MD According to embodiments, as shown by dashed line, an end or completion of a first sense sequence (e.g., reading of P3) of multiple-read operation N aligns with an end or completion of the transfer of data (e.g., the P2 data transfer) associated with the previous operation (e.g., multiple-read operation N−1). According to embodiments, causing the start of the first sense sequence (e.g., the P3 sense sequence) of multiple-read operation N to be delayed by the multiple-read delay Tenables the alignment, such that a next sense sequence (e.g., the P4 sense sequence) can be executed without undesirable waiting time associated with the communication interface. This results in the elimination or a reduction in read disturb that can be caused by read stress (the memory array remaining polarized) during a waiting time when the communication interfaceis busy transferring data.

5 FIG. 1 1 FIGS.A-B 500 500 500 135 137 is a flow diagram of a methodto cause execution of a multiple-read operation (e.g., a seamless read operation) including multiple sense or sense sequences (e.g., a first sense sequence to read data from a first page, a second sense sequence to read data from a second page, etc.) to read data from multiple pages in a single operation (e.g., with a shared setup and discharge sequence), where a delay period (i.e., the multiple-read delay) from a time of the multiple-read operation request is caused prior to a start of an initial sense sequence (i.e., initial read) of the multiple pages, in accordance with some embodiments of the present disclosure. The methodcan be performed by control logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the methodis performed by the local media controllerand/or the read managerof. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

510 520 3 4 FIGS.and 3 FIG. 3 4 FIGS.and At operation, a request is identified. For example, control logic can identify, at a first time, a request to execute a multiple-read operation including a first sense sequence to read first data associated with a first page of a plurality of pages of a memory device and a second sense sequence to read second data associated with a second page of the plurality of pages of the memory device. In an embodiment, the request to perform the multiple-read operation (e.g., multiple-read operation N of) is received at the first time to read multiple the pages (e.g., page 2 and page 3 of) in the same or single operation (e.g., a read operation including a shared setup sequence, multiple sense sequences, and a shared discharge sequence). At operation, a delay is caused. For example, control logic can cause execution of the multiple-read operation to be delayed to a second time. In an embodiment, the delay period (e.g., the multiple-read operation delay of) is a preset or predetermined duration that can be caused from the time of identifying the request (i.e., the first time) to perform the multiple-read operation. In an embodiment, the delay period is a duration that spans from the first time to a second time.

530 510 530 3 FIG. 3 4 FIGS.and 3 FIG. 1 4 FIGS.A- MD At operation, an operation is executed. For example, control logic can cause, at the second time, the execution of the multiple-read operation, where the first sense sequence and a transfer of data associated with a prior operation via a communication interface associated with the memory device complete at substantially a same time (e.g., substantially concurrently). In an embodiment, with reference to the example shown in, the initial or first page of the multiple pages associated with the multiple-read operation is P2. In an embodiment, the delay period (e.g., T) of) that is waited prior to starting the read or sense sequence of the first page in the set of multiple pages (e.g., P2) causes the completion of the sense sequence of the first page to align or coincide in time (e.g., occur substantially concurrently) with a completion of a data transfer of a read data associated with a previous operation (e.g., the P1 data transfer of) by a communication interface of the memory sub-system. Advantageously, the alignment in time (e.g., the substantially concurrent completion) of the completion of the first sense sequence of the multiple-read operation being execute and the transfer of data associated with a previous operation by the communication interface (e.g., transfer of the read data to the host system) enables a waiting time (and associated read stress) between the first sense sequence and a next sense sequence to be eliminated or reduced. Further details regarding operations-are described above with reference to.

6 FIG. 1 FIG.A 1 FIG.A 1 FIG.A 600 600 120 110 135 137 illustrates an example machine of a computer systemwithin which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some embodiments, the computer systemcan correspond to a host system (e.g., the host systemof) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-systemof) or can be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to the local media controllerand/or the read managerof). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a memory cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

600 602 604 606 618 630 The example computer systemincludes a processing device, a main memory(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system, which communicate with each other via a bus.

602 602 602 626 600 608 620 Processing devicerepresents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing devicecan also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing deviceis configured to execute instructionsfor performing the operations and steps discussed herein. The computer systemcan further include a network interface deviceto communicate over the network.

618 624 626 626 604 602 600 604 602 624 618 604 110 1 FIG.A The data storage systemcan include a machine-readable storage medium(also known as a computer-readable medium) on which is stored one or more sets of instructionsor software embodying any one or more of the methodologies or functions described herein. The instructionscan also reside, completely or at least partially, within the main memoryand/or within the processing deviceduring execution thereof by the computer system, the main memoryand the processing devicealso constituting machine-readable storage media. The machine-readable storage medium, data storage system, and/or main memorycan correspond to the memory sub-systemof.

626 135 136 624 1 FIG.A In one embodiment, the instructionsinclude instructions to implement functionality corresponding to a local media controller and/or PPM component (e.g., the local media controllerand/or the read managerof). While the machine-readable storage mediumis shown in an example embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMS, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.