Disk Device

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2024-115853, filed on Jul. 19, 2024; the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a disk device.

In a disk device having a disk medium in which multiple tracks each including multiple sectors is defined, error correction for each of the sectors is performed for the disk medium on a per track basis, in some cases. In the disk device, it is desirable to appropriately perform error correction.

In general, according to one embodiment, there is provided a disk device including a head, a disk medium and a controller. The disk medium has a recording surface configured to face the head, the disk medium being medium where multiple tracks defined on the recording surface, each of the multiple tracks including multiple sectors. The controller is configured to perform error correction for each of the sectors on a per track basis. The controller is configured to predict, while writing data to a first track of the multiple tracks by the head, that the number of error sectors of a second track adjacent to the first track reaches a correction limit number of sectors, according to a track margin identified by first management information and an off-track amount of the first track. The controller is configured to update the first management information according to a bit error rate reference value and a bit error rate of information read from a track.

Exemplary embodiments of a disk device will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.

The disk device according to an embodiment includes the disk medium in which the multiple tracks each including the multiple sectors is defined, and error correction is performed for the disk medium for each of the sectors on a per track basis, where the error correction is devised appropriately.

1 1 1 FIG. 1 FIG. A disk devicecan be configured as illustrated in.is a diagram illustrating a configuration of the disk device.

1 2 1 2 2 1 2 The disk deviceis configured to be connected to a hostvia a communication medium. The disk deviceis connected to the hostand configured to function as a storage medium for the host. The disk deviceis configured to receive an access command from the host. The access command includes a write command and a read command.

1 11 12 13 15 16 21 22 24 30 27 28 29 The disk deviceincludes a disk medium, a spindle motor (SPM), a ramp, an actuator arm, a voice coil motor (VCM), a driver, a head, a preamplifier, a controller, a volatile memory, a nonvolatile memory, and a buffer memory.

30 1 30 23 25 26 30 The controllerenables integral control of the units of the disk device. The controllerincludes a hard disk controller (HDC), a read/write channel (RWC), and a processor. The controllercan be constituted by a system-on-chip (SoC).

11 11 The disk mediumis a disk-type storage medium, and may be, for example, a magnetic disk or a magneto-optical disk. When the disk mediumis the magnetic disk, magnetic layer is formed on a surface thereof, and information is recordable according to a magnetization direction.

12 11 1 The SPMrotatably supports the disk mediumin a housing (not illustrated) of the disk device.

21 12 16 26 21 The driveris configured to drive the SPMand the VCMunder the control of the processor. The drivercan be constituted by an integrated circuit (IC).

22 11 22 11 22 22 22 22 15 22 11 16 21 w r The headis configured to face the recording surface of the disk medium. The headwrites or reads data to or from the disk mediumby using a write elementand a read elementthat are provided at the head. Furthermore, the headis mounted to an end of the actuator arm. The headis moved for seeking in a radial direction of the disk mediumby the VCMdriven by the driver.

11 22 13 13 22 11 For example, when the rotation of the disk mediumis stopped, the headis moved onto the ramp. The rampis configured to hold the headat a position separated from the disk medium.

24 11 22 25 24 25 22 24 The preamplifieramplifies a signal read from the disk mediumby the head, outputs the amplified signal, and supplies the output signal to the RWC, upon reading. In addition, the preamplifieramplifies a signal corresponding to data supplied from the RWCand supplies the amplified signal to the head, upon writing. The preamplifiercan be constituted by an integrated circuit (IC).

25 23 24 25 11 24 23 The RWCperforms modulation including error correction coding on data supplied from the HDCand supplies the modulated data to the preamplifier. In addition, the RWCperforms demodulation including error correction decoding on the signal read from the disk mediumand supplied from the preamplifier, and outputs the signal to the HDCas digital data.

25 25 The error correction coding performed by the RWCincludes generation of a parity for track ECC. The error correction performed by the RWCincludes the track ECC. The track ECC will be described later.

23 2 29 The HDCperforms control of transmission and reception of data to and from the hostvia the I/F bus, control of the buffer memory, and the like.

29 2 29 29 29 Furthermore, the buffer memoryis used as a buffer for data transmitted to and received from the host. The buffer memoryis constituted by, for example, a volatile memory capable of high-speed operation. The type of the memory constituting the buffer memoryis not limited to a specific type. The buffer memorycan be constituted by, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), or a combination thereof.

26 27 28 29 26 The processoris, for example, a central processing unit (CPU). The volatile memory, the nonvolatile memory (flash read only memory), and the buffer memoryare connected to the processor.

28 28 27 11 The nonvolatile memorystores firmware (program data), various operation parameters, and the like. In addition, the nonvolatile memoryis used as an emergency storage destination for various information in the volatile memorywhen power supply is stopped. Note that part or all of the firmware may be stored in the disk medium.

27 27 26 The volatile memoryis constituted by, for example, DRAM, SRAM, or a combination thereof. The volatile memoryis used by the processor, as an area into which the firmware is loaded or an area in which various management information is cached or buffered.

26 28 27 21 24 25 23 26 27 The processorloads the firmware from the nonvolatile memoryinto the volatile memoryto execute control of the driver, the preamplifier, the RWC, the HDC, and the like according to the loaded firmware. The processoruses, upon control, various management information cached or buffered in the volatile memory.

25 26 23 30 30 27 28 29 Note that a configuration including the RWC, the processor, and the HDCcan be considered as the controller. In addition to these components, the controllermay include another component (e.g., the volatile memory, the nonvolatile memory, the buffer memory, or the like).

30 30 26 Some or all of the functions of the controllermay be implemented by a hardware circuit such as a field-programmable gate array (FPGA) or an application specific integrated circuit (ASIC). Some or all of the functions of the controllermay be implemented by executing the firmware by the processor.

2 FIG. 2 FIG. 2 FIG. 1 11 1 11 3 15 1 15 4 22 1 22 6 11 1 11 3 22 1 22 6 11 1 11 3 22 1 22 6 11 1 11 3 As illustrated in, the disk devicemay include multiple disk media_to_, multiple actuator arms_to_, and multiple heads_to_.is a diagram illustrating a configuration of the disk media_to_and the heads_to_.illustrates the configuration of the disk media_to_and the heads_to_, with the disk media_to_viewed from a side along the recording surface.

11 1 11 3 12 12 15 1 15 4 16 16 15 1 15 2 15 3 15 4 11 1 11 2 11 3 11 3 11 4 11 4 The multiple disk media_to_are arranged to be spaced apart along a shaft of the SPMand is rotatably supported by the shaft of the SPM. The multiple actuator arms_to_are arranged spaced apart along a shaft of the VCMand is rotatably supported by the shaft of the VCM. The actuator arms_,_,_, and_is configured to move for seeking in the radial direction, above the disk medium_, between the disk media_and_, between the disk media_and_, and below the disk medium_, respectively.

22 1 15 1 11 1 22 2 15 2 11 1 22 3 15 2 11 2 22 4 15 3 11 2 22 5 15 3 11 3 22 6 15 1 11 3 The head_is provided at an end on a lower side of the actuator arm_so as to face a recording surface on an upper side of the disk medium_. The head_is provided at an end on an upper side of the actuator arm_so as to face a recording surface on a lower side of the disk medium_. The head_is provided an end on a lower side of the actuator arm_so as to face a recording surface on an upper side of the disk medium_. The head_is provided at an end on an upper side of the actuator arm_so as to face a recording surface on a lower side of the disk medium_. The head_is provided an end on a lower side of the actuator arm_so as to face a recording surface on an upper side of the disk medium_. The head_is provided at an end on an upper side the actuator arm_and so as to face a recording surface on a lower side of the disk medium_.

11 11 3 FIG. 3 FIG. Each of the disk mediacan be configured as illustrated in.is a diagram illustrating a configuration of the disk medium.

11 42 3 FIG. Servo information is written on the disk mediumby, for example, a servo writer or self-servo write (SSW) in a manufacturing process.illustrates servo areasradially arranged, as an example of the arrangement of the servo areas in which the servo information is written.

11 The servo information includes sector/cylinder information, a burst pattern, a post code, and the like. The sector/cylinder information can give position information (servo sector address) in a circumferential direction of the disk mediumand position information (track number) of a track set in the radial direction. The track number obtained from the sector/cylinder information is an integer value indicating the position of a track, and the burst pattern represents an offset after the decimal point relative to the position indicated by the track number. The post code is a correction amount for correcting the distortion of the track set on the basis of a combination of the sector/cylinder information and the burst pattern.

26 21 22 42 The processorand the driverperform positioning control for the head, such as seeking and following, on the basis of the servo information read from a servo area.

43 42 42 43 42 44 41 11 Data areasin which data can be written are provided between servo areas. One servo areaand one data areasubsequent to the servo areaconstitute a servo sector. Multiple concentric tracksare set in the radial direction of the disk medium.

43 41 22 11 In the data area, multiple sectors are provided along each of the tracks. Writing and reading by the headare executed on a per sector basis. Each sector may have any storage capacity, but basically has a uniform storage capacity in the disk medium.

41 41 42 4 FIG. 4 FIG. 4 FIG. Each trackmay have a configuration as illustrated in.is a diagram illustrating a configuration of the track. In, the servo areais not illustrated.

4 FIG. 41 Each sector is identified by a sector number. A sector whose sector number is x is represented as a sector #x. In an example illustrated in, the trackincludes (n+1) sectors from a sector #1 to a sector #(n+1).

The trailing sector of the (n+1) sectors, that is, the sector #(n+1) to which the largest sector number is given is set to a dedicated sector in which the parity is written. Data pieces #1 to #n having sizes corresponding to the respective sectors are written to n sectors #1 to #n, and the parity generated on the basis of the n data pieces #1 to #n written to the sectors #1 to #n is written to the sector #(n+1).

Therefore, when n data pieces are written to the sectors #1 to #n and the parity generated on the basis of the n data pieces is written to the sector #(n+1), the n data pieces written to the sectors #1 to #n are protected by the parity. In other words, even if read from any of the n sectors #1 to #n fails, error correction using the parity written to the sector #(n+1) enables acquisition of the data piece not containing an error. Note that the failure in reading means failure in acquiring the data piece not containing an error.

Hereinafter, a sector configured so that the parity such as the sector #(n+1) is written is referred to as a parity sector. Furthermore, a sector, such as each of the sectors #1 to #n, configured so that a data piece that can be a source of generation of the parity is written to is referred to as a data sector.

Error correction using the parity written to the parity sector is referred to as the track ECC. An error correction coding method for the track ECC, that is, a method of generating the parity is not limited to a specific method. In one example, the parity is generated by an XOR bit operation for all data pieces written to all data sectors.

In the track ECC, error correction for each sector is performed on a per track basis, but there is an upper limit of the number of sectors that can be corrected. This upper limit will be referred to as the correction limit in the number of sectors. When the number of error sectors exceeds the correction limit in the number of sectors before writing the last sector on a track, uncorrectable read error may occur at the track, leading to loss of data.

30 30 30 22 30 30 30 For this reason, the controllermay have a correction limit prediction function. The controllerpredicts whether the number of error sectors reaches the correction limit in the number of sectors before writing the last sector on the track. The controlleris configured to predict the number of error sectors on an adjacent track according to the track margin and the off-track amount of the head, upon writing. When the off-track amount is within a range of the track margin, the controllerdetermines that a sector being written to is not an error sector. When the off-track amount is out of the range of the track margin, the controllerdetermines that the sector being written to is not the error sector. Therefore, the controllercan predict that the number of error sectors on the adjacent track reaches the correction limit in the number of sectors.

30 30 When the number of error sectors on the adjacent track does not reach the correction limit in the number of sectors, the controllerperforms control to continue an off-track write. When the number of error sectors on the adjacent track reaches the correction limit in the number of sectors, the controllerprohibits subsequent off-track write and performs a write retry to another track.

1 11 11 1 In the disk device, characteristics may change over time. When the disk mediumis a magnetic disk, the bit error rate tends to increase even if the off-track amount is identical, as a holding force of the disk mediumdeteriorates over time. In other words, in the disk device, as the bit error rate increases, the appropriate track margin tends have a stricter value.

1 For example, when the track margin is fixedly set, there is a possibility that accuracy in determination of the error sector decreases due to a change in characteristics over time, and accuracy in prediction of whether the number of error sectors reaches the correction limit in the number of sectors decreases, in the disk device.

30 1 Therefore, in the present embodiment, the controllerupdates track margin management information according to the bit error rate reference value and the bit error rate of information read from a track, in the disk device, thereby improving accuracy in prediction of the correction limit, leading to prevention of the read error.

30 31 31 5 FIG. 5 FIG. For example, the controllermay have update management informationas illustrated in.is a graph illustrating a configuration of the update management information.

31 31 0 5 FIG. 5 FIG. In the update management information, the bit error rate and the track margin are associated with each other, for multiple bit error rates. The update management informationmay be implemented in the form of a table, or may be implemented in the form of a function. In, appropriate track margins are experimentally determined for multiple bit error rates, and a relationship between bit error rate and track margin is approximated by a function represented by a solid line. In, the vertical axis represents a track margin (TM) coefficient, and the horizontal axis represents the magnitude of the bit error rate (BER). The track margin coefficient is a coefficient for obtaining the track margin by being multiplied by an initial value TMof the track margin. The track margin coefficient can be regarded as information indicating the track margin.

31 31 Referring to the update management informationmakes it possible to identify a value of an appropriate track margin coefficient to a bit error rate value. With reference to the update management information, when the bit error rate is “E1”, the appropriate track margin coefficient is identified as “K1”. When the bit error rate is “E2”, the appropriate track margin coefficient is identified as “K2”. When the bit error rate is “E3”, the appropriate track margin coefficient is identified as “K3”. When the bit error rate is “E4”, the appropriate track margin coefficient is identified as “K4”. When the bit error rate is “E5”, the appropriate track margin coefficient is identified as “K5”. When the bit error rate is “E6”, the appropriate track margin coefficient is identified as “K6”. When the bit error rate is “E7”, the appropriate track margin coefficient is identified as “K7”.

30 32 32 6 FIG. 6 FIG. The controllermay have reference bit error rate management informationas illustrated in.is a table illustrating a configuration of the reference bit error rate management information.

32 22 22 32 32 311 312 311 22 312 312 1 6 FIG. In the reference bit error rate management information, identification information for each headand the bit error rate reference value are associated with each other, for the multiple heads. The reference bit error rate management informationmay be implemented in the form of a table as illustrated in. The reference bit error rate management informationincludes a head identification information columnand a reference BER column. In the head identification information column, identification information for the respective headsis recorded. In the reference BER column, the bit error rate reference values are recorded. In the reference BER column, the bit error rate reference values may be recorded that are acquired upon testing before shipment of the disk device.

32 22 32 22 1 22 2 22 3 22 4 22 5 22 6 Referring to the reference bit error rate management informationmakes it possible to identify the bit error rate reference value corresponding to the identification information for each head. For example, with reference to the reference bit error rate management information, the bit error rate reference value of the head “_” is identified as “E2”. The bit error rate reference value of the head “_” is identified as “E2”. The bit error rate reference value of the head “_” is identified as “E3”. The bit error rate reference value of the head “_” is identified as “E2”. The bit error rate reference value of the head “_” is identified as “E4”. The bit error rate reference value of the head “_” is identified as “E2”.

30 33 31 32 33 7 FIG. 5 FIG. 6 FIG. 7 FIG. The controllermay create track margin management informationas illustrated in, according to the update management informationas illustrated inand the reference bit error rate management informationas illustrated in.is a table illustrating a configuration of the track margin management information(before update).

33 22 22 33 33 331 332 331 22 332 332 31 32 1 7 FIG. 5 FIG. 6 FIG. In the track margin management information, the identification information for each headand the track margin are associated with each other, for the multiple heads. The track margin management informationmay be implemented in the form of a table as illustrated in. The track margin management informationincludes a head identification information columnand a TM coefficient column. In the head identification information column, identification information for the respective headsis recorded. In the TM coefficient column, values of the track margin coefficient are recorded. In the TM coefficient column, the values of the track margin coefficient may be recorded that are determined according to the update management informationas illustrated inand the reference bit error rate management informationas illustrated in, upon testing before shipment of the disk device.

32 22 1 31 33 22 1 For example, according to the reference bit error rate management information, the bit error rate reference value of the head “_” is “E2”, and according to the update management information, when the bit error rate is “E2”, the appropriate track margin coefficient is “K2”. Therefore, in the track margin management information, “K2” is registered as the value of the track margin coefficient of the head “_”.

32 22 2 31 33 22 2 According to the reference bit error rate management information, the bit error rate reference value of the head “_” is “E2”, and according to the update management information, when the bit error rate is “E2”, the appropriate track margin coefficient is “K2”. Therefore, in the track margin management information, “K2” is registered as the value of the track margin coefficient of the head “_”.

32 22 3 31 33 22 3 According to the reference bit error rate management information, the bit error rate reference value of the head “_” is “E3”, and according to the update management information, when the bit error rate is “E3”, the appropriate track margin coefficient is “K3”. Therefore, in the track margin management information, “K3” is registered as the value of the track margin coefficient of the head “_”.

32 22 4 31 33 22 4 According to the reference bit error rate management information, the bit error rate reference value of the head “_” is “E2”, and according to the update management information, when the bit error rate is “E2”, the appropriate track margin coefficient is “K2”. Therefore, in the track margin management information, “K2” is registered as the value of the track margin coefficient of the head “_”.

32 22 5 31 33 22 5 According to the reference bit error rate management information, the bit error rate reference value of the head “_” is “E4”, and according to the update management information, when the bit error rate is “E4”, the appropriate track margin coefficient is “K4”. Therefore, in the track margin management information, “K4” is registered as the value of the track margin coefficient of the head “_”.

32 22 6 31 33 22 6 According to the reference bit error rate management information, the bit error rate reference value of the head “_” is “E2”, and according to the update management information, when the bit error rate is “E2”, the appropriate track margin coefficient is “K2”. Therefore, in the track margin management information, “K2” is registered as the value of the track margin coefficient of the head “_”.

1 30 8 FIG. 8 FIG. After shipment of the disk device, the controllermay perform a bit error rate testing process as illustrated in.is a flowchart illustrating the bit error rate testing process.

30 1 1 1 The controllerwaits until test timing (No in S). The test timing may be the time of activation of the disk device, the time when a predetermined period has elapsed from the previous test, or the time when the disk deviceis idle.

1 30 22 30 22 22 1 22 6 At the test timing (Yes in S), the controllerselects a test target in terms of track margin management. When the track margin is managed for each head, the controllerselects a headto be tested from the multiple heads_to_.

30 11 22 22 2 The controllerreads information from the disk mediumby using the headto be tested, and obtains the bit error rate (BER) of the headto be tested by using a read signal (S).

30 2 3 The controllerdetermines whether the bit error rate obtained in Sexceeds the bit error rate reference value (reference BER) (S).

2 3 30 22 4 When the bit error rate obtained in Sexceeds the bit error rate reference value (Yes in S), the controllerdetermines that the bit error rate degrades, and updates the track margin of the headto be tested (S).

22 22 1 2 30 31 30 33 332 22 1 33 0 0 5 6 FIGS.and 7 FIG. 9 FIG. 9 FIG. For example, when the headto be tested is the head_, the bit error rate E3 exceeds the bit error rate reference value E2, if the bit error rate obtained in Sis E3 (See). Therefore, the controllerrefers to the update management informationand identifies the track margin coefficient K3 corresponding to the bit error rate E3. The controlleraccesses the track margin management informationas illustrated inand updates the value of the TM coefficient columncorresponding to the head_to “K3” by overwriting, as illustrated in.is a table illustrating a configuration of the track margin management information(after update). As a result, the value of the track margin is updated from TM×K2 to a stricter value TM×K3.

2 3 30 5 When the bit error rate obtained in Sis equal to or less than the bit error rate reference value (No in S), the controllerdetermines that the bit error rate does not degrade, and maintains the current track margin (S).

22 22 1 2 30 33 0 5 6 FIGS.and 7 FIG. For example, when the headto be tested is the head_, the bit error rate E2 is equal to or less than the bit error rate reference value E2, if the bit error rate obtained in Sis E2 (See). Therefore, the controllermaintains the track margin management informationin a state as illustrated in. As a result, the value of the track margin is maintained at TM×K2.

6 30 2 When there are other unselected test targets (Yes in S), the controllerselects one test target from the unselected test targets, and the process returns to S.

6 30 When there is no other unselected test target (No in S), the controllerfinishes the process.

1 30 As described above, according to the embodiment, in the disk device, the controllerupdates the track margin management information, according to the bit error rate reference value and the bit error rate of information read from a track. This configuration makes it possible to improve the accuracy in prediction of the correction limit, thus, suppressing occurrence of read error.

11 22 Note that, as a first modification of the embodiment, the track margin may be managed for each zone in which multiple tracks in the disk mediumare grouped, in addition to being managed for each head.

41 11 11 10 FIG. 10 FIG. For example, the multiple tracksin each disk mediummay be grouped into multiple zones Z1 to Z3 as illustrated in.is a diagram illustrating a configuration of the disk mediumaccording to the first modification of the embodiment.

41 41 41 41 41 11 10 FIG. 10 FIG. 10 FIG. The multiple zones Z1 to Z3 is concentrically arranged from an inner peripheral side to an outer peripheral side. The zones Z each include two or more tracks. In, of eight tracks, three trackson the inner peripheral side are included in the zone Z1, three tracksin a mid-periphery are included in the zone Z2, and two trackson the outer peripheral side are included in the zone Z3. The number of tracks included in each zone Z may be the same, or there may be zones in which the number of tracks is different between the zones. The number of tracks in the disk mediummay be larger than the number of tracks illustrated in, and the number of tracks included in each zone Z may be larger than the number of tracks illustrated in.

22 30 32 32 i i 11 FIG. 11 FIG. In this configuration, the bit error rate reference value may also be managed for each zone Z, in addition to being managed for each head. The controllermay have reference bit error rate management informationas illustrated in.is a table illustrating a configuration of the reference bit error rate management informationaccording to the first modification of the embodiment.

32 22 22 32 32 321 323 322 321 22 323 322 322 1 i i i 11 FIG. In the reference bit error rate management information, the identification information of each head, the identification information of each zone Z, and the bit error rate reference value are associated with each other, for the multiple headsand the multiple zones Z1 to Z3. The reference bit error rate management informationmay be implemented in the form of a table as illustrated in. The reference bit error rate management informationincludes a head identification information column, a zone identification information column, and a reference BER column. In the head identification information column, identification information for the respective headsis recorded. In the zone identification information column, identification information of the respective zones Z is recorded. In the reference BER column, the bit error rate reference values are recorded. In the reference BER column, the bit error rate reference values may be recorded that are acquired upon testing before shipment of the disk device.

32 22 32 22 1 22 1 22 1 22 6 22 6 22 6 i i Referring to the reference bit error rate management informationmakes it possible to identify the bit error rate reference value corresponding to the identification information for each head. For example, with reference to the reference bit error rate management information, the bit error rate reference value of the zone “Z1” of the head “_” is identified as “E2”. The bit error rate reference value of the head “_” in the zone “Z2” is identified as “E2”. The bit error rate reference value of the head “_” in the zone “Z3” is identified as “E3”. The bit error rate reference value of the head “_” in the zone “Z1” is identified as “E2”. The bit error rate reference value of the head “_” in the zone “Z2” is identified as “E3”. The bit error rate reference value of the head “_” in the zone “Z3” is identified as “E3”.

30 33 31 32 33 i i i 12 FIG. 5 FIG. 11 FIG. 12 FIG. The controllermay create track margin management informationas illustrated in, according to the update management informationas illustrated inand the reference bit error rate management informationas illustrated in.is a table illustrating a configuration of the track margin management information(before update) according to the first modification of the embodiment.

33 22 22 33 33 331 333 332 331 22 333 332 332 31 32 1 i i i i 12 FIG. 5 FIG. 12 FIG. In the track margin management information, the identification information of each head, the identification information of each zone Z, and the track margin are associated with each other, for the multiple heads. The track margin management informationmay be implemented in the form of a table as illustrated in. The track margin management informationincludes the head identification information column, a zone identification information column, and the TM coefficient column. In the head identification information column, identification information for the respective headsis recorded. In the zone identification information column, identification information of the respective zone Z is recorded. In the TM coefficient column, values of the track margin coefficient are recorded. In the TM coefficient column, the values of the track margin coefficient may be recorded that are determined according to the update management informationas illustrated inand the reference bit error rate management informationas illustrated in, upon testing before shipment of the disk device.

32 22 1 31 33 22 1 i i For example, according to the reference bit error rate management information, the bit error rate reference value of the head “_” in the zone “Z1” is “E2”, and according to the update management information, when the bit error rate is “E2”, the appropriate track margin coefficient is “K2”. Therefore, in the track margin management information, “K2” is registered as the value of the track margin coefficient of the head “_” in the zone “Z1”.

32 22 1 31 33 22 1 i i According to the reference bit error rate management information, the bit error rate reference value of the head “_” in the zone “Z2” is “E2”, and according to the update management information, when the bit error rate is “E2”, the appropriate track margin coefficient is “K2”. Therefore, in the track margin management information, “K2” is registered as the value of the track margin coefficient of the head “_” in the zone “Z2”.

32 22 1 31 33 22 1 i i According to the reference bit error rate management information, the bit error rate reference value of the head “_” in the zone “Z3” is “E3”, and according to the update management information, when the bit error rate “E3”, the appropriate track margin coefficient is “K3”. Therefore, in the track margin management information, “K3” is registered as the value of the track margin coefficient of the head “_” in the zone “Z3”.

32 22 6 31 33 22 6 i i According to the reference bit error rate management information, the bit error rate reference value of the head “_” in the zone “Z1” is “E2”, and according to the update management information, when the bit error rate is “E2”, the appropriate track margin coefficient is “K2”. Therefore, in the track margin management information, “K2” is registered as the value of the track margin coefficient of the head “_” in the zone “Z1”.

32 22 6 31 33 22 6 i i According to the reference bit error rate management information, the bit error rate reference value of the head “_” in the zone “Z2” is “E3”, and according to the update management information, when the bit error rate is “E3”, the appropriate track margin coefficient is “K3”. Therefore, in the track margin management information, “K3” is registered as the value of the track margin coefficient of the head “_” in the zone “Z2”.

32 22 6 31 33 22 6 i i According to the reference bit error rate management information, the bit error rate reference value of the head “_” in the zone “Z3” is “E3”, and according to the update management information, when the bit error rate is “E3”, the appropriate track margin coefficient is “K3”. Therefore, in the track margin management information, “K3” is registered as the value of the track margin coefficient of the head “_” in the zone “Z3”.

1 30 8 FIG. After shipment of the disk device, the controllermay perform a bit error rate testing process as illustrated in.

1 3 2 3 30 22 4 After Sto Sare performed similarly to the embodiment, when the bit error rate obtained in Sexceeds the bit error rate reference value (Yes in S), the controllerdetermines that the bit error rate degrades, and updates the track margin of the headto be tested (S).

22 22 1 2 30 31 30 33 332 22 1 33 0 0 5 11 FIGS.and 12 FIG. 13 FIG. 13 FIG. i i For example, when the headto be tested is the head_and a zone Z to be tested is the zone Z1, the bit error rate E3 exceeds the bit error rate reference value E2, if the bit error rate obtained in Sis E3 (See). Therefore, the controllerrefers to the update management informationand identifies the track margin coefficient K3 corresponding to the bit error rate E3. The controlleraccesses the track margin management informationas illustrated inand updates the value of the TM coefficient columncorresponding to the head_and the zone Z1 to “K3” by overwriting, as illustrated in.is a table illustrating a configuration of the track margin management information(after update) according to the first modification of the embodiment. As a result, the value of the track margin is updated from TM×K2 to the stricter value TM×K3.

5 6 Thereafter, Sto Sare performed similarly to the embodiment.

1 30 In the disk deviceconfigured as above, the controllerupdates the track margin management information, according to the bit error rate reference value and the bit error rate of information read from a track. This configuration makes it possible to improve the accuracy in prediction of the correction limit, thus, suppressing occurrence of read error.

Alternatively, as a second modification of the embodiment, a correction limit prediction process in consideration of the bit error rate testing process may be performed.

1 1 14 FIG. 8 FIG. 14 FIG. For example, the disk devicemay perform an operation as illustrated inin parallel with the bit error rate testing process illustrated in.is a flowchart illustrating an operation of the disk deviceaccording to the second modification of the embodiment; and

1 30 In the disk device, in starting writing of a track TR_k (k is any integer of 1 or more), the controllerperforms initialization so that a track ECC valid flag FTE=1, the number N of write sectors on the track TR_k=0, and the number M of sectors determined to be damaged on the track TR_k=0.

1 1 Note that a value of the track ECC valid flag FTE of 1 indicates that an operation mode of the disk deviceis a track ECC valid mode. When a value of the track ECC valid flag FTE of 0 indicates that the operation mode of the disk deviceis a track ECC invalid mode.

11 30 12 30 13 When a positioning error PE [N] in the number N of write sectors on the track TR_k does not exceed a track margin TM (No in S), the controllerwrites the sector SC [N] (S). The controllerincrements the number N of write sectors (S).

30 11 14 14 14 30 The controllerrepeats a loop of Sto Suntil the number N of write sectors is equal to a total number Ne of sectors (No in S). When the number N of write sectors is equal to the total number Ne of sectors (Yes in S), the controllerdetermines that the writing of the total number Ne of sectors has been completed, and finishes the process.

11 30 20 When the positioning error PE [N] in the number N of write sectors on the track TR_k exceeds the track margin TM (Yes in S), the controllerperforms a track ECC mode control process (S).

20 21 30 22 23 30 20 In the track ECC mode control process (S), during the track ECC valid mode (Yes in S), the controllerpredicts the number Mp of sectors determined to be damaged at the end of writing the total number Ne of sectors, from a change rate dM/dN in the number M of sectors determined to be damaged with respect to the number N of write sectors, the number of remaining sectors (Ne−N), and the number M of sectors determined to be damaged (S). When the number Mp of sectors determined to be damaged does not reach correction limit Mx in the number of sectors (No in S), the controllerexits the track ECC mode control process (S).

30 20 23 31 12 32 The controllerafter exit of Svia Sincrements the number M of sectors determined to be damaged (S), and writes the sector SC [N] (S), when the number M of sectors determined to be damaged does not reach the correction limit Mx in the number of sectors (Yes in S).

32 30 33 When the number M of sectors determined to be damaged reaches the correction limit Mx in the number of sectors (No in S), the controllerregisters the remaining sectors SC [N] to SC [Ne−1] before completion of writing, as replacement information or writes the remaining sectors SC [N] to SC [Ne−1] to the replacement area (S).

20 23 30 24 30 28 11 In the track ECC mode control process (S), when the number Mp of sectors determined to be damaged reaches the correction limit Mx in the number of sectors (Yes in S), the controllersets the track ECC valid flag FTE=0 and shifts the operation mode to the track ECC invalid mode (S). The controllerproceeds to write retry processing, waits for rotation for writing the sector SC [N] to another track (S), and performs the processing in and after Sfor another track TR_k+1.

20 21 30 25 In the track ECC mode control process (S), during the track ECC invalid mode (No in S), the controllerpredicts the number Mp of sectors determined to be damaged at the end of writing the total number Ne of sectors, from the change rate dM/dN in the number M of sectors determined to be damaged with respect to the number N of write sectors, the number of remaining sectors (Ne−N), and the number M of sectors determined to be damaged (S).

8 FIG. 1 At this time, this prediction is performed in parallel with the bit error rate testing process (see), and there is a possibility that the state of the disk devicemay change due to the update of the track margin.

26 30 27 31 Therefore, when the number Mp of sectors determined to be damaged is smaller than the correction limit Mx in the number of sectors during the track ECC invalid mode (No in S), the controllersets the track ECC valid flag FTE=1, returns the operation mode to the track ECC valid mode (S), and performs the processing in and after S.

20 26 30 28 11 In the track ECC mode control process (S), when the number Mp of sectors determined to be damaged reaches the correction limit Mx in the number of sectors during the track ECC invalid mode (Yes in S), the controllermaintains the track ECC valid flag FTE=0, proceeds to the write retry processing, waits for rotation for writing the sector SC [N] to another track (S), and performs the processing in and after Sfor the another track TR_k+1.

In this manner, the correction limit prediction process can be performed by dynamically adapting to the update of the track margin management information, in consideration of the bit error rate testing process. Therefore, the accuracy in prediction of the correction limit can be further improved.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.