Semiconductor Device and Method for Fabricating the Same

This application claims priority from Korean Patent Application No. 10-2024-0095616, filed on Jul. 19, 2024 in the Korean Intellectual Property Office, the contents of which in its entirety are herein incorporated by reference.

The disclosure relates to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device including a stacked multi-gate transistor and a method for fabricating the same.

As one of scaling technologies to increase a density of integrated circuit (IC) devices, multi-gate transistors have been proposed in which a fin-or nanowire-shaped silicon body is formed on a substrate and then gates are formed on the surface of the silicon body.

Since these multi-gate transistors utilize three-dimensional (3D) channels, scaling is easier. Moreover, current control capabilities can be enhanced without increasing the gate length of the multi-gate transistors. Additionally, a short channel effect (SCE), where a potential of a channel region is influenced by a drain voltage, can be effectively suppressed.

To implement more devices in the same area, research is being conducted on semiconductor devices that use stacked multi-gate transistors, where multi-gate transistors in an upper region are stacked on multi-gate transistors in a lower region.

One or more embodiments of the disclosure provide a semiconductor device which may have improved integration.

According to an aspect of the disclosure, a method for fabricating a semiconductor device with improved integration is provided.

According to an aspect of the disclosure, a semiconductor device includes: a substrate including a first surface and a second surface that are opposite to each other; a first active pattern and a second active pattern sequentially stacked on the first surface, the first active pattern and the second active pattern extending in a first direction and spaced apart from each other; a first gate electrode and a second gate electrode that extend in a second direction that intersects the first direction, the first gate electrode intersecting the first active pattern, and the second gate electrode intersecting the second active pattern; a first-level source/drain pattern on a sidewall of the first gate electrode and connected to the first active pattern; a second-level source/drain pattern on a sidewall of the second gate electrode and connected to the second active pattern; a first backside source/drain contact penetrating the substrate and connected to the first-level source/drain pattern; a second backside source/drain contact penetrating the substrate and connected to the second-level source/drain pattern; a connection wiring pattern on the second surface and connecting the first backside source/drain contact and the second backside source/drain contact; and a backside gate contact penetrating the substrate and connected to the first gate electrode and the second gate electrode, wherein the second-level source/drain pattern includes: a first base portion overlapping the first-level source/drain pattern in a third direction that intersects the first direction and the second direction; and a first extension portion extending from the first base portion in the second direction and not overlapping the first-level source/drain pattern in the third direction, and wherein the second backside source/drain contact is connected to the first extension portion.

According to an aspect of the disclosure, a semiconductor device includes: a substrate; a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern sequentially stacked and spaced apart from one another, on the substrate; a first gate electrode, a second gate electrode, a third gate electrode, and a fourth gate electrode sequentially stacked on the substrate and intersecting the first active pattern, the second active pattern, the third active pattern, and the fourth active pattern, respectively; a fifth gate electrode, a sixth gate electrode, a seventh gate electrode, and an eighth gate electrode sequentially stacked on the substrate and intersecting the first active pattern, the second active pattern, the third active pattern, and the fourth active pattern, respectively, wherein the fifth gate electrode, the sixth gate electrode, the seventh gate electrode, and the eighth gate electrode are spaced apart from the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode; a first source/drain pattern between the first gate electrode and the fifth gate electrode and connected to the first active pattern; a second source/drain pattern connected to the first active pattern, the first gate electrode being between the first source/drain pattern and the second source/drain pattern; a third source/drain pattern connected to the first active pattern, the second gate electrode being between the first source/drain pattern and the third source/drain pattern; a fourth source/drain pattern between the second gate electrode and the sixth gate electrode and connected to the second active pattern; a fifth source/drain pattern connected to the second active pattern, the second gate electrode being between the fourth source/drain pattern and the fifth source/drain pattern; a sixth source/drain pattern connected to the second active pattern; a seventh source/drain pattern between the third gate electrode and the seventh gate electrode and connected to the third active pattern; an eighth source/drain pattern connected to the third active pattern, the seventh gate electrode being between the seventh source/drain pattern and the eighth source/drain pattern; a ninth source/drain pattern between the fourth gate electrode and the eighth gate electrode and connected to the fourth active pattern; and a tenth source/drain pattern connected to the fourth active pattern, the fourth gate electrode being between the ninth source/drain pattern and the tenth source/drain pattern, wherein the second source/drain pattern, the fifth source/drain pattern, the tenth source/drain pattern, the fifth gate electrode, and the sixth gate electrode are electrically connected to each other, and wherein the third source/drain pattern, the sixth source/drain pattern, the seventh source/drain pattern, the first gate electrode, and the second gate electrode are electrically connected to each other.

According to an aspect of the disclosure, a semiconductor device includes: a substrate including a first surface and a second surface that are opposite to each other; a first power supply line on the second surface and configured to receive a first power supply voltage; a second power supply line on the second surface and configured to receive a second power supply voltage that is different from the first power supply voltage; a latch circuit including a first inverter and a second inverter arranged in parallel on the first surface, the first inverter and the second inverter being between the first power supply line and the second power supply line; a bitline on the first surface; a complementary bitline on the first surface; a first pass transistor connecting the bitline and an output node of the first inverter; a second pass transistor connecting the complementary bitline and an output node of the second inverter; and a wordline on the first surface and connected to a gate of the first pass transistor and a gate of the second pass transistor, wherein the first inverter includes a first pull-up transistor and a first pull-down transistor connected in series between the first power supply line and the second power supply line, wherein the second inverter includes a second pull-up transistor and a second pull-down transistor connected in series between the first power supply line and the second power supply line, wherein the first pull-up transistor and the second pull-up transistor are at a first level on the first surface, wherein the first pull-down transistor and the second pull-down transistor are at a second level, that is higher than the first level, on the first surface, wherein the second pass transistor is at a third level, that is higher than the second level, on the first surface, and wherein the first pass transistor is at a fourth level, that is higher than the third level, on the first surface.

However, aspects and effects of embodiments of the disclosure are not restricted to those set forth herein. The above and other aspects and effects of embodiments of the disclosure will become more apparent to one of ordinary skill in the art to which the disclosure pertains by referencing the detailed description of the disclosure given below.

It will be understood that, although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component, or a first section discussed below could be termed a second element, a second component, or a second section without departing from the scope of the disclosure.

It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

1 9 FIGS.through A semiconductor device according to example embodiments will hereinafter be described with reference to. The embodiments described below describe a static random-access memory (SRAM) device as an example semiconductor device, but embodiments of the disclosure are not limited thereto. Those skilled in the art to which the disclosure pertains will understand that embodiments of the disclosure are applicable not only to an SRAM device but also to other various semiconductor devices, such as a logic device, a complementary metal-oxide semiconductor (CMOS) inverter, etc.

1 FIG. is an example circuit diagram for explaining a semiconductor device according to one or more embodiments.

1 FIG. 1 2 1 2 1 2 1 2 DD SS Referring to, the semiconductor device according to one or more embodiments may include a pair of a first inverter INVand a second inverter INVthat are connected in parallel between a power supply node Vand a ground node V, and a first pass transistor PSand a second pass transistor PSthat are respectively connected to output nodes Nand Nof the first inverter INVand the second inverter INV.

1 1 2 2 2 1 To form a latch circuit, the output node Nof the first inverter INVmay be connected to the input node of the second inverter INV, and the output node Nof the second inverter INVmay be connected to the input node of the first inverter INV.

1 1 1 2 2 2 1 2 1 2 DD SS DD SS The first inverter INVmay include a first pull-up transistor PUand a first pull-down transistor PDthat are connected in series between the power supply node Vand the ground node V, and the second inverter INVmay include a second pull-up transistor PUand a second pull-down transistor PDthat are connected in series between the power supply node Vand the ground node V. The first pull-up transistor PUand the second pull-up transistor PUmay be P-type field-effect transistors (PFETs), and the first pull-down transistor PDand the second pull-down transistor PDmay be N-type field-effect transistors (NFETs).

1 1 1 2 2 2 1 2 The first pass transistor PSmay connect a bitline BL to the output node Nof the first inverter INV. The second pass transistor PSmay connect a complementary bitline/BL to the output node Nof the second inverter INV. The gate of the first pass transistor PSand the gate of the second pass transistor PSmay be commonly connected to a wordline WL.

2 FIG. 3 FIG. 2 FIG. 4 FIG. 2 FIG. 5 FIG. 2 FIG. 6 FIG. 2 FIG. 7 FIG. 2 FIG. 8 FIG. 2 FIG. 9 FIG. 2 FIG. is an example layout view for explaining the semiconductor device according to one or more embodiments.is a schematic cross-sectional view taken along a line A-A of.is a schematic cross-sectional view taken along a line B-B of.is a schematic cross-sectional view taken along a line C-C of.is a schematic cross-sectional view taken along a line D-D of.is a schematic cross-sectional view taken along a line E-E of.is a schematic cross-sectional view taken along a line F-F of.is a schematic cross-sectional view taken along a line G-G of.

1 9 FIGS.through 100 1 4 1 2 161 163 261 263 361 363 461 462 190 290 390 490 3 4 11 12 13 21 22 3 4 Referring to, the semiconductor device according to one or more embodiments may include a substrate, first through fourth active patterns Athrough A, a first gate structure G, a second gate structure G, first-level source/drain patterns (e.g., first through third source/drain patternsthrough), second-level source/drain patterns (e.g., the fourth through sixth source/drain patternsthrough), third-level source/drain patterns (e.g., a seventh source/drain patternand an eighth source/drain pattern), fourth-level source/drain patterns (e.g., a ninth source/drain patternand a tenth source/drain pattern), first, second, third, and fourth interlayer insulating films,,, and, frontside source/drain contacts (e.g., a first frontside source/drain contact CAand a second frontside source/drain contact CA), a frontside wiring structure FW, backside source/drain contacts (e.g., the first through sixth backside source/drain contacts BCA, BCA, BCA, BCA, BCA, BCA, and BCA), and a backside wiring structure BW.

100 100 100 The substratemay be a bulk silicon (Si) substrate or an Si-on-insulator (SOI) substrate. Alternatively, the substratemay be an Si substrate, or may include other materials such as, for example, silicon-germanium (SiGe), SiGe-on-insulator (SGOI), indium antimonide, a lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substratemay be a substrate where an epitaxial layer is formed on a base substrate.

100 100 100 In one or more embodiments, the substratemay be an insulating substrate that includes an insulating material. For example, the substratemay include at least one from among silicon oxide, silicon oxynitride, silicon oxycarbonitride, and a combination thereof, but embodiments of the disclosure are not limited thereto. For example, the substratemay include a silicon oxide film.

100 100 100 100 100 100 100 a b a b The substratemay include a first surfaceand a second surfacethat are opposite to each other. Here, the first surfacemay also be referred to as the front side of the substrate, and the second surfacemay also be referred to as the back side of the substrate.

1 4 100 1 4 100 1 4 100 100 a a, a. The first through fourth active patterns Athrough Amay be formed on the substrate. The first through fourth active patterns Athrough Amay be sequentially stacked on the first surfaceto be spaced apart from one another. For example, the first through fourth active patterns Athrough Amay be spaced apart from one another in a third direction Z that intersects the first surfaceand may extend in a first direction X that is parallel to the first surface

1 4 1 4 The first through fourth active patterns Athrough Amay each include an elemental semiconductor material such as Si or germanium (Ge). Alternatively, the first through fourth active patterns Athrough Amay each include a compound semiconductor such as, for example, a Group IV-IV compound semiconductor or a Group III-V compound semiconductor. The Group IV-IV compound semiconductor may include, for example, a binary or ternary compound containing at least two from among carbon (C), Si, Ge, and tin (Sn), or a compound obtained by doping the binary or ternary compound with a Group IV element. The Group III-V compound semiconductor may include, for example, a binary, ternary, or quaternary compound obtained by combining at least one Group III element such as aluminum (Al), gallium (Ga), or indium (In) with at least one Group V element such as phosphorus (P), arsenic (As), or antimony (Sb).

1 2 4 In one or more embodiments, the first active pattern Amay be provided as the channel region of a PFET, and the second through fourth active patterns Athrough Amay be provided as the channel region of an NFET.

1 4 100 1 111 112 2 211 212 3 311 312 4 411 412 1 4 1 4 a In one or more embodiments, each of the first through fourth active patterns Athrough Amay include a plurality of bridge patterns that are sequentially stacked on the first surfaceand are spaced apart from one another. For example, the first active pattern Amay include first bridge patternsand second bridge patterns. For example, the second active pattern Amay include third bridge patternsand fourth bridge patterns. For example, the third active pattern Amay include fifth bridge patternsand sixth bridge patterns. For example, the fourth active pattern Amay include seventh bridge patternsand eighth bridge patterns. The first through fourth active patterns Athrough Amay be used as the channel regions of MBCFETs®, which include multi-bridge channels. The number of bridge patterns included in each of the first through fourth active patterns Athrough Ais merely example and is not particularly limited.

1 2 100 1 4 1 2 1 4 1 2 100 1 4 1 2 a The first gate structure Gand the second gate structure Gmay be formed on the substrateand the first through fourth active patterns Athrough A. The first gate structure Gand the second gate structure Gmay be spaced apart from each other and intersect the first through fourth active patterns Athrough A. For example, the first gate structure Gand the second gate structure Gmay be spaced apart from each other in the first direction X, and each may extend in a second direction Y, which is parallel to the first surfaceand intersects the first direction X. The first through fourth active patterns Athrough Amay extend in the first direction X and penetrate the first gate structure Gand the second gate structure G.

1 131 231 331 431 131 231 331 431 100 131 231 331 431 1 2 3 4 1 131 2 231 3 331 4 431 a. The first gate structure Gmay include first, second, third, and fourth gate electrodes,,, and. The first, second, third, and fourth gate electrodes,,, andmay be sequentially stacked on the first surfaceThe first, second, third, and fourth gate electrodes,,, andmay intersect the first, second, third, and fourth active patterns A, A, A, and A, respectively. For example, the first active pattern Amay extend in the first direction X and penetrate the first gate electrode. For example, the second active pattern Amay extend in the first direction X and penetrate the second gate electrode. For example, the third active pattern Amay extend in the first direction X and penetrate the third gate electrode. For example, the fourth active pattern Amay extend in the first direction X and penetrate the fourth gate electrode.

2 132 232 332 432 132 232 332 432 100 132 232 332 432 1 4 1 132 2 232 3 332 4 432 a. The second gate structure Gmay include fifth, sixth, seventh, and eighth gate electrodes,,, and. The fifth, sixth, seventh, and eighth gate electrodes,,, andmay be sequentially stacked on the first surfaceThe fifth, sixth, seventh, and eighth gate electrodes,,, andmay intersect the first through fourth active patterns Athrough A, respectively. For example, the first active pattern Amay extend in the first direction X and penetrate the fifth gate electrode. For example, the second active pattern Amay extend in the first direction X and penetrate the sixth gate electrode. For example, the third active pattern Amay extend in the first direction X and penetrate the seventh gate electrode. For example, the fourth active pattern Amay extend in the first direction X and penetrate the eighth gate electrode.

131 231 331 431 132 232 332 432 The first, second, third, and fourth gate electrodes,,, andand the fifth, sixth, seventh, and eighth gate electrodes,,, andmay each include a conductive material such as, for example, at least one from among TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al, and a combination thereof, but embodiments of the disclosure are not limited thereto.

131 231 331 431 132 232 332 432 131 231 331 431 132 232 332 432 131 231 331 431 132 232 332 432 The first, second, third, and fourth gate electrodes,,, and, and the fifth, sixth, seventh, and eighth gate electrodes,,, andare illustrated as being single films, but embodiments of the disclosure are not limited thereto. Alternatively, the first, second, third, and fourth gate electrodes,,, and, and the fifth, sixth, seventh, and eighth gate electrodes,,, andmay be multi-films obtained by stacking a plurality of conductive films. For example, the first, second, third, and fourth gate electrodes,,, and, and the fifth, sixth, seventh, and eighth gate electrodes,,, andmay each include a work function control film that adjusts the work function, and a filling conductive film that fills the space formed by the work function control film. The work function control film may include, for example, at least one from among TiN, TaN, TiC, TaC, TiAlC, and a combination thereof. The filling conductive film may include, for example, W or Al.

131 1 1 131 1 The first gate electrodemay serve as the gate of the first pull-up transistor PU. For example, the region of the first active pattern Athat intersects the first gate electrodemay serve as the channel region of the first pull-up transistor PU.

231 1 2 231 1 The second gate electrodemay serve as the gate of the first pull-down transistor PD. For example, the region of the second active pattern Athat intersects the second gate electrodemay serve as the channel region of the first pull-down transistor PD.

431 1 4 431 1 The fourth gate electrodemay serve as the gate of the first pass transistor PS. For example, the region of the fourth active pattern Athat intersects the fourth gate electrodemay serve as the channel region of the first pass transistor PS.

132 2 1 132 2 The fifth gate electrodemay serve as the gate of the second pull-up transistor PU. For example, the region of the first active pattern Athat intersects the fifth gate electrodemay serve as the channel region of the second pull-up transistor PU.

232 2 2 232 2 The sixth gate electrodemay serve as the gate of the second pull-down transistor PD. For example, the region of the second active pattern Athat intersects the sixth gate electrodemay serve as the channel region of the second pull-down transistor PD.

332 2 3 332 2 The seventh gate electrodemay serve as the gate of the second pass transistor PS. For example, the region of the third active pattern Athat intersects the seventh gate electrodemay serve as the channel region of the second pass transistor PS.

1 2 100 1 2 100 2 100 4 100 a. a. a. a. The first pull-up transistor PUand the second pull-up transistor PUmay be disposed at a first level on the first surfaceThe first pull-down transistor PDand the second pull-down transistor PDmay be disposed at a second level that is higher than the first level, on the first surfaceThe second pass transistor PSmay be disposed at a third level that is higher than the second level, on the first surfaceThe fourth pass transistor PSmay be disposed at a fourth level that is higher than the third level, on the first surface

1 2 120 220 320 420 440 450 Each of the first gate structure Gand the second gate structure Gmay include first, second, third, and fourth gate dielectric films,,, and, gate spacers, and a gate capping film.

120 220 320 420 1 4 131 231 331 431 1 4 132 232 332 432 120 1 131 1 132 220 2 231 2 232 320 3 331 3 332 420 4 431 4 432 The first, second, third, and fourth gate dielectric films,,, andmay be interposed between the first through fourth active patterns Athrough Aand the first, second, third, and fourth gate electrodes,,, and, and between the first through fourth active patterns Athrough Aand the fifth, sixth, seventh, and eighth gate electrodes,,, and. For example, the first gate dielectric filmmay be interposed between the first active pattern Aand the first gate electrode, and between the first active pattern Aand the fifth gate electrode. For example, the second gate dielectric filmmay be interposed between the second active pattern Aand the second gate electrode, and between the second active pattern Aand the sixth gate electrode. For example, the third gate dielectric filmmay be interposed between the third active pattern Aand the third gate electrode, and between the third active pattern Aand the seventh gate electrode. For example, the fourth gate dielectric filmmay be interposed between the fourth active pattern Aand the fourth gate electrode, and between the fourth active pattern Aand the eighth gate electrode.

120 220 320 420 The first, second, third, and fourth gate dielectric films,,, andmay each include a dielectric material such as, for example, at least one from among silicon oxide, silicon oxynitride, silicon nitride, and a high-k dielectric material having a greater dielectric constant than silicon oxide. The high-k dielectric material may include, for example, at least one from among hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalate, lead zinc niobate, and a combination thereof, but embodiments of the disclosure are not limited thereto.

120 220 320 420 120 220 320 420 120 220 320 420 1 4 1 4 The first, second, third, and fourth gate dielectric films,,, andare illustrated as being single films, but embodiments of the disclosure are not limited thereto. Alternatively, the first, second, third, and fourth gate dielectric films,,, andmay be multi-films formed by stacking a plurality of dielectric films. For example, the first, second, third, and fourth gate dielectric films,,, andmay each include an interface film and a high-k dielectric film that are sequentially stacked on the first through fourth active patterns Athrough A. The interface film may include, for example, an oxide film formed by oxidizing the surfaces of the first through fourth active patterns Athrough A. The high-k dielectric film may include, for example, a high-k dielectric material having a greater dielectric constant than silicon oxide.

120 100 100 220 515 320 525 420 535 a In one or more embodiments, part of the first gate dielectric filmmay extend along the first surfaceof the substrate. In one or more embodiments, part of the second gate dielectric filmmay extend along the upper surface of a first gate separation pattern. In one or more embodiments, part of the third gate dielectric filmmay extend along the upper surface of a second gate separation pattern. In one or more embodiments, part of the fourth gate dielectric filmmay extend along the upper surface of a third gate separation pattern.

440 131 231 331 431 132 232 332 432 1 4 440 440 The gate spacersmay extend along the sidewalls of the first, second, third, and fourth gate electrodes,,, and, and the sidewalls of the fifth, sixth, seventh, and eighth gate electrodes,,, and. Each of the first through fourth active patterns Athrough Amay extend in the first direction X and penetrate the gate spacers. The gate spacersmay include an insulating material such as, for example, at least one from among silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and a combination thereof, but embodiments of the disclosure are not limited thereto.

120 220 320 420 440 In one or more embodiments, parts of the first, second, third, and fourth gate dielectric films,,, andmay extend further along the inner sidewalls of the gate spacers.

450 431 450 The gate capping filmmay extend along the upper surface of the fourth gate electrode. The gate capping filmmay include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and a combination thereof, but embodiments of the disclosure are not limited thereto.

1 2 515 515 131 231 132 232 515 515 131 231 132 232 In one or more embodiments, each of the first gate structure Gand the second gate structure Gmay include the first gate separation pattern. The first gate separation patternmay be interposed between the first gate electrodeand the second gate electrode, and between the fifth and sixth gate electrodesand. The first gate separation patternmay extend in the second direction Y. The first gate separation patternmay separate the first gate electrodefrom the second gate electrode, and the fifth gate electrodefrom the sixth gate electrode.

1 2 525 525 231 331 232 332 525 525 231 331 232 332 In one or more embodiments, each of the first gate structure Gand the second gate structure Gmay include the second gate separation pattern. The second gate separation patternmay be interposed between the second gate electrodeand the third gate electrode, and between the sixth and seventh gate electrodesand. The second gate separation patternmay extend in the second direction Y. The second gate separation patternmay separate the second gate electrodefrom the third gate electrode, and the sixth gate electrodefrom the seventh gate electrode.

1 2 535 535 331 431 332 432 535 535 331 431 332 432 In one or more embodiments, each of the first gate structure Gand the second gate structure Gmay include the third gate separation pattern. The third gate separation patternmay be interposed between the third gate electrodeand the fourth gate electrode, and between the seventh gate electrodeand the eighth gate electrode. The third gate separation patternmay extend in the second direction Y. The third gate separation patternmay separate the third gate electrodefrom the fourth gate electrode, and the seventh gate electrodefrom the eighth gate electrode.

515 525 535 The first, second, and third gate separation patterns,, andmay each include an insulating material such as, for example, at least one from among silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and a combination thereof, but embodiments of the disclosure are not limited thereto.

161 163 1 1 2 1 1 2 161 163 161 163 131 132 440 120 The first-level source/drain patterns (e.g., the first through third source/drain patternsthrough) may be formed within the first active pattern Aon the sidewalls of the first gate structure Gand the second gate structure G. The first active pattern Amay extend through the first gate structure Gand the second gate structure Gand be connected to the first-level source/drain patterns (e.g., the first through third source/drain patternsthrough). The first-level source/drain patterns (e.g., the first through third source/drain patternsthrough) may be separated from the first and fifth gate electrodesandby the gate spacersand/or the first gate dielectric film.

161 162 163 161 131 132 131 161 162 132 161 163 The first-level source/drain patterns may include the first source/drain pattern, the second source/drain pattern, and the third source/drain pattern. The first source/drain patternmay be interposed between the first gate electrodeand the fifth gate electrode. The first gate electrodemay be interposed between the first source/drain patternand the second source/drain pattern. The fifth gate electrodemay be interposed between the first source/drain patternand the third source/drain pattern.

161 163 161 163 1 In one or more embodiments, the first-level source/drain patterns (e.g., the first through third source/drain patternsthrough) may each include an epitaxial layer doped with impurities. For example, the first-level source/drain patterns (e.g., the first through third source/drain patternsthrough) may include epitaxial patterns grown by an epitaxial growth method from the first active pattern A.

1 161 163 If the first active pattern Aserves as the channel region of a PFET, the first-level source/drain patterns (e.g., the first through third source/drain patternsthrough) may each include p-type impurities (e.g., B, In, Ga, or Al) or impurities to prevent the diffusion of the p-type impurities.

261 263 2 1 2 2 1 2 261 263 261 263 231 232 440 220 The second-level source/drain patterns (e.g., the fourth through sixth source/drain patternsthrough) may be formed within the second active pattern Aon the sidewalls of the first gate structure Gand the second gate structure G. The second active pattern Amay extend through the first gate structure Gand the second gate structure Gand be connected to the second-level source/drain patterns (e.g., the fourth through sixth source/drain patternsthrough). The second-level source/drain patterns (e.g., the fourth through sixth source/drain patternsthrough) may be separated from the second and sixth gate electrodesandby the gate spacersand/or the second gate dielectric film.

261 263 261 262 263 261 231 232 231 261 262 232 261 263 The second-level source/drain patterns (e.g., the fourth through sixth source/drain patternsthrough) may include the fourth source/drain pattern, the fifth source/drain pattern, and the sixth source/drain pattern. The fourth source/drain patternmay be interposed between the second gate electrodeand the sixth gate electrode. The second gate electrodemay be interposed between the fourth source/drain patternand the fifth source/drain pattern. The sixth gate electrodemay be interposed between the fourth source/drain patternand the sixth source/drain pattern.

261 263 261 263 2 In one or more embodiments, the second-level source/drain patterns (e.g., the fourth through sixth source/drain patternsthrough) may each include an epitaxial layer doped with impurities. For example, the second-level source/drain patterns (e.g., the fourth through sixth source/drain patternsthrough) may include epitaxial patterns grown by an epitaxial growth method from the second active pattern A.

2 261 263 If the second active pattern Aserves as the channel region of an NFET, the second-level source/drain patterns (e.g., the fourth through sixth source/drain patternsthrough) may each include n-type impurities (e.g., B, In, Ga, or Al) or impurities to prevent the diffusion of the n-type impurities.

361 363 3 1 2 3 1 2 361 363 361 363 331 332 440 320 The third-level source/drain patterns (e.g., the seventh source/drain patternand the eighth source/drain pattern) may be formed within the third active pattern Aon the sidewalls of the first gate structure Gand the second gate structure G. The third active pattern Amay extend through the first gate structure Gand the second gate structure Gand be connected to the third-level source/drain patterns (e.g., the seventh source/drain patternand the eighth source/drain pattern). The third-level source/drain patterns (e.g., the seventh source/drain patternand the eighth source/drain pattern) may be separated from the third gate electrodeand the seventh gate electrodeby the gate spacersand/or the third gate dielectric film.

361 363 361 363 361 331 332 332 361 363 The third-level source/drain patterns (e.g., the seventh source/drain patternand the eighth source/drain pattern) may include the seventh source/drain patternand the eighth source/drain pattern. The seventh source/drain patternmay be interposed between the third gate electrodeand the seventh gate electrode. The seventh gate electrodemay be interposed between the seventh source/drain patternand the eighth source drain/pattern.

361 363 361 363 3 In one or more embodiments, the third-level source/drain patterns (e.g., the seventh source/drain patternand the eighth source/drain pattern) may each include an epitaxial layer doped with impurities. For example, the third-level source/drain patterns (e.g., the seventh source/drain patternand the eighth source/drain pattern) may include epitaxial patterns grown by an epitaxial growth method from the third active pattern A.

3 361 363 If the third active pattern Aserves as the channel region of an NFET, the third-level source/drain patterns (e.g., the seventh source/drain patternand the eighth source/drain pattern) may each include n-type impurities (e.g., B, In, Ga, or Al) or impurities to prevent the diffusion of the n-type impurities.

461 462 4 1 2 4 1 2 461 462 461 462 431 432 440 420 The fourth-level source/drain patterns (e.g., the ninth source/drain patternand the tenth source/drain pattern) may be formed within the fourth active pattern Aon the sidewalls of the first gate structure Gand the second gate structure G. The fourth active pattern Amay extend through the first gate structure Gand the second gate structure Gand be connected to the fourth-level source/drain patterns (e.g., the ninth source/drain patternand the tenth source/drain pattern). The fourth-level source/drain patterns (e.g., the ninth source/drain patternand the tenth source/drain pattern) may be separated from the fourth gate electrodeand the eighth gate electrodeby the gate spacersand/or the fourth gate dielectric film.

461 462 461 462 461 431 432 431 461 462 The fourth-level source/drain patterns (e.g., the ninth source/drain patternand the tenth source/drain pattern) may include the ninth source/drain patternand the tenth source/drain pattern. The ninth source/drain patternmay be interposed between the fourth and eighth gate electrodesand. The fourth gate electrodemay be interposed between the ninth source/drain patternand the tenth source/drain pattern.

461 462 461 462 4 In one or more embodiments, the fourth-level source/drain patterns (e.g., the ninth source/drain patternand the tenth source/drain pattern) may each include an epitaxial layer doped with impurities. For example, the fourth-level source/drain patterns (e.g., the ninth source/drain patternand the tenth source/drain pattern) may include epitaxial patterns grown by an epitaxial growth method from the fourth active pattern A.

4 461 462 If the fourth active pattern Aserves as the channel region of an NFET, the fourth-level source/drain patterns (e.g., the ninth source/drain patternand the tenth source/drain pattern) may each include n-type impurities (e.g., B, In, Ga, or Al) or impurities to prevent the diffusion of the n-type impurities.

190 290 390 490 100 190 290 390 490 100 190 290 390 490 1 2 a. The first, second, third, and fourth interlayer insulating films,,, andmay be formed on the substrate. The first, second, third, and fourth interlayer insulating films,,, andmay be sequentially stacked on the first surfaceThe first, second, third, and fourth interlayer insulating films,,, andmay fill the spaces on the sidewalls of the first gate structure Gand the second gate structure G.

190 100 190 161 163 290 190 290 261 263 390 290 390 361 363 490 390 490 461 462 a. The first interlayer insulating filmmay be formed on the first surfaceThe first interlayer insulating filmmay cover the first-level source/drain patterns (e.g., the first through third source/drain patternsthrough). The second interlayer insulating filmmay be formed on the first interlayer insulating film. The second interlayer insulating filmmay cover the second-level source/drain patterns (e.g., the fourth through sixth source/drain patternsthrough). The third interlayer insulating filmmay be formed on the second interlayer insulating film. The third interlayer insulating filmmay cover the third-level source/drain patterns (e.g., the seventh source/drain patternand the eighth source/drain pattern). The fourth interlayer insulating filmmay be formed on the third interlayer insulating film. The fourth interlayer insulating filmmay cover the fourth-level source/drain patterns (e.g., the ninth source/drain patternand the tenth source/drain pattern).

190 290 390 490 The first, second, third, and fourth interlayer insulating films,,, andmay each include, for example, at least one from among silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbon nitride, silicon oxycarbonitride, and a low-k dielectric material with a less dielectric constant than silicon oxide, but embodiments of the disclosure are not limited thereto.

361 363 462 361 3 331 390 331 In one or more embodiments, the third-level source/drain patterns (e.g., the seventh source/drain patternand the eighth source/drain pattern) may not overlap with the tenth source/drain patternin the third direction Z. For example, the seventh source/drain patternmay be connected to the third active pattern Aon one side of the third gate electrode, and part of the third interlayer insulating filmmay fill the area on the opposite side of the third gate electrode.

461 462 363 461 4 432 490 432 In one or more embodiments, the fourth-level source/drain patterns (e.g., the ninth source/drain patternand the tenth source/drain pattern) may not overlap with the eighth source/drain patternin the third direction Z. For example, the ninth source/drain patternmay be connected to the fourth active pattern Aon one side of the eighth gate electrode, and part of the fourth interlayer insulating filmmay fill the area on the opposite side of the eighth gate electrode.

3 4 100 3 4 1 4 3 4 a. The frontside source/drain contacts (e.g., the first frontside source/drain contact CAand the second frontside source/drain contact CA) may each be disposed on the first surfaceThe frontside source/drain contacts (e.g., the first frontside source/drain contact CAand the second frontside source/drain contact CA) may each extend in the third direction Z and be connected to the first through fourth active patterns Athrough A. The number, shape, and arrangement of the frontside source/drain contacts (e.g., the first frontside source/drain contact CAand the second frontside source/drain contact CA) are merely example and are not particularly limited.

3 4 4 3 In one or more embodiments, the frontside source/drain contacts (e.g., the first frontside source/drain contact CAand the second frontside source/drain contact CA) may include the first frontside source/drain contact CAand the second frontside source/drain contact CA.

4 1 2 4 461 4 490 461 The first frontside source/drain contact CAmay be interposed between the first gate structure Gand the second gate structure G. The first frontside source/drain contact CAmay be connected to the ninth source/drain pattern. For example, the first frontside source/drain contact CAmay penetrate the fourth interlayer insulating filmand be connected to the upper surface of the ninth source/drain pattern.

2 4 3 3 363 3 490 390 363 The second gate structure Gmay be interposed between the first frontside source/drain contact CAand the second frontside source/drain contact CA. The second frontside source/drain contact CAmay be connected to the eighth source/drain pattern. For example, the second frontside source/drain contact CAmay penetrate the fourth interlayer insulating filmand the third interlayer insulating filmand be connected to the upper surface of the eighth source/drain pattern.

100 495 490 495 495 11 13 2 11 13 2 11 13 2 a. The frontside wiring structure FW may be formed on the first surfaceFor example, a fifth interlayer insulating filmmay be formed to cover the fourth interlayer insulating film. The frontside wiring structure FW may be formed on the fifth interlayer insulating film. The frontside wiring structure FW may include a frontside wiring insulating film FD that covers the fifth interlayer insulating film, and frontside wiring patterns (e.g., first through fourth frontside wiring patterns FMthrough FMand a fifth frontside wiring pattern FM) within the frontside wiring insulating film FD. The frontside wiring patterns (e.g., the first through fourth frontside wiring patterns FMthrough FMand the fifth frontside wiring pattern FM) may be spaced apart and insulated from one another by the frontside wiring insulating film FD. The number, shape, and arrangement of the frontside wiring patterns (e.g., the first through fourth frontside wiring patterns FMthrough FMand the fifth frontside wiring pattern FM) are merely example and are not particularly limited.

11 12 13 2 In one or more embodiments, the frontside wiring patterns may include a first frontside wiring pattern FM, a second frontside wiring pattern FM, a third frontside wiring pattern FM, and a fourth frontside wiring pattern FM.

11 12 13 11 12 13 11 12 13 11 12 13 100 11 12 13 The first, second, and third frontside wiring patterns FM, FM, and FMmay each extend in the first direction X. The first, second, and third frontside wiring patterns FM, FM, and FMmay be arranged along the second direction Y. In one or more embodiments, the first, second, and third frontside wiring patterns FM, FM, and FMmay be disposed at the same level. Here, “disposed at the same level” means that the first, second, and third frontside wiring patterns FM, FM, and FMare positioned at the same height relative to the substrate. In one or more embodiments, the first frontside wiring pattern FMmay be interposed between the second frontside wiring pattern FMand the third frontside wiring pattern FMin the second direction Y.

11 4 1 495 4 11 11 1 4 The first frontside wiring pattern FMmay be connected to the first frontside source/drain contact CA. For example, a first contact via VAmay be formed to penetrate the fifth interlayer insulating filmand connect the first frontside source/drain contact CAand the first frontside wiring pattern FM. The first frontside wiring pattern FMmay be provided as a bitline BL and may be connected to the first pass transistor PSthrough the first frontside source/drain contact CA.

12 3 2 495 3 12 12 2 3 The second frontside wiring pattern FMmay be connected to the second frontside source/drain contact CA. For example, a second contact via VAmay be formed to penetrate the fifth interlayer insulating filmand connect the second frontside source/drain contact CAand the second frontside wiring pattern FM. The second frontside wiring pattern FMmay be provided as a complementary bitline/BL and may be connected to the second pass transistor PSthrough the second frontside source/drain contact CA.

13 431 332 1 495 450 431 13 2 495 450 535 332 13 The third frontside wiring pattern FMmay be connected to the fourth gate electrodeand the seventh gate electrode. For example, a first frontside gate contact CBmay be formed to penetrate the fifth interlayer insulating filmand the gate capping filmand connect the fourth gate electrodeand the third frontside wiring pattern FM. Additionally, for example, a second frontside gate contact CBmay be formed to penetrate the fifth interlayer insulating film, the gate capping film, and the third gate separation patternand connect the seventh gate electrodeand the third frontside wiring pattern FM.

2 2 11 13 2 13 13 2 2 1 431 2 332 The fourth frontside wiring pattern FMmay extend in the second direction Y. In one or more embodiments, the fourth frontside wiring pattern FMmay be disposed at a higher level than the first through third frontside wiring patterns FMthrough FM. The fourth frontside wiring pattern FMmay be connected to the third frontside wiring pattern FM. For example, a frontside via FV may be formed to extend in the third direction Z and connect the third frontside wiring pattern FMand the fourth frontside wiring pattern FM. The fourth frontside wiring pattern FMmay be provided as a wordline WL and may be connected to the gate of the first pass transistor PS, i.e., the fourth gate electrode, and the gate of the second pass transistor PS, i.e., the seventh gate electrode.

11 12 13 21 22 3 4 100 11 12 13 21 22 3 4 1 4 11 12 13 21 22 3 4 The backside source/drain contacts (e.g., the first through sixth backside source/drain contacts BCA, BCA, BCA, BCA, BCA, BCA, and BCA) may each penetrate the substrate. The backside source/drain contacts (e.g., the first through sixth backside source/drain contacts BCA, BCA, BCA, BCA, BCA, BCA, and BCA) may each extend in the third direction Z and be connected to the first through fourth active patterns Athrough A. The number, shape, and arrangement of the backside source/drain contacts (e.g., the first through sixth backside source/drain contacts BCA, BCA, BCA, BCA, BCA, BCA, and BCA) are merely example and are not particularly limited.

11 12 13 21 22 3 4 11 12 13 21 22 3 4 In one or more embodiments, the backside source/drain contacts (e.g., the first through sixth backside source/drain contacts BCA, BCA, BCA, BCA, BCA, BCA, and BCA) may include a first backside source/drain contact BCA, a second backside source/drain contact BCA, a third backside source/drain contact BCA, a fourth backside source/drain contact BCA, a fifth backside source/drain contact BCA, a sixth backside source/drain contact BCA, and a seventh backside source/drain contact BCA.

11 1 2 11 161 11 100 161 The first backside source/drain contact BCAmay be interposed between the first gate structure Gand the second gate structure G. The first backside source/drain contact BCAmay be connected to the first source/drain pattern. For example, the first backside source/drain contact BCAmay penetrate the substrateand be connected to the lower surface of the first source/drain pattern.

1 11 12 12 162 12 100 162 The first gate structure Gmay be interposed between the first backside source/drain contact BCAand the second backside source/drain contact BCA. The second backside source/drain contact BCAmay be connected to the second source/drain pattern. For example, the second backside source/drain contact BCAmay penetrate the substrateand be connected to the lower surface of the second source/drain pattern.

2 11 13 13 163 13 100 163 The second gate structure Gmay be interposed between the first backside source/drain contact BCAand the third backside source/drain contact BCA. The third backside source/drain contact BCAmay be connected to the third source/drain pattern. For example, the third backside source/drain contact BCAmay penetrate the substrateand be connected to the lower surface of the third source/drain pattern.

21 1 2 21 261 The fourth backside source/drain contact BCAmay be interposed between the first gate structure Gand the second gate structure G. The fourth backside source/drain contact BCAmay be connected to the fourth source/drain pattern.

261 261 261 261 161 261 261 261 161 21 261 11 21 a b. a b a b b. In one or more embodiments, the fourth source/drain patternmay include a first base portionand a first extension portionThe first base portionmay overlap with the first source/drain patternin the third direction Z. The first extension portionmay extend from the first base portionin the second direction Y. The first extension portionmay not overlap with the first source/drain patternin the third direction Z. The fourth backside source/drain contact BCAmay extend in the third direction Z and contact the first extension portionThe first backside source/drain contact BCAand the fourth backside source/drain contact BCAmay be arranged along the second direction Y.

2 21 22 22 263 The second gate structure Gmay be interposed between the fourth backside source/drain contact BCAand the fifth backside source/drain contact BCA. The fifth backside source/drain contact BCAmay be connected to the sixth source/drain pattern.

263 263 263 263 163 263 263 263 163 22 263 22 22 a b. a b a b b. In one or more embodiments, the sixth source/drain patternmay include a second base portionand a second extension portionThe second base portionmay overlap with the third source/drain patternin the third direction Z. The second extension portionmay extend from the second base portionin the second direction Y. The second extension portionmay not overlap with the third source/drain patternin the third direction Z. The fifth backside source/drain contact BCAmay extend in the third direction Z and contact the second extension portionThe third backside source/drain contact BCAand the fifth backside source/drain contact BCAmay be arranged along the second direction Y.

3 1 2 3 361 The sixth backside source/drain contact BCAmay be interposed between the first gate structure Gand the second gate structure G. The sixth backside source/drain contact BCAmay be connected to the seventh source/drain pattern.

361 361 361 361 261 361 361 361 261 261 3 361 11 21 3 a b. a a b a b a b b. In one or more embodiments, the seventh source/drain patternmay include a third base portionand a third extension portionThe third base portionmay overlap with the first base portionin the third direction Z. The third extension portionmay extend from the third base portionin the second direction Y. The third extension portionmay not overlap with the first base portionor the first extension portionin the third direction Z. The sixth backside source/drain contact BCAmay extend in the third direction Z and contact the third extension portionThe first backside source/drain contact BCAmay be interposed between the fourth backside source/drain contact BCAand the sixth backside source/drain contact BCAin the second direction Y.

1 21 4 4 262 462 The first gate structure Gmay be interposed between the fourth backside source/drain contact BCAand the seventh backside source/drain contact BCA. The seventh backside source/drain contact BCAmay be connected to the fifth source/drain patternand the tenth source/drain pattern.

262 262 262 262 162 262 262 262 162 4 262 12 4 a b. a b a b b. In one or more embodiments, the fifth source/drain patternmay include a fourth base portionand a fourth extension portionThe fourth base portionmay overlap with the second source/drain patternin the third direction Z. The fourth extension portionmay extend from the fourth base portionin the second direction Y. The fourth extension portionmay not overlap with the second source/drain patternin the third direction Z. The seventh backside source/drain contact BCAmay extend in the third direction Z and contact the fourth extension portionThe second backside source/drain contact BCAand the seventh backside source/drain contact BCAmay be arranged along the second direction Y.

462 462 462 462 262 462 462 462 262 4 262 462 a b. a a b a b b b b. In one or more embodiments, the tenth source/drain patternmay include a fifth base portionand a fifth extension portionThe fifth base portionmay overlap with the fourth base portionin the third direction Z. The fifth extension portionmay extend from the fifth base portionin the second direction Y. The fifth extension portionmay overlap with the fourth extension portionin the third direction Z. The seventh backside source/drain contact BCAmay extend in the third direction Z and contact both the fourth extension portionand the fifth extension portion

100 100 11 12 21 22 11 12 21 22 11 12 21 22 b. b, The backside wiring structure BW may be formed on the second surfaceThe backside wiring structure BW may include a backside wiring insulating film BD that covers the second surfaceand backside wiring patterns (e.g., a first connection wiring pattern BM, a second connection wiring pattern BM, a first backside wiring pattern BM, and a second backside wiring pattern BM) within the backside wiring insulating film BD. The backside wiring patterns (e.g., the first connection wiring pattern BM, the second connection wiring pattern BM, the first backside wiring pattern BM, and the second backside wiring pattern BM) may be spaced apart and insulated from one another by the backside wiring insulating film BD. The number, shape, and arrangement of the backside wiring patterns (e.g., the first connection wiring pattern BM, the second connection wiring pattern BM, the first backside wiring pattern BM, and the second backside wiring pattern BM) are merely example and are not particularly limited.

11 12 21 22 In one or more embodiments, the backside wiring patterns may include a first connection wiring pattern BM, a second connection wiring pattern BM, a first backside wiring pattern BM, and a second backside wiring pattern BM.

11 12 100 11 12 b. The first connection wiring pattern BMand the second connection wiring pattern BMmay be disposed on the second surfaceIn one or more embodiments, the first connection wiring pattern BMand the second connection wiring pattern BMmay be disposed at the same level.

11 12 4 132 232 2 100 515 132 232 11 12 4 2 11 1 1 2 132 232 The first connection wiring pattern BMmay be connected to the second backside source/drain contact BCA, the seventh backside source/drain contact BCA, the fifth gate electrode, and the sixth gate electrode. For example, a first backside gate contact BCBmay be formed to penetrate the substrateand the first gate separation patternand be connected to the fifth gate electrodeand the sixth gate electrode. The first connection wiring pattern BMmay connect the second backside source/drain contact BCA, the seventh backside source/drain contact BCA, and the first backside gate contact BCB. Through this, the first connection wiring pattern BMmay connect the output node Nof the first inverter INVto the input node of the second inverter INV, i.e., the fifth gate electrodeand the sixth gate electrode.

12 13 22 3 131 231 1 100 515 131 231 12 13 22 3 1 12 2 2 1 131 231 The second connection wiring pattern BMmay be connected to the third, fifth, and sixth backside source/drain contacts BCA, BCA, BCAand the first gate electrodeand the second gate electrode. For example, a second backside gate contact BCBmay be formed to penetrate the substrateand the first gate separation patternand be connect to the first gate electrodeand the second gate electrode. The second connection wiring pattern BMmay connect the third, fifth, and sixth backside source/drain contacts BCA, BCA, and BCAand the second backside gate contact BCB. Through this, the second connection wiring pattern BMmay connect the output node Nof the second inverter INVto the input node of the first inverter INV, i.e., the first gate electrodeand the second gate electrode.

21 22 21 22 21 22 21 22 11 12 The first backside wiring pattern BMand the second backside wiring pattern BMmay each extend longitudinally in the first direction X. The first backside wiring pattern BMand the second backside wiring pattern BMmay be arranged along the second direction Y. In one or more embodiments, the first backside wiring pattern BMand the second backside wiring pattern BMmay be disposed at the same level. In one or more embodiments, the first backside wiring pattern BMand the second backside wiring pattern BMmay be disposed at a higher level than the first connection wiring pattern BMand the second connection wiring pattern BM.

21 11 1 11 21 21 1 2 DD The first backside wiring pattern BMmay be connected to the first backside source/drain contact BCA. For example, a first backside via BVmay be formed to extend in the third direction Z and connect the first backside source/drain contact BCAand the first backside wiring pattern BM. The first backside wiring pattern BMmay be provided as a first power supply line for applying a first power supply voltage (e.g., V) to the first pull-up transistor PUand the second pull-up transistor PU.

22 21 2 21 22 22 1 2 SS The second backside wiring pattern BMmay be connected to the fourth backside source/drain contact BCA. For example, a second backside via BVmay be formed to extend in the third direction Z and connect the fourth backside source/drain contact BCAand the second backside wiring pattern BM. The second backside wiring pattern BMmay be provided as a second power supply line for applying a second power supply voltage (e.g., V), which is different from the first power voltage, to the first pull-down transistor PDand the second pull-down transistor PD.

1 39 FIGS.through A method for manufacturing a semiconductor device according to example embodiments will hereinafter be described with reference to.

10 39 FIGS.through 1 9 FIGS.through are cross-sectional views for explaining a method for manufacturing a semiconductor device according to one or more embodiments. For convenience of explanation, content that overlaps with what has been described above with reference tomay be briefly explained or omitted.

10 FIG. 10 Referring to, a fin structure FS is formed on a base substrate.

15 1 4 510 520 530 540 515 525 535 The fin structure FS may extend in the first direction X. The fin structure FS may include a fin pattern, first through fourth active patterns Athrough A, first through fourth sacrificial patterns,,, and, and first through third sacrificial separation patternsS,S, andS.

15 10 1 510 15 515 1 510 2 520 515 525 2 520 3 530 525 535 3 530 4 540 535 The fin patternmay protrude from the upper surface of the base substrateand extend in the first direction X. The first active pattern Aand the first sacrificial patternmay be alternately stacked on the fin pattern. The first sacrificial separation patternS may be stacked on the first active pattern Aand the first sacrificial pattern. The second active pattern Aand the second sacrificial patternmay be alternately stacked on the first sacrificial separation patternS. The second sacrificial separation patternS may be stacked on the second active pattern Aand the second sacrificial pattern. The third active pattern Aand the third sacrificial patternmay be alternately stacked on the second sacrificial separation patternS. The third sacrificial separation patternS may be stacked on the third active pattern Aand the third sacrificial pattern. The fourth active pattern Aand the fourth sacrificial patternmay be alternately stacked on the third sacrificial separation patternS.

510 520 530 540 1 4 1 4 510 520 530 540 The first, second, third, and fourth sacrificial patterns,,, andmay each include a material that has an etch selectivity with respect to the first through fourth active patterns Athrough A. For example, the first through fourth active patterns Athrough Amay each include an Si film, and the first, second, third, and fourth sacrificial patterns,,, andmay each include an SiGe film.

515 525 535 1 4 510 520 530 540 510 520 530 540 515 525 535 The first, second, and third sacrificial separation patternsS,S, andS may each include a material that has an etch selectivity with respect to the first through fourth active patterns Athrough Aand the first, second, third, and fourth sacrificial patterns,,, and. For example, the first, second, third, and fourth sacrificial patterns,,, andmay each include an SiGe film containing a first concentration of Ge, and the first, second, and third sacrificial separation patternsS,S, andS may each include an SiGe film containing a second concentration of Ge that is higher than the first concentration.

11 FIG. 1 2 Referring to, a first dummy gate structure DGand a second dummy gate structure DGare formed on the fin structure FS.

1 2 1 2 The first dummy gate structure DGand the second dummy gate structure DGmay be spaced apart from each other and intersect the fin structure FS. For example, the first dummy gate structure DGand the second dummy gate structure DGmay be spaced apart from each other in the first direction X and may each extend longitudinally in a second direction Y.

1 2 630 440 650 650 650 630 440 630 Each of the first dummy gate structure DGand the second dummy gate structure DGmay include a dummy gate electrode, gate spacers, and a first mask pattern. For example, a material film may be formed on the fin structure FS. Thereafter, the first mask pattern, which extends in parallel in the second direction Y, may be formed on the material film. Thereafter, using the first mask patternas an etching mask, a patterning process may be performed on the material film to form the dummy gate electrode. Thereafter, the gate spacers, which extend along the sidewalls of the dummy gate electrode, may be formed.

630 1 4 630 The dummy gate electrodemay include a material having an etch selectivity with respect to the first through fourth active patterns Athrough A. For example, the dummy gate electrodemay include a polysilicon film.

12 FIG. 515 525 535 Referring to, the first, second, and third gate separation patterns,, andare formed.

515 525 535 515 525 535 515 525 535 15 1 4 510 520 530 540 515 525 535 For example, the first, second, and third sacrificial separation patternsS,S, andS may be selectively removed. Thereafter, the first, second, and third gate separation patterns,, and, which replace the removed first through third sacrificial separation patternsS,S, andS, respectively, may be formed. Through this, the fin structure FS, which includes the fin pattern, the first through fourth active patterns Athrough A, the first, second, third, and fourth sacrificial patterns,,,, and the first, second, and third gate separation patterns,,, may be formed.

13 FIG. 1 2 Referring to, a recess process is performed on the fin structure FS using the first dummy gate structure DGand the second dummy gate structure DG.

1 2 4 520 530 540 515 525 535 As the recess process is performed, first recesses Rmay be formed within the second through fourth active patterns Athrough A, the second, third, and fourth sacrificial patterns,, and, and the first, second, and third gate separation patterns,, and.

14 FIG. 640 Referring to, a first liner filmis formed.

640 640 1 640 13 FIG. The first liner filmmay be formed over the result from. For example, the first liner filmmay conformally extend along the profile of the first recesses R. The first liner filmmay include an insulating material such as, for example, at least one from among silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and a combination thereof, but embodiments of the disclosure are not limited thereto.

15 FIG. 1 510 640 Referring to, a recess process is performed on the first active pattern Aand the first sacrificial patternusing the first liner film.

2 1 510 2 As the recess process is performed, second recesses Rmay be formed within the first active pattern Aand the first sacrificial pattern. In one or more embodiments, the bottom surfaces of the second recesses Rmay be formed lower than the upper surface of the fin structure FS.

16 FIG. 161 163 Referring to, first-level source/drain patterns (e.g., the first through third source/drain patternsthrough) are formed.

161 163 1 161 163 1 The first-level source/drain patterns (e.g., the first through third source/drain patternsthrough) may be formed through an epitaxial growth process that uses the first active pattern Aas a seed layer. Through this, the first-level source/drain patterns (e.g., the first through third source/drain patternsthrough), which are connected to the first active pattern A, may be formed.

660 161 163 660 660 10 15 10 15 660 660 In one or more embodiments, a holder patternmay be formed within the fin structure FS. The first-level source/drain patterns (e.g., the first through third source/drain patternsthrough) may be formed on the holder pattern. The holder patternmay include a material having an etch selectivity with respect to the base substrateand the fin pattern. For example, the base substrateand the fin patternmay each include an Si film, and the holder patternmay include an SiGe film. In one or more embodiments, the holder patternmay be omitted.

17 FIG. 190 161 163 Referring to, a first interlayer insulating filmis formed on the first-level source/drain patterns (e.g., the first through third source/drain patternsthrough).

190 161 163 190 2 The first interlayer insulating filmmay cover the first-level source/drain patterns (e.g., the first through third source/drain patternsthrough). In one or more embodiments, the upper surface of the first interlayer insulating filmmay be formed lower than the lower surface of the second active pattern A.

18 FIG. 260 190 Referring to, a first sacrificial source/drain patternS is formed on the first interlayer insulating film.

260 1 260 525 The first sacrificial source/drain patternS may be formed within the first recesses R. In one or more embodiments, the upper surface of the first sacrificial source/drain patternS may be formed lower than the upper surface of the second gate separation pattern.

19 FIG. 670 640 Referring to, a second liner filmis formed on the first liner film.

670 260 670 640 670 The second liner filmmay expose the upper surface of the first sacrificial source/drain patternS. For example, the second liner filmmay conformally extend along the profile of the outer surface of the first liner film. The second liner filmmay include an insulating material such as, for example, at least one from among silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and a combination thereof, but embodiments of the disclosure are not limited thereto.

20 FIG. 670 2 Referring to, the second liner filmis used to expose the second active pattern A.

260 670 260 640 3 2 520 640 670 For example, an etching process may be performed on the first sacrificial source/drain patternS using the second liner film. Thereafter, as the first sacrificial source/drain patternS is removed, part of the first liner filmthat is exposed may also be etched. Through this, third recesses Rare formed, exposing the second active pattern Aand the second sacrificial patternfrom the first liner filmand the second liner film.

21 22 FIGS.and 261 263 290 Referring to, second-level source/drain patterns (e.g., the fourth through sixth source/drain patternsthrough) and a second interlayer insulating filmare formed.

261 263 290 161 163 190 The formation of the second-level source/drain patterns (e.g., the fourth through sixth source/drain patternsthrough) and the second interlayer insulating filmmay be similar to the formation of the first-level source/drain patterns (e.g., the first through third source/drain patternsthrough) and the first interlayer insulating film, and thus, a repeated explanation thereof may be omitted.

261 261 161 a The fourth source/drain patternmay include a first base portionthat overlaps with the first source/drain patternin a third direction Z.

23 FIG. 261 Referring to, part of the fourth source/drain patternis exposed.

290 261 290 290 161 290 261 h h h a. For example, a source/drain holeexposing part of the fourth source/drain patternmay be formed within the second interlayer insulating film. In one or more embodiments, at least part of the source/drain holemay not overlap with the first source/drain patternin the third direction Z. For example, at least part of the source/drain holemay be arranged along the second direction Y with the first base portion

24 FIG. 261 a Referring to, an epitaxial growth process is performed using the first base portionas a seed layer.

261 261 261 261 261 b a. a b, As the epitaxial growth process is performed, the first extension portionmay grow in the second direction Y from the first base portionThrough this, the fourth source/drain pattern, including the first base portionand the first extension portionmay be formed.

25 FIG. 290 Referring to, the second interlayer insulating filmis formed.

290 290 261 h For example, an insulating material filling the source/drain holemay be formed. Through this, the second interlayer insulating filmcovering the fourth source/drain patternmay be formed.

261 261 261 263 263 263 262 262 262 a b, a b, a b, 22 25 FIGS.through Only the fourth source/drain pattern, including the first base portionand the first extension portionhas been described so far with reference to, but those skilled in the art to which the disclosure pertains will understand that the sixth source/drain pattern, including the second base portionand the second extension portionand the fifth source/drain pattern, including the fourth base portionand the fourth extension portioncan also be similarly formed.

26 FIG. 361 362 363 390 Referring to, third-level source/drain patterns (e.g., a seventh source/drain pattern, an eleventh source/drain pattern, and an eighth source/drain pattern) and a third interlayer insulating filmare formed.

361 362 363 390 261 263 290 The formation of the third-level source/drain patterns (e.g., the seventh source/drain pattern, the eleventh source/drain pattern, and the eighth source/drain pattern) and the third interlayer insulating filmmay be similar to the formation of the second-level source/drain patterns (e.g., the fourth through sixth source/drain patternsthrough) and the second interlayer insulating film, and thus, a repeated explanation thereof may be omitted.

27 FIG. 361 362 363 Referring to, parts of the third-level source/drain patterns (e.g., the seventh source/drain pattern, the eleventh source/drain pattern, and the eighth source/drain pattern) are removed.

362 1 2 390 362 361 363 For example, a second mask pattern MP that exposes the eleventh source/drain patternmay be formed on the first dummy gate structure DG, the second dummy gate structure DG, and the third interlayer insulating film. Thereafter, an etching process may be performed on the eleventh source/drain patternusing the second mask pattern MP. Through this, the third-level source/drain patterns, which include the seventh source/drain patternand the eighth source/drain pattern, may be formed.

28 29 FIGS.and 390 Referring to, a third interlayer insulating filmis formed.

362 390 361 363 For example, an insulating material that fills the region where the eleventh source/drain patternhas been removed may be formed. Through this, the third interlayer insulating filmthat covers the third-level source/drain patterns (e.g., the seventh source/drain patternand the eighth source/drain pattern) may be formed.

30 FIG. 361 361 361 a b, Referring to, the seventh source/drain pattern, including the third base portionand the third extension portionis formed.

361 361 361 261 261 263 a b, a b, The formation of the seventh source/drain pattern, including the third base portionand the third extension portionmay be similar to the formation of the fourth source/drain pattern, including the first base portionand the second extension portionand thus, a repeated explanation thereof may be omitted.

31 FIG. 461 462 463 490 Referring to, fourth-level source/drain patterns (e.g., a ninth source/drain pattern, a tenth source/drain pattern, and an eleventh source/drain pattern) and a fourth interlayer insulating filmare formed.

461 462 463 490 361 362 363 390 The formation of the fourth-level source/drain patterns (e.g., the ninth source/drain pattern, the tenth source/drain pattern, and the eleventh source/drain pattern) and the fourth interlayer insulating filmmay be similar to the formation of the third-level source/drain patterns (e.g., the seventh source/drain pattern, the eleventh source/drain pattern, and the eighth source/drain pattern) and the third interlayer insulating film, so a repeated explanation may be omitted here.

32 FIG. 461 462 463 Referring to, parts of the fourth-level source/drain patterns (e.g., the ninth source/drain pattern, the tenth source/drain pattern, and the eleventh source/drain pattern) are removed.

461 462 463 361 362 363 461 462 461 462 The removal of parts of the fourth-level source/drain patterns (e.g., the ninth source/drain pattern, the tenth source/drain pattern, and the eleventh source/drain pattern) may be similar to the removal of parts of the third-level source/drain patterns (e.g., the seventh source/drain pattern, the eleventh source/drain pattern, and the eighth source/drain pattern), and thus, a repeated explanation thereof may be omitted. Through this, the fourth-level source/drain patterns (e.g., the ninth source/drain patternand the tenth source/drain pattern), including the ninth source/drain patternand the tenth source/drain pattern, may be formed.

33 FIG. 1 2 Referring to, the first gate structure Gand the second gate structure Gare formed.

650 630 510 520 530 540 120 220 320 420 630 510 520 530 540 131 231 331 431 132 232 332 432 120 220 320 420 450 431 432 For example, the first mask patternmay be removed. Thereafter, the dummy gate electrodeand the first, second, third, and fourth sacrificial patterns,,, andmay be selectively removed. Thereafter, first, second, third, and fourth gate dielectric films,,, andmay be formed in the regions where the dummy gate electrodeand the first through fourth sacrificial patterns,,, andhave been removed. Thereafter, first, second, third, and fourth gate electrodes,,, andand fifth, sixth, seventh, and eighth gate electrodes,,, andmay be formed on the first, second, third, and fourth gate dielectric films,,, and. Thereafter, a gate capping filmmay be formed to cover the fourth and eighth gate electrodesand.

34 FIG. 3 4 1 2 490 Referring to, frontside source/drain contacts (e.g., the first frontside source/drain contact CAand the second frontside source/drain contact CA) and a frontside wiring structure FW are formed on the first gate structure G, the second gate structure G, and the fourth interlayer insulating film.

35 FIG. 700 Referring to, the frontside wiring structure FW is attached to a carrier substrate.

700 700 34 FIG. 34 FIG. For example, the carrier substratemay be attached to the result from. After the carrier substrateis attached, the result frommay be inverted.

36 FIG. 10 15 Referring to, the base substrateand the fin patternare removed.

10 15 660 In one or more embodiments, the base substrateand the fin patternmay be selectively removed relative to the holder pattern.

37 FIG. 100 Referring to, a substrateis formed.

38 FIG. 100 100 h Referring to, contact holesare formed in the substrate.

100 161 163 660 660 161 163 h The contact holesmay expose the first-level source/drain patterns (e.g., the first through third source/drain patternsthrough). For example, a preliminary contact hole exposing the holder patternmay be formed. Thereafter, an etching process may be performed on the holder patternusing the preliminary contact hole. Through this, the first-level source/drain patterns (e.g., the first through third source/drain patternsthrough) may be exposed.

39 FIG. 11 12 13 21 22 3 4 Referring to, backside source/drain contacts (e.g., the first through sixth backside source/drain contacts BCA, BCA, BCA, BCA, BCA, BCA, and BCA) are formed.

11 12 13 100 11 12 13 21 22 3 4 1 4 h For example, first, second, and third backside source/drain contacts BCA, BCA, and BCAfilling the contact holesmay be formed. Through this, the backside source/drain contacts (e.g., the first through sixth backside source/drain contacts BCA, BCA, BCA, BCA, BCA, BCA, and BCA), connected to the first through fourth active patterns Athrough A, may be formed.

3 FIG. 1 9 FIGS.through 100 11 12 13 21 22 3 4 Thereafter, referring again to, a backside wiring structure BW may be formed on the substrateand the backside source/drain contacts (e.g., the first through sixth backside source/drain contacts BCA, BCA, BCA, BCA, BCA, BCA, and BCA). Through this, the semiconductor device described earlier usingcan be manufactured.

While non-limiting example embodiments of the disclosure have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Therefore the example embodiments should be considered in all respects as illustrative and not restrictive.