Semiconductor Device

This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0096442 filed in the Korean Intellectual Property Office on Jul. 22, 2024, the entire contents of which are incorporated herein by reference.

In modern society, semiconductor devices are closely related to our daily lives. In particular, power semiconductor devices are becoming increasingly important in various fields including transportation, such as electric vehicles, railways, and electric trams, renewable energy systems, such as solar energy generation and wind power generation, and mobile devices. Power semiconductor devices are semiconductor devices used to handle high voltages or high currents, perform functions such as power conversion, and control large power systems and high-power electronic devices. Power semiconductor devices can handle high power and durability and thus are capable of handling large amounts of current and withstanding high voltages. For example, power semiconductor devices may handle voltages of hundreds to thousands of volts and currents of tens to thousands of amperes. Power semiconductor devices may improve the efficiency of electrical energy by minimizing power losses. Power semiconductor devices may also operate reliably in diverse environments, such as high temperatures.

These power semiconductor devices may be categorized by material, and may include, for example, SiC power semiconductor devices and GaN power semiconductor devices. By utilizing SiC or GaN in place of traditional silicon (Si) to manufacture power semiconductor devices, the disadvantages of silicon, such as its instability at high temperatures, may be overcome. SiC power semiconductor devices are resistant to high temperatures and have low power loss, and may be suitable for electric vehicles, renewable energy systems, and more. GaN power semiconductor devices are relatively expensive compared to SiC power semiconductor devices, but are efficient in terms of speed, and may be suitable for fast charging of mobile devices.

In a first general aspect, a semiconductor device includes: a main transistor; and a sub-transistor connected to one end of the main transistor, in which the main transistor includes: a main channel layer; a main gate electrode located on the main channel layer; a main gate semiconductor layer located between the main channel layer and the main gate electrode; a source electrode and a drain electrode located on opposite sides of the main gate electrode and connected to the main channel layer; and a field dispersion layer located on the main channel layer, and located between the main gate electrode and the drain electrode, and the sub-transistor includes: a sub-channel layer including a drift region having two-dimensional electron gas, and including a first contact portion connected with the source electrode, a second contact portion connected with the field dispersion layer, and an extension portion connecting the first contact portion and the second contact portion; and a sub-gate electrode located on the extension portion of the sub-channel layer, and connected with the main gate electrode.

In a second general aspect, a semiconductor device includes: a main channel layer; a gate electrode located on the main channel layer; a gate semiconductor layer located between the main channel layer and the gate electrode; a source electrode and a drain electrode located on opposite sides of the gate electrode and connected to the main channel layer; a field dispersion layer located on the main channel layer, and located between the gate electrode and the drain electrode; and a sub-channel layer including a drift region having two-dimensional electron gas, and including a first contact portion connected with the source electrode, a second contact portion connected with the field dispersion layer, and an extension portion connecting the first contact portion and the second contact portion, in which the gate electrode overlaps the extension portion of the sub-channel layer in a thickness direction of the sub-channel layer.

In a third general aspect, a semiconductor device includes: a main transistor; and a sub-transistor connected to one end of the main transistor, in which the main transistor includes: a main channel layer including GaN; a barrier layer located on the main channel layer and including AlGaN; a main gate electrode located on the barrier layer; a main gate semiconductor layer located between the main channel layer and the main gate electrode and including GaN doped with p-type impurities; a source electrode and a drain electrode located on opposite sides of the main gate electrode and connected to the main channel layer; a first protective layer located on the main gate electrode and the barrier layer; and a field dispersion layer located on the first protective layer, and located between the main gate electrode and the drain electrode, and the sub-transistor includes: a sub-channel layer located on one side of the main channel layer, including the same material as the main channel layer, and including a first contact portion penetrating the barrier layer to be connected with the source electrode, a second contact portion penetrating the first protective layer and the barrier layer to be connected with the field dispersion layer, and an extension portion connecting the first contact portion and the second contact portion; and a sub-gate electrode located on the extension portion of the sub-channel layer, connected to the main gate electrode, and including the same material as the main gate electrode.

In some implementations, the semiconductor devices of the present disclosure attempts have stable electrical characteristics and improved reliability compared to conventional semiconductor devices.

The drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification.

In the following detailed description, only certain exemplary embodiments of the present disclosure have been illustrated and described, simply by way of illustration. The present disclosure may be variously implemented and is not limited to the following exemplary embodiments.

In addition, the size and thickness of each configuration illustrated in the drawings are arbitrarily illustrated for understanding and ease of description, but the present disclosure is not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, for understanding and ease of description, the thickness of some layers and areas is exaggerated.

Further, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it may be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, when an element is “on” a reference portion, the element is located above or below the reference portion, and it does not necessarily mean that the element is located “above” or “on” in a direction opposite to gravity.

In addition, unless explicitly described to the contrary, the word “comprise”, and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

Further, in the entire specification, when it is referred to as “on a plan view”, it means when a target part is viewed from above, and when it is referred to as “in a cross-sectional view”, it means when the cross-section obtained by cutting a target part vertically is viewed from the side.

1 FIG. is a circuit diagram illustrating an example of a semiconductor device.

1 FIG. 100 320 First, as illustrated in, a semiconductor device includes a main device region MA including a main transistorand a peripheral circuit region PA including a sub-transistor.

100 100 100 100 The main transistormay be located within the main device region MA. For example, the main transistorof the semiconductor device may be a normally off high electron mobility transistor (HEMT). However, the present disclosure is not limited thereto, and the main transistorof the semiconductor device may be a normally on high electron mobility transistor. That is, in this example, the main device region MA may refer to the region where the main transistoris disposed.

100 100 100 190 100 170 100 190 100 170 100 100 320 3 FIG. 3 FIG. 3 FIG. 3 FIG. In this example, the main transistormay include a gate electrode G, a first electrode D, and a second electrode S. The main transistormay control the drain-to-source current between the first electrode D and the second electrode S according to a gate signal applied to the gate electrode G. For example, when a turn-on signal is applied to the gate electrode G of the main transistor, current may flow from the first electrode D to the second electrode S. The first electrode D may be supplied with a first supply voltage VD, and the second electrode S may be supplied with a second supply voltage Vs. The magnitude of the second supply voltage Vs may be smaller than the magnitude of the first supply voltage VD. For example, the second supply voltage Vs may be a ground voltage. Here, the first electrode D may refer to a drain electrode (in) of the main transistor, and the second electrode S may refer to a source electrode (in) of the main transistor. Further, the first supply voltage Vp may mean a voltage supplied to the drain electrode (in) of the main transistor. The second supply voltage Vs may mean a voltage supplied to the source electrode (in) of the main transistor. In the implementations illustrated herein, the phrases “source electrode” and “drain electrode” may be understood to mean a source terminal region and a drain terminal region, respectively, of either of the main transistorand sub-transistor.

100 310 310 100 100 100 100 3 FIG. The main transistormay include a field dispersion layer. The field dispersion layermay be located between the gate electrode G and the first electrode D of the main transistorand may serve to dissipate an electric field that is concentrated around the gate electrode G of the main transistor. Accordingly, the leakage current in the main transistormay be reduced, and the breakdown voltage of the main transistormay be increased. This will be described in more detail with reference tobelow.

100 320 100 320 100 310 310 100 100 320 100 320 The peripheral circuit region PA of the semiconductor device may include elements electrically connected to the main transistor. Specifically, the peripheral circuit region PA of the semiconductor device may include a sub-transistorelectrically connected to one end of the main transistor. In this example, the sub-transistormay serve to electrically isolate the second electrode S of the main transistorfrom the field dispersion layer, or to discharge charge within the field dispersion layerof the main transistorto the second electrode S of the main transistor. However, the present disclosure is not limited thereto, and the peripheral circuit region PA may further include passive elements, such as capacitors or inductors, in addition to the sub-transistor, or may further include active elements, such as integrated circuit (IC) chips. As another example, the peripheral circuit region PA may further include a current divider, a voltage divider, a voltage clipper, a protection element of the main transistor, and the like. In this example, the peripheral circuit region PA may refer to the region where the sub-transistoris disposed.

320 320 In this example, the sub-transistormay include a gate electrode Ga, a first electrode Da, and a second electrode Sa. The sub-transistormay control a drain-to-source current between the first electrode Da and the second electrode Sa according to a gate signal applied to the gate electrode Ga.

320 100 320 310 320 100 320 The sub-transistormay be electrically connected with one end of the main transistor. For example, the first electrode Da of the sub-transistormay be electrically connected to the field dispersion layer, and the second electrode Sa of the sub-transistormay be electrically connected to the second electrode S of the main transistor. The second electrode Sa of the sub-transistormay be electrically connected with a second power source supplying a second supply voltage Vs.

320 100 320 100 100 320 100 320 100 100 320 Further, the gate electrode Ga of the sub-transistormay be electrically connected with the gate electrode G of the main transistor. Accordingly, the same signal may be applied to the gate electrode Ga of the sub-transistorand the gate electrode G of the main transistor. For example, when a turn-on signal is applied to the gate electrode G of the main transistor, the same turn-on signal may be applied to the gate electrode Ga of the sub-transistor. Furthermore, when a turn-off signal is applied to the gate electrode G of the main transistor, the same turn-off signal may be applied to the gate electrode Ga of the sub-transistor. Thus, when the turn-on signal is applied to the gate electrode G of the main transistor, a current may flow from the first electrode D to the second electrode S of the main transistor, and a current may flow from the first electrode Da to the second electrode Sa of the sub-transistor.

320 310 320 320 170 100 320 155 320 320 160 100 3 FIG. 3 FIG. 3 FIG. 3 FIG. s Here, the first electrode Da of the sub-transistormay correspond to the field dispersion layer(in) of the sub-transistor, the second electrode Sa of the sub-transistormay correspond to the source electrode(in) of the main transistor, the gate electrode Ga of the sub-transistormay correspond to the sub-gate electrode(in) of the sub-transistor. The sub-transistormay be divided by a separation structure(in) and configured as a part of the main transistorlocated in the peripheral circuit region PA, but the present disclosure is not limited thereto.

2 FIG. Hereinafter, a method of operating a semiconductor device will be described with reference to.

2 FIG. 100 320 is a circuit diagram illustrating the semiconductor device when current flows, and the main transistorand the sub-transistorare turned on.

2 FIG. 100 100 320 100 320 310 320 100 320 310 310 100 100 310 310 100 Referring further to, in a first mode, the main transistoris turned off. Then, as described above, the gate electrode G of the main transistorand the gate electrode Ga of the sub-transistorare electrically connected, so that when the main transistoris turned off, the sub-transistormay also be turned off. Thus, the field dispersion layerconfiguring the first electrode Da of the sub-transistormay be electrically isolated from the second electrode S of the main transistorconfiguring the second electrode Sa of the sub-transistor. That is, the field dispersion layermay be floated. The field dispersion layermay serve to dissipate an electric field that is concentrated around the gate electrode G of the main transistor. On the other hand, when a high voltage is applied to the first electrode D of the main transistor, a charge may accumulate in the field dispersion layerby an electric field, leakage current, or the like. When enough charge accumulates in the field dispersion layer, the turn-on voltage of the main transistormay become unstable.

100 100 100 11 100 320 100 320 320 100 12 310 100 12 310 310 100 Then, in the second mode, a turn-on signal may be applied to the gate electrode G of the main transistorto turn the main transistoron. In this case, the current may flow from the first electrode D to the second electrode S of the main transistoralong a first path. On the other hand, as described above, the gate electrode G of the main transistorand the gate electrode Ga of the sub-transistorare electrically connected, so that when the main transistoris turned on, the sub-transistormay also be turned on. Accordingly, the current may flow from the first electrode Da to the second electrode Sa of the sub-transistortogether and may flow to the second electrode S of the main transistoralong a second path. Accordingly, a charge within the field dispersion layermay be discharged to the second electrode S of the main transistoralong the second path. Thus, the influence of the charge in the field dispersion layermay be eliminated, and the field dispersion layermay effectively dissipate the electric field concentrated around the gate electrode G of the main transistor, and the reliability of the semiconductor device may be improved.

3 FIG. 3 FIG. Hereinafter, an example of the semiconductor device will be described with reference to.is a top plan view illustrating the semiconductor device.

3 FIG. 100 320 100 Referring to, the peripheral circuit region PA of the semiconductor device is spaced apart from the main device region MA. For example, the peripheral circuit region PA may be spaced apart from the main device region MA in a second direction (Y direction), but the peripheral circuit region PA is not limited thereto. As another example, the peripheral circuit region PA may be spaced apart from the main device region MA in a first direction (X direction), or the peripheral circuit region PA may surround a lateral surface of the main device region MA. Various other modifications are of course possible. Within the main device region MA, the main transistormay be located, and the peripheral circuit region PA may include the sub-transistorthat is electrically connected to one end of the main transistor.

132 134 155 132 132 155 170 190 155 132 310 155 190 132 The semiconductor device may include a channel layerwith two-dimensional electron gas (2DEG)located therein, a gate electrodelocated above the channel layer, a gate semiconductor layer located between the channel layerand the gate electrode, a source electrodeand a drain electrodelocated on opposite sides of the gate electrodeabove the channel layer, and a field dispersion layerlocated between the gate electrodeand the drain electrodeabove the channel layer.

132 155 132 132 132 132 155 155 155 155 152 152 m s m s m s. In this example, the channel layer, the gate electrode, and the gate semiconductor layer may be located in the main device region MA and the peripheral circuit region PA. Hereinafter, for ease of description, the portion of the channel layerlocated in the main device region MA may be referred to as a main channel layerand the portion of the channel layerlocated in the peripheral circuit region PA may be referred to as a sub-channel layer. Further, the portion of the gate electrodelocated in the main device region MA may be referred to as a main gate electrode, and the portion of the gate electrodelocated in the peripheral circuit region PA may be referred to as a sub-gate electrode. Further, the portion of the gate semiconductor layer located in the main device region MA may be referred to as a main gate semiconductor layer, and the portion of the gate semiconductor layer located in the peripheral circuit region PA may be referred to as a sub-gate semiconductor layer

4 5 FIGS.and Hereinafter, the main transistor of the semiconductor device will be described with reference to.

4 5 FIGS.and 3 FIG. 4 FIG. 5 FIG. are cross-sectional views taken along lines A-A′ of.illustrates a case in which the semiconductor device is in an off state, andillustrates a case in which the semiconductor device is in an on state.

4 FIG. 100 132 155 132 152 132 155 170 190 132 310 132 155 190 m m m m m m m m m Referring further to, the main transistorof the semiconductor device includes the main channel layer, the main gate electrodelocated above the main channel layer, the main gate semiconductor layerlocated between the main channel layerand the main gate electrode, the source electrodeand the drain electrodespaced apart from each other on the main channel layer, and the field dispersion layerlocated above the main channel layerand located between the main gate electrodeand the drain electrode.

132 170 190 134 132 134 134 134 132 136 134 132 136 132 132 m m m m m The main channel layeris a layer that forms a channel between the source electrodeand the drain electrode, and the two dimensional electron gas (2DEG)may be located within the main channel layer. The two-dimensional electron gasis a charge transport model used in solid state physics and refers to a bunch of electrons that move freely in two dimensions (e.g., in the x-y plane direction), but cannot in one other dimension (e.g., in the z direction), and are tightly confined within two dimensions. In other words, the two-dimensional electron gasmay exist in a two-dimensional planar form within a three-dimensional space. Two-dimensional electron gasesare commonly found in semiconductor heterojunction structures and may be generated at the interface between a main channel layerand a barrier layerin a semiconductor device. For example, the two-dimensional electron gasmay be generated in a portion of the main channel layeradjacent to the barrier layer. In this example, the main channel layermay refer to a portion of channel layerlocated in the main device region MA.

132 132 132 132 132 132 m m m m m m x y 1-x-y The main channel layermay include one or more materials selected from group III-V materials, for example, nitrides including Al, Ga, In, B, or combinations thereof. The main channel layermay be a single layer or multiple layers. The main channel layermay be AlInGaN (0≤x≤1, 0≤y≤1, x+y≤1). For example, the main channel layermay include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. The main channel layermay be an impurity doped layer or an impurity undoped layer. The main channel layermay have a thickness of about a few hundred nm or less.

132 110 121 120 110 132 m m. The main channel layermay be located above the substrate, and a seed layerand a buffer layermay be located between the substrateand the main channel layer

110 121 120 132 132 110 121 120 110 132 132 110 121 120 110 132 120 110 121 120 m m m m m The substrate, the seed layer, and the buffer layerform the main channel layerand may be omitted in some cases. For example, when a substrate formed of GaN is used as the main channel layer, at least one of the substrate, the seed layer, and the buffer layermay be omitted. Considering that the substrate formed of GaN is relatively expensive, the substrateformed of Si may be used to grow the main channel layerincluding GaN. In this case, growing the main channel layerdirectly on the substratemay be difficult because the lattice structure of Si and the lattice structure of GaN are different. Accordingly, the seed layerand the buffer layermay be grown on the substratefirst, and then the main channel layermay be grown on the buffer layer. Additionally, at least one of the substrate, the seed layer, and the buffer layermay be removed from the final structure of the semiconductor device after it is used in the manufacturing process.

110 110 110 110 110 132 m The substratemay include a semiconductor material. For example, the substratemay include sapphire, Si, SiC, AlN, GaN, or combinations thereof. The substratemay also be a silicon on insulator (SOI) substrate. However, the material of the substrateis not limited to this, and any commonly used substrate may be applied. In some cases, the substratemay include an insulating material. For example, several layers, including the main channel layer, may be formed first on top of a semiconductor substrate, and then the semiconductor substrate may be removed and replaced with an insulating substrate.

121 110 110 121 121 120 120 120 121 121 120 121 121 121 x y 1-x-y The seed layermay be located directly on the substrate. However, the present disclosure is not limited thereto, and any other predetermined layers may be further located between the substrateand the seed layer. The seed layeris a layer that serves as a seed for growing the buffer layerand may be formed of a crystal lattice structure that serves as a seed for the buffer layer. The buffer layermay be located directly on the seed layer. However, the present disclosure is not limited thereto, and any other predetermined layer may be further located between the seed layerand the buffer layer. The seed layermay include one or more materials selected from group III-V materials, for example, nitrides including Al, Ga, In, B, or combinations thereof. The seed layermay be AlInGaN (0≤x≤1, 0≤y≤1, x+y≤1). For example, the seed layermay include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof.

120 121 120 121 132 120 121 132 132 120 120 120 m m m x y 1-x-y The buffer layermay be located on the seed layer. The buffer layermay be located between the seed layerand the main channel layer. The buffer layermay be a layer to mitigate differences in lattice constants and thermal expansion coefficients between the seed layerand the main channel layer, or to prevent leakage current from flowing through the main channel layer. The buffer layermay include one or more materials selected from group III-V materials, for example, nitrides including Al, Ga, In, B, or combinations thereof. The buffer layermay be AlInGaN (0≤x≤1, 0≤y≤1, x+y≤1). For example, the buffer layermay include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof.

120 124 121 126 124 124 126 110 The buffer layerof the semiconductor device may include a superlattice layerlocated on the seed layer, and a high-resistance layerlocated on the superlattice layer. The superlattice layerand the high-resistance layermay be sequentially located on the substrate.

124 121 124 121 121 124 124 110 132 110 132 124 124 124 m m x y 1-x-y The superlattice layermay be located on the seed layer. The superlattice layermay be located directly on the seed layer. However, the present disclosure is not limited thereto, and any other predetermined layer may be further located between the seed layerand the superlattice layer. The superlattice layeris a layer for mitigating differences in lattice constants and thermal expansion coefficients between the substrateand the main channel layer, and thus mitigating tensile stresses and compressive stresses generated between the substrateand the main channel layer, and mitigating stresses between all layers formed by growth in the final structure of the semiconductor device. The superlattice layermay include one or more materials selected from group III-V materials, for example, nitrides including Al, Ga, In, B, or combinations thereof. The superlattice layermay be AlInGaN (0≤x≤1, 0≤y≤1, x+y≤1). For example, the superlattice layermay include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof.

124 124 124 124 124 124 124 In this example, the superlattice layermay be formed of multiple layers in which layers including different materials are stacked alternately. For example, the superlattice layermay have the structure in which layers of AlGaN and layers of AlN are repeatedly stacked. That is, AlGaN/AlN/AlGaN/AlN/AlGaN/AlN may be stacked sequentially to form the superlattice layer. The number of AlGaN layers and GaN layers configuring the superlattice layermay be varied, and the material configuring the superlattice layermay be varied. As another example, the superlattice layermay have a structure in which layers of AlGaN and layers of GaN are repeatedly stacked. That is, AlGaN/GaN/AlGaN/GaN/AlGaN/GaN may be stacked sequentially to form the superlattice layer. In this example, where the superlattice layerincludes GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, or combinations thereof, the superlattice layermay have n-type semiconductor properties where the concentration of electrons is greater than the concentration of holes, but the present disclosure is not limited thereto.

126 124 126 124 124 126 126 124 132 126 132 126 110 132 126 126 126 m m m x y 1-x-y The high-resistance layermay be located on the superlattice layer. The high-resistance layermay be located directly on the superlattice layer. However, the present disclosure is not limited thereto, and any other predetermined layer may be further located between the superlattice layerand the high-resistance layer. The high-resistance layermay be located between the superlattice layerand the main channel layer. The high-resistance layeris a layer for preventing leakage current from flowing through the main channel layer, thereby preventing degradation of the semiconductor device. The high-resistance layermay be made of a low-conductivity material such that the substrateand the main channel layermay be electrically isolated. The high-resistance layer may include one or more materials selected from group III-V materials, for example, nitrides including Al, Ga, In, B, or combinations thereof. The high-resistance layermay be AlInGaN (0≤x≤1, 0≤y≤1, x+y≤1). For example, the high-resistance layermay include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The high-resistance layermay be a single layer or multiple layers.

136 132 m. The semiconductor device may further include a barrier layerlocated on the main channel layer

136 132 136 132 132 136 132 136 170 190 170 190 170 190 m m m m The barrier layermay be located on the main channel layer. The barrier layermay be located directly on the main channel layer. However, the present disclosure is not limited thereto, and any other predetermined layer may be further located between the main channel layerand the barrier layer. The area of the main channel layerthat overlaps the barrier layerbetween the source electrodeand the drain electrodemay be a main drift region DTRm. The main drift region DTRm may be located between the source electrodeand the drain electrode. The main drift region DTRm may refer to the region in which carriers migrate when a potential difference occurs between the source electrodeand the drain electrode.

155 155 m m The semiconductor device may be turned on/off depending on whether a voltage is applied to the main gate electrodeand/or the magnitude of the voltage applied to the main gate electrode, thereby enabling or blocking carrier mitigation in the main drift region DTRm.

136 136 136 136 136 136 136 136 x y 1-x-y The barrier layermay include one or more materials selected from group III-V materials, for example, nitrides including Al, Ga, In, B, or combinations thereof. The barrier layermay be AlInGaN (0≤x≤1, 0≤y≤1, x+y≤1). The barrier layermay include GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, or combinations thereof. An energy band gap of the barrier layermay be controlled by the composition ratio of Al and/or In. The barrier layermay be doped with a predetermined impurity. In this case, the impurities doped into the barrier layermay be p-type dopants that may provide holes. For example, the impurity doped in the barrier layermay be magnesium (Mg). By increasing or decreasing the impurity doping concentration of the barrier layer, the threshold voltage, on-resistance, and the like of the semiconductor device may be adjusted.

136 132 136 132 136 132 136 132 132 134 132 136 136 134 132 132 136 134 m m m m m m m m The barrier layermay include a semiconductor material having different properties from the main channel layer. The barrier layermay differ from the main channel layerin at least one of polarization characteristics, energy band gap, and lattice constant. For example, the barrier layermay include a material having a different energy band gap from the main channel layer. In this case, the barrier layermay have a higher energy band gap than the main channel layerand may have higher electrical polarizability than the main channel layer. The two-dimensional electron gasmay be induced in the main channel layerwith relatively low electrical polarizability by the barrier layer. In this respect, the barrier layermay also be referred to as a channel supply layer or a two-dimensional electron gas supply layer. The two-dimensional electron gasmay be formed within a portion of the main channel layerlocated below the interface between the main channel layerand the barrier layer. The two-dimensional electron gasmay have very high electron mobility.

136 136 136 132 m The barrier layermay be a single layer or multiple layers. When the barrier layeris multi-layered, the materials of each layer configuring the multi-layers may have different energy band gaps. In this case, the multiple layers configuring the barrier layermay be disposed such that the closer the layers are to the main channel layer, the larger the energy band gap.

155 136 155 136 155 132 155 170 190 155 170 190 155 170 190 155 170 155 190 155 155 132 m m m m m m m m m m m. The main gate electrodemay be located on the barrier layer. The main gate electrodemay overlap with a portion of the barrier layerin a third direction (Z direction). The main gate electrodemay overlap a portion of the main drift region DTRm of the main channel layerin the third direction (Z direction). The main gate electrodemay be located between the source electrodeand the drain electrode. The main gate electrodemay be spaced apart from the source electrodeand the drain electrode. For example, the main gate electrodemay be located closer to the source electrodethan the drain electrode. That is, the separation distance between the main gate electrodeand the source electrodemay be smaller than the separation distance between the main gate electrodeand the drain electrode, but the present disclosure is not limited thereto. In this example, the main gate electrodemay refer to a portion of the gate electrodelocated in the main device region MA. Here, the third direction (Z direction) may refer to the thickness direction of the main channel layer

155 155 155 155 m m m m The main gate electrodemay include a conductive material. For example, the main gate electrodemay include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal nitric oxide. For example, the main gate electrodemay include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbon nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbon nitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni—Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination thereof, but is not limited thereto. The main gate electrodemay be a single layer or multiple layers.

155 155 155 m m m In this example, the main gate electrodemay further include a hard mask layer located on the main gate electrode. The hard mask layer may be a hard mask that was used to pattern the gate electrode material layer and/or the gate semiconductor layer during the process of forming the main gate electrode. However, the hard mask layer may be removed during etching of the gate electrode material layer and/or the gate semiconductor layer based on etching conditions or post-etch cleaning conditions. In one example, the hard mask layer may include a silicon oxide, a silicon nitride, a silicon nitric oxide, or a combination thereof.

152 136 155 152 136 155 152 155 152 152 155 152 155 152 155 152 155 155 152 m m m m m m m m m m m m m m m m m. The main gate semiconductor layermay be located between the barrier layerand the main gate electrode. That is, the main gate semiconductor layermay be located on top of the barrier layer, and the main gate electrodemay be located on top of the main gate semiconductor layer. The main gate electrodemay be in Schottky contact or ohmic contact with the main gate semiconductor layer. The main gate semiconductor layermay overlap the main gate electrodein the third direction (Z direction). In this case, the main gate semiconductor layermay completely overlap the main gate electrodein the third direction (Z direction), and the main gate semiconductor layermay have a top surface entirely covered by the main gate electrode. In other words, the main gate semiconductor layermay have substantially the same planar shape as the main gate electrode. However, the present disclosure is not limited thereto, and the main gate electrodemay also be located to cover at least a portion of the main gate semiconductor layer

152 170 190 152 170 190 152 170 190 152 170 152 190 m m m m m The main gate semiconductor layermay be located between the source electrodeand the drain electrode. The main gate semiconductor layermay be spaced apart from the source electrodeand the drain electrode. The main gate semiconductor layermay be located closer to the source electrodethan the drain electrode. That is, the separation distance between the main gate semiconductor layerand the source electrodemay be smaller than the separation distance between the main gate semiconductor layerand the drain electrode, but the present disclosure is not limited thereto.

152 155 152 155 152 155 152 155 m m m m m m m m. In this example, the main gate semiconductor layermay overlap the main gate electrodein the third direction (Z direction). For example, the main gate semiconductor layermay fully overlap the main gate electrodein the third direction (Z direction). That is, a lateral surface of the main gate semiconductor layermay be aligned with a lateral surface of the main gate electrode. However, the present disclosure is not limited thereto, and the main gate semiconductor layermay partially overlap the main gate electrode

152 152 152 152 136 152 136 152 152 152 152 152 m m m m m m m m m m x y 1-x-y The main gate semiconductor layermay include one or more materials selected from group III-V materials, for example, nitrides including Al, Ga, In, B, or combinations thereof. The main gate semiconductor layermay be AlInGaN (0≤x≤1, 0≤y≤1, x+y≤1). For example, the main gate semiconductor layermay include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. The main gate semiconductor layermay include a material having a different energy band gap from the barrier layer. For example, the main gate semiconductor layermay include GaN, and the barrier layermay include AlGaN. The main gate semiconductor layermay be doped with a predetermined impurity. In this case, the impurities doped in the main gate semiconductor layermay be p-type dopants that may provide holes. For example, the main gate semiconductor layermay include GaN doped with p-type impurities. That is, the main gate semiconductor layermay include a p-GaN layer. However, the present disclosure is not limited thereto, and the main gate semiconductor layermay be a p-AlGaN layer.

132 152 152 136 136 136 152 132 152 132 134 134 170 190 m m m m m m m A depletion region DPR may be formed within the main channel layerby the main gate semiconductor layer. The depletion region DPR may be located within the main drift region DTRm and may have a narrower width than the main drift region DTRm. As the main gate semiconductor layerhaving a different energy band gap from the barrier layeris located on the barrier layer, the energy band level of the portion of the barrier layeroverlapping the main gate semiconductor layermay be increased. Accordingly, a depletion region DPR may be formed in a region of the main channel layeroverlapping the main gate semiconductor layer. The depletion region DPR may be a region in the channel path of the main channel layerwhere the two-dimensional electron gasis not formed or has a lower electron concentration than the rest of the region. In other words, the depletion region DPR may be a region where the flow of the two-dimensional electron gasis interrupted within the main drift region DTRm. As the depletion region DPR is generated, no current flows between the source electrodeand the drain electrode, and the channel path may be blocked. Accordingly, the semiconductor device may have a normally off characteristic.

4 FIG. 5 FIG. 155 155 134 134 170 190 134 134 170 190 134 155 134 170 190 134 170 190 m m m That is, the semiconductor device may be a normally off high electron mobility transistor (HEMT). As illustrated in, in the normal state with no voltage applied to the main gate electrode, the depletion region DPR is present and the semiconductor device may be in the off state. As illustrated in, when a voltage equal to or greater than a threshold voltage is applied to the main gate electrode, the depletion region DPR disappears, and the two-dimensional electron gaswithin the main drift region DTRm may continue without interruption. That is, the two-dimensional electron gasmay be formed throughout the channel path between the source electrodeand the drain electrode, and the semiconductor device may be in the on state. In summary, the semiconductor device may include semiconductor layers with different electrical polarization characteristics, and a semiconductor layer having relatively large polarizability may cause two-dimensional electron gasin other heterojunction semiconductor layers. The two-dimensional electron gasmay be utilized as a channel between the source electrodeand the drain electrode, and the continuation or interruption of the flow of the two-dimensional electron gasmay be controlled by a bias voltage applied to the main gate electrode. In the gate-off state, the flow of the two-dimensional electron gasis blocked, so that no current may flow between the source electrodeand the drain electrode. In the gate-on state, as the flow of the two-dimensional electron gascontinues, current may flow between the source electrodeand the drain electrode.

152 155 136 155 136 134 155 170 190 155 155 134 m m m m m m The semiconductor device has been described above as being a normally off high electron mobility transistor, but the present disclosure is not limited thereto. For example, the semiconductor device may be a normally on high electron mobility transistor. In the case of a normally on high electron mobility transistor, the main gate semiconductor layermay be omitted, and thus, the main gate electrodemay be located directly on the barrier layer. That is, the main gate electrodemay be in contact with the barrier layer. In the structure, the two-dimensional electron gasmay be utilized as a channel when no voltage is applied to the main gate electrode, and current flow may occur between the source electrodeand the drain electrode. Additionally, when a negative voltage is applied to the main gate electrode, the depletion region DPR may occur at the lower portion of the main gate electrodewhere the flow of the two-dimensional electron gasis interrupted.

121 124 126 132 136 152 110 121 124 126 132 136 152 121 124 126 132 136 152 m m m m m m The previously described seed layer, superlattice layer, high-resistance layer, main channel layer, barrier layer, and main gate semiconductor layermay be sequentially stacked on the substrate. At least one of the seed layer, the superlattice layer, the high-resistance layer, the main channel layer, the barrier layer, and the main gate semiconductor layermay be omitted in the semiconductor device. The seed layer, the superlattice layer, the high-resistance layer, the main channel layer, the barrier layer, and the main gate semiconductor layermay be made of the same base semiconductor material, and the material composition ratio of each layer may be different in consideration of the role of each layer, the performance required of the semiconductor device, and the like.

140 136 The semiconductor device may further include a first protective layerlocated on the barrier layer.

140 136 155 140 155 152 140 136 155 136 152 155 140 155 140 152 140 155 140 152 140 140 140 m m m m m m m m m m 2 2 3 The first protective layermay be located on the barrier layerand the main gate electrode. The first protective layermay cover the top surface and the lateral surface of the main gate electrodeand the lateral surface of the main gate semiconductor layer. A lower surface of the first protective layermay be in contact with the barrier layerand the main gate electrode. Accordingly, the barrier layer, the main gate semiconductor layer, and the main gate electrodemay be protected by the first protective layer. However, the present disclosure is not limited thereto, and the main gate electrodemay penetrate the first protective layerto be connected with the main gate semiconductor layer, and the first protective layermay not cover the top surface of the main gate electrode. Alternatively, the lower surface of the first protective layermay be in contact with the main gate semiconductor layer. The first protective layermay include an insulating material. For example, the first protective layermay include an oxide, such as SiOor AlO. As another example, the first protective layermay include a nitride, such as SiN, or an oxynitride, such as SiON.

4 5 FIGS.and 140 140 In, the first protective layeris illustrated as a single layer, but is not limited thereto, and the first protective layermay include multiple layers including different materials.

170 190 132 170 190 132 132 170 132 170 1 132 m m m s s 6 8 FIGS.to The source electrodeand the drain electrodemay be located on the main channel layer. The source electrodeand the drain electrodemay be in direct contact with the main channel layerand may be electrically connected to the main channel layer. Additionally, the source electrodemay be electrically connected to the sub-channel layer. For example, the source electrodemay be electrically connected to a first contact portion CPof the sub-channel layer. This will be described in more detail later with reference to.

170 190 170 190 155 152 170 190 155 152 170 190 170 132 155 190 132 155 170 190 132 170 132 190 132 190 190 m m m m m m m m m m m The source electrodeand the drain electrodemay extend in the second direction (Y direction). The source electrodeand the drain electrodemay be spaced apart from each other, and the main gate electrodeand the main gate semiconductor layermay be located between the source electrodeand the drain electrode. The main gate electrodeand the main gate semiconductor layermay be spaced apart from the source electrodeand the drain electrode. For example, the source electrodemay be electrically connected to the main channel layeron one side of the main gate electrode, and the drain electrodemay be electrically connected to the main channel layeron the other side of the main gate electrode. The source electrodeand the drain electrodemay be located on the outer side of the main drift region DTRm of the main channel layer. A boundary between the source electrodeand the main channel layermay be one edge of the main drift region DTRm. Similarly, the boundary between the drain electrodeand the main channel layermay be the other edge of the main drift region DTRm. In this example, the drain electrodemay refer to a portion of the drain electrodelocated in the main device region MA.

132 170 190 132 170 190 132 132 170 190 134 132 134 170 190 170 190 134 132 136 m m m m m m However, the present disclosure is not limited thereto, and the main channel layermay not be recessed, and the source electrodeand the drain electrodemay be located on the top surface of the main channel layer. In this case, the bottom surfaces of the source electrodeand the drain electrodemay in contact with the top surface of the main channel layer. The portion of the main channel layerthat is in contact with the source electrodeand the drain electrodemay be doped at a high concentration. In this case, carriers passing through the two-dimensional electron gasmay pass through the portion of the main channel layerthat is doped at a high concentration, that is, the upper portion of the two-dimensional electron gas, and delivered to the source electrodeand the drain electrode. The source electrodeand the drain electrodemay not be in direct contact with the two-dimensional electron gasin a horizontal direction. Here, a horizontal direction may mean a direction parallel to the top surface of the main channel layeror the barrier layer.

140 136 132 155 170 190 155 170 190 170 190 132 136 132 136 170 190 132 170 190 136 170 190 132 136 m m m m m m m Specifically, trenches penetrating the first protective layerand the barrier layerand recessing the top surface of the main channel layermay be spaced apart from each other on opposite sides of the main gate electrode. The source electrodeand the drain electrodemay be respectively located within the trenches located on opposite sides of the main gate electrode. The source electrodeand the drain electrodemay be formed to be filled within the trenches. Within the trench, the source electrodeand the drain electrodemay be in contact with the main channel layerand the barrier layer. The main channel layermay form the bottom surface and the lateral wall of the trench, and the barrier layermay form the lateral wall of the trench. Thus, the source electrodeand the drain electrodemay be in contact with the top surface and the lateral surface of the main channel layer. Further, the source electrodeand the drain electrodemay be in contact with the lateral surface of the barrier layer. That is, the source electrodeand the drain electrodemay cover the lateral surfaces of the main channel layerand the barrier layer.

170 190 140 170 190 140 170 190 140 170 190 140 170 190 140 140 140 170 190 In this example, the source electrodeand the drain electrodemay cover at least a portion of the lateral surface of the first protective layer. For example, the source electrodeand the drain electrodemay cover the lateral surface of the first protective layer. The top surfaces of the source electrodeand the drain electrodemay protrude above the top surface of the first protective layer. Further, at least one of the source electrodeand the drain electrodemay cover at least a portion of the top surface of the first protective layer. However, the present disclosure is not limited thereto, and the source electrodeand the drain electrodemay cover at least a portion of the lateral surface of the first protective layerand may not cover the remaining portion of the lateral surface of the first protective layer. In this case, the remaining portion of the first protective layermay be located on the top surface of the source electrodeand the drain electrode.

170 190 170 190 170 190 170 190 170 190 132 132 170 190 m m The source electrodeand the drain electrodemay include a conductive material. For example, the source electrodeand the drain electrodemay include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal nitric oxide. For example, the source electrodeand the drain electrodemay include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbon nitride (TiAlC—N), titanium aluminum carbide (TiAlC), titanium carbide (TIC), tantalum carbon nitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni—Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination thereof, but is not limited thereto. The source electrodeand the drain electrodemay be a single layer or multiple layers. The source electrodeand the drain electrodemay be in ohmic contact with the main channel layer. Within the main channel layer, the regions in contact with the source electrodeand the drain electrodemay be doped at relatively high concentrations compared to other regions.

4 5 FIGS.and 9 FIG. 170 190 170 190 170 132 190 132 m m illustrate the semiconductor device as including a pair of source electrodeand drain electrode, but the number of source electrodesand drain electrodesis not limited thereto. For example, the source electrodemay include a plurality of source electrodes stacked sequentially in the third direction (Z-direction) on the main channel layer, and the drain electrodemay include a plurality of drain electrodes stacked sequentially in the third direction (Z-direction) on the main channel layer. These will be described hereinafter with reference to.

310 155 190 310 170 190 310 140 310 132 310 160 132 310 155 170 190 m m s m The field dispersion layermay be located between the main gate electrodeand the drain electrode. The field dispersion layermay be located between the source electrodeand the drain electrode. The field dispersion layermay be located on the first protective layer. The field dispersion layermay overlap the main channel layerin the third direction (Z direction). Further, the field dispersion layermay overlap at least a portion of a separation structureand the sub-channel layerin the third direction (Z direction), which will be described later, but is not limited thereto. The field dispersion layermay not overlap, e.g., is spaced apart from, the main gate electrode, the source electrode, and the drain electrodein the third direction (z-direction), but is not limited thereto.

310 170 310 170 310 170 310 132 320 310 2 132 310 170 132 320 310 170 320 310 170 s s s 6 8 FIGS.to The field dispersion layermay be spaced apart from the source electrode. The field dispersion layermay extend, e.g., is elongated, in the same direction as the source electrode. For example, the field dispersion layerand the source electrodemay extend in the second direction (Y direction), but are not limited thereto. The field dispersion layermay be electrically connected to the sub-channel layerof the sub-transistor, which will be described later. For example, the field dispersion layermay be directly connected to a second contact portion CPof the sub-channel layer, which will be described later. Accordingly, the field dispersion layermay be electrically connected to the source electrodevia the sub-channel layer, which will be described later. Specifically, when the sub-transistoris turned on, the field dispersion layermay be electrically connected to the source electrode. When the sub-transistoris turned off, the field dispersion layermay be electrically isolated from the source electrodeand may be floated. These will be described hereinafter with reference to.

310 132 s 10 FIG. In some implementations, the field dispersion layermay be connected to the sub-channel layervia a separate contact electrode. These will be described hereinafter with reference to.

310 170 310 170 170 140 310 310 170 310 170 The field dispersion layermay include the same material as the source electrode. The field dispersion layermay be located in the same layer as at least a portion of the source electrode. For example, the portion of the source electrodethat is located on the first protective layermay be located in the same layer as the field dispersion layer. The field dispersion layermay be formed simultaneously in the same process as the source electrode. However, the present disclosure is not limited thereto, and the field dispersion layermay be located in a different layer than the source electrodeand may be formed in a different process.

310 155 132 155 170 132 155 190 134 155 152 155 152 100 155 152 310 320 310 310 310 320 310 170 320 310 m m m m m m m m m m m The field dispersion layermay serve to dissipate the electric field concentrated around the main gate electrode. Specifically, in the gate-off state, a portion of the main channel layerlocated between the main gate electrodeand the source electrodeand a portion of the main channel layerlocated between the main gate electrodeand the drain electrodemay have a very high concentration of two-dimensional electron gas. In this case, an electric field may be concentrated on the main gate electrodeor the main gate semiconductor layer. On the other hand, the main gate electrodeand the main gate semiconductor layerare vulnerable to electric fields, which may increase the leakage current and decrease the breakdown voltage of the main transistorwhen the electric field is concentrated. In this case, the electric field concentrated around the main gate electrodeor the main gate semiconductor layerby the field dispersion layermay be dissipated, so that the leakage current may be reduced, and the breakdown voltage may be increased. On the other hand, as described above, when the sub-transistoris turned off, the field dispersion layeris being floated, so that charges may accumulate within the field dispersion layerby the electric field around the field dispersion layer. When the sub-transistoris turned on, the field dispersion layeris electrically connected to the source electrodevia the sub-transistor, such that the charge accumulated within the field dispersion layermay be discharged.

4 5 FIGS.and 18 FIG. 310 310 310 140 140 illustrate the semiconductor device as including one field dispersion layer, but the number of field dispersion layersis not limited thereto. For example, the field dispersion layermay include a plurality of field dispersion layers located on the first protective layer. As another example, a plurality of protective layers may be located on the first protective layerand may include a plurality of field dispersion layers located on different protective layers. This will be described later with reference to.

180 310 140 The semiconductor device may further include a second protective layerlocated on the field dispersion layerand the first protective layer.

180 140 310 170 190 180 141 143 170 190 170 190 141 143 180 180 140 180 180 2 2 3 The second protective layermay cover the top surface of the first protective layer, the top surface and the lateral surface of the field dispersion layer, and the top surfaces of the source electrodeand the drain electrode. The second protective layermay include trenchesandthat expose the source electrodeand the drain electrode. The source electrodeand the drain electrodemay be electrically connected to the wires by the trenchesand, respectively. The second protective layermay include an insulating material. The second protective layermay include the same material as the first protective layer, but is not limited thereto. For example, the second protective layermay include an oxide, such as SiOor AlO. As another example, the second protective layermay include a nitride, such as SiN, or an oxynitride, such as SiON.

3 FIG. 6 8 FIGS.to Hereinafter, a peripheral circuit element of the semiconductor device will be described with reference toand.

6 FIG. 3 FIG. 7 FIG. 3 FIG. 8 FIG. 3 FIG. is a cross-sectional view taken along line B-B′ of.is a cross-sectional view taken along line C-C′ of.is a cross-sectional view taken along line D-D′ of.

3 FIG. 6 8 FIGS.to 320 100 Referring toand, the semiconductor device includes the sub-transistorconnected to one end of the main transistor.

320 132 170 310 155 132 155 132 320 310 320 170 320 155 320 s s s m s s 1 FIG. 1 FIG. 1 FIG. The sub-transistorof the semiconductor device may include a sub-drift region DTRs with two-dimensional electron gas, with the sub-channel layerconnected with the source electrodeand the field dispersion layer. The sub-gate electrodeis located above the sub-channel layerand connected with the main gate electrode. In this example, the sub-channel layermay configure a channel of the sub-transistor, the field dispersion layermay configure the first electrode (Da in) of the sub-transistor, the source electrodemay configure the second electrode (Sa in) of the sub-transistor, and the sub-gate electrodemay configure the gate electrode (Ga in) of the sub-transistor.

132 110 132 170 310 134 132 134 132 136 134 132 136 132 132 320 s s s s s s The sub-channel layermay be located above the substrate. The sub-channel layeris a layer that forms a channel between the source electrodeand the field dispersion layer, and two dimensional electron gas (2DEG)may be located inside the sub-channel layer. The two-dimensional electron gasmay be generated at the interface between the sub-channel layerand the barrier layerin the semiconductor device. For example, the two-dimensional electron gasmay be generated in a portion inside the sub-channel layeradjacent to the barrier layer. In this example, the sub-channel layermay refer to a portion of channel layerthat is located in the peripheral circuit region PA and configures the channel of the sub-transistor.

132 132 132 132 132 170 132 310 132 132 170 310 132 170 310 s m s m s s s s s 17 FIG. In this example, the sub-channel layermay be located on one side of the main channel layer. For example, the sub-channel layermay be located on one side along the second direction (Y direction) of the main channel layer, but is not limited thereto. One end of the sub-channel layermay be connected to the source electrodeand the other end of the sub-channel layermay be connected to the field dispersion layer. The sub-channel layermay have various shapes in a planar view. For example, the sub-channel layermay include a portion extending in the second direction (Y direction) to be connected with the source electrode, a portion extending in the second direction (Y direction) to be connected with the field dispersion layer, and a portion extending in the first direction (X direction). However, the present disclosure is not limited thereto, and the shape of the sub-channel layermay be varied within the extent of the connection between the source electrodeand the field dispersion layer. These will be described hereinafter with reference to.

132 132 100 132 132 132 132 132 132 132 110 132 110 132 132 110 132 132 132 132 160 s m s m s m s m s m s m s m s m In this example, the sub-channel layermay be integrally formed by the same process as the main channel layerof the main transistor. The sub-channel layermay be located on the same layer as the main channel layer. A lower surface of the sub-channel layermay be located at the same level as a lower surface of the main channel layer, and a top surface of the sub-channel layermay be located at the same level as a top surface of the main channel layer. In other words, the distance between lower surface of the sub-channel layerand the top surface of the substratemay be the same as the distance between the lower surface of the main channel layerand the top surface of the substrate. Further, the top surface of the sub-channel layermay be located at the same distance from the top surface of the main channel layerand the top surface of the substrate. The thickness along the third direction (Z direction) of the sub-channel layermay be substantially the same as the thickness along the third direction (Z direction) of the main channel layer, but is not limited thereto. In this case, the sub-channel layerand the main channel layermay be separated by a separation structure, which will be described later.

132 132 132 s m s In this example, the sub-channel layermay include the same material as the main channel layer. In one example, the sub-channel layermay include one or more materials selected from group III-V materials, for example, nitrides including Al, Ga, In, B, or combinations thereof.

132 1 170 2 310 1 2 s The sub-channel layerof the semiconductor device may include the first contact portion CPconnected with the source electrode, the second contact portion CPconnected with the field dispersion layer, and an extension portion EP connecting the first contact portion CPand the second contact portion CP.

1 170 1 170 170 140 136 1 170 1 170 136 132 1 170 1 170 132 1 132 170 6 FIG. s s s The first contact portion CPmay be connected to the source electrode. The first contact portion CPmay be in contact with the source electrode. For example, as illustrated in, the source electrodemay penetrate the first protective layerand the barrier layerto be electrically connected with the first contact portion CP. In this case, the source electrodemay be located within the recessed space of the first contact portion CP. The source electrodemay penetrate the barrier layerto be in contact with the lateral surface of the sub-channel layer. As another example, the first contact portion CPmay not be recessed, and the source electrodemay be located on the top surface of the first contact portion CP. The boundary between the source electrodeand the sub-channel layermay be one edge of the sub-drift region DTRs. The first contact portion CPmay refer to the portion of the sub-channel layerto which the source electrodeis connected.

2 310 2 310 310 2 140 136 310 2 310 136 132 2 310 2 310 132 2 132 310 310 132 132 6 7 FIGS.and s s s m s The second contact portion CPmay be connected to the field dispersion layer. The second contact portion CPmay be in contact with the field dispersion layer. For example, as illustrated in, the field dispersion layermay be electrically connected to the second contact portion CPthrough the first protective layerand the barrier layer. In this case, the field dispersion layermay be located within the recessed space of the second contact portion CP. The field dispersion layermay penetrate the barrier layerto be in contact with the lateral surface of the sub-channel layer. However, the present disclosure is not limited thereto, and for example, the second contact portion CPmay not be recessed and the field dispersion layermay be located on the top surface of the second contact portion CP. The boundary between the field dispersion layerand the sub-channel layermay be the other edge of the sub-drift region DTRs. The second contact portion CPmay refer to the portion of the sub-channel layerto which the field dispersion layeris connected. Accordingly, the field dispersion layermay overlap the main channel layerin the third direction (Z direction), and may overlap at least a portion of the sub-channel layerin the third direction (Z direction).

1 2 1 2 1 310 170 310 3 FIG. The extension portion EP may be located between the first contact portion CPand the second contact portion CP. The extension portion EP may connect the first contact portion CPand the second contact portion CP. The extension portion EP may have various shapes in a planar view. For example, as illustrated in, the extension portion EP may include a portion extending in the second direction (Y direction) to be connected with the first contact portion CP, a portion extending in the second direction (Y direction) to be connected with the field dispersion layer, and a portion extending in the first direction (X direction). However, the present disclosure is not limited thereto, and the shape of the extension portion EP may be varied within the extent of the connection between the source electrodeand the field dispersion layer.

121 120 110 132 110 121 120 132 110 121 120 110 121 120 s s In this example, the seed layerand the buffer layermay be located between the substrateand the sub-channel layer. The substrate, the seed layer, and the buffer layerare layers that are required to form the sub-channel layerand may be omitted in some cases. In this example, the substrate, the seed layer, and the buffer layerlocated in the peripheral circuit region PA may be integrally formed by the same process as the substrate, the seed layer, and the buffer layerlocated in the main device region MA, respectively.

136 132 136 132 136 132 132 136 132 136 136 132 134 132 136 s s s s s s s The barrier layerof the semiconductor device may be located further above the sub-channel layer. That is, the barrier layermay extend further above the sub-channel layer. The barrier layermay be located directly on the sub-channel layer. However, the present disclosure is not limited thereto, and any other predetermined layer may be further located between the sub-channel layerand the barrier layer. The region of the sub-channel layerthat overlaps the barrier layermay be a drift region. Specifically, as the barrier layerdiffers from the sub-channel layerin at least one of polarization characteristics, energy band gap, and lattice constant, the two-dimensional electron gasmay be induced in the sub-channel layerthat has relatively low electrical polarizability by the barrier layer.

6 7 FIGS.and 132 310 170 132 132 170 310 132 136 310 170 170 132 310 132 132 170 310 s s s s s s s As illustrated in, in the peripheral circuit region PA, the sub-channel layermay include the sub-drift region DTRs between the field dispersion layerand the source electrode. That is, the sub-drift region DTRs may refer to a region of the sub-channel layerfrom one side of the sub-channel layerthat is in contact with the source electrodeto the field dispersion layer. The sub-drift region DTRs may refer to regions of the sub-channel layerthat overlap the barrier layerbetween the field dispersion layerand the source electrode. For example, the boundary where the source electrodeand the sub-channel layermeet may be one edge of the sub-drift region DTRs, and the boundary where the field dispersion layerand the sub-channel layermeet may be the other edge of the sub-drift region DTRs. In other words, the sub-drift region DTRs may refer to a region of carrier migration between one side of the sub-channel layerthat is in contact with the source electrodeand the field dispersion layerwithin the peripheral circuit region PA.

155 155 132 155 132 155 132 155 155 155 132 s s s s s s s s s The sub-gate electrodemay be located in the peripheral circuit region PA. The sub-gate electrodemay be located above the extension portion EP of the sub-channel layer. For example, the sub-gate electrodemay overlap the extension portion EP of the sub-channel layerin the third direction (Z-direction). That is, the sub-gate electrodemay overlap a portion of the sub-drift region DTRs of the sub-channel layerin the third direction (Z-direction). In this example, the sub-gate electrodemay refer to a portion of the gate electrodelocated in the peripheral circuit region PA. Accordingly, the gate electrodemay overlap the extension portion EP of the sub-channel layerin the third direction (Z direction).

155 136 155 155 s s m. The sub-gate electrodemay be located above the barrier layer. The sub-gate electrodemay be electrically connected to the main gate electrode

155 310 170 132 155 1 132 170 2 310 155 310 170 155 310 170 155 310 155 170 s s s s s s s s The sub-gate electrodemay be located between the field dispersion layerand the source electrodeon the sub-channel layer. That is, the sub-gate electrodemay be located between the first contact portion CPof the sub-channel layerto which the source electrodeis connected and the second contact portion CPto which the field dispersion layeris connected. The sub-gate electrodemay be spaced apart from the field dispersion layerand the source electrode. The sub-gate electrodemay be located closer to the field dispersion layerthan the source electrode, but is not limited thereto. That is, the separation distance between the sub-gate electrodeand the field dispersion layermay be smaller than the separation distance between the sub-gate electrodeand the source electrode, but the present disclosure is not limited thereto.

155 155 100 155 155 100 155 155 155 155 155 155 110 155 110 155 155 155 s m s m s m s m s m s m s m 8 FIG. In this example, the sub-gate electrodemay be integrally formed with the main gate electrodeof the main transistor. That is, the sub-gate electrodemay be integrally formed by the same process as the main gate electrodeof the main transistor. For example, as illustrated in, the sub-gate electrodemay be located on the same layer as the main gate electrode. A lower surface of the sub-gate electrodemay be located at the same level as a lower surface of the main gate electrode, and a top surface of the sub-gate electrodemay be located at the same level as a top surface of the main gate electrode. In other words, the distance between the top surface of the substrateand the lower surface of the sub-gate electrodemay be the same distance as between the top surface of the substrateand the lower surface of the main gate electrode. The thickness along the third direction (Z direction) of the sub-gate electrodemay be substantially the same as the thickness along the third direction (Z direction) of the main gate electrode, but is not limited thereto.

155 155 155 155 s m s m However, the present disclosure is not limited thereto, and in some implementations, the sub-gate electrodemay not be integrally formed with the main gate electrode. However, even in this case, the sub-gate electrodemay be electrically connected to the main gate electrodevia upper wires or the like.

155 155 155 155 155 s s m s m. The sub-gate electrodemay include a conductive material. The sub-gate electrodemay include the same material as the main gate electrode. However, the present disclosure is not limited thereto, and the sub-gate electrodemay include a different material from the main gate electrode

155 155 s s In some implementations, a hard mask layer located on the sub-gate electrodemay be further included. The hard mask layer may be a hard mask that was used to pattern the gate electrode material layer and/or the gate semiconductor layer during the process of forming the sub-gate electrode. However, the hard mask layer may be removed during etching of the gate electrode material layer and/or the gate semiconductor layer based on etching conditions or post-etch cleaning conditions. In one example, the hard mask layer may include a silicon oxide, a silicon nitride, a silicon nitric oxide, or a combination thereof.

152 136 155 152 155 152 155 152 160 155 152 152 155 152 155 152 136 155 155 136 s s s s s s s s s s s m m s s s The sub-gate semiconductor layermay be located between the barrier layerand the sub-gate electrode. The sub-gate semiconductor layermay overlap the sub-gate electrodein the third direction (Z direction). In one example, the sub-gate semiconductor layermay fully overlap the sub-gate electrodein the third direction (Z-direction), but is not limited thereto. Further, the sub-gate semiconductor layermay overlap the separation structurein the third direction (Z-direction), but not limited thereto. The sub-gate electrodemay be in Schottky contact or ohmic contact with the sub-gate semiconductor layer. The structural shape of the sub-gate semiconductor layerand the sub-gate electrodemay be substantially the same as the structural shape of the main gate semiconductor layerand the main gate electrode. However, the present disclosure is not limited thereto. In some implementations, the sub-gate semiconductor layermay not be located between the barrier layerand the sub-gate electrode. In this case, the lower surface of the sub-gate electrodemay be in contact with the barrier layer.

152 310 170 132 152 132 152 1 132 170 2 310 152 310 170 s s s s s s s In this example, the sub-gate semiconductor layermay be located between the field dispersion layerand the source electrodeabove the sub-channel layer. The sub-gate semiconductor layermay be located above the extension portion EP of the sub-channel layer. That is, the sub-gate semiconductor layermay be located between the first contact portion CPof the sub-channel layerto which the source electrodeis connected and the second contact portion CPto which the field dispersion layeris connected. The sub-gate semiconductor layermay be spaced apart from the field dispersion layerand the source electrode.

152 152 100 152 152 100 152 152 152 152 152 152 110 152 110 152 152 152 s m s m s m s m s m s m s m 8 FIG. In this example, the sub-gate semiconductor layermay be integrally formed with the main gate semiconductor layerof the main transistor. That is, the sub-gate semiconductor layermay be integrally formed with the main gate semiconductor layerof the main transistorby the same process. For example, as illustrated in, the sub-gate semiconductor layermay be located on the same layer as the main gate semiconductor layer. A lower surface of the sub-gate semiconductor layermay be located at the same level as a lower surface of the main gate semiconductor layer, and a top surface of the sub-gate semiconductor layermay be located at the same level as a top surface of the main gate semiconductor layer. In other words, the distance between the top surface of the substrateand lower surface of the sub-gate semiconductor layermay be the same distance as between the top surface of the substrateand the lower surface of the main gate semiconductor layer. The thickness along the third direction (Z direction) of the sub-gate semiconductor layermay be substantially the same as the thickness along the third direction (Z direction) of the main gate semiconductor layer, but is not limited thereto.

152 152 s m 11 FIG. In some implementations, the sub-gate semiconductor layermay be spaced apart from the main gate semiconductor layer. These will be described hereinafter with reference to.

152 152 152 152 152 s s m s m. The sub-gate semiconductor layermay include a conductive material. The sub-gate semiconductor layermay include the same material as the main gate semiconductor layer. However, the present disclosure is not limited thereto, and the sub-gate semiconductor layermay include a different material from the main gate semiconductor layer

132 152 134 310 170 s s The depletion region DPR may be formed in the sub-channel layerby the sub-gate semiconductor layer. The depletion regions DPRs may be located within the sub-drift region DTRs. In other words, the depletion region DPR may be a region where the flow of the two-dimensional electron gasis interrupted within the sub-drift region DTRs. As the depletion region DPR is generated, no current flows between the field dispersion layerand the source electrode, and the channel path may be blocked.

320 132 155 170 310 132 155 320 310 170 s s s s In summary, the sub-transistorof the semiconductor device may include the sub-channel layer, the sub-gate electrode, the source electrode, and the field dispersion layer. Within the sub-channel layer, the sub-drift region DTRs and depletion regions DPRs may be formed. In response to a signal from the sub-gate electrode, the sub-transistormay be turned on, thereby controlling the current flowing between the field dispersion layerand the source electrode.

155 155 155 155 320 310 320 170 320 310 310 155 100 310 310 190 155 s m m s m m 1 FIG. 1 FIG. Specifically, the sub-gate electrodemay be electrically connected to the main gate electrode. Accordingly, when a turn-off signal is applied to the main gate electrode, a turn-off signal may also be applied to the sub-gate electrode, and the sub-transistormay be turned off. Accordingly, the field dispersion layerconfiguring the first electrode (Da in) of the sub-transistormay be electrically isolated from the source electrodeconfiguring the second electrode (Sa in) of the sub-transistor. That is, the field dispersion layermay be floated, and the field dispersion layermay play a role to dissipate the electric field concentrated around the main gate electrodeof the main transistor. At this time, charges may accumulate within the field dispersion layerby a voltage-induced electric field, leakage current, or the like. When charges accumulate in the field dispersion layer, the voltage of the drain electrodeand the main gate electrodemay become unstable.

155 155 320 310 170 310 170 310 310 155 100 m s m On the other hand, when a turn-on signal is applied to the main gate electrode, a turn-on signal may be applied to the sub-gate electrodetogether, and the sub-transistormay be turned on. Accordingly, current may flow from the field dispersion layerto the source electrode, and the charge accumulated within the field dispersion layermay be discharged through the source electrode. Thus, the influence of the accumulated charge in the field dispersion layermay be eliminated, and the field dispersion layermay effectively dissipate the electric field concentrated around the main gate electrodeof the main transistor, and the reliability of the semiconductor device may be improved.

140 180 140 180 132 160 140 136 155 132 180 140 s s s The first protective layerand the second protective layerof the semiconductor device may be further located in the peripheral circuit region PA. That is, the first protective layerand the second protective layermay extend further above the sub-channel layerand the separation structure, which will be described later. Accordingly, the first protective layermay cover the barrier layerand the sub-gate electrodelocated above the sub-channel layer, and the second protective layermay cover the first protective layer.

160 320 100 The semiconductor device may further include the separation structurelocated between the sub-transistorand the main transistor.

320 100 160 100 320 160 3 FIG. In this example, the sub-transistormay be separated from the main transistorby the separation structure. For example, as illustrated in, the main transistorand the sub-transistormay be spaced apart in the second direction (Y direction) by the separation structure, but the relative locations are not limited thereto.

160 136 160 136 132 121 120 110 160 152 152 132 132 160 136 132 120 160 136 132 132 136 100 320 132 136 136 132 160 152 152 136 152 152 152 152 136 132 120 160 132 160 136 132 132 136 160 140 180 160 160 160 140 132 132 6 8 FIGS.to m s s m m s m s m s m s m s m s 2 2 3 In this example, the separation structuremay penetrate the barrier layer. For example, as illustrated in, the separation structuremay penetrate the barrier layer, the channel layer, the seed layer, and the buffer layerto recess at least a portion of the substrate. The separation structuremay be located between the main gate semiconductor layerand the sub-gate semiconductor layer, but is not limited thereto. Accordingly, the sub-drift region DTRs of the sub-channel layermay be electrically isolated from the main drift region DTRm of the main channel layer. As another example, the present disclosure is not limited thereto, and the separation structuremay penetrate the barrier layerand the channel layerand recess at least a portion of the buffer layer. In this example, the separation structuremay be formed by forming the barrier layeron top of the main channel layerand the sub-channel layer, and performing an ion implant process within the barrier layerthat is located between the main transistorand the sub-transistor. For example, no or very little two-dimensional electron gas may be formed in the region of the channel layerthat overlaps the region where the ion implantation process was performed in the barrier layerin the third direction (Z direction). In this case, the ion implanted region of the barrier layerand the region of the channel layercorresponding to the ion implanted region may correspond to the separation structure. As another example, gate semiconductor layersandmay be formed on top of barrier layer, and after performing the ion implantation process on top of gate semiconductor layersand, the gate semiconductor layersandmay be patterned. Accordingly, the exposed barrier layer, the channel layer, and the ion implanted region of the buffer layermay correspond to the separation structure. The region of the channel layerwhere the ion implantation process was performed may have no or very little two-dimensional electron gas formed. The material used in the ion implantation process may be argon (Ar) ions. However, the present disclosure is not limited thereto, and the separation structuremay also be formed by forming the barrier layeron the main channel layerand the sub-channel layer, forming a trench through the barrier layer, and then filling the trench with an insulating material. The insulating material configuring the separation structuremay include the same material as the first protective layerand/or the second protective layer. For example, the insulating material configuring the separation structuremay include an oxide, such as SiOor AlO. As another example, the insulating material configuring the separation structuremay include a nitride, such as SiN, or an oxynitride, such as SiON. However, the present disclosure is not limited thereto, and the insulating material configuring the separation structuremay also include a different material from the first protective layer. In this case, at least a portion of the main channel layerand/or the sub-channel layermay be recessed together.

9 17 FIGS.to Hereinafter, an example of a resistive element of a semiconductor device will be described with reference to.

9 FIG. 17 FIG. toare top plan views illustrating semiconductor devices.

9 17 FIGS.to 1 8 FIGS.to 9 17 FIGS.to 1 8 FIGS.to illustrate various modified examples of the semiconductor device illustrated in. Since some parts of the examples illustrated inare substantially the same as those of the examples illustrated in, a description thereof will be omitted, and the differences will be mainly described. Also, the same reference numerals are used for components that are identical to the preceding examples.

9 10 FIGS.and 170 1 190 1 Referring to, the semiconductor device includes the plurality of the source electrodes_and the drain electrodes_.

9 FIG. 170 1 171 172 132 190 1 191 192 132 171 191 140 136 132 172 192 180 171 191 171 191 172 192 m m m Referring to, the source electrodes_of the semiconductor device include a first source electrodeand a second source electrodestacked sequentially in the third direction (Z direction) on the main channel layer, and the drain electrodes_include a first drain electrodeand a second drain electrodestacked sequentially in the third direction (Z direction) on the main channel layer. The first source electrodeand the first drain electrodemay penetrate the first protective layerand the barrier layerto be connected with the main channel layer. Each of the second source electrodeand the second drain electrodemay penetrate the second protective layerand be connected to the first source electrodeand the first drain electrode. Each of the first source electrodeand the first drain electrodemay include the same material as the second source electrodeand the second drain electrode, but may also include different materials.

310 1 180 310 1 180 170 1 190 1 310 1 172 310 1 172 172 310 1 172 Additionally, the field dispersion layer_of the semiconductor device may be located on the second protective layer. The field dispersion layer_may be located on the second protective layerand spaced apart from the source electrode_and the drain electrode_. The field dispersion layer_may include the same material as the second source electrode. The field dispersion layer_may be formed by the same process as the second source electrodeand may be located in the same layer as at least a portion of the second source electrode. However, the present disclosure is not limited thereto, and the field dispersion layer_may be located in a different layer from the second source electrode, and may be formed by a different process.

10 FIG. 310 310 1 132 s. Referring further to, the semiconductor device may further include a contact electrodeC located between the field dispersion layer_and the sub-channel layer

310 140 136 132 310 132 310 132 310 171 191 310 171 191 310 171 191 310 171 191 s s s The contact electrodeC may penetrate the first protective layerand the barrier layerto be electrically connected with the sub-channel layer. The contact electrodeC may be located within the recessed space of the sub-channel layer. Accordingly, the contact electrodeC may be in contact with a portion of the lateral surface of the sub-channel layer, but is not limited thereto. The contact electrodeC may include the same material as the first source electrodeand the first drain electrode. The contact electrodeC may be formed together in the same process as the first source electrodeand the first drain electrode. However, the present disclosure is not limited thereto, and the contact electrodeC may include a different material from the first source electrodeand the first drain electrode. The contact electrodeC may be formed in a different process from the first source electrodeand the first drain electrode.

310 1 180 310 310 1 310 310 1 132 310 s In some implementations, the field dispersion layer_may penetrate the second protective layerand be connected to the contact electrodeC. The field dispersion layer_may overlap the contact electrodeC in the third direction (Z direction). The field dispersion layer_may be electrically connected to the sub-channel layervia the contact electrodeC.

11 FIG. 152 152 s m. Referring to, the sub-gate semiconductor layerof the semiconductor device according to some exemplary embodiments may be spaced apart from the main gate semiconductor layer

152 132 152 132 152 160 1 132 132 152 160 1 152 132 155 152 155 152 155 152 155 152 155 155 s s m m s m s s s s s s m m s s m m s m In some implementations, the sub-gate semiconductor layermay be located above the sub-channel layer, and the main gate semiconductor layermay be located above the main channel layer. In this case, the sub-gate semiconductor layermay not be located on the separation structure_located between the main channel layerand the sub-channel layer. The sub-gate semiconductor layermay not overlap the separation structure_in the third direction (Z direction). That is, the sub-gate semiconductor layermay be located only above the sub-channel layer, but is not limited thereto. In this case, the sub-gate electrodemay cover the lateral surface and the top surface of the sub-gate semiconductor layer, and the main gate electrodemay cover the lateral surface and the top surface of the main gate semiconductor layer, but the present disclosure is not limited thereto. As another example, the sub-gate electrodemay cover only the top surface of the sub-gate semiconductor layer, the main gate electrodemay cover only the top surface of the main gate semiconductor layer, and the sub-gate electrodemay be electrically connected to the main gate electrodevia separate top wires or the like.

12 14 FIGS.to 310 Referring now to, the field dispersion layerof the semiconductor device may have various shapes.

310 190 310 2 310 310 310 2 190 310 2 190 310 3 310 3 310 3 190 310 4 310 190 310 190 12 FIG. 13 FIG. 14 FIG. In some implementations, the field dispersion layermay have a shape that protrudes toward the drain electrode. For example, as illustrated in, the field dispersion layer_may include a stepped portionS stepped toward the second direction (Y direction) in a planar view. By the stepped portionS, the field dispersion layer_may have a protruding shape in a planar view toward the drain electrode. Accordingly, the width along the second direction (Y direction) of the field dispersion layer_may include a portion that decreases as it approaches the drain electrode. As another example, as illustrated in, the field dispersion layer_may have a trapezoidal shape in a planar view. Accordingly, the width along the second direction (Y direction) of the field dispersion layer_may decrease as the field dispersion layer_approaches the drain electrode. As another example, as illustrated in, the field dispersion layer_may include a protruding portionP convex toward the drain electrode. The protruding portionP may have a convex shape toward the drain electrode.

15 FIG. 170 5 170 5 170 5 132 170 5 132 a a s a s Referring to, a source electrode_of the semiconductor device may further extend into the peripheral circuit region PA. In some implementations, the source electrode_may extend in the second direction (Y direction) and be located in the main device region MA and the peripheral circuit region PA. The source electrode_may overlap the sub-channel layerin the third direction (Z direction). The source electrode_may be connected to the sub-channel layerin the peripheral circuit region PA.

16 FIG. 155 2 155 2 132 155 2 170 310 155 2 1 155 2 2 155 21 170 310 170 s s s s s s s Referring to, the sub-gate electrode_of the semiconductor device may have various shapes. For example, the sub-gate electrode_may overlap the extension portion EP of the sub-channel layerin the third direction (Z direction). In this case, the portion of the sub-gate electrode_that overlaps the extension portion EP in the third direction (Z direction) may be located closer to the source electrodethan the field dispersion layer. In other words, the distance between the portion of the sub-gate electrode_that overlaps the extension portion EP in the third direction (Z direction) and the first contact portion CPmay be smaller than the distance between the portion of the sub-gate electrode_that overlaps the extension portion EP in the third direction (Z direction) and the second contact portion CP. However, the present disclosure is not limited thereto, and the extension portion EP and the portion of the sub-gate electrode_overlapping in the third direction (Z direction) may be located further from the source electrodethan the field dispersion layer, or may be located substantially the same distance from the source electrode.

17 FIG. 132 132 s m. Referring to, the sub-channel layerof the semiconductor device may be spaced apart from the main channel layer

132 132 160 132 132 132 132 160 132 s m s m s m s In some implementations, the sub-channel layermay be spaced apart from the main channel layerin the second direction (Y direction), but other variations are not limited thereto. The separation structuremay be located between the sub-channel layerand the main channel layer. That is, the sub-channel layerand the main channel layermay be separated by the separation structure. In some implementations, the sub-channel layermay have a square shape in a plane view, but the shape is not limited thereto.

170 155 3 310 s Additionally, the source electrode, the sub-gate electrode_, and the field dispersion layerof the semiconductor device may extend further into the peripheral circuit region PA.

170 155 3 310 170 155 3 310 170 155 3 310 170 310 132 170 140 136 1 132 310 140 136 2 132 170 310 160 s s s s s s For example, the source electrode, the sub-gate electrode_, and the field dispersion layermay extend side-by-side. The source electrode, the sub-gate electrode_, and the field dispersion layermay extend in the second direction (Y direction). The source electrode, the sub-gate electrode_and the field dispersion layermay be spaced apart from each other. The source electrodeand the field dispersion layermay be connected with the sub-channel layer′. For example, the source electrodemay penetrate the first protective layerand the barrier layerto be connected with the first contact portion CPof the sub-channel layer. The field dispersion layermay penetrate the first protective layerand the barrier layerto be connected with the second contact portion CPof the sub-channel layer. The source electrodeand the field dispersion layermay overlap the separation structurein the third direction (Z direction), but the relative positions are not limited thereto.

155 3 170 310 155 3 132 155 3 132 155 3 1 2 132 s s s s s s s. In some implementations, the sub-gate electrode_may be located between the source electrodeand the field dispersion layer. The sub-gate electrode_may overlap the sub-channel layerin a third direction (z-direction). The sub-gate electrode_may be located on the extension portion EP of the sub-channel layer. That is, the sub-gate electrode_may be located between the first contact portion CPand the second contact portion CPof the sub-channel layer

18 23 FIGS.to The field dispersion layer and the sub-transistor of the semiconductor device will be described below with reference to.

18 FIG. 19 FIG. 18 FIG. 20 FIG. 19 FIG. 21 FIG. 19 FIG. 19 21 FIGS.to 18 FIG. 22 23 FIGS.and 18 FIG. is a circuit diagram illustrating an example of a semiconductor device.is a top plan view illustrating an example of the semiconductor device of.is a cross-sectional view taken along line E-E′ of.is a cross-sectional view taken along line F-F′ of.are diagrams illustrating the semiconductor device of.are diagrams illustrating the semiconductor device of.

18 23 FIGS.to 1 8 FIGS.to 18 23 FIGS.to 1 8 FIGS.to illustrate various modified examples of the semiconductor device illustrated in. Since some parts of the examples illustrated inare substantially the same as those of the examples illustrated in, a description thereof will be omitted, and the differences will be mainly described. Also, the same reference numerals are used for components that are identical to the preceding example.

18 FIG. 310 6 311 313 311 313 100 6 320 6 321 323 311 313 Referring to, the field dispersion layer_of the semiconductor device may include a plurality of field dispersion layersto. For example, the semiconductor device may include first to third field dispersion layerstolocated between the gate electrode G and the first electrode D of the main transistor_. Additionally, the semiconductor device may include a plurality of sub-transistors_. For example, the semiconductor device may include first to third sub-transistorstoconnected to the first to third field dispersion layersto, respectively.

311 313 100 6 100 6 100 6 The first to third field dispersion layerstomay serve to dissipate an electric field that is concentrated around the gate electrode G of the main transistor_. Accordingly, the leakage current in the main transistor_may be reduced, and the breakdown voltage of the main transistor_may be increased.

321 323 321 323 100 6 321 323 100 6 321 311 322 312 323 313 Each of the first to third sub-transistorstomay control the drain-to-source current in response to a gate signal applied to the gate electrode. Each of the first to third sub-transistorstomay be electrically connected to one end of the main transistor_. For example, a first electrode of each of the first to third sub-transistorstomay be electrically connected to a second electrode S of the main transistor_and to a second power source supplying the second supply voltage Vs. Further, the second electrode of the first sub-transistormay be electrically connected with the first field dispersion layer, the second electrode of the second sub-transistormay be electrically connected with the second field dispersion layer, and the second electrode of the third sub-transistormay be electrically connected with the third field dispersion layer.

321 323 100 6 321 323 100 6 321 323 100 6 Further, the gate electrodes of the first to third sub-transistorstomay be electrically connected with the gate electrode G of the main transistor_. Accordingly, the same signal may be applied to the gate electrodes of the first to third sub-transistorstoand the gate electrode G of the main transistor_, and the first to third sub-transistorstomay be turned on depending on whether the main transistor_is turned on or not.

19 21 FIGS.to 311 313 155 190 321 323 311 313 m Referring now to, an example of the semiconductor device includes first to third field dispersion layerstolocated between the main gate electrodeand the drain electrode, and first to third sub-transistorstoconnected with the first to third field dispersion layersto, respectively.

311 313 155 190 311 313 155 311 155 312 312 311 313 313 312 190 m m m The first to third field dispersion layerstomay be located between the main gate electrodeand the drain electrode. For example, the first to third field dispersion layerstomay be located sequentially in a direction away from the main gate electrode. That is, the first field dispersion layermay be located between the main gate electrodeand the second field dispersion layer, the second field dispersion layermay be located between the first field dispersion layerand the third field dispersion layer, and the third field dispersion layermay be located between the second field dispersion layerand the drain electrode.

311 313 311 313 311 313 155 190 311 313 311 313 170 155 190 m m The first to third field dispersion layerstomay be spaced apart from each other. The first to third field dispersion layerstomay extend in a side-by-side direction. The first to third field dispersion layerstomay extend in a side-by-side direction with the main gate electrodeand the drain electrode. For example, but not limited to, the first to third field dispersion layerstomay extend in the second direction (Y direction) and be spaced apart from each other. Further, the first to third field dispersion layerstomay be spaced apart from the source electrode, the main gate electrode, and the drain electrode.

311 313 311 313 140 311 313 140 311 313 20 FIG. 22 23 FIGS.and In some implementations, the first to third field dispersion layerstomay be located on the same layer as each other. For example, as illustrated in, the first to third field dispersion layerstomay be located directly on the first protective layer. The first to third field dispersion layerstomay be in contact with the top surface of the first protective layer. However, the present disclosure is not limited thereto, and the first to third field dispersion layerstomay be located in different layers. These will be described hereinafter with reference to.

1 311 312 2 312 313 311 313 1 311 2 312 3 313 1 311 2 312 3 313 In this case, a first distance Dalong the first direction (X direction) between the first field dispersion layerand the second field dispersion layerand a second distance Dalong the first direction (X direction) between the second field dispersion layerand the third field dispersion layermay be substantially the same, but the present disclosure is not limited thereto. Furthermore, the widths of the first to third field dispersion layerstomay be substantially the same as each other. For example, a first width Walong the first direction (X direction) of the first field dispersion layer, a second width Walong the first direction (X direction) of the second field dispersion layer, and a third width Walong the first direction (X direction) of the third field dispersion layermay be substantially the same as each other, but are not limited thereto. As another example, at least one of the first width Walong the first direction (X direction) of the first field dispersion layer, the second width Walong the first direction (X direction) of the second field dispersion layer, and the third width Walong the first direction (X direction) of the third field dispersion layermay have a different width.

311 313 132 311 132 1 312 132 2 313 132 3 132 1 132 3 132 321 323 s s s s s s s In some implementations, each of the first to third field dispersion layerstomay be connected with the sub-channel layer. For example, the first field dispersion layermay be connected with the first sub-channel layer, the second field dispersion layermay be connected with the second sub-channel layer, and the third field dispersion layermay be connected with the third sub-channel layer. Here, the first to third sub-channel layerstomay refer to the portion of the sub-channel layerthat configures the channel layers of the first to third sub-transistorsto.

311 313 311 321 312 322 313 323 Accordingly, each of the first to third field dispersion layerstomay configure one electrode of one of the transistors. For example, the first field dispersion layermay configure the one electrode of the first sub-transistor, the second field dispersion layermay configure the one electrode of the second sub-transistor, and the third field dispersion layermay configure the one electrode of the third sub-transistor.

132 132 1 132 3 310 6 132 132 1 132 3 s s s s s In some implementations, the sub-channel layermay include first to third sub-channel layersto, each connected with one field dispersion layer_, and a connection portion_C connected with the first to third sub-channel layersto.

132 1 132 3 132 1 132 3 132 1 132 3 132 1 132 3 311 313 311 132 1 140 136 312 132 2 140 136 313 132 3 140 136 132 1 132 3 132 321 323 s s s s s s s s s s s s s s 19 FIG. The first to third sub-channel layerstomay be spaced apart from each other. For example, as illustrated in, the first to third sub-channel layerstomay extend in the second direction (Y direction) and be spaced apart in the first direction (X direction), but the first to third sub-channel layerstoare not limited thereto. The first to third sub-channel layerstomay be connected with the first to third field dispersion layersto. For example, the first field dispersion layermay be connected to the first sub-channel layerthrough the first protective layerand the barrier layer, the second field dispersion layermay be connected to the second sub-channel layerthrough the first protective layerand the barrier layer, and the third field dispersion layermay be connected to the third sub-channel layerthrough the first protective layerand the barrier layer. Here, the first to third sub-channel layerstomay refer to the portion of the sub-channel layerthat configures the channel layers of the first to third sub-transistorsto.

132 170 170 140 136 132 132 132 1 132 3 132 1 132 3 170 132 s s s s In some implementations, the connection portion_C may be connected to the source electrode. For example, the source electrodemay penetrate the first protective layerand the barrier layerto be connected with the connection portion_C. The connection portion_C may be connected to the first to third sub-channel layersto. Accordingly, the first to third sub-channel layerstomay be electrically connected to the source electrodevia the connection portion_C.

155 132 1 132 3 155 132 1 132 3 132 155 311 313 155 132 1 132 3 155 132 1 132 3 160 155 132 170 132 311 132 170 132 312 132 170 132 313 155 311 313 155 321 323 s s s s s s s s s s s s s s s s s s s s s s In some implementations, the sub-gate electrodemay be located above the first to third sub-channel layersto. The sub-gate electrodemay overlap the first to third sub-channel layerstoin a third direction (z-direction) and not overlap the connection portion_C in a third direction (z-direction), but the present disclosure is not limited thereto. The sub-gate electrodemay be located adjacent to the first to third field dispersion layersto, but the relative location is not limited thereto. The sub-gate electrodemay extend to overlap the first to third sub-channel layerstoin the third direction (Z direction). For example, the sub-gate electrodemay extend in the first direction (X direction) to overlap the first to third sub-channel layerstoand the separation structurein the third direction (Z direction). The sub-gate electrodemay be located between the portion of the sub-channel layerto which the source electrodeis connected and the portion of the sub-channel layerto which the first field dispersion layeris connected, between the portion of the sub-channel layerto which the source electrodeis connected and the portion of the sub-channel layerto which the second field dispersion layeris connected, and between the portion of the sub-channel layerto which the source electrodeis connected and the portion of the sub-channel layerto which the third field dispersion layeris connected. The sub-gate electrodemay be spaced apart from the first to third field dispersion layersto. The sub-gate electrodemay configure the gates of the first to third sub-transistorsto.

152 136 155 152 132 132 3 152 132 1 132 3 152 132 132 3 152 132 1 132 3 160 152 132 1 132 3 152 132 1 132 3 160 152 132 1 132 3 160 s s s sl s s s s s sl s s s s s s s s s s s s s 21 FIG. In some implementations, the sub-gate semiconductor layermay be located between the barrier layerand the sub-gate electrode. The sub-gate semiconductor layermay be located on the first to third sub-channel layersto. The sub-gate semiconductor layermay overlap the first to third sub-channel layerstoin the third direction (Z direction). For example, as illustrated in, the sub-gate semiconductor layermay overlap each of the first to third sub-channel layerstoin the third direction (Z direction). The sub-gate semiconductor layerslocated on each of the first to third sub-channel layerstomay be spaced apart from each other. The separation structuremay be located between the sub-gate semiconductor layerslocated on the first to third sub-channel layersto, respectively. The sub-gate semiconductor layerslocated on each of the first to third sub-channel layerstomay be separated from each other by the separation structure, but the present disclosure is not limited thereto. The sub-gate semiconductor layerslocated on each of the first to third sub-channel layerstomay not overlap the separation structurein the third direction (Z direction), but the present disclosure is not limited thereto.

132 152 1 132 152 2 132 2 3 132 3 1 3 134 s s sl s s s 21 FIG. The depletion region DPR may be formed in the sub-channel layerby the sub-gate semiconductor layer. For example, as illustrated in, a first depletion region DPRmay be formed in the first sub-channel layerby the sub-gate semiconductor layer, a second depletion region DPRmay be formed in the second sub-channel layer, and a third depletion region DPRmay be formed in the third sub-channel layer. The first to third depletion regions DPRto DPRmay refer to regions where the flow of the two-dimensional electron gasis interrupted within the sub-drift region DTRs.

155 132 1 132 3 321 323 321 323 155 321 323 320 6 s s s s 1 8 FIGS.to The sub-gate electrodeof the semiconductor device may overlap each of the first to third sub-channel layerstoconfiguring the channel layers of the first to third sub-transistorstoin the third direction (Z direction). Thus, the first to third sub-transistorstomay be turned on or turned off together depending on a gate signal applied to the sub-gate electrode. The method of operating the first to third sub-transistorstois substantially the same as the method of operating the sub-transistor_of the examples of, and therefore will be omitted.

22 23 FIGS.and 185 180 310 7 311 313 311 313 Referring to, the semiconductor device may further include a third protective layerlocated on the second protective layer. The field dispersion layer_of the semiconductor device may include a plurality of field dispersion layersto, and the first to third field dispersion layerstomay be located on different layers.

170 7 190 7 170 7 171 173 132 190 7 191 193 132 m m. Additionally, the semiconductor device may include the plurality of source electrodes_and the plurality of drain electrodes_. For example, the source electrode_may include first to third source electrodestostacked sequentially in the third direction (Z direction) on top of the main channel layer, and the drain electrode_may include first to third drain electrodestostacked sequentially in the third direction (Z direction) on top of the main channel layer

311 140 311 140 311 180 311 180 311 171 171 140 311 311 171 311 171 311 171 For example, the first field dispersion layermay be located on the first protective layer. The first field dispersion layermay be located directly on the top surface of the first protective layer. The first field dispersion layermay be covered by the second protective layer. For example, the top surface and the lateral surface of the first field dispersion layermay be covered by the second protective layer. In this case, the first field dispersion layermay be located in the same layer as at least a portion of the first source electrode. For example, the portion of the first source electrodethat is located on the first protective layermay be located in the same layer as the first field dispersion layer, but the present disclosure is not limited thereto. The first field dispersion layermay include the same material as the first source electrode. The first field dispersion layermay be formed together by the same process as the first source electrode. However, the present disclosure is not limited thereto, and the first field dispersion layermay include a different material from the first source electrodeand/or may be formed by a different process.

312 180 312 180 312 185 312 185 312 172 172 180 312 312 172 312 172 312 172 The second field dispersion layermay be located on the second protective layer. The second field dispersion layermay be located directly on the top surface of the second protective layer. The second field dispersion layermay be covered by the third protective layer. For example, the top surface and the lateral surface of the second field dispersion layermay be covered by the third protective layer. In this case, the second field dispersion layermay be located in the same layer as at least a portion of the second source electrode. For example, the portion of the second source electrodethat is located on the second protective layermay be located in the same layer as the second field dispersion layer, but the present disclosure is not limited thereto. The second field dispersion layermay include the same material as the second source electrode. The second field dispersion layermay be formed together by the same process as the second source electrode. However, the present disclosure is not limited thereto, and the second field dispersion layermay comprise a different material from the second source electrode, or may be formed by a different process.

313 185 313 185 313 173 173 185 313 313 173 313 173 313 173 The third field dispersion layermay be located on the third protective layer. The third field dispersion layermay be located directly on the top surface of the third protective layer. In this case, the third field dispersion layermay be located in the same layer as at least a portion of the third source electrode. For example, the portion of the third source electrodelocated above the third protective layermay be located in the same layer as the third field dispersion layer, but the present disclosure is not limited thereto. The third field dispersion layermay include the same material as the third source electrode. The third field dispersion layermay be formed together by the same process as the third source electrode. However, the present disclosure is not limited thereto, and the third field dispersion layermay include a different material from the third source electrode, or may be formed by a different process.

22 FIG. 23 FIG. 23 FIG. 311 313 311 313 As another example,anddepict another semiconductor device. In, the first to third field dispersion layerstoare illustrated as being located in different layers, but the present disclosure is not limited thereto, and at least one of the first to third field dispersion layerstomay be located in a different layer.

18 23 FIGS.to 310 310 310 310 The examples ofdescribe three field dispersion layers, but the number of field dispersion layersis not limited thereto. For example, a semiconductor device may include two field dispersion layers, or may include four or more field dispersion layers.

24 30 FIGS.to Hereinafter, an example of a method of manufacturing a semiconductor device will be described with reference to.

24 FIG. 27 FIG. 24 FIG. 28 FIG. 24 FIG. 25 FIG. 29 FIG. 25 FIG. 26 FIG. 30 FIG. 26 FIG. is a top plan view of an intermediate operation illustrating an example of a method of manufacturing a semiconductor device.is a cross-sectional view taken along line H-H′ and I-I′ of.is a cross-sectional view corresponding to H-H′ and I-I′ ofillustrating the method of manufacturing the semiconductor device.is a top plan view of an intermediate operation illustrating the example of method of manufacturing a semiconductor device.is a cross-sectional view taken along line J-J′ and K-K′ of.is a top plan view of an intermediate operation illustrating the method of manufacturing the semiconductor device.is a cross-sectional view taken along lines L-L′ and M-M′ of.

24 25 FIGS.and 121 120 132 136 110 160 155 152 As illustrated in, a seed layer, a buffer layer, a channel layer, and a barrier layer, a gate semiconductor material layer may be formed sequentially on a substrate, a separation isolation structuremay be formed, and a gate electrodeand a gate semiconductor layermay be formed.

121 120 110 120 124 126 First, the seed layerand the buffer layermay be formed sequentially on the substratein the main device region MA and a peripheral circuit region PA. In this example, the buffer layermay include a superlattice layerand a high-resistance layer.

110 110 110 110 The substratemay include a semiconductor material. For example, the substratemay include sapphire, Si, SiC, AlN, GaN, or combinations thereof. The substratemay also be a silicon on insulator (SOI) substrate. However, the material of the substrateis not limited thereto, and any commonly used substrate may be applied.

121 124 121 124 121 124 121 124 121 124 x y 1-x-y The seed layerand the superlattice layermay be formed sequentially using an epitaxial growth method. The seed layerand the superlattice layermay be made of the same base semiconductor material. However, the material composition ratio of each layer may be different in consideration of the role of each layer, the performance required of the semiconductor device, and the like. The seed layerand the superlattice layermay include one or more materials selected from group III-V materials, for example, for example, nitrides comprising Al, Ga, In, B, or combinations thereof. The seed layerand the superlattice layermay be AlInGaN (0≤x≤1, 0≤y≤1, x+y≤1). For example, the seed layerand the superlattice layermay include AlN, GaN, InN, InGaN, AlGaN, AllInN, AlInGaN, or a combination thereof.

124 124 124 In this example, the superlattice layermay be formed of multiple layers in which layers including different materials are stacked alternately. For example, the superlattice layermay have the structure in which layers of AlGaN and layers of AlN are repeatedly stacked. That is, AlGaN/AlN/AlGaN/AlN/AlGaN/AlN/may be stacked sequentially to form the superlattice layer.

126 110 132 126 126 126 m x y 1-x-y The high-resistance layermay be made of a low-conductivity material such that the substrateand the channel layerare electrically isolated. The high-resistance layer may include one or more materials selected from group III-V materials, for example, nitrides including Al, Ga, In, B, or combinations thereof. The high-resistance layermay be AlInGaN (0≤x≤1, 0≤y≤1, x+y≤1). For example, the high-resistance layermay include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The high-resistance layermay be a single layer or multiple layers.

132 136 126 Subsequently, the channel layerand the barrier layermay be formed sequentially on top of the high-resistance layerin the main device region MA and the peripheral circuit region PA.

132 136 132 126 136 132 In this example, the channel layerand the barrier layermay be formed sequentially using an epitaxial growth method. For example, the channel layermay be formed on top of the high-resistance layer, and the barrier layermay be formed on top of the channel layer.

132 136 132 136 132 136 132 136 136 132 136 132 x y 1-x-y The channel layerand the barrier layermay be made of the same base semiconductor material. However, the material composition ratio of each layer may be different based on the role of each layer, the performance required of the semiconductor device, etc. The channel layerand the barrier layermay include one or more materials selected from group III-V materials, for example, nitrides including Al, Ga, In, B, or combinations thereof. The channel layerand the barrier layermay be AlInGaN (0≤x≤1, 0≤y≤1, x+y≤1). For example, the channel layerand the barrier layermay include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The barrier layermay include a material having a different energy band gap than that of the channel layer. The barrier layermay have a higher energy band gap than that of the channel layer.

110 121 124 126 132 136 132 136 In one example, the substratemay include Si, the seed layermay include AlN, and the superlattice layermay include AlGaN and AlN. The high-resistance layermay include GaN, the channel layermay include GaN, and the barrier layermay include AlGaN. The channel layerand the barrier layermay be doped with impurities or may be undoped.

136 Next, a gate semiconductor material layer may be formed on top of the barrier layer. The gate semiconductor material layer may be formed using an epitaxial growth method.

160 132 132 m s Then, an ion implantation process may be performed to form the separation structureto separate the main channel layerand the sub-channel layerfrom each other.

160 136 132 120 121 110 160 136 132 120 121 110 For example, the separation structuremay be formed by performing the ion implantation process on a portion of the gate semiconductor material layer and a portion of the barrier layerlocated between the main device region MA and the peripheral circuit region PA. In this case, the ion implantation process may be performed on at least a portion of the channel layer, the buffer layer, the seed layer, and the substratetogether. The separation structuremay penetrate the gate semiconductor material layer, the barrier layer, the channel layer, the buffer layer, and the seed layerto recess at least a portion of the substrate, but the present disclosure is not limited thereto.

160 132 132 132 132 132 136 m s m s As the separation structureis formed, the channel layermay be separated into the main channel layerand the sub-channel layer. However, the present disclosure is not limited thereto, and the main channel layerand the sub-channel layermay also be separated from each other by forming a trench through the gate semiconductor material layer and the barrier layerbetween the main device region MA and the peripheral circuit region PA.

155 152 Next, a gate electrode material layer may be formed on top of the gate semiconductor material layer in the main device region MA and the peripheral circuit region PA, and the gate semiconductor material layer and the gate electrode material layer may be patterned to form the gate electrodeand the gate semiconductor layer.

Specifically, the gate electrode material layer may be formed using a deposition process. For example, the gate electrode material layer may be formed using at least one of, but not limited to, electron beam evaporation (E-beam evaporation), sputtering, physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low pressure chemical vapor deposition (LP-CVD), plasma enhanced chemical vapor deposition (PE-CVD), or atomic layer deposition (ALD) techniques.

155 152 155 152 152 136 155 155 152 155 152 The gate electrode material layer and the gate semiconductor material layer may then be patterned using a photolithography and etch process to form the gate electrodeand the gate semiconductor layer. For example, a hard mask layer may be formed on the gate electrode material layer, and then at least a portion of the gate semiconductor material layer may be removed by etching the gate semiconductor material layer using the hard mask layer as a mask. Accordingly, the portion of the gate electrode material layer that remains may become the gate electrode. Further, the portion of the gate semiconductor material layer that remains may be the gate semiconductor layer. The gate semiconductor layermay be located between the barrier layerand the gate electrode. However, the present disclosure is not limited thereto, and the gate electrodeand the gate semiconductor layermay also be formed by utilizing a photoresist pattern in addition to the hard mask layer, or by patterning without utilizing the hard mask layer. The gate electrodemay be in Schottky contact or ohmic contact with the gate semiconductor layer.

155 155 155 155 152 152 m s m s. In this case, the portion of the gate electrodelocated in the main device region MA may be referred to as the main gate electrode, and the portion of the gate electrodelocated in the peripheral circuit region PA may be referred to as the sub-gate electrode. Further, the portion of the gate semiconductor layer located in the main device region MA may be referred to as a main gate semiconductor layer, and the portion of the gate semiconductor layer located in the peripheral circuit region PA may be referred to as a sub-gate semiconductor layer

28 FIG. 140 136 155 140 136 155 136 140 160 140 140 140 2 2 3 As illustrated in, a first protective layermay be formed on the barrier layerand the gate electrode. For example, the first protective layermay be formed to cover the barrier layerin the main device region MA and the gate electrodeand the barrier layerin the peripheral circuit region PA. Further, a first protective layermay be formed on the separation structure. The first protective layermay include an insulating material. For example, the first protective layermay include an oxide, such as SiOor AlO. As another example, the first protective layermay include a nitride, such as SiN, or an oxynitride, such as SiON.

28 29 FIGS.and 140 1 2 3 140 136 132 As illustrated in, by patterning the first protective layerusing a photo and etch process, a first trench TRand a second trench TRmay be formed in the main device region MA, and a third trench TRmay be formed in the peripheral circuit region PA. At this time, the first protective layer, as well as the barrier layerand the channel layer, may be patterned together.

140 140 136 132 140 136 1 2 132 132 1 2 140 136 3 132 132 3 m m s s For example, a photoresist pattern may be formed on the first protective layerand used as a mask to sequentially etch the first protective layer, the barrier layer, and the channel layer. At this time, the first protective layerand the barrier layermay be penetrated by the first trench TRand the second trench TR, and the top surface of the main channel layermay be recessed. The main channel layermay not be penetrated by the first trench TRor the second trench TR. Additionally, the first protective layerand the barrier layermay be penetrated by the third trench TR, and the top surface of the sub-channel layermay be recessed. The sub-channel layermay not be penetrated by the third trench TR.

132 132 132 132 132 136 132 132 m s m m s m s In this case, the depth at which the top surface of the main channel layerand the top surface of the sub-channel layerare recessed may be much smaller compared to the overall thickness of the main channel layer. Further, the depth at which the top surface of the main channel layerand the top surface of the sub-channel layerare recessed may be small relative to the thickness of the barrier layer. However, the present disclosure is not limited thereto, and the depth at which the top surface of the main channel layerand the top surface of the sub-channel layerare recessed may be varied.

1 2 140 136 132 132 1 132 132 1 136 1 132 2 136 2 m s m s m By the first trench TRand the second trench TR, the lateral surface of the first protective layerand the barrier layermay be exposed to the outside, and the top surface and the lateral surface of the main channel layermay be exposed. The lateral surface of the sub-channel layermay be exposed by the first trench TR. The main channel layerand the sub-channel layermay form the bottom surface and the lateral wall of the first trench TR, and the barrier layermay form the lateral wall of the first trench TR. The main channel layermay form the bottom surface and the lateral wall of the second trench TR, and the barrier layermay form the lateral wall of the second trench TR.

3 140 136 132 132 3 136 3 s s By the third trench TR, the lateral surfaces of the first protective layerand the barrier layermay be exposed to the outside, and the top surface and the lateral surface of the sub-channel layermay be exposed. The sub channel layermay form the bottom surface and the lateral wall of the third trench TR, and the barrier layermay form the lateral wall of the third trench TR.

1 2 1 2 155 1 155 155 2 155 155 1 155 2 155 1 2 1 2 The first trench TRand the second trench TRmay be spaced apart from each other. The first trench TRand the second trench TRmay be located on opposite sides of the gate electrode. The first trench TRmay be located on one side of the gate electrodewhile being spaced apart from the gate electrode. The second trench TRmay be located on the other side of the gate electrodewhile being spaced apart from the gate electrode. The distance by which the first trench TRis spaced from the gate electrodemay be less than the distance by which the second trench TRis spaced from the gate electrode. The first trench TRand the second trench TRare illustrated as having similar shapes, such as widths and depths, but are not limited thereto. The shapes of the first trench TRand the second trench TRmay be varied.

29 30 FIGS.and 1 3 170 190 310 As illustrated in, a conductive material may be deposited within the first trench TRto the third trench TR, and patterned to form a source electrode, a drain electrode, and a field dispersion layer.

170 1 1 170 132 136 170 132 136 170 132 136 170 132 1 170 132 1 170 140 m m m m s In this example, the source electrodemay be formed to fill the interior of the first trench TR. Within the first trench TR, the source electrodemay be in contact with the main channel layerand the barrier layer. The source electrodemay be in contact with the lateral surfaces of the main channel layerand the barrier layer. The source electrodemay cover the lateral surfaces of the main channel layerand the barrier layer. The source electrodemay be electrically connected to the main channel layervia the first trench TR. Additionally, the source electrodemay be electrically connected to the sub-channel layervia the first trench TR. The top surface of the source electrodemay protrude above the top surface of the first protective layer.

190 2 2 190 132 136 190 132 136 190 132 136 190 132 2 190 140 m m m m The drain electrodemay be formed to fill the interior of the second trench TR. Within the second trench TR, the drain electrodemay be in contact with the main channel layerand the barrier layer. The drain electrodemay be in contact with the lateral surfaces of the main channel layerand the barrier layer. The drain electrodemay cover the lateral surfaces of the main channel layerand the barrier layer. The drain electrodemay be electrically connected to the main channel layervia the second trench TR. The top surface of the drain electrodemay protrude above the top surface of the first protective layer.

170 190 132 132 170 190 132 136 132 136 132 136 170 190 132 136 m m m m m m The source electrodeand the drain electrodemay be in ohmic contact with the main channel layer. Within the main channel layer, the regions in contact with the source electrodeand the drain electrodemay be doped at relatively high concentrations compared to other regions. For example, the main channel layeror the barrier layermay be doped by an ion implantation process, an annealing process, or the like. However, the present disclosure is not limited thereto, and the doping process of the main channel layeror the barrier layermay be accomplished by a variety of other processes. The doping process of the main channel layeror the barrier layermay be performed prior to forming the source electrodeand the drain electrode, but the present disclosure is not limited thereto. In some cases, the main channel layerand/or the barrier layermay not be doped.

310 3 310 170 190 310 155 190 310 140 170 190 310 170 190 310 170 190 3 310 132 310 132 136 310 132 3 310 170 190 m s s s In this example, the field dispersion layermay be formed to fill the interior of the third trench TR. The field dispersion layermay be formed between the source electrodeand the drain electrode. Additionally, the field dispersion layermay be formed between the main gate electrodeand the drain electrode. The field dispersion layermay be formed to extend on the first protective layerin the same direction as the source electrodeand the drain electrode. The field dispersion layermay be formed to be spaced apart from the source electrodeand the drain electrode. For example, the field dispersion layermay extend in the second direction (Y direction) and be spaced apart from the source electrodeand the drain electrodein the first direction (X direction), but is not limited thereto. Within the third trench TR, the field dispersion layermay be in contact with the sub-channel layer. The field dispersion layermay be in contact with the lateral surfaces of the sub-channel layerand the barrier layer. The field dispersion layermay be electrically connected to the sub-channel layervia the third trench TR. The field dispersion layermay include, but is not limited to, the same material as the source electrodeand the drain electrode.

While this disclosure contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed. Certain features that are described in this disclosure in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations, one or more features from a combination can in some cases be excised from the combination, and the combination may be directed to a subcombination or variation of a subcombination.

Although examples of the present disclosure has been described in detail, the scope of the present disclosure is not limited by the examples. Various changes and modifications using the basic concept of the present disclosure defined in the accompanying claims by those skilled in the art shall be construed to belong to the scope of the present disclosure.

100 : Main transistor 320 : Sub-transistor 110 : Substrate 132 m : Main channel layer 132 s : Sub-channel layer 136 : Barrier layer 152 : Gate semiconductor layer 155 m : Main gate electrode 170 : Source electrode 190 : Drain electrode 310 : Field dispersion layer 140 : First protective layer