Method of Manufacturing a Display Apparatus

This application is a Continuation of co-pending U.S. patent application Ser. No. 18/342,091, filed on Jun. 27, 2023, which is a Division of U.S. patent application Ser. No. 17/032,326 filed on Sep. 25, 2020 (issued on Aug. 15, 2023 as U.S. Pat. No. 11,730,025), which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0119830, filed on Sep. 27, 2019, in the Korean Intellectual Property Office, the disclosure of each of which is incorporated by reference herein in its entirety.

The present invention relates to a display apparatus and a method of manufacturing the display apparatus, and more particularly, to a display apparatus having a transmission area and a method of manufacturing the display apparatus.

Usage of display apparatuses has diversified considerable. In addition, the thickness and the weight of the display apparatuses are decreasing, and the range of use thereof is widening.

Various functions have been added to display apparatuses while the area occupied by a display area in such display apparatuses has increased. As a method for adding various functions while enlarging the area, research into display apparatuses having an area for adding various functions other than an image display inside a display area is continuing.

One or more embodiments include a display apparatus having a display panel having a transmission area inside a display area and a method of manufacturing the display apparatus, wherein transmittance of the transmission area may be increased. However, this is merely an example, and the scope of the disclosure is not limited thereto.

Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

According to an exemplary embodiment, a display apparatus includes a buffer layer on a substrate, a first hole penetrating the buffer layer and exposing a portion of the substrate, a display layer with display elements and bypass lines on the buffer layer, a second hole penetrating the display layer and connected to the first hole, and an encapsulation member covering the display elements and the bypass lines. The bypass lines are configured to extend along a portion of a perimeter of the second hole and are disposed between the second hole and the display elements. At least a portion of an upper surface of the buffer layer is exposed by the second hole.

According to an exemplary embodiment of the present invention, a method of manufacturing a display apparatus includes forming a buffer layer on a substrate, forming a first hole penetrating the buffer layer and exposing a portion of the substrate, forming a display layer on the buffer layer, the display layer including display elements and bypass lines, forming a second hole penetrating the display layer, and forming an encapsulation member to cover the display layer. The second hole is connected to the first hole and concentric thereto. At least a portion of an upper surface of the buffer layer is exposed by the second hole. The first hole is formed after the second hole is formed.

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the exemplary embodiments are merely described below, by referring to the figures, to explain aspects of the present description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used to denote the same elements, and repeated descriptions thereof will be omitted.

It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various components, these components should not be limited by these terms.

An expression used in the singular encompasses the expression of the plural, unless it has a clearly different meaning in the context.

It will be further understood that the terms “comprises” and/or “comprising” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

It will be understood that when a layer, region, or element is referred to as being “formed on” another layer, region, or element, it can be directly or indirectly formed on the other layer, region, or element. For example, for example, intervening layers, regions, or elements may be present.

Sizes of elements in the drawings may be exaggerated for convenience of explanation. In other words, since sizes and thicknesses of components in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.

When a certain embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order.

It will be understood that when a layer, region, or component is connected to another portion, the layer, region, or component may be directly connected to the portion or an intervening layer, region, or component may exist, such that the layer, region, or component may be indirectly connected to the portion. For example, when a layer, region, or component is electrically connected to another portion, the layer, region, or component may be directly electrically connected to the portion or may be indirectly connected to the portion through another layer, region, or component.

1 FIG. is a perspective view of a display apparatus according to an exemplary embodiment.

1 FIG. 1 1 2 1 2 2 2 1 2 1 1 1 Referring to, a display apparatusmay include a first area Aand a second area Asurrounding the first area A. A plurality of pixels, for example, an array of pixels, may be arranged in the second area A, and the second area Amay display an image through the array of pixels. The second area Acorresponds to an active area capable of displaying an image. The first area Amay be entirely surrounded by the second area A. The first area Amay be an area in which a component for providing various functions to the display apparatusis arranged. For example, when the component includes a sensor, a camera, or the like using light, the first area Acorresponds to a transmission area through which light of the sensor or light traveling to the camera may pass.

3 1 2 3 1 3 4 2 4 A third area Amay be provided between the first area Aand the second area A. The third area A, which is a non-display area in which pixels are not arranged, may include lines bypassing the first area A. Similarly to the third area A, a fourth area Asurrounding the second area Amay be a non-display area in which pixels are not arranged. Various types of lines, internal circuits, and the like may be in the fourth area A.

1 Each pixel included in the display apparatusmay include a light-emitting diode as a display element capable of emitting light of a certain color. The light-emitting diode may include an organic light-emitting diode including an organic material, as a light emitting layer. Alternatively, the light-emitting diode may include an inorganic light-emitting diode. Alternatively, the light-emitting diode may include a quantum dot as a light emitting layer. Hereinafter, for convenience of description, a case in which a light-emitting diode includes an organic light-emitting diode will be described.

1 FIG. 1 2 1 1 1 1 1 In, the first area Ais arranged in the center of the second area Ain a width direction of the display apparatus(e.g., a ±x direction), but in an exemplary embodiment, the first area Amay be arranged to be offset from the left side or the right side in the width direction of the display apparatus. In addition, the first area Amay be arranged at various positions, for example, in an upper side, in the middle, or in a lower side in a longitudinal direction of the display apparatus(e.g., ±y direction).

1 FIG. 1 1 1 1 illustrates that the display apparatusincludes one first area A. The present invention is not limited thereto. In an exemplary embodiment, the display apparatusmay include a plurality of first areas A.

2 FIG. 1 FIG. 1 is a cross-sectional view schematically showing the display apparatusaccording to an exemplary embodiment, and may correspond to a cross section taken along line II-II′ in.

2 FIG. 1 10 40 10 50 60 60 50 1 Referring to, the display apparatusmay include a display panel, an input sensing section (e.g., a touch sensor)on the display panel, and an optical functional section. These may be covered with a window. The windowmay be coupled with components therebelow, such as the optical functional sectionthrough an adhesive layer, such as an optical clear adhesive OCA. The display apparatusmay be provided in various electronic devices such as a mobile phone, a tablet PC, a notebook computer, and a smart watch.

10 2 40 40 40 10 40 The display panelmay include a plurality of diodes arranged in the second area A. The input sensing sectionmay obtain coordinate information according to an external input, for example, a touch event. The input sensing sectionmay include a sensing electrode (or a touch electrode) or trace lines connected to the sensing electrode. The input sensing sectionmay be on the display panel. The input sensing sectionmay sense an external input by a mutual capacitance method or a self capacitance method, for example.

40 10 40 10 40 10 2 FIG. The input sensing sectionmay be directly (i.e., integrally) formed on the display panel. Alternatively, the input sensing sectionmay be separately formed and then coupled to the display panelthrough an adhesive layer such as the optical clear adhesive OCA. In an exemplary embodiment, as illustrated in, the input sensing sectionmay be formed directly on the display panel, and in this case, the adhesive layer may be omitted.

50 10 60 The optical functional sectionmay include an antireflection layer. The antireflection layer may reduce the reflectance of light (external light) incident from the outside toward the display panelthrough the window. The antireflection layer may include a retarder and a polarizer. The retarder may be of a film type or a liquid crystal coating type, and may include a λ/2 retarder and/or a λ/4 retarder. The polarizer may also be of a film type or a liquid crystal coating type. The film type may include a stretch-type synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a certain arrangement. The retarder and the polarizer may further include a protective film.

10 In an exemplary embodiment, the antireflection layer may include a structure of a black matrix and color filters. The color filters may be arranged considering the color of light emitted from each of the pixels of the display panel. In an exemplary embodiment, the antireflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer on different layers from each other. First reflected light and second reflected light respectively reflected by the first reflective layer and the second reflective layer may be destructively interfered, and thus external light reflectance may be reduced.

50 10 50 The optical functional sectionmay include a lens layer. The lens layer may increase luminous efficiency of light emitted from the display panelor may reduce color deviation. The lens layer may include a layer having a concave or convex lens shape or/and may include a plurality of layers having different refractive indices. The optical functional sectionmay include all or any one of the antireflection layer and the lens layer, which are described above.

40 50 40 50 40 40 40 50 50 50 40 40 50 50 1 40 40 50 50 40 50 Each of the input sensing sectionand the optical functional sectionmay include a hole. In an exemplary embodiment, a hole may penetrate each of the input sensing sectionand the optical functional section. For example, the input sensing sectionmay include a holeH penetrating through upper and lower surfaces of the input sensing section, and the optical functional sectionmay include a holeH penetrating upper and lower surfaces of the optical functional section. The holeH of the input sensing sectionand the holeH of the optical functional sectionmay be in the first area Aand may be connected to each other. In an exemplary embodiment, the holeH may penetrate the input sensing section, and the holeH may penetrate the optical functional section. The holeH and the holeH may be positioned in the first area and may be connected to each other.

60 50 1 50 When the adhesive layer between the windowand the optical functional sectionincludes the optical clear adhesive OCA, the adhesive layer may not include a hole in the first area A. In an example embodiment, the optical clear adhesive OCA may cover an upper entrance of the holeH.

20 1 20 20 1 20 A componentmay be in the first area A. The componentmay include an electronic element. For example, the componentmay include an electronic component utilizing light or sound. For example, the electronic component may include a sensor that receives light, such as an infrared sensor, a camera that captures an image by receiving light, a sensor that outputs and detects light and sound to measure distance or recognize fingerprints, a small lamp that outputs light, a speaker that outputs sound, and the like. In the case of an electronic element using light, light of various wavelength bands such as visible light, infrared light, ultraviolet light, and the like may be used. In some exemplary embodiments, the first area Amay be a transmission area in which light that is output from the componentto the outside or that travels from the outside toward the electronic element may be transmitted.

1 20 1 20 60 60 1 In an exemplary embodiment, when the display apparatusis used as a smart watch or a vehicle instrument panel, the componentmay be a member such as a clock needle or a needle indicating certain information (e.g., vehicle speed, etc.). When the display apparatusincludes a clock needle or a vehicle instrument panel, the componentmay be exposed to the outside through the window. The windowmay include an opening in the first area A.

20 1 10 The componentmay include component(s) capable of adding a certain function to the display apparatusas described above, or may include components, such as accessories, that increase aesthetics of the display panel.

3 FIG. 10 is a cross-sectional view of the display panelaccording to an exemplary embodiment.

3 FIG. 10 200 100 100 100 2 Referring to, the display panelincludes a display layeron the substrate. The substratemay include a glass material or a polymer resin. For example, the substratemay include a glass material containing SiO, or a resin such as a reinforced plastic.

200 2 200 The display layermay be located in the second area Aand may include a plurality of pixels. Each of the pixels included in the display layermay include a pixel circuit and a display element electrically connected to the pixel circuit. The pixel circuit may include a transistor and a storage capacitor, and the display element may include a light-emitting diode, for example, an organic light-emitting diode OLED.

200 300 300 300 300 300 100 100 300 4 200 100 300 100 2 2 The display layermay be covered with an encapsulation substrateA. The encapsulation substrateA may be also referred to as an encapsulation member. The encapsulation substrateA may include a glass material or may include a polymer resin. For example, the encapsulation substrateA may include a glass material containing SiO, or a resin such as a reinforced plastic. The encapsulation substrateA may be arranged to face the substrate, and a sealant ST may be between the substrateand the encapsulation substrateA. The sealant ST is in the fourth area Aand may entirely surround the display layerbetween the substrateand the encapsulation substrateA. When viewed in a direction perpendicular to an upper surface of the substrate(or on a plan view), the second area Amay be entirely surrounded by the sealant ST.

2 100 300 The sealant ST may be an inorganic material, and may be, for example, a frit. The sealant ST may be formed by applying a dispenser or a screen printing method. A frit generally refers to a glass raw material in powder form, but in the disclosure, the frit also includes a paste state in which a main material, such as SiO, contains a laser or infrared absorber, an organic binder, and a filler for reducing a coefficient of thermal expansion. The frit in the paste state may be cured by removing the organic binder and moisture through a drying or firing process. The laser or infrared absorber may include a transition metal compound. Laser may be used as a heat source for curing the sealant ST and bonding the substrateand the encapsulation substrateA together.

200 1 200 1 200 200 200 200 3 FIG. A portion of the display layer, for example, a portion in the first area A, may be removed. In this regard,illustrates that the display layerincludes a hole in the first area Athat is a transmission area. The display layermay further include not only the pixel circuits and the display elements described above, but also insulating layers between lines connected to each of the pixel circuits, between electrodes, and/or between electrodes of the display elements. For example, the hole of the display layermay be formed by overlapping respective holes of the above-described insulating layers provided in the display layer. Details of the hole of the display layerwill be described later below.

3 FIG. 200 300 200 illustrates that the display layeris sealed with the encapsulation substrateA and the sealant ST. However, the present invention is not limited thereto. In an exemplary embodiment, the display layermay be covered by a thin film encapsulation layer in which at least one inorganic encapsulation layer and at least one organic encapsulation layer are stacked.

4 FIG. 5 FIG. 10 10 is a plan view of the display panelaccording to an exemplary embodiment, andis an equivalent circuit diagram of a pixel that may be applied to the display panel.

10 1 2 1 3 1 2 4 2 The display panelmay include the first area A, the second area Asurrounding the first area A, the third area Abetween the first area Aand the second area A, and the fourth area Asurrounding the second area A.

10 2 1 2 1 2 5 FIG. The display panelmay include a plurality of pixels P in the second area A. As illustrated in, each pixel P may include a pixel circuit PC and a display element connected to the pixel circuit PC, for example, the organic light-emitting diode OLED. The pixel circuit PC may include a first transistor T, a second transistor T, and a storage capacitor Cst. Each pixel P may emit, for example, red, green, or blue light from the organic light-emitting diode OLED. Alternatively, each pixel P may emit, for example, red, green, blue, or white light from the organic light-emitting diode OLED. The first transistor Tand the second transistor Tmay be thin-film transistors.

2 1 2 2 The second transistor Tis a switching transistor which is connected to a scan line SL and a data line DL and may be configured to transfer a data voltage input from the data line DL to the first transistor Taccording to a switching voltage input from the scan line SL. The storage capacitor Cst is connected to the second transistor Tand a driving voltage line PL and may store a voltage corresponding to a difference between a voltage received from the second transistor Tand a first power supply voltage ELVDD supplied to the driving voltage line PL.

1 The first transistor Tis a driving transistor which is connected to the driving voltage line PL and the storage capacitor Cst and may control a driving current flowing to the organic light-emitting diode OLED from the driving voltage line PL corresponding to a voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED may emit light having certain luminance according to the driving current. An opposite electrode (e.g., cathode) of the organic light-emitting diode OLED may be supplied with a second power supply voltage ELVSS.

5 FIG. Althoughillustrates that the pixel circuit PC includes two transistors and one storage capacitor, in an exemplary embodiment, the number of transistors and the number of storage capacitors may vary according to the design of the pixel circuit PC.

4 FIG. 3 1 3 1 3 4 1100 1200 1300 1100 1200 4 2 2 Referring again to, the third area Amay surround the first area A. The third area Ais an area in which a display element such as an organic light-emitting diode that emits light is not arranged, and signal lines that provide signals to the pixels P provided around the first area Amay pass through the third area A. The fourth area Amay include a first scan driverfor providing a scan signal to each pixel P, a second scan driver, a data driverfor providing a data signal to each pixel P, and a main power line (not shown) for providing first and second power supply voltages. The first scan driverand the second scan drivermay be arranged in the fourth area A, and may be arranged on opposite sides of the second area A, respectively, with the second area Atherebetween.

4 FIG. 1300 100 1300 10 shows that the data driveris adjacent to one side of the substrate. However, the present invention is not limited thereto. In an exemplary embodiment, the data drivermay be on a flexible printed circuit board (FPCB) electrically connected to a pad on one side of the display panel.

6 FIG. is a plan view of a portion of a display panel according to an exemplary embodiment.

6 FIG. 6 FIG. 6 FIG. 2 1 1 1 Referring to, some of the pixels P formed in the second area Amay be spaced apart from each other with respect to the first area A. For example, the first area Amay be between two pixels P arranged in the ±x direction of. Similarly, the first area Amay be between two pixels P arranged in a ±y direction of.

1 3 1 1 3 1 The two pixels P arranged in the ±y direction with the first area Atherebetween may be electrically connected to the same data line DL, but the data line DL may be bent in the third area A. For example, the data line DL may be arranged to bypass the first area A. For example, a portion of the data line DL may be bent and extended along an edge of the first area Ain the third area A, for example, in an arc direction of the first area A.

1 1 2 1 1 2 3 1 1 In an exemplary embodiment, the data line DL may be disconnected with the first area Atherebetween. For example, the data line DL may include a first data line DL-Land a second data line DL-Lspaced apart from each other with the first area Atherebetween. The first data line DL-Land the second data line DL-Lmay be connected to each other by a bypass line DWL. The bypass line DWL may be on a different layer from the data line DL and connected to the data line DL through a contact hole. The bypass line DWL may be in the third area Ato bypass the first area Aalong the edge of the first area A.

2 3 1 In the present specification, the bypass line DWL may refer to lines extending from the second area Aand passing through the third area Aas well as connection lines connecting disconnected lines that are disconnected with the first area Atherebetween.

1 1 1100 1 1200 10 1 1 4 FIG. 4 FIG. 4 FIG. In an exemplary embodiment, the two pixels P arranged in the ±x direction with the first area Atherebetween may be electrically connected to different scan lines SL. The scan lines SL on the left side of the first area Amay be electrically connected to the first scan driverdescribed with reference to, and the scan lines SL on the right side of the first area Amay be electrically connected to the second scan driverdescribed above with reference to. As shown in, when the display panelincludes two scan driving circuits, the pixels P at opposite sides of the first area Amay be electrically connected to the scan lines SL that are spaced apart from each other, respectively. For example, some scan lines SL may be spaced apart from each other with the first area Atherebetween.

1200 1 1 3 In an exemplary embodiment, when the second scan driveris omitted, the two pixels P arranged in the ±x direction with the first area Atherebetween may be connected to the same scan line. Like the data line DL, the above-described scan line may include a bypass portion extending in the arc direction of the first area Ain the third area A.

7 FIG. 6 FIG. is a cross-sectional view of any one pixel according to an exemplary embodiment, and may correspond to a cross section taken along line VIII-VIII′ in.

7 FIG. 100 100 100 Referring to, the pixel circuit PC may be on the substrate, and the organic light-emitting diode OLED electrically connected to the pixel circuit PC may be on the pixel circuit PC. The substratemay include glass or a polymer resin. The substratemay be a single layer or multiple layers.

101 100 100 100 101 100 101 A buffer layermay be on the substrateto reduce or block the penetration of foreign matter, moisture, or outside air from a lower portion of the substrate, and may provide a flat surface on the substrate. The buffer layermay include an inorganic material, such as oxide or nitride, an organic material, or an organic-inorganic composite material, and may have a single layer structure or a multilayer structure including an inorganic material or an organic material. A barrier layer (not shown) may be further between the substrateand the buffer layerto block penetration of outside air.

101 201 The pixel circuit PC may be on the buffer layer. The pixel circuit PC may include a thin-film transistor TFT and the storage capacitor Cst. The thin-film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. The present embodiment shows a top gate type in which the gate electrode GE is on the semiconductor layer Act with a gate insulating layeras a center. However, the present invention is not limited thereto. In an exemplary embodiment, the thin-film transistor TFT may be a bottom gate type.

The semiconductor layer Act may include polysilicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, an organic semiconductor, or the like. The gate electrode GE may include a low resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a single layer or multiple layers including the above-described materials.

201 201 The gate insulating layerbetween the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and the like. The gate insulating layermay include a single layer or multiple layers including the above-described materials.

The source electrode SE and the drain electrode DE may include a material having good conductivity. The source electrode SE and the drain electrode DE may include a conductive material including Mo, Al, Cu, Ti, or the like, and may be formed as a single layer or multiple layers including the above-described materials. In an exemplary embodiment, the source electrode SE and the drain electrode DE may include multiple layers of Ti/Al/Ti.

1 2 203 1 205 7 FIG. The storage capacitor Cst may include a lower electrode CEand an upper electrode CEwhich overlap each other with a first interlayer insulating layertherebetween. The storage capacitor Cst may overlap the thin-film transistor TFT. In this regard,shows that the gate electrode GE of the thin-film transistor TFT is the lower electrode CEof the storage capacitor Cst. The present invention is not limited thereto. In an exemplary embodiment, the storage capacitor Cst may not overlap the thin-film transistor TFT. The storage capacitor Cst may be covered with a second interlayer insulating layer.

203 205 203 205 Each of the first interlayer insulating layerand the second interlayer insulating layermay include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and/or the like. Each of the first interlayer insulating layerand the second interlayer insulating layermay include a single layer or multiple layers including the above materials.

207 207 207 207 209 The pixel circuit PC including the thin-film transistor TFT and the storage capacitor Cst may be covered with a planarization layer. The planarization layermay include an approximately planar upper surface. The planarization layermay include an organic insulation material. In an exemplary embodiment, the organic insulation material of the planarization layermay include a general commercial polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative including a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol polymer, and a blend thereof. In an exemplary embodiment, the planarization layermay include polyimide.

221 207 221 221 221 2 3 2 3 A pixel electrodemay be formed on the planarization layer. The pixel electrodemay include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (InO), indium gallium oxide (IGO), and/or aluminum zinc oxide (AZO). In an exemplary embodiment, the pixel electrodemay include a reflective layer including silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In an exemplary embodiment, the pixel electrodemay further include a film formed of ITO, IZO, ZnO, or InOabove or below the reflective layer.

215 221 215 221 221 215 215 215 215 A pixel defining layermay be formed on the pixel electrode. The pixel defining layermay include an opening exposing a portion of an upper surface of the pixel electrodeand may cover an edge of the pixel electrode. The pixel defining layermay include an organic insulating material. Alternatively, the pixel defining layermay include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. Alternatively, the pixel defining layermay include an organic insulating material and an inorganic insulating material. Hereinafter, for convenience of description, a case where the pixel defining layerincludes an organic insulating material will be mainly described in detail.

222 222 222 222 222 222 222 222 222 b b b a b c b. An intermediate layermay include a light emitting layer. The light emitting layermay include, for example, an organic material. The light emitting layermay include a polymer organic material or a low molecular weight organic material that emits light of a certain color. The intermediate layermay include a first functional layerunder the light emitting layerand/or a second functional layeron the light emitting layer

222 222 222 222 222 a a a a a The first functional layermay include a single layer or multiple layers. For example, when the first functional layerincludes a polymer material, the first functional layer, which is a hole transport layer (HTL) having a single-layer structure, may include poly-(3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). When the first functional layeris formed of a low molecular weight material, the first functional layermay include a hole injection layer (HIL) and a hole transport layer (HTL).

222 222 222 222 222 222 c a b c c c The second functional layermay be optional. For example, when the first functional layerand the light emitting layerinclude a polymer material, the second functional layermay be formed. The second functional layermay include a single layer or multiple layers. The second functional layermay include an electron transport layer (ETL) and/or an electron injection layer (EIL).

222 222 2 222 215 221 222 222 222 2 3 b b a c 4 FIG. The light emitting layerin the intermediate layermay be arranged for each pixel in the second area A. The light emitting layermay be arranged to overlap an opening of the pixel defining layerand/or the pixel electrode. The first and second functional layersandof the intermediate layerare formed as a single body, respectively, and may be formed not only in the second area Abut also in the third area Adescribed above with reference to.

223 223 223 223 211 2 222 223 2 3 The opposite electrodemay include a conductive material having a low work function. For example, the opposite electrodemay include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the opposite electrodemay further include a layer such as ITO, IZO, ZnO, or InOon the (semi) transparent layer including the above-mentioned material. The opposite electrodeis a single body and may be formed to cover the plurality of pixel electrodesin the second area A. The intermediate layerand the opposite electrodemay be formed by thermal evaporation.

217 215 217 217 A spacermay be formed on the pixel defining layer. The spacermay include an organic insulating material such as polyimide. Alternatively, the spacermay include an inorganic insulating material such as silicon nitride or silicon oxide, or may include an organic insulating material and an inorganic insulating material.

217 215 217 215 215 217 215 217 In an exemplary embodiment, the spacermay include a material different from that of the pixel defining layer. Alternatively, in an exemplary embodiment, the spacermay include the same material as that of the pixel defining layer. In this case, the pixel defining layerand the spacermay be formed together in a mask process using a halftone mask or the like. In an exemplary embodiment, the pixel defining layerand the spacermay include polyimide.

230 223 230 230 A capping layermay be on the opposite electrode. The capping layermay include LiF, an inorganic material, or/and an organic material. In an exemplary embodiment, the capping layermay be omitted.

8 FIG. 40 is a plan view of the input sensing sectionon a display panel according to an exemplary embodiment.

8 FIG. 40 410 415 1 415 4 410 420 425 1 425 5 420 410 420 2 415 1 415 4 425 1 425 5 4 Referring to, the input sensing sectionmay include first sensing electrodes, first trace lines-to-connected to the first sensing electrodes, second sensing electrodes, and second trace lines-to-connected to the second sensing electrodes. The first sensing electrodesand the second sensing electrodesmay be arranged in the second area A, and the first trace lines-to-and the second trace lines-to-may be arranged in the fourth area A.

410 420 410 411 410 410 1 410 4 420 421 420 420 1 420 5 410 1 410 4 420 1 420 5 410 1 410 4 420 1 420 5 The first sensing electrodesmay be arranged in the ±y direction, and the second sensing electrodesmay be arranged in the ±x direction crossing the ±y direction. The first sensing electrodesarranged in the ±y direction may be connected to each other by a first connection electrodebetween the neighboring first sensing electrodes, and may form first sensing linesCtoC, respectively. The second sensing electrodesarranged in the ±x direction may be connected to each other by a second connection electrodebetween the neighboring second sensing electrodes, and may form second sensing linesRtoR, respectively. The first sensing linesCtoCand the second sensing linesRtoRmay cross each other. For example, the first sensing linesCtoCand the second sensing linesRtoRmay vertically cross each other.

410 1 410 4 440 415 1 415 4 4 415 1 415 4 410 1 410 4 415 1 415 4 410 1 410 4 The first sensing linesCtoCmay be connected to pads of a sensing signal pad portionthrough the first trace lines-to-formed in the fourth area A. For example, the first trace lines-to-may have a double routing structure connected to upper and lower sides of the first sensing linesCtoC, respectively. The first trace lines-to-connected to the upper and lower sides of the first sensing linesCtoCmay be connected to the corresponding pads, respectively.

420 1 420 5 440 425 1 425 5 4 425 1 425 5 The second sensing linesRtoRmay be connected to the pads of the sensing signal pad portionthrough the second trace lines-to-formed in the fourth area A. For example, the second trace lines-to-may be connected to corresponding pads, respectively.

2 FIG. 1 1 450 1 3 450 As described above with reference to, the first area Ais an area in which components may be arranged, and sensing electrodes are not in the first area A. A metal layermay be around the first area A, for example, in the third area A, and the metal layerwill be described later below.

8 FIG. 415 1 415 4 410 1 410 4 415 1 415 4 410 1 410 4 illustrates a double routing structure in which the first trace lines-to-are connected to the upper and lower sides of the first sensing linesCtoC, respectively, which may improve the sensing sensitivity. In an exemplary embodiment, the first trace lines-to-may have a single routing structure connected to the upper or lower sides of the first sensing linesCtoC.

9 FIG. 40 is a cross-sectional view of a stacked structure of the input sensing sectionaccording to an exemplary embodiment.

9 FIG. 8 FIG. 40 1 2 43 1 2 45 2 410 411 420 421 1 2 Referring to, the input sensing sectionmay include a first conductive layer CMLand a second conductive layer CML. A first insulating layermay be between the first conductive layer CMLand the second conductive layer CML, and a second insulating layermay be on the second conductive layer CML. Each of the first sensing electrodes, first connection electrodes, second sensing electrodes, and second connection electrodesdescribed with reference tomay be included in one of the first conductive layer CMLor the second conductive layer CML.

1 2 The first conductive layer CMLor the second conductive layer CMLmay include a metal layer or a transparent conductive layer. The metal layer may include Mo, mendelevium (Md), Ag, Ti, Cu, Al, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as ITO, IZO, ZnO, indium tin zinc oxide (ITZO), or the like. In addition, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, graphene, or the like.

1 2 1 2 1 2 1 2 1 2 1 2 1 2 The first conductive layer CMLor the second conductive layer CMLmay be a single layer or multiple layers. The first conductive layer CMLor the second conductive layer CMLof the single layer may include a metal layer or a transparent conductive layer, and materials of the metal layer and the transparent conductive layer are as described above. One of the first conductive layer CMLand the second conductive layer CMLmay include a single metal layer. One of the first conductive layer CMLand the second conductive layer CMLmay include a multi-layered metal layer. The multi-layered metal layer may include, for example, three layers of titanium layer/aluminum layer/titanium layer or two layers of molybdenum layer/mendelevium layer. Alternatively, the multilayer metal layer may include a metal layer and a transparent conductive layer. The first conductive layer CMLand the second conductive layer CMLmay have different stacked structures or have the same stacked structure. For example, the first conductive layer CMLmay include a metal layer and the second conductive layer CMLmay include a transparent conductive layer. Alternatively, the first conductive layer CMLand the second conductive layer CMLmay include the same metal layer.

1 2 1 2 The arrangement of materials of the first conductive layer CMLand the second conductive layer CMLand sensing electrodes provided in the first conductive layer CMLand the second conductive layer CMLmay be determined in consideration of the sensing sensitivity. Resistive-capacitive (RC) delay may affect the sensing sensitivity. Since sensing electrodes including a metal layer have less resistance compared to the transparent conductive layer, an RC value may be reduced, and thus the charging time of a capacitor defined between the sensing electrodes may be reduced. The sensing electrodes including the transparent conductive layer may not be visible to a user compared to the metal layer, and an input area of the sensing electrodes including the transparent conductive layer may be increased to increase the capacitance.

43 45 Each of the first insulating layerand the second insulating layermay include an inorganic insulating material or/and organic insulating material. The inorganic insulating material may include silicon oxide, silicon nitride, silicon oxynitride, or the like, and the organic insulating material may include a polymer organic material.

410 420 411 421 1 2 8 FIG. Some of the first sensing electrodes, the second sensing electrodes, the first connection electrodes, and the second connection electrodesdescribed above with reference tomay be included in the first conductive layer CML, and the rest may be included in the second conductive layer CML.

1 411 2 410 420 421 1 410 420 421 2 411 1 410 411 2 420 421 410 411 420 421 1 2 8 FIG. 8 FIG. 8 FIG. 8 FIG. 8 FIG. 8 FIG. 8 FIG. 8 FIG. 8 FIG. 8 FIG. In an exemplary embodiment, the first conductive layer CMLmay include the first connection electrodes(of), and the second conductive layer CMLmay include the first and second sensing electrodesand(of) and the second connection electrodes(of). In an exemplary embodiment, the first conductive layer CMLmay include the first and second sensing electrodesand(of) and the second connection electrodes(of), and the second conductive layer CMLmay include the first connection electrodes(of). In an exemplary embodiment, the first conductive layer CMLmay include the first sensing electrodes(of) and the first connection electrodes(of), and the second conductive layer CMLmay include the second sensing electrodes(of) and the second connection electrodes(of). In this case, since the first sensing electrodesand the first connection electrodesare provided on the same layer and are integrally connected, and the second sensing electrodesand the second connection electrodesare also provided on the same layer, a contact hole may not be provided in an insulating layer between the first conductive layer CMLand the second conductive layer CML.

9 FIG. 40 1 43 2 45 1 In, the input sensing sectionincludes the first conductive layer CML, the first insulating layer, the second conductive layer CML, and the second insulating layer. However, the present invention is not limited thereto. In an exemplary embodiment, a buffer layer including an inorganic insulating material, or an organic insulating material may further be under the first conductive layer CML.

10 FIG. is a plan view of a portion of a display apparatus according to an exemplary embodiment.

10 FIG. 410 420 420 421 410 411 411 411 410 411 421 421 421 b Referring to, the first sensing electrodesmay be arranged in the ±y direction, the second sensing electrodesmay be arranged in the ±x direction, and the neighboring second sensing electrodesmay be connected to each other through the second connection electrodelocated therebetween. The first sensing electrodesmay be connected to each other through the first connection electrode, wherein the first connection electrodemay include an island portionapart from the first sensing electrodes. The first connection electrodemay be in a hole formed in the second connection electrode, and is apart from the second connection electrodeto be electrically insulated from the second connection electrode.

410 411 411 410 411 411 411 411 411 411 411 410 420 421 2 411 410 420 421 411 411 411 1 411 411 b a b c a b c b b a c b a c. 9 FIG. 9 FIG. 9 FIG. 9 FIG. One of the neighboring first sensing electrodesmay be connected to the island portionthrough a first bridge portion, and the other of the first sensing electrodesmay be connected to the island portionthrough a second bridge portion. The first connection electrodemay include a connection structure of the first bridge portion, the island portion, and the second bridge portion. In an exemplary embodiment, island portionsmay be on the same layer as the first sensing electrodes, the second sensing electrodes, and the second connection electrodes. For example, the second conductive layer CML(of) described above with reference tomay include the island portions, the first sensing electrodes, the second sensing electrodes, and the second connection electrodes. In an exemplary embodiment, the first bridge portionsand the second bridge portionsmay be on a different layer from the island portions. For example, the first conductive layer CML(of) described above with reference tomay include the first bridge portionsand the second bridge portions

430 410 420 430 431 432 410 420 431 432 430 430 10 FIG. A dummy electrodemay be between a first sensing electrodeand a second sensing electrodeneighboring each other. For example, as illustrated in, the dummy electrodemay include a first dummy electrodeand a second dummy electrodeextending along an edge of the first sensing electrodeor the second sensing electrode. For example, the extended first dummy electrodeand the second dummy electrodemay have a zigzag shape. The dummy electrodemay be arranged to improve the sensing sensitivity. The dummy electrodemay be a floating electrode.

410 420 1 410 420 1 Shapes of the first sensing electrodesand the second sensing electrodesaround the first area Amay be different from those of other sensing electrodes. An area of the first sensing electrodesand the second sensing electrodesaround the first area Amay be less than that of other sensing electrodes.

410 420 1 410 420 1 Each of the first sensing electrodesand the second sensing electrodesadjacent to the first area Amay include a rounded edge, and an array of the rounded edges of each of the first sensing electrodeand the second sensing electrodemay have a shape surrounding the first area A.

450 1 410 420 410 420 2 450 3 The metal layermay be between the first area Aand the first and second sensing electrodesand. The first sensing electrodeand the second sensing electrodemay be in the second area A, which is an active area, and the metal layermay be in the third area A.

450 3 3 450 1 20 1 2 FIG. The metal layermay be in the third area Ato cover bypass lines DWL arranged in the third area A. When the bypass layers DWL are exposed without being covered because the metal layeris not arranged, external light incident through the first area Amay be reflected by the bypass lines DWL to be viewed or may affect characteristics of the component(of) that may be in the first area A.

450 1 However, according to the embodiments of the disclosure, the influence of the reflected light may be minimized because the metal layeraround the first area Ablocks external light that is obliquely traveling.

450 1 450 1 450 450 410 420 430 The metal layerwith a certain width may surround the first area A. The metal layermay have a ring shape surrounding the first area Aon a plan view. The metal layermay include Mo, Md, Ag, Ti, Cu, Al, or an alloy thereof. The metal layermay be in a floating state that is not electrically connected to peripheral elements, such as the first and second sensing electrodesandand the dummy electrode.

11 FIG.A 11 FIG.B 11 FIG.A is a cross-sectional view of a display apparatus according to an exemplary embodiment.is an enlarged view of a first area and a third area of.

11 11 FIGS.A andB 101 201 203 205 207 100 Referring to, the buffer layer, the gate insulating layer, the first interlayer insulating layer, the second interlayer insulating layer, and the planarization layermay be on the substrate. The pixel circuit PC may include a thin-film transistor and a storage capacitor. A semiconductor layer and electrodes of the thin-film transistor and electrodes of the storage capacitor may be on the insulating layers described above.

221 207 The pixel electrodemay be connected to the thin-film transistor of the pixel circuit PC through a contact hole of the planarization layer.

215 221 221 215 222 222 222 223 230 215 200 100 a b c 7 FIG. The pixel defining layeron the pixel electrodemay include an opening overlapping the pixel electrode, and the opening of the pixel defining layermay define a light-emitting area EA. The first functional layer, the light emitting layer, the second functional layer, the opposite electrode, and the capping layermay be on the pixel defining layer. Materials and features of the display layeron the substrateare as described above with reference to.

1 101 200 222 222 223 230 1 a c Through holes in the first area Amay be provided in insulating layers included in the buffer layerand the display layer, the first functional layer, the second functional layer, the opposite electrode, and the capping layer. Accordingly, light transmittance of the first area Amay increase.

101 1 1 1 101 100 101 101 1 101 101 1 The buffer layermay include a first hole Hin the first area A. For example, the first hole Hmay penetrate the buffer layerto expose a portion of the substrate. In an exemplary embodiment, a side surfaceS of the buffer layerincluding the first hole Hmay be provided to be inclined. In an exemplary embodiment, the side surfaceS of the buffer layerincluding the first hole Hmay be curved.

201 203 205 207 215 201 203 205 207 215 2 2 1 201 203 205 207 215 2 1 2 1 2 101 1 As described above, the insulating layers may include at least one inorganic insulating layer and at least one organic insulating layer. For example, the at least one inorganic insulating layer may be one of the gate insulating layer, the first interlayer insulating layer, or the second interlayer insulating layer, and the at least one organic insulating layer may be one of the planarization layeror the pixel defining layers. Through holes respectively formed in the gate insulating layer, the first interlayer insulating layer, the second interlayer insulating layer, the planarization layer, and the pixel defining layermay overlap each other to form a second hole H. In an exemplary embodiment, the second hole Hmay penetrate, in the first area A, the gate insulating layer, first interlayer insulating layer, the second interlayer insulating layer, the planarization layer, and the pixel defining layer. The second hole Hmay be a stepped side surface with a decreasing width toward the first hole H. A minimum width of the second hole Hmay be greater than a width of the first hole H. In an exemplary embodiment, the second hole Hmay expose a portion of the buffer layerwhich is adjacent to the first hole H.

3 1 201 203 205 3 3 3 205 205 The inorganic insulating layer may include a third hole Hin the first area A. For example, through holes of the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layermay overlap to form the third hole H. In an exemplary embodiment, a side surface of the inorganic insulating layer having the third hole H(i.e., a side surface of the third hole H) may be inclined. For example, a side surfaceS of the second interlayer insulating layermay be inclined. In an exemplary embodiment, a side surface of the inorganic insulating layer may be curved.

1 5 207 1 6 215 1 207 207 5 215 6 101 1 101 205 207 215 The organic insulating layer may include a fourth hole in the first area A. The fourth hole may be formed by overlapping a fifth hole Hpenetrating the planarization layerin the first area Aand a sixth hole Hpenetrating the pixel defining layerin the first area A. In an exemplary embodiment, a side surfaceS of the planarization layerhaving the fifth hole Hor a side surface of the pixel defining layerhaving the sixth hole Hmay be inclined like the side surfaceS of the first hole Hin the buffer layeror the side surfaceS of the inorganic insulating layer. In an exemplary embodiment, the side surfaceS or the side surface of the pixel defining layermay be curved.

101 101 2 101 101 3 101 101 3 1 3 At least a portionU of an upper surface of the buffer layermay be exposed by the second hole H. In an exemplary embodiment, the portionU of the upper surface of the buffer layermay be exposed by the third hole Hof the inorganic insulating layer. Therefore, the portionU of the upper surface of the buffer layermay be exposed in the third area A. For example, inner surfaces of the first hole Hand the third hole Hmay be arranged to be offset from each other to form a step.

101 101 2 101 101 3 3 2 101 3 1 101 101 3 The portionU of the upper surface of the buffer layermay be defined by a bottom of the second hole H. In an exemplary embodiment, the portionU of the upper surface of the buffer layermay be defined by a bottom of the third hole H. The bottom of the third hole Hmay be the bottom of the second hole H. For example, the buffer layermay extend from the third area Ainto the first area A, and the portionU of the upper surface of the buffer layeris the inside of the third hole H.

1 2 1 2 1 2 As described above, inner surfaces of the first hole Hand the second hole Hmay have a step because the first hole Hand the second hole Hare not formed at the same time but are formed by different process procedures. For example, the first hole Hmay be formed using a first mask, and the second hole Hmay be formed using a second mask different from the first mask.

1 2 101 200 1 101 1 1 When the first hole Hand the second hole Hare simultaneously formed by one process procedure, both the buffer layerand the display layerin the first area Aneed to be removed by the process procedure. In this case, a portion of the buffer layerin the first area Amay remain so that the first hole Hmay not be formed.

1 2 101 1 1 2 In the present embodiment, the first hole Hmay be formed by a different process procedure from the second hole H, and the buffer layerin the first area Amay be removed. Detailed description of a method of forming the first hole Hand the second hole Hwill be described later below.

205 205 5 207 205 205 3 3 5 At least a portion of an upper surface of the inorganic insulating layer may be exposed by the fourth hole. In an exemplary embodiment, at least a portionU of an upper surface of the second interlayer insulating layermay be exposed by the fifth hole Hof the planarization layer. Therefore, the portionU of the upper surface of the second interlayer insulating layermay be exposed in the third area A. For example, inner surfaces of the third hole Hand the fifth hole Hmay be arranged to be offset from each other to form a step.

205 205 5 205 3 1 5 At least a portion of the upper surface of the inorganic insulating layer may be arranged in the inside of the fourth hole. In an exemplary embodiment, the portionU of the upper surface of the second interlayer insulating layermay be arranged to correspond to the inside of the fifth hole H. For example, the second interlayer insulating layermay extend in a direction from the third area Ato the first area Ato correspond to the inside of the fifth hole H.

207 207 6 207 207 3 5 6 At least a portionU of an upper surface of the planarization layermay be exposed by the sixth hole H. Therefore, the portionU of the upper surface of the planarization layermay be exposed in the third area A. For example, inner surfaces of the fifth hole Hand the sixth hole Hmay be arranged to be offset from each other to form a step.

207 207 6 207 3 1 3 The portionU of the upper surface of the planarization layermay be arranged to correspond to the inside of the sixth hole H. For example, the planarization layermay extend in the direction from the third area Ato the first area Ato correspond to the inside of the sixth hole H.

3 5 6 1 2 As described above, the inner side surfaces of the third hole H, the fifth hole H, and the sixth hole Hare arranged to be offset from each other, and thus a step is formed. This is because processes for forming each hole may be different from each other in the same manner as the first hole Hand the second hole Hform a step.

222 222 223 230 1 220 220 6 220 5 222 222 223 230 207 222 222 223 230 220 a c a c a c In addition, through holes respectively formed in the first functional layer, the second functional layer, the opposite electrode, and the capping layerto correspond to the first area Amay overlap each other, and an intermediate through holeH may be provided accordingly. In an exemplary embodiment, the diameter of the intermediate through holeH may be less than the diameter of the sixth hole H. In addition, the diameter of the intermediate through holeH may be greater than the diameter of the fifth hole H. For example, the first functional layer, the second functional layer, the opposite electrode, and the capping layermay be on the upper surface of the planarization layer. In this case, the first functional layer, the second functional layer, the opposite electrode, and the capping layermay be formed using a mask having a shielding film corresponding to the intermediate through holeH.

300 100 200 300 100 1 1 100 300 The encapsulation substrateA is arranged to face the substrate. In an exemplary embodiment, materials included in the display layerare not between a lower surface of the encapsulation substrateA and the upper surface of the substratein the first area A. In other words, in the first area A, the upper surface of the substratemay directly face the lower surface of the encapsulation substrateA.

300 100 100 300 The encapsulation substrateA may include the same material as the substrateand may have the same refractive index. For example, the substrateand the encapsulation substrateA may have a refractive index of about 1.3 to about 1.7, for example, about 1.5.

450 3 450 3 The metal layermay be in the third area A. The metal layermay overlap the bypass lines DWL in the third area A.

450 300 415 450 4 300 415 4 11 11 FIGS.A andB The metal layermay directly contact an upper surface of the encapsulation substrateA. In this regard,illustrate that first trace linesand the metal layerlocated in the fourth area Aare arranged directly on the upper surface of the encapsulation substrateA, respectively. At least one of trace lines, for example, the first trace lines, in the fourth area Amay overlap the sealant ST.

43 450 45 43 43 45 43 45 1 The first insulating layersuch as silicon nitride, silicon oxide, or silicon oxynitride is on the metal layer. Sensing electrodes and the second insulating layermay be sequentially arranged on the first insulating layer. The first insulating layerand the second insulating layermay include holesH andH in the first area A, respectively.

43 450 45 43 43 45 43 45 An end of the first insulating layermay cover an inner edge of the metal layer, and an end of the second insulating layermay cover the end of the first insulating layer. The first insulating layerand the second insulating layermay include the same material or different materials. Each of the first insulating layerand the second insulating layermay include an inorganic insulating material or an organic insulating material.

450 43 410 43 43 In an exemplary embodiment, the metal layeris under the first insulating layer. In an exemplary embodiment, the sensing electrodes including the first sensing electrodeand the second connection electrode may be under the first insulating layer, and a trace line may be arranged over the first insulating layer.

50 450 60 61 60 4 415 61 61 61 2 61 The optical functional sectionmay cover a portion of the metal layer, and a clear adhesive OCA and the windowmay be arranged thereon. A light shielding portionmay be on a rear surface of the windowto cover components arranged in the fourth area A, for example, components such as the first trace lines. The light shielding portioncovering a dead area may include a colored layer. For example, the light shielding portionmay include layers of various colors such as white, black, silver, gold, and pink. The light shielding portionmay have a polygonal ring or frame shape surrounding the second area A. For example, the light shielding portionmay have a substantially rectangular ring or frame shape.

1 1 3 In an exemplary embodiment, in the present embodiment, a distance from a center line CPL of the first area Ato each component may be set to provide transmittance of the first area Aand a step in which the holes are offset from each other. In addition, in order to reduce the area of the third area Awhich is a non-display area, the distance from the center line CPL to each element may be set.

11 FIG.B 1 1 3 3 1 3 Referring to, a first vertical distance d, which is the distance from the center line CPL to an edge of the first hole H, may be less than a third vertical distance d, which is the distance from the center line CPL to an edge of the third hole H. In this case, a difference between the first vertical distance dand the third vertical distance dmay be about 1 μm to about 2 μm.

3 5 5 5 6 6 The third vertical distance dmay be less than a fifth vertical distance d, which is the distance from the center line CPL to an edge of the fifth hole H. In addition, the fifth vertical distance dmay be less than a sixth vertical distance d, which is the distance from the center line CPL to an edge of the sixth hole H.

2 3 5 6 2 3 1 As described above, the second hole Hmay be provided by overlapping the third hole H, the fifth hole H, and the sixth hole H. In this case, since the minimum value of a second vertical distance from the center line CPL to an edge of the second hole His the same as the third vertical distance d, the first vertical distance dmay be less than the second vertical distance.

450 7 1 1 7 7 3 Metal layersmay have a seventh hole Hin the first area A. In an exemplary embodiment, the first vertical distance dmay be less than a seventh vertical distance dfrom the center line CPL to an edge of the seventh hole H. This may be to reduce the third area Awhich is a non-display area.

1 101 1 1 101 100 1 20 1 101 1 As described above, the first hole His provided in the buffer layerto correspond to the first area Ain order to increase the transmittance of the first area A. When the buffer layeris continuously arranged on the substrate, the transmittance of light/signal incident from the outside into the first area Aor the transmittance of light/signal emitted from the componentin the first area Amay be reduced. In the present embodiment, as the buffer layerincludes the first hole H, the transmittance of light/signal may be increased in the above situation.

101 1 12 12 FIGS.A toO Hereinafter, a method of manufacturing a display apparatus provided with the buffer layerincluding the first hole Hwill be described in detail with reference to.

12 12 FIGS.A toO 12 12 FIGS.A toO 11 11 FIGS.A andB are cross-sectional views illustrating a method of manufacturing a display apparatus according to an exemplary embodiment. In, the same reference numerals as those used indenote the same elements, and a duplicate description will not be given herein.

12 FIG.A 101 100 101 1 2 3 100 Referring to, the buffer layermay be continuously formed on the substrate. For example, the buffer layermay be continuously formed on the first area A, the second area A, and the third area Aon the substrate.

100 101 Although not shown, a barrier layer (not shown) through which outside air penetrates may be formed between the substrateand the buffer layer.

Next, a preliminary semiconductor pattern Act′ may be formed. The preliminary semiconductor pattern Act′ may include a silicon semiconductor material. After a semiconductor film is formed, the preliminary semiconductor pattern Act′ may be formed by patterning the semiconductor film.

Next, the preliminary semiconductor pattern Act′ may be crystallized. In an exemplary embodiment, the semiconductor film may be crystallized and patterned to form the preliminary semiconductor pattern Act′.

12 FIG.B 201 201 201 1 2 3 Next, referring to, the gate insulating layermay be formed. The gate insulating layermay be formed using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a plasma enhanced CVD (PECVD) process, a high density plasma-CVD (HDP-CVD) process, a vacuum deposition process, or the like. In an exemplary embodiment, the gate insulating layermay be continuously formed in the first area A, the second area A, and the third area Ato cover the preliminary semiconductor pattern Act′.

12 FIG.C 1 1 201 1 1 Next, referring to, the lower electrode CEand some of the bypass line DWL may be formed. The lower electrode CEand the bypass line DWL may be formed by forming a conductive layer on the gate insulating layerand then patterning the conductive layer. In an exemplary embodiment, when a gate electrode GE is different from the lower electrode CE, the gate electrode GE may also be formed in the same manner as the lower electrode CE.

1 Hereinafter, for convenience of description, a case where the lower electrode CEis the same as the gate electrode GE will be described in detail.

1 2 3 3 The lower electrode CEmay be formed to overlap the second area Aor the third area A, and a portion of the bypass line DWL may be formed to overlap the third area A.

1 1 Next, the preliminary semiconductor pattern Act′ may be doped with a semiconductor layer Act using the lower electrode CEas a mask. An area overlapping the lower electrode CE(hereinafter, referred to as a channel area) may be undoped, and opposite areas (input and output areas) of the channel region may be doped.

12 FIG.D 203 1 203 1 2 3 Next, referring to, the first interlayer insulating layermay be continuously formed to cover the lower electrode CEand the bypass line DWL. The first interlayer insulating layermay be continuously formed in the first area A, the second area A, and the third area A.

12 FIG.E 2 203 2 1 Next, referring to, the upper electrode CEand some of the bypass lines DWL may be formed on the first interlayer insulating layer. The upper electrode CEand some of the bypass lines DWL may be formed in the same manner as the lower electrode CE.

2 1 3 201 203 The upper electrode CEmay be formed to overlap the lower electrode CE. Some of the bypass lines DWL may be arranged in the third area A. The bypass line DWL on the gate insulating layerand the bypass line DWL on the first interlayer insulating layermay be alternately arranged. For example, one of the bypass lines DWL may be arranged so as not to overlap the other of the bypass lines DWL.

12 FIG.F 205 2 205 1 2 3 3 Next, referring to, after forming the second interlayer insulating layercovering the upper electrode CE, a bypass line may be formed. The second interlayer insulating layermay be continuously formed in the first area A, the second area A, and the third area A, and the bypass line may be formed in the third area A. The bypass lines may be arranged not to overlap each other.

12 FIG.G 201 203 205 1 3 1 1 3 Next, referring to, portions of the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layermay be removed. For example, a first contact hole CNTexposing an input area and an output area of the semiconductor layer Act may be formed. In addition, the third hole Hmay be formed in the first area A. The forming of the first contact hole CNTand the forming of the third hole Hmay be performed in a single process. Therefore, the number of masks used in the method of manufacturing the display apparatus may be reduced.

12 FIG.H 1 Next, referring to, a source electrode SE and a drain electrode DE may be formed to be connected to the semiconductor layer Act through the first contact hole CNT. After a conductive layer is formed through a deposition process, the source electrode SE and the drain electrode DE may be formed through a patterning process.

12 FIG.I 12 FIG.I 207 207 1 2 3 207 3 207 207 100 3 Next, referring to, the planarization layermay be formed. The planarization layermay be continuously arranged in the first area A, the second area A, and the third area A. Therefore, the planarization layermay be formed in the third hole H. In an exemplary embodiment, as shown in, the planarization layermay be formed such that the upper surface thereof includes a substantially flat surface. In an exemplary embodiment, the planarization layermay include a groove concave in a direction away from the substratein a region in the third hole H.

12 FIG.J 207 2 5 1 2 5 Next, referring to, a portion of the planarization layermay be removed. For example, a second contact hole CNTexposing the source electrode SE or the drain electrode DE may be formed. In addition, the fifth hole Hmay be formed in the first area A. In an exemplary embodiment, the forming of the second contact hole CNTand the forming of the fifth hole Hmay be performed in a single process. Therefore, the number of masks used in the method of manufacturing the display apparatus may be reduced.

5 3 207 205 3 In an exemplary embodiment, the diameter of the fifth hole Hmay be greater than the diameter of the third hole H. Accordingly, the planarization layerand the second interlayer insulating layermay be formed to form a step in the third area A.

12 FIG.K 221 221 2 221 Next, referring to, the pixel electrodemay be formed. For example, the pixel electrodemay be connected to the source electrode SE or the drain electrode DE through the second contact hole CNT. The pixel electrodemay be formed through a patterning process after forming a conductive layer through a deposition process.

12 FIG.L 101 1 1 101 1 101 1 Next, referring to, a portion of the buffer layermay be removed. For example, the first hole Hin the first area Amay be formed in the buffer layer. In an exemplary embodiment, the first hole Hmay be formed using a mask for removing a portion of the buffer layerin the first area A.

1 3 1 3 101 201 3 101 3 The diameter of the first hole Hmay be less than the diameter of the third hole H. A difference between the diameter of the first hole Hand the diameter of the third hole Hmay be about 1 μm to about 2 μm. In an exemplary embodiment, the buffer layerand the gate insulating layermay be formed to form a step in the third area A. Therefore, at least a portion of the upper surface of the buffer layermay be exposed in the third area A.

1 1 101 101 1 1 101 101 1 1 1 101 As described above, after holes are formed in an inorganic insulating layer in the first area A, the first hole His formed in the buffer layerto form the buffer layerin the first area A. When the first hole His formed in the buffer layerwhen forming holes in the inorganic insulating layer, a portion of the buffer layerin the first area Amay be left. In the present embodiment, after the holes are formed in the inorganic insulating layer and in the first area A, the forming of the first holes Hin the buffer layermay be performed to increase transmittance of the display apparatus.

12 FIG.M 215 215 1 2 3 Next, referring to, a preliminary insulating layer′ may be formed. The preliminary insulating layer′ may be continuously formed in the first area A, the second area A, and the third area A.

12 FIG.M 215 215 1 100 In an exemplary embodiment, as shown in, an upper surface of the preliminary insulating layer′ may be flat. In an exemplary embodiment, the preliminary insulating layer′ may include a groove in the first area Aand concave in a direction away from the substrate.

12 FIG.N 215 215 217 6 Next, referring to, a portion of the preliminary insulating layer′ may be removed, and the pixel defining layer, the spacer, and the sixth hole Hmay be formed.

215 217 215 217 215 217 217 215 217 215 215 217 In an exemplary embodiment, the pixel defining layermay be formed simultaneously with the spacer. For example, the pixel defining layerand the spacermay be simultaneously formed using a halftone mask. In this case, the pixel defining layerand the spacermay include the same material. In an exemplary embodiment, the spacermay be formed by a process different from that of the pixel defining layer. In this case, the spacermay be formed of a material different from that of the pixel defining layer. Hereinafter, for convenience of description, the case where the pixel defining layerand the spacerare simultaneously formed using a halftone mask will be mainly described in detail.

215 3 215 3 221 221 3 The pixel defining layermay be formed with a third contact hole CNT. The pixel defining layermay include a third contact hole CNTexposing the upper surface of the pixel electrodeand may be formed while covering the edge of the pixel electrode. The third contact hole CNTmay define a light-emitting area.

6 1 3 6 3 The sixth hole Hmay be formed in the first area Aand the third area A. In an exemplary embodiment, the sixth hole Hmay be formed by the same process as forming the third contact hole CNT. Therefore, the number of masks used in the method of manufacturing of the display apparatus may be reduced.

6 3 207 3 In an exemplary embodiment, the diameter of the sixth hole Hmay be greater than the diameter of the fifth hole H. Therefore, an upper surface of a portion of the planarization layerin the third area Amay be exposed.

12 FIG.O 222 222 222 223 230 222 222 222 223 230 220 a b c a b c Next, referring to, the first functional layer, the light emitting layer, the second functional layer, the opposite electrode, and the capping layermay be formed. In an exemplary embodiment, as described above, the first functional layer, the light emitting layer, the second functional layer, the opposite electrode, and the capping layermay be formed using a mask having a shielding film corresponding to the intermediate through holeH.

222 222 222 223 230 1 1 a b c In an exemplary embodiment, the first functional layer, the light emitting layer, the second functional layer, the opposite electrode, and the capping layermay be successively formed, and then an intermediate through hole may be formed using a laser beam. In this case, the diameter of the intermediate through hole may be less than the diameter of the first hole H. When the intermediate through hole is greater than the first hole H, an insulating layer may be damaged by the laser beam or outgassed.

200 2 3 1 2 101 200 1 300 200 11 FIG.A As described above, after the display layerincluding display elements in the second area Aand including the bypass lines DWL in the third area Amay be formed, and the first hole Hand the second hole Hare formed in a plurality of insulating layers and the buffer layerincluded in the display layerand in the first area A, the encapsulation substrateA () covering the display layermay be formed.

220 1 300 However, in an exemplary embodiment, after the intermediate through holeH is formed, a filler may be arranged in the first area Abefore the encapsulation substrateA is formed.

40 50 60 Next, the input sensing section, the optical functional section, and the windowmay be formed.

450 40 The metal layermay be formed in the same process as the process of forming the input sensing section, for example, the process of forming a trace line and a first connection electrode.

13 FIG. 13 FIG. 11 FIG.A is a cross-sectional view of a display apparatus according to an exemplary embodiment. In, the same reference numerals as those used indenote the same elements, and a duplicate description will not be given herein.

13 FIG. 100 1 101 200 300 450 50 60 101 1 1 200 2 101 2 Referring to, the display apparatus may include the substratehaving the first area Aas a transmission area, the buffer layer, the display layer, the encapsulation substrateA, the metal layer, the optical functional section, and the window. The buffer layermay include the first hole Hin the first area A, and the display layermay include the second hole H. In this case, at least a portion of the upper surface of the buffer layermay be exposed by the second hole H.

220 222 222 223 230 1 220 6 222 222 223 230 215 215 220 a c a c In the present embodiment, the intermediate through holeH may be provided as the through holes respectively formed in the first functional layer, the second functional layer, the opposite electrode, and the capping layerin the first area Aoverlap each other. In this case, the diameter of the intermediate through holeH may be greater than the diameter of the sixth hole H. Accordingly, the first functional layer, the second functional layer, the opposite electrode, and the capping layermay be on an upper surface of the pixel defining layer. In this case, at least a portion of the upper surface of the pixel defining layermay be exposed by the intermediate through holeH.

14 FIG. 14 FIG. 11 FIG.A is a cross-sectional view of a display apparatus according to an exemplary embodiment. In, the same reference numerals as those used indenote the same elements, and a duplicate description will not be given herein.

14 FIG. 100 1 101 200 300 450 50 60 101 1 1 200 2 101 2 Referring to, the display apparatus may include the substratehaving the first area Aas a transmission area, the buffer layer, the display layer, the encapsulation substrateA, the metal layer, the optical functional section, and the window. The buffer layermay include the first hole Hin the first area A, and the display layermay include the second hole H. In this case, at least a portion of the upper surface of the buffer layermay be exposed by the second hole H.

220 222 222 223 230 1 220 1 222 222 223 230 1 a c a c In the present embodiment, an intermediate through holeH′ may be formed such that the through holes respectively formed in the first functional layer, the second functional layer, the opposite electrode, and the capping layerin the first area Amay overlap each other. In this case, the diameter of the intermediate through holeH′ may be less than the diameter of the first hole H. For example, the first functional layer, the second functional layer, the opposite electrode, and the capping layermay be on a sidewall of the first hole H.

220 220 1 101 200 220 1 101 200 A laser beam may be used to form the intermediate through holeH′. In this case, when the intermediate through holeH′ is greater than the first hole H, an insulating layer of the buffer layeror the display layermay be damaged or outgassed due to the laser beam. Therefore, by designing the intermediate through holeH′ to be arranged inside the first hole H, the buffer layeror the display layermay be prevented from being damaged.

15 FIG. 15 FIG. 11 FIG.A is a cross-sectional view of a display apparatus according to an exemplary embodiment. In, the same reference numerals as those used indenote the same elements, and a duplicate description will not be given herein.

15 FIG. 100 1 101 200 300 450 50 60 101 1 1 200 2 101 2 Referring to, the display apparatus may include the substratehaving the first area Aas a transmission area, a buffer layer, the display layer, the encapsulation substrateA, the metal layer, the optical functional section, and the window. The buffer layermay include the first hole Hin the first area A, and the display layermay include the second hole H. In this case, at least a portion of the upper surface of the buffer layermay be exposed by the second hole H.

500 1 500 1 500 3 In the present embodiment, the display apparatus may further include a fillerin the first area A. The fillermay be arranged in the first area A, and in some exemplary embodiments, the fillermay be arranged on a portion of the third area A.

217 500 2 217 300 500 1 3 2 In an exemplary embodiment, the spacermay be shielded such that the fillermay not be arranged in the second area A. In this case, the spacermay be connected to the encapsulation substrateA. Therefore, the fillermay be arranged in a portion of the first area Aor the third area Aand may be arranged to be non-overlapping with the second area A.

500 500 500 In an exemplary embodiment, the fillermay include a transparent material having high light transmittance. For example, the fillermay include a material having light transmittance of about 90% or more. In particular, the fillermay include a material having light transmittance of about 95% or more.

500 100 300 100 300 In the present embodiment, the fillermay be between the substrateand the encapsulation substrateA to increase structural stability of the substrateand the encapsulation substrateA. Accordingly, the reliability of the display apparatus may be increased.

As described above, according to the embodiments of the disclosure, the light transmittance of the transmission area may be increased by providing a hole in the transmission area in a buffer layer.

In addition, in the display apparatuses according to the embodiments of the disclosure and the display apparatuses manufactured by the method of manufacturing the display apparatuses according to the embodiments of the present disclosure, a first non-display area outside a display area may be minimized.

It should be understood that exemplary embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each exemplary embodiment should typically be considered as available for other similar features or aspects in other exemplary embodiments. While one or more exemplary embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.