Liquid Crystal Display Device and Manufacturing Method Thereof

This application claims priority to Chinese Patent Applications No. CN 202411551935.9 filed on 2024 Oct. 31; CN 202411907678.8 filed on 2024 Dec. 20; CN 202411032639.8 filed on 2024 Jul. 29; CN 202411051811.4 filed on 2024 Jul. 31; CN 202411039469.6 filed on 2024 Jul. 31; CN 202411095077.1 filed on 2024 Aug. 9; CN 202411499711.8 filed on 2024 Oct. 25, the disclosures of which are incorporated herein in their entirety by reference.

The present disclosure relates to a liquid crystal display device and a manufacturing method thereof, especially to a liquid crystal display device with quantum dots and a manufacturing method thereof.

With the advancement of technology, existing electronic products are generally equipped with display panels to have display functions, such as smartphones, tablet computers, notebook computers, wearable bracelets, and wearable watches. To meet the requirements of wide color gamut, light weight, thinness, and low energy consumption of display panels, existing display panels use quantum dot materials as a layer in the backlight module of the display panel (hereinafter referred to as the quantum dot layer). The quantum dot layer is used to receive the light emitted by the backlight unit in the backlight module to generate light of different colors.

However, affected by the moisture in the air, the quantum dot materials at the edge of the quantum dot layer are prone to failure due to contact with moisture, so that the light emitted around the backlight module (corresponding to the edge of the quantum dot layer) fails to effectively perform light-color conversion, resulting in a light-leakage defect of blue/violet light. In other words, there is a certain range of failure areas at the edge of the quantum dot layer, which causes the light-leakage phenomenon around the backlight module. Although existing display panels are generally provided with frames to shield the periphery of the backlight module, the failure areas at the edge of the quantum dot layer in the backlight module still cannot be completely shielded, therefore the existing liquid crystal display devices still have the problem of light leakage.

On the other hand, with the development of technology, printed circuit boards have become an indispensable part of different electronic products (such as but not limited to motherboards, light-emitting panels, and development boards). Common printed circuit boards include single-layer printed circuit boards (single-layer PCB), double-layer printed circuit boards (double-layer PCB), and multi-layer printed circuit boards (multi-layer PCB), and the structures of each printed circuit board are different.

For example, a single-layer printed circuit board only has one conductor layer as the conductive traces of the circuit, and electronic components can only be arranged on one surface of the single-layer printed circuit board. In contrast, double-layer printed circuit boards and multi-layer printed circuit boards have two conductor layers and multiple conductor layers respectively as the conductive traces of the circuit, and electronic components can be arranged on the front and back surfaces of the double-layer printed circuit boards and the front and back surfaces of the multi-layer printed circuit boards.

However, limited by the structure of the printed circuit board (PCB), the multiple conductive traces on the same conductor layer cannot cross each other. In other words, the multiple conductive traces on the same conductor layer must each form independent circuits to avoid short-circuits, which makes the circuit design more complex. Even though the electronic components on the front and back surfaces of double-layer PCBs and multi-layer PCBs can be electrically connected through multiple conductive layers, through holes, blind vias, and/or buried holes, there may still be a problem of short-circuits caused by the crossing of multiple conductive traces on the same conductor layer in double-layer PCBs and multi-layer PCBs.

On the other hand, the existing backlight board has a scanning circuit and a driving circuit. The scanning circuit can send scan signals to specified light emission points through each column of scan lines, and the driving circuit can send drive signals to the light emission points that receive the drive signals to light up the light-emitting elements of the light emission points. The current scanning circuit scans each column of scan lines in a preset scanning order, so that multiple light emission points on each column of scan lines can receive scan signals simultaneously. In order to ensure that the light emission points on the same column of scan lines all receive scan signals, the scanning circuit actuates multiple switches connected to the light emission points on the same column of scan lines simultaneously in one scanning sequence. However, when multiple switches are actuated simultaneously, each switch turns on and off instantaneously, and the voltage of each switch is instantaneously increased and then suddenly decreased. As a result, the power supply circuit that supplies power to the scanning circuit will produce a resonance phenomenon (for example, the resonant circuit of the power supply circuit resonates in response to the instantaneous voltage change). Here, the power supply circuit will generate low-frequency noise under the resonance phenomenon, and the continuous scanning of each scan line will further amplify the low-frequency noise.

On the other hand, the thin-film transistor liquid-crystal panel (TFT-LCD panel) is a common display panel and is often used in various types of displays. In the existing TFT-LCD panels, conductive gold balls are placed between a TFT-LCD substrate and a color filter substrate, so that the TFT-LCD substrate is electrically connected to the color filter substrate. However, since the material of the conductive gold balls is different from the materials of each layer in the TFT-LCD substrate, when forming the conductive gold balls on the TFT-LCD substrate, the instruments and materials of the manufacturing process need to be changed to perform the step of forming the conductive gold balls. Therefore, the manufacturing process of the TFT-LCD panel becomes complex and time-consuming.

On the other hand, the Liquid Crystal Display (LCD) is an important part of the existing display technologies and is widely used in the screens of electronic devices such as mobile phones, tablet computers, televisions, and computers. In the manufacturing process of LCDs, large-sized display panels are first synthesized, and then the panels are cut into sizes that meet the requirements of end products using panel cutting technology.

The panel cutting technology and its cutting effectiveness directly affect the yield, quality of end electronic devices, and the experience of end users. Generally speaking, an LCD consists of a thin film transistor (TFT), a color filter (CF), and liquid crystals. The liquid crystals are filled between the TFT and the CF, and a peripheral sealant is used to form an enclosed space between the TFT and the CF to seal the liquid crystals inside.

When cutting the display panel, a cutter wheel is used to cut the area coated with the peripheral sealant to prevent the liquid crystals from leaking out, and methods such as breaking or laser are used to break the cut area. However, even so, since both the TFT and the CF are made of thin glass materials, the panel is still prone to cracking or generating cracks during cutting or breaking, which affects the quality of the LCD.

In the past, methods such as using jigs for breaking, adjusting the number of teeth, angle, tooth depth of the cutter wheel, the cutting parameters of the cutter wheel, or the thickness of the cutting liner paper were often used to reduce the damage caused during cutting and breaking.

On the other hand, with the rapid development of display technology, the market demand for high-quality display effects is becoming stronger and stronger. Early display technologies mainly focused on improving resolution and color performance. However, with the continuous advancement of technology, users' requirements for displays are no longer limited to basic picture display quality. They also need the display to provide stable and consistent picture quality in different usage scenarios.

On the other hand, in the existing display devices, the LED panel adopts a 2S1P (2 Series 1 Parallel) circuit architecture. In other words, at any time point when the LED panel is operating (i.e., the LED panel scans all the light emitting diodes within a cycle), two light emitting diodes connected in series in the LED panel will emit light simultaneously. However, limited by the 2S1P circuit architecture, when the picture displayed by the existing display device contains graphics or text with edges, the LED panel may cause additional light emitting diodes to emit light, resulting in a halo (corresponding to the additionally emitting light emitting diodes) on the picture displayed by the display device, which in turn affects the quality of the display device.

In view of this, the inventor proposes a liquid crystal display device, which includes: a backlight module, a quantum dot repairing film, a quantum dot layer, and a panel module. The backlight module has a light-emitting surface, and the light-emitting surface has a central area and a peripheral area surrounding the central area; the quantum dot repairing film is disposed on the peripheral area; the quantum dot layer is disposed on the central area and the quantum dot repairing film; and the panel module is disposed on the quantum dot layer. The panel module includes a light-shielding layer, wherein the projection of the light-shielding layer along the normal of the light-emitting surface partially overlaps with the projection of the quantum dot repairing film along the normal of the light-emitting surface, and the projection of the inner edge of the light-shielding layer along the normal of the light-emitting surface is located within the projection of the quantum dot repairing film along the normal of the light-emitting surface.

In some embodiments, the backlight module includes: a substrate layer, which includes a plurality of sidewalls and a base plate, wherein the plurality of sidewalls are disposed around the base plate; a reflective layer, which is disposed on the base plate; a light guide layer, which is disposed on the reflective layer; and an edge-lit backlight unit, which is disposed on the wall surface of at least one of the plurality of sidewalls.

In some embodiments, the light-shielding layer is disposed on the quantum dot layer and the substrate layer through an adhesive.

In some embodiments, the quantum dot repairing film is further disposed on the wall surface of each of the remaining sidewalls.

In some embodiments, the backlight module includes: a substrate layer, which includes a plurality of sidewalls and a base plate, wherein the plurality of sidewalls are disposed around the base plate; a reflective layer, which is disposed on the base plate; a light guide layer, which is disposed on the reflective layer; and a direct-lit backlight unit, which is disposed between the reflective layer and the light guide layer.

In some embodiments, the light-shielding layer is disposed on the quantum dot layer and the substrate layer through an adhesive.

In some embodiments, the quantum dot repairing film is further disposed on the wall surfaces of each of the sidewalls.

In some embodiments, the panel module includes: a first polarization layer; a thin film transistor layer, which is disposed on the first polarization layer; a color filter layer, which is disposed on the thin film transistor layer; and a second polarization layer, which is disposed on the color filter layer; wherein the sum of the thickness of the first polarization layer, the thickness of the thin film transistor layer, the thickness of the color filter layer, and the thickness of the second polarization layer is equal to the thickness of the light-shielding layer, and the light-shielding layer surrounds the first polarization layer, the thin film transistor layer, the color filter layer, and the second polarization layer.

In some embodiments, the material of the light-shielding layer is a black matrix material.

In some embodiments, the liquid crystal display device further includes an optical film layer, wherein the optical film layer is disposed between the quantum dot layer and the panel module.

The inventor also proposes a manufacturing method of a liquid crystal display device, including: providing a backlight module, the backlight module having a light-emitting surface, the light-emitting surface having a central area and a peripheral area surrounding the central area; disposing a quantum dot repairing film on the peripheral area; disposing a quantum dot layer on the central area and the quantum dot repairing film; disposing a panel module on the quantum dot layer; and disposing a light-shielding layer on the panel module, wherein the projection of the light-shielding layer along the normal of the light-emitting surface partially overlaps with the projection of the quantum dot repairing film along the normal of the light-emitting surface, and the projection of the inner edge of the light-shielding layer along the normal of the light-emitting surface is located within the projection of the quantum dot repairing film along the normal of the light-emitting surface.

In some embodiments, the manufacturing method of a liquid crystal display device includes: providing a backlight module, the backlight module having a light-emitting surface, wherein the light-emitting surface has a central area and a peripheral area surrounding the central area; disposing a quantum dot repairing film on the peripheral area; disposing a quantum dot layer on the central area and the quantum dot repairing film; forming a thin-film transistor substrate, wherein the thin-film transistor substrate includes a plurality of electrode layers; forming a metal post, wherein the metal post extends from one of the plurality of electrode layers along the normal direction of the surface of the thin-film transistor substrate to be exposed on the surface of the thin-film transistor substrate, and the material of the metal post is the same as that of one of the plurality of electrode layers; disposing a liquid crystal material on the thin-film transistor substrate to form a liquid crystal layer, wherein the liquid crystal layer is adjacent to the metal post; disposing a color filter substrate on the liquid crystal layer and the metal post, wherein the color filter substrate is electrically connected to the thin-film transistor substrate through the metal post to form a panel module; disposing the panel module on the quantum dot layer; and disposing a light-shielding layer on the panel module, wherein the projection of the light-shielding layer along the normal of the light-emitting surface partially overlaps with the projection of the quantum dot repairing film along the normal of the light-emitting surface, and the projection of the inner edge of the light-shielding layer along the normal of the light-emitting surface is located within the projection of the quantum dot repairing film along the normal of the light-emitting surface.

In some embodiments, the plurality of electrode layers include a gate layer, a drain layer, and a source layer. The steps of forming the thin-film transistor substrate include: forming the gate layer on a glass layer; forming a first insulating layer on the glass layer to cover the gate layer; forming a channel layer on the first insulating layer; respectively forming the drain layer and the source layer on two sides of the channel layer, wherein there is an interval between the drain layer and the source layer; and forming a second insulating layer on the source layer, the drain layer, and the channel layer in the interval. The step of forming the metal post is synchronized with the step of forming the gate layer, the drain layer, or the source layer.

In some embodiments, the metal post is a cylinder or a truncated cone. The bottom surface of the metal post is coupled to the surface of one of the plurality of electrode layers, and the top surface of the metal post is coupled to the color filter substrate.

The inventor also proposes a light-emitting diode (LED) circuit, which includes: a circuit board, a plurality of first light-emitting units, a first terminal set, a first conductive trace, a plurality of second light-emitting units, a second terminal set, a second conductive trace, and at least one resistor. The circuit board includes a first surface; the plurality of first light-emitting units are disposed on the first surface; the first terminal set is disposed on the first surface; the first conductive trace is disposed on the first surface to electrically connect the plurality of first light-emitting units and the first terminal set together; the plurality of second light-emitting units are disposed on the first surface; the second terminal set is disposed on the first surface; the second conductive trace is disposed on the first surface to electrically connect the plurality of second light-emitting units and the second terminal set together; and at least one resistor is disposed on the first conductive trace and/or the second conductive trace to serve as a jumper for any section of the first conductive trace and/or a jumper for any section of the second conductive trace.

In some embodiments, the circuit board includes a first section and a second section vertically connected to the first section. The first section is longer than the second section. The plurality of first light-emitting units and the plurality of second light-emitting units are located in the first section, and the first terminal set and the second terminal set are located in the second section.

In some embodiments, the first terminal set includes a first positive electrode and a first negative electrode, and the first positive electrode and the first negative electrode are respectively disposed at two ends of the first conductive trace.

In some embodiments, the second terminal set includes a second positive electrode and a second negative electrode, and the second positive electrode and the second negative electrode are respectively disposed at two ends of the second conductive trace.

In some embodiments, the plurality of first light-emitting units and the plurality of second light-emitting units are arranged in a staggered manner to form an array.

In some embodiments, the at least one resistor is further used to replace any section of the first conductive trace, and the at least one resistor is further used to adjust the resistance value of the first conductive trace.

In some embodiments, the at least one resistor is further used to replace any section of the second conductive trace, and the at least one resistor is further used to adjust the resi stance value of the second conductive trace.

In some embodiments, the circuit board is a single-layer printed circuit board.

The inventor also proposes a circuit board structure, including: a circuit board, a plurality of electronic components, a plurality of conductive traces, and at least one resistor. The circuit board includes a first surface; the plurality of electronic components are disposed on the first surface; the plurality of conductive traces are disposed on the first surface, and each of the conductive traces is used to electrically connect at least two of the plurality of electronic components together; and at least one resistor is disposed on at least one of the plurality of conductive traces and used as a jumper for any section of at least one of the plurality of conductive traces.

The inventor also proposes a light emitting diode (LED) backlight panel, including: a circuit board, a plurality of drive lines, and a plurality of scan lines. The circuit board has an operable area; the plurality of drive lines are located on the circuit board and are sequentially arranged on the operable area in a first arrangement direction; and the plurality of scan lines are located on the circuit board and define a plurality of light emission points in a matrix configuration with the drive lines on the operable area. The relative positions of the plurality of light emission points formed by the same scan line and the drive lines among the light emission points are staggered from each other in a second arrangement direction, and the first arrangement direction is different from the second arrangement direction.

In some embodiments, the LED backlight panel further includes a scanning circuit located on the circuit board and coupled to the scan lines for sending scan signals to the scan lines. In each scanning sequence, the scanning circuit sends the scan signal to one of the scan lines, and the arrangement order of the plurality of light emission points that receive the scan signal among the light emission points on the drive lines is staggered from each other.

In some embodiments, the LED backlight panel further includes a driving circuit coupled to the drive lines for sending drive signals to the drive lines.

In some embodiments, the LED backlight panel further includes a plurality of light emitting diodes respectively coupled between the drive lines and the scan lines that define the light emission points and used to emit light according to the drive signals.

In some embodiments, the driving circuit includes a drive signal generation module having a plurality of transmission channels and used to generate the drive signals and output them to the transmission channels.

In some embodiments, the number of the transmission channels is a multiple of the number of the scan lines.

In some embodiments, the scanning circuit further includes a plurality of scan switches. The scan switches are turned on in response to the scan signals to send the scan signals.

In some embodiments, these drive lines include a first drive line, a second drive line, a third drive line, and a fourth drive line. These scan lines include a first scan line, a second scan line, a third scan line, and a fourth scan line.

In some embodiments, these light emission points are divided into multiple first light emission points, multiple second light emission points, multiple third light emission points, and multiple fourth light emission points according to the scanning sequence. Among them, the intersections of the first scan line with the first drive line, the second drive line, the third drive line, and the fourth drive line are these first light emission points; the intersections of the second scan line with the first drive line, the second drive line, the third drive line, and the fourth drive line are these second light emission points; the intersections of the third scan line with the first drive line, the second drive line, the third drive line, and the fourth drive line are these third light emission points; and the intersections of the fourth scan line with the first drive line, the second drive line, the third drive line, and the fourth drive line are these fourth light emission points.

In some embodiments, during the first scanning sequence, these first light emission points obtain the scan signal; during the second scanning sequence, these second light emission points obtain the scan signal; during the third scanning sequence, these third light emission points obtain the scan signal; during the fourth scanning sequence, these fourth light emission points obtain the scan signal.

The inventor also proposes a TFT-LCD panel unit, which includes: a thin-film transistor substrate, a liquid crystal layer, a metal post, and a color filter substrate. The thin-film transistor substrate includes a plurality of electrode layers; the liquid crystal layer is disposed on the surface of the thin-film transistor substrate; the metal post extends from one of the plurality of electrode layers along the normal direction of the surface of the thin-film transistor substrate to be exposed on the surface of the thin-film transistor substrate, and the metal post is adjacent to the liquid crystal layer; and the color filter substrate is disposed on the liquid crystal layer and the metal post and is electrically connected to the thin-film transistor substrate through the metal post. Among them, the material of the metal post is the same as that of one of the plurality of electrode layers.

In some embodiments, the plurality of electrode layers include a gate layer, a drain layer, and a source layer, and the thin-film transistor substrate further includes: a glass layer, wherein the gate layer is disposed on the glass layer; a first insulating layer, disposed on the glass layer to cover the gate layer; a channel layer, disposed on the first insulating layer, wherein the drain layer and the source layer are respectively disposed on two sides of the channel layer and are spaced apart by an interval; and a second insulating layer, disposed on the drain layer, the source layer, and the channel layer in the interval.

In some embodiments, the metal post is a cylinder. The bottom surface of the metal post is coupled to the surface of one of the plurality of electrode layers, and the top surface of the metal post is coupled to the color filter substrate.

In some embodiments, the metal post further includes at least one metal truncated cone. The bottom surface of the at least one metal truncated cone is coupled to the top surface of the metal post, and the top surface of the at least one metal truncated cone is coupled to the color filter substrate.

In some embodiments, the metal post is a truncated cone. The bottom surface of the metal post is coupled to the surface of one of the plurality of electrode layers, and the top surface of the metal post is coupled to the color filter substrate.

The inventor also proposes a manufacturing method for a TFT-LCD panel unit, which includes: forming a thin-film transistor substrate, wherein the thin-film transistor substrate includes a plurality of electrode layers; forming a metal post, wherein the metal post extends from one of the plurality of electrode layers along the normal direction of the surface of the thin-film transistor substrate to be exposed on the surface of the thin-film transistor substrate; disposing a liquid crystal material on the thin-film transistor substrate to form a liquid crystal layer, wherein the liquid crystal layer is adjacent to the metal post; and disposing a color filter substrate on the liquid crystal layer and the metal post, wherein the color filter substrate is electrically connected to the thin-film transistor substrate through the metal post; wherein, the material of the metal post is the same as the material of one of the plurality of electrode layers.

In some embodiments, the plurality of electrode layers include a gate layer, a drain layer, and a source layer, and the step of forming the thin-film transistor substrate includes: forming the gate layer on a glass layer; forming a first insulating layer on the glass layer to cover the gate layer; forming a channel layer on the first insulating layer; respectively forming the drain layer and the source layer on two sides of the channel layer, wherein there is an interval between the drain layer and the source layer; and forming a second insulating layer on the source layer, the drain layer, and the channel layer in the interval; wherein, the step of forming the metal post is synchronized with the step of forming the gate layer, the step of forming the drain layer, or the step of forming the source layer.

In some embodiments, the metal post is a cylinder. The bottom surface of the metal post is coupled to the surface of one of the plurality of electrode layers, and the top surface of the metal post is coupled to the color filter substrate.

In some embodiments, the metal post further includes at least one metal truncated cone. The bottom surface of the at least one metal truncated cone is coupled to the top surface of the metal post, and the top surface of the at least one metal truncated cone is coupled to the color filter substrate.

In some embodiments, the metal post is a truncated cone. The bottom surface of the metal post is coupled to the surface of one of the plurality of electrode layers, and the top surface of the metal post is coupled to the color filter substrate.

The inventor also proposes a panel manufacturing method, including: cutting a first substrate to form a first cutting line, wherein the first substrate includes a display area and a terminal area, the first end of the terminal area is connected to the display area, and the first cutting line is located at the second end of the terminal area; cutting the first substrate to form a second cutting line, with a first excess material between the second cutting line and the first cutting line; cutting a second substrate to form a third cutting line, wherein the second substrate is connected to the display area of the first substrate, and the third cutting line corresponds to the first end of the terminal area; cutting the second substrate to form a fourth cutting line, with a second excess material between the fourth cutting line and the third cutting line, and the fourth cutting line corresponding to the second cutting line; and cutting the second excess material to form a fifth cutting line, wherein the fifth cutting line corresponds to the first cutting line so that the first substrate and the second substrate break at the first cutting line, the second cutting line, the third cutting line, and the fourth cutting line.

In some embodiments, the first substrate includes a plurality of first sub-substrates adjacent to each other, and each of the first sub-substrates includes the display area and the terminal area.

In some embodiments, the number of the first excess materials is plural, and each has a first side and a second side opposite to each other. The first sub-substrate is connected to the first side of the first excess material with the second end of the terminal area, and is connected to the second side of the first excess material with the display area of another adjacent first sub-substrate.

In some embodiments, the second substrate includes a plurality of second sub-substrates adjacent to each other. The number of the second excess materials is plural, and each has a third side and a fourth side opposite to each other. The second sub-substrate is connected to the third side of the second excess material, and another adjacent second sub-substrate is connected to the fourth side of the second excess material.

In some embodiments, the first cutting line, the second cutting line, the third cutting line, the fourth cutting line, and the fifth cutting line are respectively formed by a cutting wheel.

In some embodiments, the second substrate and the display area of the first substrate are connected by glue.

In some embodiments, after breaking at the first cutting line, the second cutting line, the third cutting line, and the fourth cutting line, the first excess material and the second excess material are separated from the first substrate and the second substrate to expose the terminal area.

In some embodiments, the first substrate is a thin-film transistor substrate.

In some embodiments, the second substrate is a color filter.

In some embodiments, the terminal area can be used for electrically connecting signal lines.

The inventor also proposes an image processing method, including: outputting a display screen with a display module; detecting a type of the display screen; selecting a corresponding driving parameter set according to the type; and adjusting the display screen according to the driving parameter set.

In some embodiments, the type of the display screen includes a first type, and the driving parameter set includes a first parameter set corresponding to the first type. When the type of the display screen is the first type, the first parameter set is selected and the display screen is adjusted according to the first parameter set.

In some embodiments, the type of the display screen includes a second type, and the driving parameter set includes a second parameter set corresponding to the second type. The first type is different from the second type, and the first parameter set is different from the second parameter set. When the type of the display screen is the second type, the second parameter set is selected and the display screen adjusted according to the second parameter set.

In some embodiments, the first type is a normal display screen, and the second type is a special screen. The special screen includes a flicker test screen, a heavy-load screen, or a dynamic test screen.

In some embodiments, the driving parameter set includes charging time, charging speed, display time, pixel inversion mode, page-update frequency, gate voltage, or pixel voltage.

In some embodiments, detecting the type of the display screen includes: detecting a screen feature of the display screen output by the display module; and analyzing the type of the display screen according to the screen feature.

In some embodiments, the screen feature is a touch feature value, and the touch feature value includes noise and capacitance change.

In some embodiments, the screen feature is screen data, including brightness distribution, contrast, or color composition.

In some embodiments, the image processing method further includes performing pixel inversion on the display screen; and adjusting the driving parameter set to compensate for the brightness of the display screen.

The inventor also proposes an image processing panel, including: a display module and a drive module. The display module includes a display and a display circuit. The display circuit is electrically connected to the display to control the display to output a display screen; the drive module is electrically connected to the display circuit and includes: a computing module and a driving circuit. The computing module is used to detect a type of the display screen; and the driving circuit is electrically connected to the computing module. The driving circuit includes a plurality of driving parameter sets. The driving circuit selects the corresponding driving parameter set according to the type of the display screen and drives the display circuit to adjust the display screen according to the driving parameter set.

The inventor also proposes an LED array, which includes: a first light emitting diode and a plurality of second light emitting diodes. The plurality of second light emitting diodes are connected in parallel to the first light emitting diode; wherein, in response to the first light emitting diode being grounded and one of the second light emitting diodes receiving a modulation signal, the first light emitting diode and the second light emitting diode receiving the modulation signal emit light.

In some embodiments, the LED array further includes: a control element, electrically connected to the first light emitting diode, for controlling the first light emitting diode to be open-circuited or grounded; and a modulation signal generation element, electrically connected to the plurality of second light emitting diodes, for generating the modulation signal to be provided to each of the second light emitting diodes.

In some embodiments, the LED array further includes: a control element, electrically connected to the first light emitting diode, for controlling the first light emitting diode to be open-circuited or grounded; and a plurality of modulation signal generation elements, each of which is electrically connected to each of the second light emitting diodes, and each of the modulation signal generation elements is used to generate the modulation signal to be provided to each of the second light emitting diodes.

In some embodiments, the LED array further includes: a circuit board, on which the first light emitting diode and the plurality of second light emitting diodes are arranged; wherein, the plurality of second light emitting diodes are four second light emitting diodes, and each of the second light emitting diodes is individually adjacent to a first side of the first light emitting diode, a second side of the first light emitting diode, a third side of the first light emitting diode, and a fourth side of the first light emitting diode.

In some embodiments, the direction of the first side of the first light emitting diode corresponds to the positive X direction in the Cartesian coordinate system, the direction of the second side of the first light emitting diode corresponds to the positive Y direction in the Cartesian coordinate system, the direction of the third side of the first light emitting diode corresponds to the negative X direction in the Cartesian coordinate system, and the direction of the fourth side of the first light emitting diode corresponds to the negative Y direction in the Cartesian coordinate system.

The inventor also proposed an LED panel, which includes a plurality of LED arrays, wherein each of the LED arrays includes: a first light emitting diode and a plurality of second light emitting diodes. The plurality of second light emitting diodes are connected in parallel to the first light emitting diode; wherein, in response to the first light emitting diode being grounded and one of the second light emitting diodes receiving a modulation signal, the first light emitting diode and the second light emitting diode receiving the modulation signal emit light; two adjacent LED arrays share at least one of the plurality of second light emitting diodes.

In some embodiments, each LED array further includes: a control element electrically connected to the first light emitting diode for controlling the first light emitting diode to be open-circuited or grounded; and a modulation signal generation element electrically connected to the plurality of second light emitting diodes for generating the modulation signal to be provided to each of the second light emitting diodes.

In some embodiments, each LED array further includes: a control element electrically connected to the first light emitting diode for controlling the first light emitting diode to be open-circuited or grounded; and a plurality of modulation signal generation elements, each of which is electrically connected to each of the second light emitting diodes, and each of the modulation signal generation elements is used to generate the modulation signal to be provided to each of the second light emitting diodes.

In some embodiments, the LED panel further includes: a circuit board; wherein, the plurality of second light emitting diodes are four second light emitting diodes, the first light emitting diode and the four second light emitting diodes are disposed on the circuit board, and each of the second light emitting diodes is individually adjacent to a first side of the first light emitting diode, a second side of the first light emitting diode, a third side of the first light emitting diode, and a fourth side of the first light emitting diode.

In some embodiments, the direction of the first side corresponds to the positive X direction in the Cartesian coordinate system, the direction of the second side corresponds to the positive Y direction in the Cartesian coordinate system, the direction of the third side corresponds to the negative X direction in the Cartesian coordinate system, and the direction of the fourth side corresponds to the negative Y direction in the Cartesian coordinate system.

In order to make the purposes, means, and effects of the technical means disclosed in different embodiments of the present disclosure more understandable, the following description will elaborate on specific embodiments of the proposed technical means in combination with the drawings. The descriptions of the technical means recorded in the following embodiments of the present disclosure are merely for illustration and example, and do not represent all the embodiments of the present disclosure, nor limit the present disclosure to specific embodiments. Based on the different embodiments in the present disclosure, all other embodiments obtained by those with ordinary knowledge in the technical field without excessive experimentation should fall within the scope of protection of the present disclosure.

It should be noted that when an element is referred to as being “disposed on” another element, it can be directly on the other element, or there may be elements existing between the two. When an element is considered to be “connected” to another element, it can be directly connected to the other element or there may be elements existing between the two at the same time. The terms “vertical”, “horizontal”, “left”, “right”, “upper”, “lower”, “inner”, “outer”, “front”, “rear” and similar expressions used in the present disclosure are only used to indicate the relative positional relationship based on the drawings, and do not limit that the elements using these terms can only be implemented in the indicated manner. When the absolute position of the described object changes, the description of the relative position may also change accordingly.

The term “comprising” used in the present disclosure is an open-ended term, so it should be interpreted as “including but not limited to”; the term “disposed on” means that two or more elements are in “direct” physical or electrical contact with each other, or in “indirect” physical or electrical contact with each other; and terms such as “a”, “another”, “first”, “second”, and “third” are used to distinguish the referred elements. Unless otherwise specified, they are not used to sort or limit the differences of the referred elements, nor to limit the scope of this case.

In this disclosure, descriptions such as “substantially”, “approximately”, and “about” are used to indicate the error ranges implied by possible unexpected impacts and deviations in the manufacturing process or material selection. The said error range can include the variation range that does not significantly change the material structure, configuration, characteristics, and effects, for example, a deviation range of 0%-10%. The said error range is clear to those with ordinary knowledge in this technical field. For example, when it is described that “two objects are substantially parallel”, in fact, if it is observed that there is a slight height difference between the two objects, but this difference is negligible relative to the size of the objects themselves (for example, less than 10%) and does not affect the effect, the relative configuration between the two observed objects will still be interpreted as being within the range of “substantially parallel” described in this disclosure.

In all descriptions related to specific numerical values in this disclosure, although not directly described, they all contain the meaning of “about” or “substantially”. That is, these specific numerical values will cover the possible numerical error ranges to indicate the possible unexpected impacts and deviations in the manufacturing process or material selection. The said numerical error range can include numerical changes that do not significantly change the material structure, characteristics, and effects, for example, a deviation range of 0%-10%. This error range is clear to those with ordinary knowledge in this technical field.

Unless otherwise defined, all technical and specific terms used in this disclosure have the same meanings as commonly understood by those with ordinary knowledge in the technical field to which this disclosure belongs. The terms used in this disclosure are only for the purpose of describing specific implementation modes and are not intended to limit this disclosure. The term “and/or” used in this disclosure includes any and all combinations of one or more of the relevant listed items.

1 FIG. 2 FIG. 1 FIG. 2 FIG. 1 FIG. 1 1 2 2 1 10 11 12 13 10 11 11 11 12 11 11 12 l Please refer toand.is a top-plan view of a liquid crystal display (LCD) deviceaccording to an embodiment of this disclosure, andis a schematic cross-sectional view of the liquid crystal display deviceinalong the section line-according to this disclosure. A liquid crystal display deviceincludes a backlight module, a quantum dot repairing film, a quantum dot layer, and a panel module. The backlight modulehas a light-emitting surface s, and the light-emitting surface shas a central area Aand a peripheral area Asurrounding the central area A. The quantum dot repairing filmis disposed in the peripheral area A.

3 FIG. 3 FIG. 2 FIG. 3 FIG. 2 FIG. 10 11 10 12 12 11 11 10 11 12 11 10 11 12 11 11 12 10 11 12 11 11 12 11 10 12 10 11 Please further refer to.is a top-plan view of an embodiment of the backlight moduleinaccording to the present disclosure. Takingas an example, in some embodiments, the quantum dot repairing filmis arranged around the backlight modulein a “square” shape (width W). The quantum dot layeris arranged in the central area Aof the light-emitting surface sof the backlight moduleand on the quantum dot repairing film. In other words, in some embodiments, the quantum dot layercovers the quantum dot repairing filmand is arranged on the backlight module. In some embodiments, the quantum dot repairing filmhas ductility. Here, when the quantum dot layeris arranged on the quantum dot repairing film, the quantum dot repairing filmcan fill the gap between the quantum dot layerand the backlight module(as shown by the dotted circular frame C, Cin). In addition, in some embodiments, the quantum dot repairing filmhas adhesiveness. Here, the quantum dot repairing filmcan be arranged on the peripheral area Aof the light-emitting surface sof the backlight modulein the form of tape or double-sided tape, so that the quantum dot layeris stably arranged on the backlight moduleand the quantum dot repairing film.

13 12 13 130 130 13 11 130 11 11 11 11 130 11 12 11 11 130 12 11 11 11 130 13 12 130 11 1 FIG. 1 FIG. 3 FIG. 1 FIG. 3 FIG. 3 FIG. 1 FIG. The panel moduleis arranged on the quantum dot layer, and the panel moduleincludes a light-shielding layer. Takingas an example, in some embodiments, the light-shielding layeris arranged around the panel modulein a “square” shape (width W). In addition, a projection of the light-shielding layeralong a normal of the light-emitting surface s(corresponding to the Z-direction) partially overlaps with a projection of the quantum dot repairing filmalong the normal of the light-emitting surface s, and a projection of an inner edge Eof the light-shielding layeralong the normal of the light-emitting surface sis located in a projection of the peripheral area Aalong the normal of the light-emitting surface s. Takingandas an example, in some embodiments, the width Wof the light-shielding layershown inis smaller than the width Wof the quantum dot repairing filmshown in. It should be noted that the dotted line Dshown incorresponds to the inner edge Eof the light-shielding layershown in. Therefore, when the panel moduleis arranged on the quantum dot layer, the light-shielding layercannot completely cover the quantum dot repairing film.

10 13 13 10 1 In some embodiments, the backlight moduleis used to project light onto the panel module, and the panel moduleis used to receive the light from the backlight moduleto display images. Here, the liquid crystal display devicecan be installed on any type of electronic device, enabling the electronic device to have the function of displaying images.

11 10 12 11 10 12 11 10 11 10 11 11 10 In some embodiments, the quantum dot repairing filmis used to enable the backlight moduleto emit light with normal colors. Since the quantum dot materials at the edge of the quantum dot layermay be affected by moisture in the air and become ineffective, the light emitted from the periphery of the light-emitting surface sof the backlight module(roughly corresponding to the peripheral area Aof the light-emitting surface sof the backlight module) is not effectively subjected to light color conversion, which in turn causes the phenomenon of light leakage around the light-emitting surface sof the backlight module. Therefore, in some embodiments, the quantum dot repairing filmis used to repair the light emitted from the periphery of the light-emitting surface sof the backlight module.

10 12 11 10 11 12 13 12 12 11 11 10 12 11 12 11 10 Specifically, when the backlight unit in the backlight moduleemits light, the light incident on the peripheral area Aof the light-emitting surface sof the backlight modulefirst penetrates the quantum dot repairing filmfor light color conversion, and then penetrates the edge of the quantum dot layerand enters the panel module. In other words, even if the quantum dot materials at the edge of the quantum dot layerhave been affected by moisture in the air and become ineffective, the ineffective quantum dot materials will not affect the light that has already completed the light color conversion. It should be noted that since the quantum dot materials in the central area of the quantum dot layer(roughly corresponding to the central area Aof the light-emitting surface sof the backlight module) are not affected by moisture in the air, the light penetrating through the central area of the quantum dot layercan still undergo light color conversion. Here, all areas (including the central area Aand the peripheral area A) in the light-emitting surface sof the backlight modulecan emit light with normal colors without the problem of light leakage.

1 6 FIGS.to 4 6 FIGS.to 2 FIG. 1 10 100 101 102 103 100 100 100 100 100 100 10 11 Please refer to.are cross-sectional schematic diagrams of some embodiments of the liquid crystal display deviceinaccording to the present disclosure. In some embodiments, the backlight moduleincludes a substrate layer, a reflective layer, a light guide layer, and an edge-lit backlight unit. In some embodiments, the substrate layerincludes a plurality of sidewallsA and a base plateB, and the plurality of sidewallsA are disposed around the base plateB. The substrate layeris used to protect the optical materials in the backlight moduleand to prevent light from being emitted from places other than the light-emitting surface s.

101 100 100 102 101 101 103 102 102 11 11 10 In some embodiments, the reflective layeris disposed on the base plateB of the substrate layer, and the light guide layeris disposed on the reflective layer. The reflective layeris used to reflect the light generated by the edge-lit backlight unitto the light guide layer, and the light guide layeris used to control and guide the direction of the light so that the light is evenly emitted from the light-emitting surface s. Here, the light-emitting surface sof the backlight modulehas a uniform and sufficiently bright lighting effect.

4 FIG. 103 100 100 103 103 101 102 101 102 11 12 11 10 As shown in, in some embodiments, the edge-lit backlight unitis disposed on the wall surface of at least one of the plurality of sidewallsA of the substrate layer. Here, when the edge-lit backlight unitgenerates light, the edge-lit backlight unitemits the light to the reflective layer, and the light is reflected to the light guide layervia the reflective layer. Subsequently, the light guide layercontrols and guides the direction of the light so that the light enters the quantum dot repairing filmand the quantum dot layerfor light color conversion. Finally, the light that has completed the light color conversion is emitted from the light-emitting surface sof the backlight module.

11 100 103 100 11 100 103 11 100 11 100 103 11 12 10 1 11 100 5 FIG. In some embodiments, the quantum dot repairing filmis further disposed on the wall surfaces of the remaining sidewallsA. Takingas an example, the edge-lit backlight unitis disposed on the wall surface of one of the sidewallsA, and the quantum dot repairing filmis further disposed on the wall surfaces of the remaining sidewallsA. When part of the light generated by the edge-lit backlight unitenters the quantum dot repairing filmlocated on the wall surface of the sidewallA, the quantum dot repairing filmlocated on the wall surface of the sidewallA can also perform light color conversion on the light. Here, even if part of the light generated by the edge-lit backlight unitdoes not directly or indirectly enter the quantum dot repairing filmor the quantum dot layerlocated on the backlight module, the liquid crystal display devicecan still perform light color conversion on part of the light through the quantum dot repairing filmlocated on the wall surface of the sidewallA.

6 FIG. 1 14 14 12 13 14 103 14 14 14 103 1 As shown in, in some embodiments, the liquid crystal display devicefurther includes an optical film layer, and the optical film layeris disposed between the quantum dot layerand the panel module. In some embodiments, the optical film layeris used to further adjust the characteristics of the light from the edge-lit backlight unit. For example, in some embodiments, the optical film layermay include at least one of a prism sheet (Brightness Enhancement Film, BEF), a diffuser film, and a light guide film, but is not limited thereto. Among them, when the optical film layeris a prism sheet, the optical film layeris used to concentrate the light generated by the edge-lit backlight unitto further improve the brightness of the liquid crystal display device.

1 3 FIGS.to 7 9 FIGS.to 7 9 FIGS.to 2 FIG. 1 10 100 101 102 103 100 100 100 100 100 100 10 11 Please refer toand.are cross-sectional schematic diagrams of other embodiments of the liquid crystal display deviceinaccording to the present disclosure. In other embodiments, the backlight moduleincludes a substrate layer, a reflective layer, a light guide layer, and a direct-lit backlight unit. In some embodiments, the substrate layerincludes a plurality of sidewallsA and a base plateB, and the plurality of sidewallsA are disposed around the base plateB Among them, the substrate layeris used to protect the optical materials in the backlight moduleand to prevent light from being emitted from places other than the light-emitting surface s.

101 100 100 102 101 101 103 102 102 11 11 10 In some embodiments, the reflective layeris disposed on the base plateB of the substrate layer, and the light guide layeris disposed on the reflective layer. The reflective layeris used to reflect the light generated by the direct-lit backlight unitto the light guide layer, and the light guide layeris used to control and guide the direction of the light so that the light is emitted evenly from the light-emitting surface s. Here, the light-emitting surface sof the backlight modulehas a uniform and sufficiently bright lighting effect.

7 FIG. 103 101 102 103 103 102 11 101 101 102 102 11 12 11 10 As shown in, in some embodiments, the direct-lit backlight unitis disposed between the reflective layerand the light guide layer. Here, when the direct-lit backlight unitgenerates light, the direct-lit backlight unitemits a part of the light to the light guide layeralong the normal of the light-emitting surface s(corresponding to the Z direction) and emits another part of the light to the reflective layer. The reflective layerreflects the other part of the light to the light guide layer. Subsequently, the light guide layercontrols and guides the direction of the light so that the light enters the quantum dot repairing filmand the quantum dot layerfor light color conversion. Finally, the light after light color conversion is emitted from the light-emitting surface sof the backlight module.

11 100 11 100 103 11 12 10 1 11 100 8 FIG. In some embodiments, the quantum dot repairing filmis further disposed on the wall surface of each sidewallA. Takingas an example, the quantum dot repairing filmis further disposed on the wall surface of each sidewallA. Similar to the principle of the previous embodiments, even if some of the light generated by the direct-lit backlight unitdoes not directly or indirectly enter the quantum dot repairing filmor the quantum dot layeron the backlight module, the liquid crystal display devicecan still perform light color conversion on some of the light through the quantum dot repairing filmon the wall surface of the sidewallA.

9 FIG. 1 14 14 12 13 14 103 14 14 14 103 1 As shown in, in some embodiments, the liquid crystal display devicefurther includes an optical film layer, and the optical film layeris disposed between the quantum dot layerand the panel module. In some embodiments, the optical film layeris used to further adjust the characteristics of the light from the direct-lit backlight unit. For example, in some embodiments, the optical film layermay include at least one of a prism sheet, a diffusion sheet, and a light guide sheet, but is not limited thereto. When the optical film layeris a diffusion sheet, the optical film layeris used to uniformly disperse the light generated by the direct-lit backlight unitto further improve the uniformity of the liquid crystal display device.

4 9 FIGS.to 130 12 100 100 10 13 10 13 10 As shown in, in some embodiments, the light-shielding layeris disposed on the quantum dot layerand the sidewallA of the substrate layerthrough an adhesive. In other words, the adhesive is used to bond the backlight moduleand the panel moduletogether to enhance the tightness between the backlight moduleand the panel module. In addition, the adhesive is also used to isolate the moisture in the air to prevent it from entering the gaps in the backlight module. In some embodiments, the adhesive is waterproof to avoid losing its adhesive force and waterproof effect due to the influence of moisture in the air. The adhesive can be, for example, oil-based epoxy or carbamate, but is not limited thereto.

13 131 131 132 133 134 134 132 131 133 132 134 133 132 132 133 132 1 131 134 1 131 134 133 1 133 4 9 FIGS.to In some embodiments, the panel moduleincludes a polarization layer(hereinafter referred to as the first polarization layer), a thin film transistor (TFT) layer, a color filter (CF) layer, and another polarization layer(hereinafter referred to as the second polarization layer). The thin film transistor layeris disposed on the first polarization layer, the color filter layeris disposed on the thin film transistor layer, and the second polarization layeris disposed on the color filter layer. In some embodiments, the thin film transistor layeris used to receive current to generate an electric field change, thereby deflecting the direction of each liquid crystal molecule (not shown in) located between the thin film transistor layerand the color filter layerto allow/prohibit light from passing through the thin film transistor layer. Here, each liquid crystal molecule can produce a grayscale color effect, and each liquid crystal molecule can be regarded as each pixel in the picture displayed by the liquid crystal display device. In addition, in some embodiments, the first polarization layerand the second polarization layerare used to limit the vibration direction of light, thereby screening out light with the same vibration direction. Here, the liquid crystal display devicedetermines the light and dark states of each pixel in the picture it displays through the first polarization layerand the second polarization layer. Moreover, in some embodiments, the color filter layeris used to convert the grayscale color effect displayed by each liquid crystal molecule into a color effect. Here, the liquid crystal display devicecan convert the picture it displays from a grayscale picture to a color picture through the color filter layer.

131 132 133 134 130 130 131 132 133 134 13 1 130 10 13 In some embodiments, a sum of a thickness of the first polarization layer, a thickness of the thin film transistor layer, a thickness of the color filter layer, and a thickness of the second polarization layeris equal to a thickness of the light-shielding layer, and the light-shielding layersurrounds the first polarization layer, the thin film transistor layer, the color filter layer, and the second polarization layer. Here, the surface of the panel modulecan be kept flat to avoid problems when the liquid crystal display devicedisplays images, and the light-shielding layercan prevent the light from the backlight modulefrom emitting from the side of the panel moduleand causing light leakage.

100 100 2 In some embodiments, the material of the substrate layercan be a black matrix (BM) material or a light-reflective material, such as but not limited to metallic chromium (Cr), black photosensitive resin, carbon black pigment, black ink, black photoresist, bauxite, dielectric multilayer film, and reflective resin material. In other embodiments, the material of the substrate layercan also be an opaque insulating material, such as but not limited to silicon (Si), silicon dioxide (SiO), gallium arsenide (GaAs), and silicon carbide (SiC).

103 In some embodiments, the edge-lit backlight unit/direct-lit backlight unitincludes at least one light-emitting element, such as but not limited to light-emitting diodes (LED), organic light-emitting diodes (OLED), quantum dot light-emitting diodes (QLED), mini light-emitting diodes (Mini LED), and micro light-emitting diodes (Micro LED).

11 In some embodiments, the quantum dot repairing filmcomprises a quantum dot material, a transparent material with ductility, and a transparent material with adhesiveness. The transparent material with ductility includes, but is not limited to, silicone, epoxy, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyimide (PI), polyethylene (PE), polyvinyl chloride (PVC), polystyrene (PS), polypropylene (PP), crystallized polypropylene (CPP), oriented polypropylene (OPP), polyethylene terephthalate (PET), polyetherimide, polycarbonate (PC), or polymethyl methacrylate (PMMA). The transparent material with adhesiveness includes, but is not limited to, adhesive, underfill, anisotropic conductive paste (ACP), anisotropic conductive film (ACF), non-conductive paste (NCP), and non-conductive film (NCF).

130 130 In some embodiments, the material of the light-shielding layermay be a black matrix (BM) material, such as, but not limited to, metallic chromium (Cr), black photosensitive resin, carbon black pigment, black ink, and black photoresist. In other embodiments, the material of the light-shielding layermay also be a material with light reflectivity, such as, but not limited to, bauxite, dielectric multilayer film, and reflective resin material.

131 134 In some embodiments, the materials of the first polarization layerand the second polarization layerinclude, but are not limited to, tri-acetyl cellulose (TAC), polyvinyl alcohol (PVA), pressure-sensitive adhesive, release film, and protective film.

1 2 FIGS.and 1 10 11 12 13 10 10 10 Referring again to, in some embodiments, the liquid crystal display devicecomprises a backlight module, a quantum dot repairing film, a quantum dot layer, and a panel module. In some embodiments, when the backlight moduleis in use, there may be a problem that multiple conductive traces cross each other and cause a short circuit. In view of this, the following embodiments further describe various light emitting diode circuits and their circuit board structures. In some embodiments, the light emitting diode circuits and their circuit board structures described in the following embodiments can be used to implement or be applied to the backlight module. However, the present disclosure is not limited thereto. Under different design considerations or application scenarios, other structures, processes, or manufacturing processes may be adopted to implement the backlight moduledisclosed in the present disclosure.

10 11 FIGS.and 10 FIG. 11 FIG. 10 11 FIGS.and 21 21 21 20 21 22 23 24 21 22 23 24 21 22 21 22 21 21 Please refer to.is a schematic diagram of the circuit board structure Paccording to the seventh embodiment of the present disclosure, andis a schematic diagram of the circuit board structure Paccording to the eighth embodiment of the present disclosure. A circuit board structure includes a circuit board, a plurality of electronic components, a plurality of conductive traces, and at least one resistor. As shown in, in some embodiments, the circuit board structure Pincludes a circuit board, four electronic components E, E, E, E(hereinafter referred to as the first electronic component E, the second electronic component E, the third electronic component E, and the fourth electronic component E, respectively), two conductive traces W, W(hereinafter referred to as the first conductive trace Wand the second conductive trace W, respectively), and one resistor R(hereinafter referred to as the first resistor R).

20 21 21 21 22 23 24 21 22 21 20 21 20 21 21 22 The circuit boardincludes a surface s(hereinafter referred to as the first surface s), and the first electronic component E, the second electronic component E, the third electronic component E, the fourth electronic component E, the first conductive trace W, and the second conductive trace Ware all disposed on the first surface s. In some embodiments, the circuit boardmay be a single-layer printed circuit board (single-layer PCB) with one conductive layer, a double-layer printed circuit board (double-layer PCB) with two conductive layers, or a multi-layer printed circuit board (multi-layer PCB) with a plurality of conductive layers, but is not limited thereto. In some embodiments, the circuit board structure Pwill be described below by taking a single-layer printed board as an example. It should be noted that, since the circuit boardin the circuit board structure Ponly includes one conductive layer (not shown in the figure), both the first conductive trace Wand the second conductive trace Ware located on this conductive layer.

21 22 21 23 24 22 21 22 21 22 23 24 21 22 23 24 20 21 22 21 21 22 21 21 22 In some embodiments, the first electronic component Eis electrically connected to the second electronic component Ethrough the first conductive trace W, and the third electronic component Eis electrically connected to the fourth electronic component Ethrough the second conductive trace W. In other words, each conductive trace W/Wis used to electrically connect at least two of the plurality of electronic components E, E, E, Etogether. However, since the pin positions of each electronic component E/E/E/Eare fixed and the circuit boardonly includes one conductive layer, the first conductive trace Wand the second conductive trace Wcross each other and cause a short-circuit. Here, in some embodiments, the first resistor Rcan be disposed on at least one of the plurality of conductive traces W, W, and the first resistor Ris used as a jumper for any section of at least one of the plurality of conductive traces W, W.

10 FIG. 21 21 21 22 22 21 22 21 Takingas an example, in this embodiment, the first resistor Ris disposed on the first conductive trace Wto serve as a jumper for a section of the first conductive trace Wthat crosses the second conductive trace W, and the second conductive trace Wmaintains its original circuit. In other words, in this embodiment, the first conductive trace Wcan be regarded as two independent conductive traces, and these two conductive traces cross the second conductive trace Wthrough the first resistor Rto be electrically connected together.

11 FIG. 21 22 22 21 21 22 21 21 21 21 22 21 Takingas an example again, in this embodiment, the first resistor Ris set on the second conductive trace Was a jumper for the section of the second conductive trace Wthat intersects with the first conductive trace W, and the first conductive trace Wmaintains its original circuit. In other words, in this embodiment, the second conductive trace Wcan be regarded as two independent conductive traces, and these two conductive traces are electrically connected together by the first resistor Rcrossing the first conductive trace W. Here, the circuit board structure Pcan solve the short-circuit problem caused by the intersection between the first conductive trace Wand the second conductive trace Wthrough the first resistor Rwithout redesigning the circuit.

12 FIG. 12 FIG. 21 21 23 23 22 22 22 24 23 21 23 22 23 23 21 21 23 22 21 21 21 22 21 23 21 22 Please further refer to, which is a schematic diagram of the circuit board structure Paccording to the ninth embodiment of the present disclosure. As shown in, in some embodiments, the circuit board structure Pfurther includes another conductive trace W(hereinafter referred to as the third conductive trace W) and another resistor R(hereinafter referred to as the second resistor R), and the second electronic component Eis electrically connected to the fourth electronic component Ethrough the third conductive trace W. The first conductive trace Wand the third conductive trace Wintersect and cause a short-circuit. Therefore, the second resistor Ris set on the third conductive trace Was a jumper for the section of the third conductive trace Wthat intersects with the first conductive trace W, and the first conductive trace Wmaintains its original circuit. In other words, in this embodiment, the third conductive trace Wcan be regarded as two independent conductive traces, and these two conductive traces are electrically connected together by the second resistor Rcrossing the first conductive trace W. Here, the circuit board structure Pcan solve the short-circuit problem caused by the intersection between the first conductive trace Wand the second conductive trace Wand the short-circuit problem caused by the intersection between the first conductive trace Wand the third conductive trace Wthrough the first resistor Rand the second resistor Rrespectively without redesigning the circuit.

21 2 2 2 2 20 21 21 21 21 21 21 22 22 22 22 22 22 21 2 21 21 13 FIG. 14 FIG. 13 FIG. 14 FIG. 13 FIG. 13 FIG. 14 FIG. In some embodiments, the circuit board structure Pcan be applied to the light emitting diode (LED) circuit. Please refer toand.is a schematic diagram of the LED circuitaccording to the tenth embodiment of the present disclosure, andis a schematic diagram of the LED circuitaccording to the eleventh embodiment of the present disclosure. As shown in, in some embodiments, the LED circuitincludes a circuit board, a plurality of light-emitting units D(hereinafter referred to as the first light-emitting units D), a terminal set(hereinafter referred to as the first terminal set), a conductive trace W(hereinafter referred to as the first conductive trace W), a plurality of other light-emitting units D(hereinafter referred to as the second light-emitting units D), another terminal set(hereinafter referred to as the second terminal set), another conductive trace W(hereinafter referred to as the second conductive trace W), and at least one resistor R. Takingandas an example, in this embodiment, the LED circuitincludes one resistor R(hereinafter referred to as the first resistor R).

20 21 21 21 21 21 22 22 22 21 20 21 20 2 2 20 2 21 22 The circuit boardincludes a surface s(hereinafter referred to as the first surface s), and the plurality of first light-emitting units D, the first terminal set, the first conductive trace W, the plurality of second light-emitting units D, the second terminal set, and the second conductive trace Ware all disposed on the first surface s. Similar to the circuit boardin the circuit board structure P, in some embodiments, the circuit boardin the LED circuitcan be a single-layer printed circuit board with one conductive layer, a double-layer printed circuit board with two conductive layers, or a multi-layer printed circuit board with a plurality of conductive layers, but is not limited thereto. In some embodiments, the LED circuitwill be described below by taking a single-layer printed board as an example. It should be noted that, since the circuit boardin the LED circuitonly includes one conductive layer (not shown in the figure), both the first conductive trace Wand the second conductive trace Ware located on this conductive layer.

20 20 20 20 20 20 21 20 21 22 20 21 22 21 22 2 20 20 20 2 In some embodiments, the circuit boardincludes a first sectionA and a second sectionB vertically connected to the first sectionA, and the first sectionA is longer than the second sectionB. In addition, in some embodiments, the plurality of light-emitting units Dare located in the first sectionA, and the first terminal setand the second terminal setare located in the second sectionB. In some embodiments, since the light-emitting elements (including the first light-emitting units Dand the second light-emitting units D) and the terminal sets (including the first terminal setand the second terminal set) in the LED circuitare respectively located in different sections of the circuit board, the user can easily weld or insert the second sectionB of the circuit boardthat includes the terminal sets onto an electronic device, so that this electronic device can have a lighting function or a display function through the LED circuit.

21 21 21 22 22 22 21 22 21 22 20 21 22 21 21 22 21 21 22 In some embodiments, the first conductive trace Wis used to electrically connect the plurality of first light-emitting units Dand the first terminal settogether, and the second conductive trace Wis used to electrically connect the plurality of second light-emitting units Dand the second terminal settogether. However, since the pins of each light-emitting unit D/Dand the positions of each terminal set/are fixed and the circuit boardonly contains one conductive layer, the first conductive trace Wand the second conductive trace Wcross each other and cause a short circuit. Here, in some embodiments, the first resistor Rcan be arranged on the first conductive trace Wand/or the second conductive trace W, and the first resistor Ris used as a jumper for any section of the first conductive trace Wand/or the second conductive trace W.

13 FIG. 21 21 21 22 22 21 21 22 Takingas an example, in this embodiment, the first resistor Ris arranged on the first conductive trace Wto serve as a jumper for the section of the first conductive trace Wthat crosses the second conductive trace W, and the second conductive trace Wmaintains the original circuit. In other words, in this embodiment, the first conductive trace Wcan be regarded as two independent conductive traces, and these two conductive traces are electrically connected together by the first resistor Racross the second conductive trace W.

14 FIG. 21 22 22 21 21 22 21 21 2 21 22 21 Takingas another example, in this embodiment, the first resistor Ris arranged on the second conductive trace Wto serve as a jumper for the section of the second conductive trace Wthat crosses the first conductive trace W, and the first conductive trace Wmaintains the original circuit. In other words, in this embodiment, the second conductive trace Wcan be regarded as two independent conductive traces, and these two conductive traces are electrically connected together by the first resistor Racross the first conductive trace W. Here, the LED circuitcan solve the problem of short circuit caused by the crossing of the first conductive trace Wand the second conductive trace Wthrough the first resistor Rwithout redesigning the circuit.

15 FIG. 15 FIG. 2 21 21 21 21 21 22 22 22 22 22 21 21 21 22 22 22 21 21 21 22 22 22 p p n n p p n n p n p n p n p n. Please further refer to, which is a schematic diagram of a LED circuitaccording to the twelfth embodiment of the present disclosure. As shown in, in some embodiments, the first terminal setincludes a positive electrode(hereinafter referred to as the first positive electrode) and a negative electrode(hereinafter referred to as the first negative electrode), and the second terminal setincludes another positive electrode(hereinafter referred to as the second positive electrode) and another negative electrode(hereinafter referred to as the second negative electrode). In addition, in some embodiments, the first positive electrodeand the first negative electrodeare respectively disposed at the two ends of the first conductive trace W, and the second positive electrodeand the second negative electrodeare respectively disposed at the two ends of the second conductive trace W. In other words, the plurality of first light-emitting units Dare located on the circuit between the first positive electrodeand the first negative electrode, and the plurality of second light-emitting units Dare located on the circuit between the second positive electrodeand the second negative electrode

21 22 21 22 21 22 21 22 21 22 20 21 22 22 2 22 22 21 22 22 21 22 p p n n In some embodiments, the plurality of first light-emitting units Dand the plurality of second light-emitting units Dare alternately arranged with each other to form an array. Here, the user can alternately control the plurality of first light-emitting units Dand the plurality of second light-emitting units Dto produce various lighting effects or display effects. However, since the pins of each light-emitting unit D/D, the positions of each positive electrode/and each negative electrode/are fixed and the circuit boardonly includes one conductive layer, the first conductive trace Wand the second conductive trace Wcross each other and cause a short circuit, and a section and another section of the second conductive trace Walso cross each other and cause a short circuit. Here, in some embodiments, the LED circuitfurther includes another resistor R(hereinafter referred to as the second resistor R) to be disposed on the first conductive trace Wand/or the second conductive trace W, and the second resistor Ris used as a jumper for any section of the first conductive trace Wand/or the second conductive trace W.

15 FIG. 21 22 22 21 22 22 22 22 22 21 22 22 p n. Takingas an example, in this embodiment, the first resistor Ris disposed on the second conductive trace Wto serve as a jumper for a section of the second conductive trace Wthat crosses the first conductive trace W, and the second resistor Ris also disposed on the second conductive trace Wto serve as a jumper for a section of the second conductive trace Wthat crosses another section of the second conductive trace W. Here, the second conductive trace Wcan avoid crossing the first conductive trace Wand itself to cause a short circuit, so as to maintain the circuit between the second positive electrodeand the second negative electrode

16 FIG. 16 FIG. 16 FIG. 2 21 22 2 23 24 23 24 21 22 22 22 22 22 21 21 21 2 21 22 21 22 2 2 23 24 21 21 21 22 22 2 21 22 21 22 2 2 p n p n p n p n Please refer to.is a schematic diagram of the LED circuitaccording to the thirteenth embodiment of the present disclosure. In some embodiments, the resistor is further used to replace any section of the first conductive trace Wor any section of the second conductive trace W. Takingas an example, in this embodiment, the LED circuitfurther includes two resistors Rand R(hereinafter referred to as the third resistor Rand the fourth resistor R, respectively). Since the first resistor Rand the second resistor Rare arranged on the second conductive trace W, the resistance value of the circuit between the second positive electrodeand the second negative electrode(i.e., the second conductive trace W) is higher than that of the circuit between the first positive electrodeand the first negative electrode(i.e., the first conductive trace W). Here, when a fixed voltage is applied to the LED circuitto make the plurality of first light-emitting units Dand the plurality of second light-emitting units Demit light, the light-emitting effect of each light-emitting unit D/Don the LED circuitwill be affected by the resistance value and vary, which further makes the light-emitting effect or display effect of the LED circuituneven. Therefore, in some embodiments, the third resistor Rand the fourth resistor Rare arranged on the first conductive trace Wso that the resistance value of the circuit between the first positive electrodeand the first negative electrodeis equal to that of the circuit between the second positive electrodeand the second negative electrode. At this time, when this fixed voltage is applied to the LED circuitto make the plurality of first light-emitting units Dand the plurality of second light-emitting units Demit light, the light-emitting effect of each light-emitting unit D/Don the LED circuitis the same, which further makes the light-emitting effect or display effect of the LED circuitaverage.

21 22 23 24 In some embodiments, the first electronic component E, the second electronic component E, the third electronic component E, and the fourth electronic component Ecan be any kind of integrated circuit (IC), packaged chip, or semiconductor component, such as but not limited to a central processing unit (CPU), a system-on-chip (SoC), a microprocessor, a digital signal processor (DSP), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a microcontroller unit (MCU), a light-emitting diode (LED), a diode, a bipolar junction transistor (BJT), Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET), resistor, capacitor, and inductor.

21 22 In some embodiments, the first light-emitting unit Dand the second light-emitting unit Dmay be, but not limited to, light-emitting diodes, organic light-emitting diodes (Organic LED, OLED), quantum-dot light-emitting diodes (Quantum-dot LED, QLED), mini light-emitting diodes (Mini LED), or micro light-emitting diodes (Micro LED).

1 FIG. 2 FIG. 1 10 11 12 13 10 10 10 Referring again toand, in some embodiments, a liquid crystal display device (LCD device)includes a backlight module, a quantum dot repairing film, a quantum dot layer, and a panel module. In some embodiments, when the backlight moduleis in use, when multiple switches are actuated simultaneously, since each switch is turned on and off instantaneously, the voltage of each switch will be instantaneously pulled up and dropped suddenly. As a result, the power supply circuit that supplies power to the scanning circuit will generate a resonance phenomenon, resulting in the problem of low-frequency noise. In view of this, the following embodiments further describe various LED backlight panels. In some embodiments, the LED backlight panels of the following embodiments can be used to implement or be applied to the backlight module. However, the present disclosure is not limited to this. Under different design considerations or application scenarios, other structures, processes, or manufacturing processes can be adopted to implement the backlight moduledisclosed in the present disclosure.

17 FIG. 18 FIG. 300 302 304 306 As shown inand, in some embodiments, an LED backlight panelincludes a circuit board, a plurality of drive lines, and a plurality of scan lines.

302 308 302 308 308 The circuit boardhas an operable area (Active Area). The control circuit of the circuit boardis used to control the light emission at a specified position in the operable areato display a preset visual effect in the operable area.

304 302 308 31 304 31 308 31 304 308 The drive linesare located on the circuit boardand are sequentially arranged on the operable areain the first arrangement direction D. The drive linesare the wiring arranged in the first arrangement direction Don the operable area. It should be noted that the drive signal sgcan be transmitted via the drive linesto the specified light emission point P (to be described later) on the operable areato control the brightness and emission time of the light emitted by the specified light emission point P.

306 302 304 308 306 304 31 32 33 34 32 18 FIG. The scan linesare located on the circuit boardand define a plurality of light emission points P in a matrix configuration with these drive lineson the operable area. The relative positions of the multiple light emission points P formed by the same scan lineand these drive lines(such as the multiple light emission points P, or the multiple light emission points P, or the multiple light emission points P, or the multiple light emission points Pshown in) are staggered from each other in the second arrangement direction D.

32 302 308 306 306 32 32 306 31 306 32 306 31 32 The scan signal sgof the circuit boardcan be transmitted to the operable areavia the specified scan line, so that the light emission point P electrically connected to the specified scan linecan obtain the scan signal sg. In some embodiments, the scan signal sgcan turn on the switch electrically connected to the light emission point P, so that the light emission point P corresponding to the scan lineconnected to the turned-on switch can obtain the drive signal sg(to be described later). Conversely, the scan linethat does not send the scan signal sgfails to turn on the switch, so that the light emission point P on this scan linewill not obtain the drive signal sg(the light emission point P that does not obtain the scan signal sgwill not emit light).

31 32 31 32 18 FIG. In some embodiments, the first arrangement direction Dis different from the second arrangement direction D. As shown in, the first arrangement direction Dis perpendicular to the second arrangement direction D.

32 306 304 32 32 304 32 304 32 19 FIG.A 19 FIG.B 19 FIG.C 19 FIG.D In some embodiments, the scan signal sgis sequentially sent to the designated scan linesaccording to the scanning sequence. Specifically, in the same scanning sequence, only one light emission point P in the light emission points P formed by each drive linereceives the scan signal sg, and these light emission points P that receive the same scan signal sgare distributed at different sequential positions on the corresponding drive lines. That is to say, the positions of these light emission points P that receive the same scan signal sgon the corresponding drive linesare relatively sorted in the second arrangement direction D(examples will be given later in,,, or).

302 310 310 302 304 306 32 306 310 310 In some embodiments, the circuit boardincludes a power supply circuit. The power supply circuitis located on the circuit boardand is coupled to these drive linesand these scan linesto supply power. In the same scanning sequence, the adjacent light emission points P arranged in the same row will not receive the scan signal sgsimultaneously, so that multiple switches electrically connected to the light emission points P in the same row will not operate (turn on and off) simultaneously. Here, the voltage change caused by each switch connected to the same scan lineto the power supply circuitcan be reduced to suppress the resonance phenomenon of the resonant elements in the power supply circuit.

300 306 32 In some embodiments, the LED backlight panelcan use a preset number of scan linesas a light emission point scan group. At the beginning of a scanning sequence, each light emission point P in the same light emission point scan group can receive the scan signal sgrespectively (details will be described later).

17 FIG. 18 FIG. 300 312 312 302 306 312 32 306 312 32 306 32 304 In some embodiments, as shown inand, the LED backlight panelalso includes a scanning circuit. The scanning circuitis located on the circuit boardand is coupled to these scan lines. The scanning circuitis used to send the scan signal sgto these scan lines. In each scanning sequence, the scanning circuitsends the scan signal sgto one of these scan lines, and the arrangement order of multiple light emission points P among these light emission points P that receive the scan signal sgon these drive linesis staggered from each other.

18 FIG. 304 314 316 318 320 306 322 324 326 328 314 316 318 320 308 31 322 324 326 328 308 32 300 322 324 326 328 32 In some embodiments, as shown in, take four drive lines(hereinafter referred to as the first drive line, the second drive line, the third drive line, and the fourth drive linerespectively) and four scan lines(hereinafter referred to as the first scan line, the second scan line, the third scan line, and the fourth scan linerespectively) as an example. The first drive line, the second drive line, the third drive line, and the fourth drive lineare sequentially arranged in the operable areaalong the first arrangement direction D. The first scan line, the second scan line, the third scan line, and the fourth scan lineare sequentially arranged in the operable areaalong the second arrangement direction D. Here, the LED backlight panelneeds to perform four scans in one scan cycle. In other words, in one scan cycle, the first scan line, the second scan line, the third scan line, and the fourth scan linewill all send a scan signal sgonce.

31 32 33 34 18 FIG. 19 FIG.A 19 FIG.B 19 FIG.C 19 FIG.D In some embodiments, these light emission points P can be divided into multiple first light emission points P, multiple second light emission points P, multiple third light emission points P, and multiple fourth light emission points Paccording to the scanning sequence. The following description takes,,,, oras an example.

322 314 316 318 320 31 31 31 322 314 311 31 322 316 312 31 322 318 313 31 322 320 314 19 FIG.A In some embodiments, the intersections of the first scan linewith the first drive line, the second drive line, the third drive line, and the fourth drive lineare these first light emission points P. As shown in the first light emission point Pin, the first light emission point Pwhere the first scan lineintersects the first drive lineis the first light emission point P, the first light emission point Pwhere the first scan lineintersects the second drive lineis the first light emission point P, the first light emission point Pwhere the first scan lineintersects the third drive lineis the first light emission point P, and the first light emission point Pwhere the first scan lineintersects the fourth drive lineis the first light emission point P.

324 314 316 318 320 32 32 32 324 314 321 32 324 316 322 32 324 318 323 32 324 320 324 19 FIG.B In some embodiments, the intersections of the second scan linewith the first drive line, the second drive line, the third drive line, and the fourth drive lineare these second light emission points P. As shown in the second light emission point Pin, the second light emission point Pwhere the second scan lineintersects the first drive lineis the second light emission point P, the second light emission point Pwhere the second scan lineintersects the second drive lineis the second light emission point P, the second light emission point Pwhere the second scan lineintersects the third drive lineis the second light emission point P, and the second light emission point Pwhere the second scan lineintersects the fourth drive lineis the second light emission point P.

326 314 316 318 320 33 33 33 326 314 331 33 326 316 332 33 326 318 333 33 326 320 334 19 FIG.C In some embodiments, the third scan lineintersects the first drive lineand the second drive line, the third drive line, and the fourth drive linecorrespond to these third light emission points P. As shown in the third light emission points Pin, the third light emission point Pwhere the third scan lineintersects the first drive lineis the third light emission point P, the third light emission point Pwhere the third scan lineintersects the second drive lineis the third light emission point P, the third light emission point Pwhere the third scan lineintersects the third drive lineis the third light emission point P, and the third light emission point Pwhere the third scan lineintersects the fourth drive lineis the third light emission point P.

328 314 316 318 320 34 34 34 328 314 341 34 328 316 342 34 328 318 343 34 328 320 344 19 FIG.D In some embodiments, the fourth scan lineintersects the first drive line, the second drive line, the third drive line, and the fourth drive line, corresponding to these fourth light emission points P. As shown in the fourth light emission points Pin, the fourth light emission point Pwhere the fourth scan lineintersects the first drive lineis the fourth light emission point P, the fourth light emission point Pwhere the fourth scan lineintersects the second drive lineis the fourth light emission point P, the fourth light emission point Pwhere the fourth scan lineintersects the third drive lineis the fourth light emission point P, and the fourth light emission point Pwhere the fourth scan lineintersects the fourth drive lineis the fourth light emission point P.

19 FIG.A 19 FIG.B 19 FIG.C 19 FIG.D 322 32 311 312 313 314 322 32 324 32 321 322 323 324 324 32 326 32 331 332 333 334 326 32 328 32 341 342 343 344 328 32 300 16 311 312 313 314 321 322 323 324 331 332 333 334 341 342 343 344 32 304 310 310 In some embodiments, as shown in, during the first scanning sequence, the first scan linesends the scan signal sg, and the first light emission points (P, P, P, P) on the first scan linereceive the scan signal sg; as shown in, during the second scanning sequence, the second scan linesends the scan signal sg, and the second light emission points (P, P, P, P) on the second scan linereceive the scan signal sg; as shown in, during the third scanning sequence, the third scan linesends the scan signal sg, and the third light emission points (P, P, P, P) on the third scan linereceive the scan signal sg; as shown in, during the fourth scanning sequence, the fourth scan linesends the scan signal sg, and these fourth light emission points (P, P, P, P) on the fourth scan linereceive the scan signal sg. Here, when the LED backlight panelscans thelight emission points P in this example, only four scans are needed to scan all the light emission points P without increasing the scanning rate. In each scanning sequence, when the first light emission points (P, P, P, P), the second light emission points (P, P, P, P), the third light emission points (P, P, P, P), or the fourth light emission points (P, P, P, P) that receive the scan signal sgemit light, the arrangement order on each drive lineis staggered from each other. In this way, the switches connected to adjacent light emission points P do not operate (turn on and off) simultaneously, and the power supply circuitdoes not generate resonance, so as to suppress the resonance noise of the power supply circuit.

300 330 330 304 31 304 17 FIG. In some embodiments, the LED backlight panelalso includes a driving circuit. The driving circuitis coupled to these drive lines(see) and is used to send the drive signal sgto these drive lines.

300 332 332 304 306 31 304 31 304 32 31 32 31 32 31 300 31 304 314 316 318 320 306 322 324 326 328 18 FIG. 19 FIG.A 19 FIG.B 19 FIG.C 19 FIG.D In some embodiments, the LED backlight panelfurther includes multiple light emitting diodes. The multiple light emitting diodesare respectively coupled to the intersection positions of these drive linesand these scan linesthat define the light emission points P, and are used to emit light according to the drive signal sg. For example, after completing a scanning task (the end of the first scanning sequence, the second scanning sequence, the third scanning sequence, and the fourth scanning sequence), these drive linescan sequentially send the drive signal sgto the specified drive lines, and the light emission points P that receive the scan signal sgcan receive the drive signal sg. Conversely, the light emission points P that do not receive the scan signal sgwill not receive the drive signal sg. As a result, these light emission points P that receive the scan signal sgcan emit light according to the drive signal sg. For another example, the LED backlight panelcan also send the drive signal sgbefore performing the scanning task. In some embodiments, these drive linescan be the first drive line, the second drive line, the third drive line, or the fourth drive linein some embodiments, and these scan linescan be the first scan line, the second scan line, the third scan line, or the fourth scan linein some embodiments (as shown in,,,, or).

330 334 334 31 306 334 306 322 324 326 328 334 304 300 304 306 332 In some embodiments, the driving circuitincludes a drive signal generation module. The drive signal generation modulehas multiple transmission channels and is used to generate the drive signal sg. In some embodiments, the number of these transmission channels is a multiple of the number of these scan lines. For example, if the drive signal generation modulehas 64 transmission channels and the number of scan linesis 4 (such as the first scan line, the second scan line, the third scan line, and the fourth scan linein some embodiments), the drive signal generation modulecan control the number of drive linesto be 16. In other words, the LED backlight panelin this example can be configured with 16 drive linesand 4 scan lines, and the number of light emitting diodescan be configured to be 64.

17 FIG. 312 336 336 334 306 336 32 306 336 32 32 336 In some embodiments, as shown in, the scanning circuitfurther includes multiple scan switches. These scan switchesare configured between the drive signal generation moduleand each light emission point P on these scan lines. When these scan switchesare turned on, the scan signal sgis sent to each light emission point P on the specified scan line. Here, these scan switchescan be turned on in response to the scan signal sgto transmit the scan signal sg. In some embodiments, the scan switchcan be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

336 304 336 306 In some embodiments, these scan switchesare respectively connected to each light emission point P on these drive linesin a one-to-one manner. In other words, the number of scan switchescan be configured according to the number of each light emission point P on the scan line.

306 336 338 340 342 344 338 322 340 324 342 326 344 328 334 32 322 338 32 32 31 311 312 313 314 322 334 338 340 342 344 334 32 338 338 340 342 344 322 32 334 336 In some embodiments, taking four scan linesas an example, these scan switchesinclude a first scan switch, a second scan switch, a third scan switch, and a fourth scan switch. The first scan switchis coupled to each light emission point P on the first scan line. The second scan switchis coupled to each light emission point P on the second scan line. The third scan switchis coupled to each light emission point P on the third scan line. The fourth scan switchis coupled to each light emission point P on the fourth scan line. For example, when the drive signal generation modulesends the scan signal sgto the first scan line, the first scan switchis turned on in response to the scan signal sg, so that the scan signal sgcan be sent to the specified first light emission points P(such as the first light emission points P, P, P, P) through the first scan line. It should be noted that the drive signal generation modulecan turn on the first scan switch, the second scan switch, the third scan switch, and the fourth scan switchaccording to the scanning sequence. For example, in the first scanning sequence, the drive signal generation modulesends the scan signal sgto the first scan switchto turn on the first scan switch. Among them, the second scan switch, the third scan switch, and the fourth scan switchremain off. Accordingly, in the first scanning sequence, only the first scan linesends the scan signal sg. In some embodiments, the drive signal generation modulecan also send a switch signal to drive these scan switchesto turn on.

336 322 32 32 338 338 314 31 311 322 314 Taking the scan switchas a MOSFET as an example, when the first scan linesends the scan signal sg, the scan signal sgcan trigger the gate of the first scan switch, causing the source and drain of the first scan switchto conduct. If the first drive linesends the drive signal sg, the first light emission point Pwhere the first scan lineintersects the first drive linecan be lit up.

302 In some embodiments, the circuit boardcan be a printed circuit board or a flexible circuit board.

332 332 332 In some embodiments, the light emitting diodescan be micro light emitting diodes (Micro LED), mini light emitting diodes (Mini LED), or organic light emitting diodes (OLED). In some embodiments, the light emitting diodeswith the same wavelength can be respectively arranged at each light emission point P, or the light emitting diodeswith different wavelengths can be respectively arranged at each light emission point P.

1 FIG. 2 FIG. 1 10 11 12 13 13 13 13 Referring again toand, in some embodiments, the liquid crystal display deviceincludes a backlight module, a quantum dot repairing film, a quantum dot layer, and a panel module. In some embodiments, when the panel moduleis in use, it may happen that the materials of the conductive gold balls are different from the materials of each layer in the thin-film transistor liquid crystal substrate, and when forming the conductive gold balls on the thin-film transistor liquid crystal substrate, the instruments and materials of the process need to be replaced to perform the step of forming the conductive gold balls, which makes the panel manufacturing process complicated and time-consuming. In view of this, the following embodiments further describe various thin-film transistor liquid crystal panel units and manufacturing methods of the thin-film transistor liquid crystal panel units. In some embodiments, the thin-film transistor liquid crystal panel units and the manufacturing methods of the thin-film transistor liquid crystal panel units in the following embodiments can be used to implement or be applied to the panel module. However, the present disclosure is not limited to this. Under different design considerations or application scenarios, other structures, processes, or manufacturing processes can be adopted to implement the panel moduledisclosed in the present disclosure.

20 22 FIGS.to 20 21 FIGS.and 22 FIG. 20 21 FIGS.and 4 4 4 4 40 41 42 43 40 401 41 40 42 401 40 40 42 41 43 41 42 40 42 Please refer to.are side plan views of different embodiments of the thin-film transistor liquid crystal display (TFT-LCD) panel unitrespectively, andis an operation flowchart of the manufacturing method of the TFT-LCD panel unit. A TFT-LCD panel unitis suitable for forming a TFT-LCD panel or a TFT-LCD display. As shown in, the TFT-LCD panel unitincludes a thin-film transistor (TFT) substrate, a liquid crystal layer, a metal post, and a color filter substrate. The thin-film transistor substrateincludes a plurality of electrode layers. The liquid crystal layeris disposed on a surface of the thin-film transistor substrate. The metal postextends from one of the plurality of electrode layersalong a normal direction of the surface of the thin-film transistor substrate(corresponding to the Y direction in the rectangular coordinate system) to be exposed on the surface of the thin-film transistor substrate, and the metal postis adjacent to the liquid crystal layer. The color filter substrateis disposed on the liquid crystal layerand the metal postand is electrically connected to the thin-film transistor substratethrough the metal post.

20 21 FIGS.and 22 FIG. 4 40 40 40 40 401 42 41 42 401 40 40 42 401 40 The following will takeas examples to illustrate the manufacturing method of the TFT-LCD panel unit. As shown in, in some embodiments, first, the thin-film transistor substrateis formed (step S. The detailed steps of step Swill be described later), wherein the thin-film transistor substrateincludes a plurality of electrode layers. Then, the metal postis formed (step S), wherein the metal postextends from one of the plurality of electrode layersalong the normal direction (Y direction) of the surface of the thin-film transistor substrateto be exposed on the surface of the thin-film transistor substrate. In other words, a bottom surface of the metal postis directly coupled to one of the plurality of electrode layers, rather than directly coupled to the surface of the thin-film transistor substrate.

41 40 41 41 42 42 41 42 40 43 41 42 43 40 42 43 4 43 After step S, a liquid crystal material is disposed on the thin-film transistor (TFT) substrateto form a liquid crystal layer, wherein the liquid crystal layeris adjacent to the metal post(step S), and a thickness of the liquid crystal layeris approximately equal to a height of the metal postexposed on the surface of the thin-film transistor substrate. Finally, a color filter substrateis disposed on the liquid crystal layerand the metal post, wherein the color filter substrateis electrically connected to the thin-film transistor substratethrough the metal post(step S). Here, the manufacturing process of the TFT-LCD panel unitcan be completed. In some embodiments, the manufacturing method of the color filter substrateis well-known to those skilled in the art to which this disclosure pertains, so it will not be described in detail.

23 24 FIGS.and 23 FIG. 24 FIG. 23 FIG. 20 FIG. 21 FIG. 40 40 401 40 401 401 401 42 401 401 401 40 42 401 40 42 401 401 40 Please further refer to.is a side plan view of an embodiment of the thin-film transistor substrate, andis an operational flowchart of a manufacturing method of the thin-film transistor substrate. As shown in, in some embodiments, the plurality of electrode layersin the thin-film transistor substrateinclude a gate layerG, a drain layerD, and a source layerS. In other words, the metal postextends from the gate layerG, the drain layerD, or the source layerS to be exposed on the surface of the thin-film transistor substrate. Takingas an example, in this embodiment, the metal postextends from the gate layerG to be exposed on the surface of the thin-film transistor substrate. Takingas an example, in this embodiment, the metal postextends from the drain layerD or the source layerS to be exposed on the surface of the thin-film transistor substrate.

40 400 402 402 403 404 404 401 400 402 400 401 401 400 402 403 402 401 401 403 141 403 141 401 401 404 401 401 403 141 In some embodiments, the TFT substratefurther includes a glass layer, an insulating layer(hereinafter referred to as the first insulating layer), a channel layer, and another insulating layer(hereinafter referred to as the second insulating layer). In some embodiments, the gate layerG is disposed on the glass layer, and the first insulating layeris disposed on the glass layerto cover the gate layerG. In other words, the gate layerG is disposed between the glass layerand the first insulating layer. In some embodiments, the channel layeris disposed on the first insulating layer, wherein the drain layerD and the source layerS are respectively disposed on two sides of the channel layerand are spaced apart by an interval. In other words, the channel layerin the intervalis not covered by the drain layerD and the source layerS. In some embodiments, the second insulating layeris disposed on the drain layerD, the source layerS, and the channel layerin the interval.

23 FIG. 24 FIG. 40 40 401 400 400 402 400 401 401 403 402 402 401 401 403 401 401 141 403 404 401 401 403 141 404 The following will takeas an example to illustrate the manufacturing method of the TFT substrate. As shown in, in step S, first, a gate layerG is formed on the glass layer(step S). Then, a first insulating layeris formed on the glass layerto cover the gate layerG (step S), and a channel layeris formed on the first insulating layer(step S). Subsequently, a drain layerD and a source layerS are respectively formed on two sides of the channel layer, wherein the drain layerD and the source layerS are spaced apart by an interval(step S). Finally, the second insulating layeris formed on the drain layerD, the source layerS, and the channel layerin the interval(step S).

4 4 401 401 401 42 40 401 401 401 40 20 21 FIGS.and 23 FIG. 23 FIG. 20 21 FIGS.and It should be noted that, in some embodiments, the viewing angle of the TFT-LCD panel unitshown incorresponds to the XY plane in the Cartesian coordinate system, and the viewing angle of the TFT-LCD panel unitshown incorresponds to the YZ plane in the Cartesian coordinate system. In other words, the gate layerG, drain layerD, and source layerS shown inextend along the X direction (as shown in). Here, the metal postextends along the normal direction (Y direction) of the surface of the thin-film transistor substrateand from the extended gate layerG/drain layerD/source layerS to be exposed on the surface of the thin-film transistor substrate.

42 401 402 403 404 40 In some embodiments, the metal postand the plurality of electrode layers, the first insulating layer, the channel layer, and the second insulating layerin the thin-film transistor substratecan be formed through deposition techniques. The deposition techniques include, but are not limited to, sputtering technology, electron beam evaporation technology, chemical vapor deposition (CVD) technology, physical vapor deposition (PVD) technology, area selective deposition (ASD) technology, and atomic layer deposition (ALD) technology.

42 401 42 401 401 401 42 401 42 41 401 401 401 401 401 401 42 401 401 401 42 404 40 404 40 42 401 401 401 In some embodiments, the material of the metal postis the same as that of one of the plurality of electrode layers. In other words, the material of the metal postis the same as the material of the gate layerG, the drain layerD, or the source layerS. In addition, since the material of the metal postis the same as that of one of the plurality of electrode layers, the step of forming the metal post(step S) is synchronized with the step of forming the gate layerG, the drain layerD, or the source layerS. In other words, in response to the completion of the formation of the gate layerG/drain layerD/source layerS, the metal postis subsequently formed to extend from the gate layerG/drain layerD/source layerS, and the metal postwill be exposed on the surface of the second insulating layer(corresponding to the surface of the thin-film transistor substrate) after the formation of the second insulating layeris completed. Here, the thin-film transistor substratecan form the metal post, the gate layerG, the drain layerD, and the source layerS through the same set of process instruments and materials to save the cost of replacing process instruments and materials.

401 42 420 401 42 420 401 42 420 25 FIG. In some embodiments, the materials of the electrode layer, the metal post, and the metal truncated cone(which will be described in detail later in) can be various types of metals or alloys, such as but not limited to copper (Cu), aluminum (Al), copper-chromium-zirconium (CuCrZr) alloy, aluminum-zirconium (AlZr) alloy, beryllium-copper (BeCu) alloy, tungsten-copper (WCu) alloy, and silver-copper (AgCu) alloy. It should be noted that the materials of the electrode layer, the metal post, and the metal truncated conecan also be gold (Au). However, due to the high cost of gold, it is not suitable to be used as the material for the electrode layer, the metal post, and the metal truncated cone.

20 FIG. 21 FIG. 20 FIG. 21 FIG. 42 42 401 42 43 42 42 401 42 401 401 Please refer toandagain. In some embodiments, the metal postis a cylinder, wherein the bottom surface of the metal postis coupled to the surface of one of the plurality of electrode layers, and a top surface of the metal postis coupled to the color filter substrate. In addition, in some embodiments, the cylindrical metal postcan be formed through repeated deposition. Takingas an example, in this embodiment, the bottom surface of the metal postis coupled to the surface of the gate layerG. Takingas an example, in this embodiment, the bottom surface of the metal postis coupled to the surface of the drain layerD/source layerS.

25 FIG. 25 FIG. 4 42 420 420 42 420 43 42 420 420 420 420 420 43 43 40 43 Please refer to, which is a schematic side view of another embodiment of the TFT-LCD panel unit. In some embodiments, the metal postfurther includes at least one metal truncated cone. A bottom surface of the at least one metal truncated coneis coupled to the top surface of the metal post, and a top surface of the at least one metal truncated coneis coupled to the color filter substrate. Takingas an example, in this embodiment, the metal postfurther includes two metal truncated cones. In some embodiments, the metal truncated conecan be formed through repeated deposition, and the area of each deposition gradually decreases. Among them, when the area of the top surface of the metal truncated coneis smaller, it means that the metal truncated conegradually approximates a cone. Here, the metal truncated conecan penetrate the insulating layer in the color filter substrateto be directly coupled to the conductive film layer in the color filter substrate, thereby electrically connecting the thin-film transistor substrateto the color filter substrate.

26 FIG. 26 FIG. 4 42 42 401 42 43 42 42 42 42 43 43 40 43 Please refer to.is a schematic side view of yet another embodiment of the TFT-LCD panel unit. In some embodiments, the metal postis a truncated cone, wherein the bottom surface of the metal postis coupled to the surface of one of the plurality of electrode layers, and the top surface of the metal postis coupled to the color filter substrate. In some embodiments, the truncated cone-shaped metal postcan be formed through repeated depositions, and the area of each deposition gradually decreases. Here, when the area of the top surface of the metal postis smaller, it means that the metal postgradually approximates a cone. Here, the metal postcan penetrate the insulating layer in the color filter substrateto be directly coupled to the conductive film layer in the color filter substrate, thereby electrically connecting the thin-film transistor substrateto the color filter substrate.

23 FIG. 402 404 2 Please refer toagain. In some embodiments, the materials of the first insulating layerand the second insulating layerhave insulating properties, such as but not limited to glass, silicon (Si), silicon dioxide (SiO), gallium arsenide (GaAs), silicon carbide (SiC), silicone, epoxy resin, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene terephthalate (PET), and polyetherimide.

403 In some embodiments, the material of the channel layercan be a semiconductor material, such as but not limited to silicon (Si), amorphous silicon, single-crystalline silicon (a-silicon), poly-silicon, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), and gallium nitride (GaN).

1 FIG. 2 FIG. 1 10 11 12 13 13 13 13 13 Referring toandagain, in some embodiments, a liquid crystal display deviceincludes a backlight module, a quantum dot repairing film, a quantum dot layer, and a panel module. In some embodiments, when the panel moduleis in use, there may be a problem that since the thin-film transistors and/or color filters included in the panel moduleare made of thin glass materials, the panel is prone to breakage or cracking during cutting or disconnection, which affects the quality of the liquid crystal display. In view of this, the following embodiments further describe various panel manufacturing methods. In some embodiments, the panel manufacturing methods described in the following embodiments can be used to implement or apply to the panel module. However, the present disclosure is not limited thereto. Under different design considerations or application scenarios, other structures, processes, or manufacturing processes can be used to implement the panel moduledisclosed in the present disclosure.

27 FIG. 28 FIG. 27 FIG. 28 FIG. 510 51 510 52 518 51 52 520 510 53 520 54 524 53 54 524 55 55 510 520 51 52 53 54 Please refer toand.is a schematic diagram of a panel according to some embodiments of the present disclosure, andis a schematic diagram of the positions of each cutting line according to some embodiments of the present disclosure. The panel manufacturing method includes: cutting on a first substrateto form a first cutting line L; cutting at different positions on the first substrateto form a second cutting line L, wherein there is a first excess materialbetween the first cutting line Land the second cutting line L; cutting on a second substrateadjacent to the first substrateto form a third cutting line L; cutting at different positions on the second substrateto form a fourth cutting line L, wherein there is a second excess materialbetween the third cutting line Land the fourth cutting line L; finally, cutting the second excess materialto form a fifth cutting line L. When the fifth cutting line Lis formed, the first substrateand the second substratewill break at the first cutting line L, the second cutting line L, the third cutting line L, and the fourth cutting line L.

510 514 516 516 5162 5164 5162 516 514 5164 516 518 51 5164 516 51 5164 516 518 52 518 51 The first substrateincludes a display areaand a terminal area. The terminal areahas a first endand a second end. The first endof the terminal areais connected to the display area, and the second endof the terminal areais connected to the first excess material. The first cutting line Lis located at the second endof the terminal area. Specifically, the first cutting line Lis formed between the second endof the terminal areaand the first excess material. The second cutting line Lis located on the other side of the first excess materialrelative to the first cutting line L.

53 5162 516 53 520 520 516 514 510 54 52 510 55 51 55 520 5164 516 518 510 The third cutting line Lcorresponds to the first endof the terminal area. That is, when the third cutting line Lis formed by cutting the second substrate, it is aligned in the second substrateopposite to the connection between the terminal areaand the display areain the first substrate. The fourth cutting line Lcorresponds to the second cutting line Lin the first substrate, and the fifth cutting line Lcorresponds to the first cutting line L. That is, the fifth cutting line Lis aligned in the second substrateopposite to the position between the second endof the terminal areaand the first excess materialin the first substrate.

28 FIG. 510 512 512 518 512 514 516 518 5182 5184 512 5182 518 5164 516 512 5184 518 a Please refer toagain. In some embodiments, the first substrateincludes a plurality of first sub-substratesadjacent to each other, and each first sub-substrateis connected to each other by the first excess material. Each first sub-substrateincludes a display areaand a terminal area. Each first excess materialincludes a first sideand a second sideopposite to each other. Each first sub-substrateis connected to the first sideof the first excess materialby the second endof the terminal area, and is connected to another adjacent first sub-substrateby the second sideof the first excess material.

520 522 522 524 524 5242 5244 522 5242 524 5244 524 522 a. In some embodiments, the second substrateincludes a plurality of second sub-substratesadjacent to each other. The second sub-substratesare connected by the second excess material. The second excess materialhas a third sideand a fourth sideopposite to each other respectively. Each second sub-substrateis connected to the third sideof a second excess materialrespectively, and is connected to the fourth sideof the second excess materialby another adjacent second sub-substrate

27 FIG. 510 5122 5124 510 51 52 5122 510 Please refer toagain. In some embodiments, the first substratehas a first upper surfaceand a first lower surfaceopposite to each other. When cutting the first substrateto generate the first cutting line Land the second cutting line Lrespectively, the first upper surfaceof the first substrateis cut.

520 5226 5228 5228 5124 510 520 53 54 5226 520 In some embodiments, the second substratehas a second upper surfaceand a second lower surfaceopposite to each other. The second lower surfaceis attached to the first lower surfaceof the first substrate. When cutting the second substrateto generate the third cutting line Land the fourth cutting line Lrespectively, the second upper surfaceof the second substrateis cut.

28 FIG. 51 52 53 54 55 510 520 510 520 510 520 51 52 5122 5124 510 5122 5124 5122 5124 51 52 51 52 Please refer toagain. During cutting, the cutter wheel can be pressed against the positions where the first cutting line L, the second cutting line L, the third cutting line L, the fourth cutting line Lor the fifth cutting line Lare expected to be generated respectively, and the cutter wheel is moved relatively at these positions to scribe a scribe groove on the first substrateor the second substrate. The scribe grooves formed by cutting cause vertical cracks in the first substrateor the second substrate, that is, the first substrateor the second substrateis partially broken at the scribe grooves. Specifically, at the first cutting line Land the second cutting line L, there is a partial break between the first upper surfaceand the first lower surfaceof the first substrate, and this break extends from the first upper surfaceto the first lower surface. The depth of the scribe groove (that is, the distance of the break between the first upper surfaceand the first lower surface) can vary depending on the angle, tooth depth, number of teeth of the cutter wheel and the thickness of the backing paper used when cutting with the cutter wheel. However, the depth of this scribe groove does not cause the first cutting line Lor the second cutting line Lto break immediately during cutting, and pressure must be applied to the first cutting line Lor the second cutting line Lto make it break.

53 54 5226 5228 520 5226 5228 53 54 53 54 Similarly, at the third cutting line Land the fourth cutting line L, there is a partial break between the second upper surfaceand the second lower surfaceof the second substrate. This break extends from the second upper surfacetowards the second lower surface. The depth of the cutting line is such that the third cutting line Lor the fourth cutting line Ldoes not break immediately during cutting, and pressure needs to be applied to the third cutting line Lor the fourth cutting line Lto make it break.

524 55 51 52 53 54 524 51 512 518 52 512 518 51 52 512 512 510 518 a a In some embodiments, when cutting the second excess materialto create the fifth cutting line L, the first cutting line L, the second cutting line L, the third cutting line L, and the fourth cutting line Lcan be subjected to the force generated when the cutter wheel presses against the second excess material, and then break. Since the first cutting line Lis the connection between the first sub-substrateand the first excess material, and the second cutting line Lis the connection between another first sub-substrateand the first excess material, when the first cutting line Land the second cutting line Lbreak, separation will occur between two adjacent first sub-substratesandin the first substrateand the first excess material.

53 522 524 54 522 524 53 54 522 522 520 524 a a The third cutting line Lis the connection between the second sub-substrateand the second excess material, and the fourth cutting line Lis the connection between another second sub-substrateand the second excess material. When the third cutting line Land the fourth cutting line Lbreak, separation will occur between two adjacent second sub-substratesandin the second substrateand the second excess material.

518 524 512 522 In some embodiments, after the first excess materialor the second excess materialis separated from the first sub-substrateor the second sub-substrate, it is removed as waste.

510 530 514 512 520 51 52 53 54 512 522 53 5162 516 512 516 512 524 520 530 516 524 53 522 524 516 512 In some embodiments, the first substratecan use a peripheral sealantto bond the display areaof each first sub-substrateto the second substrate. When the first cutting line L, the second cutting line L, the third cutting line L, and the fourth cutting line Lare all separated, the bonding between the first sub-substrateand the second sub-substratewill be maintained. In addition, since the position of the third cutting line Lcorresponds to the first endof the terminal areaof the first sub-substrate, the terminal areaof the first sub-substrateis adjacent to the second excess materialof the second substrate, and there is no peripheral sealantcoated between the terminal areaand the second excess material. Therefore, when the third cutting line Lbreaks and the second sub-substrateis separated from the second excess material, the terminal areaof the first sub-substratewill be exposed to the outside.

510 520 51 52 53 54 512 522 512 522 a a In some embodiments, the first substrateis a thin film transistor (TFT) substrate, and the second substrateis a color filter (CF). The thin-film transistor substrate and the color filter form the mother board of the liquid crystal display panel. Cutting the mother board can separate it into a plurality of unit substrates that meet the terminal requirements of the liquid crystal display. After the first cutting line L, the second cutting line L, the third cutting line L, and the fourth cutting line Lare all separated, the first sub-substrateand the second sub-substrate, which are separated from another adjacent first sub-substrateand another adjacent second sub-substratebut still attached to each other, are the above-mentioned unit substrates.

514 512 522 530 514 522 In some embodiments, liquid crystal is sealed in each unit substrate. The liquid crystal is located between the display areaof the first sub-substrateand the second sub-substrate. The peripheral sealantnot only bonds the display areaand the second sub-substratetogether but also forms a sealed space between them, and the liquid crystal is placed in this sealed space.

516 514 516 512 518 516 In some embodiments, the terminal areaconnected to the display areais used to set signal lines for electrical connection with external signal terminals. Thus, the cut unit substrate can receive external signals through the terminal area. Therefore, after the first sub-substrateis separated from the first excess material, the terminal areaneeds to be exposed to the outside.

510 520 51 52 53 54 512 522 In some embodiments, after cutting the first substrateand the second substraterespectively to form the first cutting line L, the second cutting line L, the third cutting line L, and the fourth cutting line L, if pressure is applied to each cutting line (such as breaking the panel), each cutting line will break, thereby achieving the effect of separating each first sub-substrateand each second sub-substrate.

530 516 510 520 530 516 51 51 512 54 516 512 540 29 30 FIGS.and 29 FIG. 30 FIG. However, since there is no peripheral sealantbetween the terminal areaof the first substrateand the second substrate, there is a lack of supporting force from the peripheral sealantunder the terminal area. When the cutter wheel cuts the area where the first cutting line Lis expected to be formed, the penetration may be insufficient, resulting in a shallow depth of the vertical crack of the first cutting line L. If pressure is applied to each cutting line to separate each first sub-substrateafter the cutter wheel cuts to form the fourth cutting line L, it is easy to cause horizontal cracks in the terminal areaof the first sub-substrate. Please refer to.is a microscopic image of the feather crack on the cutting section of the terminal area according to some embodiments of the present disclosure, andis an electron microscopic image of the feather crack on the cutting section of the terminal area according to some embodiments of the present disclosure. The direction of the horizontal crack is perpendicular to the direction of the vertical crack formed by each cutting line and presents a feather shape (hereinafter referred to as the feather crack).

540 516 512 522 In some embodiments, the feather crackscause many uneven marks on the surface of the cutting section of the terminal area, making this surface uneven. This uneven surface may affect the reliability of the subsequent product integrated by the first sub-substrateand the second sub-substrate.

540 512 512 540 512 Specifically, these feather cracksmay weaken the mechanical strength of the first sub-substrate. During the subsequent processing, assembly, or use of the first sub-substrate, these feather cracksmay further expand, leading to structural damage to the first sub-substrate.

516 512 512 540 516 512 As mentioned before, the terminal areaof the first sub-substratecan be used to electrically connect with external signal lines so that the first sub-substratecan obtain signals. The feather cracksmay cause the surface quality of the area in the terminal areaused for bonding with the signal lines to decline, resulting in poor bonding. This may further lead to problems such as open circuits, short circuits, or unstable signal transmission in the product integrated by the first sub-substrate.

28 FIG. 524 55 54 540 51 512 Please refer toagain. If the second excess materialis cut with a cutter wheel to form the fifth cutting line Lafter the fourth cutting line Lis formed by cutter wheel cutting, the generation of feather crackscan be reduced while the first cutting line Lbreaks to separate each first sub-substrate.

5122 5124 510 51 52 5226 5228 520 53 54 51 52 53 54 512 518 522 524 As mentioned before, there is partial fracture between the first upper surfaceand the first lower surfaceof the first substrateat the first cutting line Land the second cutting line L. There is partial fracture between the second upper surfaceand the second lower surfaceof the second substrateat the third cutting line Land the fourth cutting line L. Pressure needs to be applied to the first cutting line L, the second cutting line L, the third cutting line L, or the fourth cutting line Lto make them break and achieve the effect of separating each first sub-substratefrom the first excess materialand each second sub-substratefrom the second excess material.

524 55 55 524 55 53 54 55 53 54 When the second excess materialis cut by the cutter wheel to generate the fifth cutting line L, the stress generated by the cutter wheel cutting will be applied to the position where the fifth cutting line Lis generated on the second excess material. This stress will be evenly transmitted to both sides of the fifth cutting line L. The third cutting line Land the fourth cutting line Lare located on both sides of the fifth cutting line L, which promotes the breakage of the third cutting line Land the fourth cutting line Lunder pressure.

55 51 520 51 540 51 At the same time, the position of the fifth cutting line Lis aligned with the position of the first cutting line L. When the cutter wheel applies force to the second substrate, the first cutting line Lwill also be subjected to uniform pressure and break naturally, thus avoiding the generation of the feather cracksthat are easily formed when pressure is directly applied to the first cutting line Lto make it break.

51 54 516 512 Please refer to Table 1 below (listed at the end of the text). Table 1 below shows that in one embodiment (single-sided substrate thickness of 150 μm), when the first cutting line Lis broken by means such as breaking immediately after the fourth cutting line Lis formed by cutting with a cutter wheel, the depth and quantity of feather cracks generated in the terminal areaof the first sub-substrate.

516 512 It can be seen that in this case, the number of feather cracks generated in the terminal areaof the first sub-substrateis 695 pieces. Among them, 619 pieces have a feather crack depth of less than 50 μm, accounting for 22.82% of the total number, and 76 pieces have a feather crack depth greater than 50 μm, accounting for 2.79% of the total number.

55 51 516 512 Referring to Table 2 below (listed at the end of the text), Table 2 below shows that in one embodiment, when the fifth cutting line Lis cut with a cutter wheel and the first cutting line Lis naturally broken by stress, the depth and quantity of feather cracks generated in the terminal areaof the first sub-substrate.

516 512 518 When the number of the first sub-substrates is 1000 pieces, 23 pieces have a feather crack depth of less than 50 μm, and the maximum crack depth is 12 μm, that is, there is no feather crack with a depth greater than 50 μm. It can be seen that separating the terminal areaof the first sub-substrateand the first excess materialby cutting in this way can significantly reduce the number and depth of feather cracks.

524 522 55 55 51 In some embodiments, when the cutter wheel cuts the second excess materialof the second sub-substrateto form the fifth cutting line L, the force applied by the cutter wheel to the position where the fifth cutting line Lis generated can be 3 Newtons, and the cutting depth is 0.5 millimeters, so that the force received by the first cutting line Lis 3/3.2 Newtons for natural fracture. In some embodiments, the cutting force, cutting depth of the cutter wheel and the pressure received by the cutting line are not limited.

1 2 FIGS.and 1 10 11 12 13 13 13 13 Referring again to, in some embodiments, the liquid crystal display deviceincludes a backlight module, a quantum dot repairing film, a quantum dot layerand a panel module. In some embodiments, when the panel moduleis applied, there may be a problem that the display must provide stable and consistent picture quality under different usage scenarios. In view of this, the following embodiments further describe various image processing methods and image processing panels. In some embodiments, the image processing methods and image processing panels of the following embodiments can be used to implement or be applied to the panel module. However, the present disclosure is not limited to this. Under different design considerations or application scenarios, other structures, processes or manufacturing processes can be used to implement the panel moduledisclosed in the present disclosure.

31 FIG. 32 FIG. 31 FIG. 32 FIG. 600 606 600 602 604 604 602 602 60 606 604 606 610 620 610 620 610 602 62 620 610 600 620 620 64 604 66 Please refer toand.is a functional block diagram of an image processing panel according to some embodiments of the present disclosure, andis a flowchart of an image processing method according to some embodiments of the present disclosure. The image processing panel includes a display moduleand a drive module. The display moduleincludes a displayand a display circuit. The display circuitis electrically connected to the displayto control the displayto output a display screen (step S). The drive moduleis electrically connected to the display circuit, and the drive moduleincludes a computing moduleand a driving circuit. The computing moduleis electrically connected to the driving circuit. The computing moduleis used to detect the type of the display screen displayed by the display(step S). The driving circuitis electrically connected to the computing moduleand the display module. A plurality of driving parameter sets are set in the driving circuit. The driving circuitselects the corresponding driving parameter set according to the type of the display screen (step S), and drives the display circuitto adjust the display screen according to the driving parameter set (step S).

600 604 602 In some embodiments, when the display moduleis operating, the display circuitwill receive image signals from an input source, and control the displayto output a display screen according to these signals, so as to convert the image signals into a visible screen for the user to view.

604 602 In some embodiments, the display screen includes multiple types, such as a first type and a second type. Each type can be determined according to the display characteristics of the screen when the display circuitoutputs the display screen on the display. For example, the first type is a normal display screen, and the second type is a special screen.

602 602 604 The normal display screen is the screen output by the displayin general daily use scenarios, which meets the needs of the user for the displayin daily use scenarios. For example, when the user browses the web, processes documents, watches movies, etc., the load on the display circuitfor this type of display screen is relatively low.

604 600 600 604 602 600 600 600 The special screen refers to a high-contrast screen, a rapidly changing scene, a high-resolution movie, etc., or a screen with a heavy load on the display circuit. The special screen also includes the test screen generated during the performance test of the display module. Specifically, during the performance test of the display module, the stability of the display circuitneeds to be checked to ensure that the display screen output by the displaymeets the user's expectations. Therefore, during the performance test phase of the display module, the display modulewill be made to output, for example, a flicker test screen, a dynamic test screen, etc., so as to simulate the performance of the display moduleunder some high-load scenarios.

620 606 In some embodiments, the driving circuitin the drive moduleincludes an array of driving parameter sets, such as a first parameter set and a second parameter set. Each driving parameter set may include different driving parameters, such as charging time, charging speed, display time, pixel inversion method, page update frequency, gate voltage, pixel voltage, or other display parameters. Each driving parameter set may correspond to each type of display screen, for example, there is a first parameter set corresponding to the first type and a second parameter set corresponding to the second type.

620 604 602 602 604 602 600 The driving circuitcan drive the display circuitthrough the driving parameter set to adjust the display effect shown on the display, thereby optimizing the quality of the picture shown on the displayto meet the visual needs of users. As mentioned above, when the types of display screens are different, the load borne by the display circuitmay be different. At this time, if the same driving parameter set is used to adjust the display screen, the quality of the display screen presented on the displaymay be poor when the display moduledisplays individual types of display screens.

620 600 602 620 600 602 600 For example, in an embodiment where the first type is a normal display screen and the second type is a special screen, if the driving parameter set in the driving circuitonly has the first parameter set corresponding to the normal display screen, when the display modulewants to output a special screen, unexpected bad effects such as horizontal stripes, vertical stripes, and squares will appear on the display. And if the driving parameter set in the driving circuitonly has the second parameter set corresponding to the special screen, when the display modulewants to output back to the normal display screen, the display screen on the displaymay have uneven brightness, color distortion, or fail the reliability test during the reliability test of the display module.

604 620 602 Therefore, when the driving parameters in each driving parameter set of the display circuitrespectively correspond to the types of each display screen, the driving circuitcan apply different driving parameter sets for different screen types, thereby ensuring that the displaycan provide a stable and high-quality display effect under different screen types.

604 602 610 604 When the display circuitcontrols the displayto output a display screen, the computing modulecan obtain the characteristic signal of the display screen through the display circuit, and analyze this characteristic signal to determine the type of the display screen.

33 FIG. 33 FIG. 610 600 622 624 Please refer to.is a flowchart of detecting the type of a display screen according to some embodiments of the present disclosure. In some embodiments, when the computing moduledetects the type of the display screen, it detects the picture characteristics of the display screen output by the display module(step S), and analyzes the type of the display screen based on the picture characteristics (step S).

604 602 604 610 602 610 604 602 In some embodiments, the screen feature is the touch feature value. When the display circuitcontrols the displayto output a special screen of the second type (for example, the aforementioned heavy-load screen or test screen), the display circuitmay generate a strong electromagnetic field, resulting in changes in the touch feature value, such as noise, capacitance value changes, and changes in the noise signal ratio. By monitoring the changes in the touch feature value through the computing module, it can be inferred whether the display screen currently output by the displaybelongs to a special screen. In addition, in some other embodiments, the screen feature is screen data, including brightness information, contrast, color composition information, dynamic features, etc. After the computing moduleobtains the screen data, it makes a type judgment, and then determines the type of the display screen that the display circuitcontrols the displayto display. Among them, the brightness information includes the distribution of high-brightness or low-brightness areas in the display screen, the contrast includes whether there is a high-contrast scene, the color composition information includes whether the color composition in the display screen contains a large number of monochromatic areas or high-saturation areas, and the dynamic features include the speed of the display screen change, such as whether there are fast-moving objects or frequently changing images.

610 620 620 604 Once the computing modulecalculates the type of the display screen, it will generate a type signal and transmit it to the driving circuit. Then, the driving circuitselects the corresponding driving parameter group from multiple driving parameter groups according to the type signal, so as to optimize the display screen output by the display circuitaccording to the selected driving parameter group, so as to reduce interference and improve the image quality.

610 604 620 620 620 620 604 In some embodiments, the computing modulecontinuously receives the screen features generated by the display circuit, and transmits the type signal to the driving circuitafter judging the type of the display screen. When the type signal received by the driving circuitchanges, for example, the type signal received by the driving circuitchanges from the signal of the first type to the signal of the second type, the driving circuitwill immediately change from selecting the first parameter group to selecting the second parameter group, and optimize the display screen output by the display circuitwith the second parameter group instead.

34 FIG. 34 FIG. 621 622 623 602 604 620 621 622 623 621 622 623 602 602 604 As mentioned above, the driving parameters in different driving parameter sets are different. Please refer to.is a schematic diagram of the waveform of the gate voltage signal according to some embodiments of the present disclosure. For example, the gate voltage and charging time between each driving parameter set may vary. The gate voltages,, andrespectively control the pixels in different rows on the display, so that the display circuitsequentially receives the image signals from the input source. When the driving circuitchanges from selecting the first parameter set to selecting the second parameter set according to the type of the display screen, the charging time of the gate voltages,, andcan be changed, that is, the time when the signal changes of each gate voltage,, andoccur is changed. Thus, when different types of display screens are displayed on the display, the capacitive coupling effect generated during the operation of the displaycan be reduced, the unnecessary voltage changes or interferences in the display circuitcan be reduced, and the occurrence of uneven brightness, flickering or other display abnormalities of the display screen can be avoided.

610 620 620 602 In some embodiments, the touch time and display time between each driving parameter set may vary. For example, in the embodiment where the first type is a normal display screen and the second type is a special screen, if the display screen switches from the normal display screen to the special screen, at this time, the computing moduleobtains the type of the display screen by detecting the screen features and outputs the type signal to the driving circuit. After receiving the type signal, the driving circuitchanges from selecting the first parameter set to selecting the second parameter set, so that the touch time of the displayis shortened and the display time is lengthened, thereby providing a better display effect for the user.

620 620 602 620 When the display screen switches back from the special screen to the normal display screen, the type signal received by the driving circuitwill change from the second type to the first type. Immediately afterwards, the driving circuitchanges back from selecting the second parameter set to selecting the first parameter set, so that the touch time of the displayis lengthened and the display time is shortened compared with when the driving circuitselects the second parameter set.

In some embodiments, the pixel inversion methods between each driving parameter set are different. For example, when the type of the display screen is the first type, such as a normal display screen, the pixel inversion method of the first parameter set corresponding to the first type is column inversion (Column Inversion). When the type of the display screen is the second type, such as a heavy-loaded special screen, the pixel inversion method of the second parameter set corresponding to the second type is two-line inversion (2 Line Inversion).

620 610 In some embodiments, when the pixel inversion method changes based on the driving parameter set selected by the driving circuit, for example, when changing from column inversion to two-line inversion, the flickering and texture in the horizontal direction of the display screen can be reduced. However, in some cases, pixel inversion may cause the overall brightness of the display screen to decrease. At this time, the computing modulecan obtain the screen features and perform calculations, and generate a compensation signal to adjust the voltage or other parameters in the driving parameter set corresponding to the current screen type, thereby compensating for the brightness of the display screen.

In some embodiments, the screen inversion modes in the driving parameter group can also correspond to different types of display screens, such as 2 Dot Inversion, 1+2 Dot Inversion, 4 Dot Inversion, 4 Line Inversion, etc., which are not limited here.

35 FIG. 35 FIG. 35 FIG. 604 Please refer to.is a schematic waveform diagram of the charging speed according to some embodiments of the present disclosure. In some embodiments, the charging speeds between each driving parameter group are different. For example, when the type of the display screen is the first type, such as a normal display screen, the charging speed of the driving display circuitin the first parameter group corresponding to the first type is relatively fast. When the type of the display screen is the second type, such as a heavy-load screen of a special screen, the charging speed in the second parameter group corresponding to the second type is relatively slow. The voltage waveform of the gate voltage is shown in. It can be seen that under the same charging time (marked by the dotted frame), the charging speed in the driving parameter group can be adjusted and then applied to different types of display screens to achieve the effect of optimizing the display screen.

600 In some embodiments, the adjustable parameters in the driving parameter group can be any combination of the above-listed items, and can also include any other unlisted parameters that can adjust the effect of the screen displayed by the display module.

31 FIG. 620 620 620 610 620 Please refer toagain. In some embodiments, the driving parameter sets in the driving circuitcan be adjusted and added at any time. The driving parameter sets can be multiple sets of parameters pre-adjusted for various types of display screens, and are stored in the driving circuitwhen the driving circuitis set. When the computing moduledetects the type of the display screen, the driving circuitcan switch among the multiple sets of driving parameters by itself.

630 630 620 620 In other embodiments, multiple sets of driving parameter sets can be stored in the external memory. After the external memoryis connected to the driving circuit, the driving parameter sets are stored in the driving circuit.

In some embodiments, although the above examples take the ordinary display screen as the first type of display screen and the special screen as the second type, it is not limited to this.

1 FIG. 2 FIG. 1 10 11 12 13 10 10 10 10 Referring back toand, in some embodiments, the liquid crystal display device (LCD device)includes a backlight module, a quantum dot repairing film, a quantum dot layer, and a panel module. In some embodiments, when the backlight moduleis in use, when the screen displayed by the display device contains graphics or text with edges, the light-emitting diode (LED) panel included in the backlight modulemay cause additional LEDs to emit light, resulting in a halo (corresponding to the additionally-emitting LEDs) on the screen displayed by the display device, which further affects the quality of the display device. In view of this, the following embodiments further describe various LED arrays and LED panels. In some embodiments, the LED arrays and LED panels in the following embodiments can be used to implement or be applied to the backlight module. However, the present disclosure is not limited to this. Under different design considerations or application scenarios, other structures, processes, or manufacturing processes can be adopted to implement the backlight moduledisclosed in the present disclosure.

36 FIG. 37 FIG. 36 FIG. 37 FIG. 7 71 71 72 72 72 71 72 71 72 Please refer toand.is a circuit schematic diagram of an LED array according to an embodiment of the present disclosure, andis a circuit schematic diagram of an LED array according to another embodiment of the present disclosure. An LED arrayincludes an LED D(hereinafter referred to as the first LED D) and a plurality of other LEDs D(hereinafter referred to as the second LEDs D), and the plurality of second LEDs Dare connected in parallel to the first LED D. In other words, in some embodiments, the output terminals of each second LED Dare coupled to the input terminal of the first LED Dand the output terminals of the remaining second LEDs D.

71 72 71 72 7 72 71 72 71 72 7 In some embodiments, in response to the first LED Dbeing grounded and one of the second LEDs Dreceiving a modulation signal Msg, the first LED Dand the second LED Dthat receives the modulation signal Msg emit light. Here, at any time point during the operation of the LED array, one of the plurality of second LEDs Dand the first LED Dwill emit light simultaneously. In other words, in some embodiments, the plurality of second LEDs Dwill not receive the modulation signal Msg simultaneously, and the first LED Dwill only receive one modulation signal Msg from one of the second LEDs Dat any time point during the operation of the LED array.

36 FIG. 37 FIG. 7 71 72 71 71 72 72 7 71 72 71 71 72 72 As shown in, in some embodiments, the LED arrayfurther includes a control elementand a modulation signal generation element. The control elementis electrically connected to the first LED D, and the modulation signal generation elementis electrically connected to the plurality of second LEDs D. As shown in, in other embodiments, the LED arrayfurther includes a control elementand a plurality of modulation signal generation elements. The control elementis electrically connected to the first LED D, and each modulation signal generation elementis electrically connected to each second LED D.

71 71 71 71 72 71 71 71 72 71 71 In some embodiments, the control elementis used to control the first LED Dto be open-circuited or grounded. In response to the first LED Dbeing open-circuited, even if the first LED Dreceives the modulation signal Msg from the second LED D, no potential difference is generated between the input terminal and the output terminal of the first LED D, so that the first LED Dcannot emit light. In response to the first LED Dbeing grounded and receiving the modulation signal Msg from the second LED D, a potential difference is generated between the input terminal and the output terminal of the first LED D, so that the first LED Demits light.

72 72 72 72 72 72 36 FIG. 37 FIG. In some embodiments, the modulation signal generation elementis used to generate the modulation signal Msg to be provided to each second LED D. Takingas an example, in this embodiment, the modulation signal Msg received by each second LED Dis generated through the same modulation signal generation element. Takingas an example again, in this embodiment, the modulation signal Msg received by each second LED Dis generated through its corresponding modulation signal generation element.

38 FIG. 38 FIG. 7 70 71 72 70 72 721 722 723 724 721 722 723 724 71 Please refer to.is a top view schematic diagram of a light emitting diode (LED) array according to an embodiment of the present disclosure. In some embodiments, the LED arrayfurther includes a circuit board, and the first LED Dand a plurality of second LEDs Dare disposed on the circuit board. In some embodiments, the plurality of second LEDs Dare four second LEDs D, D, D, and D, and the four second LEDs D, D, D, and Dare respectively adjacent to a first side, a second side, a third side, and a fourth side of the first LED D.

71 71 71 71 71 721 71 722 71 723 71 724 71 38 FIG. In some embodiments, the directions from the first side to the fourth side of the first LED Dcorrespond to the directions in the Cartesian coordinate system. Takingas an example, in this embodiment, the direction of the first side of the first LED Dcorresponds to the positive X direction in the Cartesian coordinate system, the direction of the second side of the first LED Dcorresponds to the positive Y direction in the Cartesian coordinate system, the direction of the third side of the first LED Dcorresponds to the negative X direction in the Cartesian coordinate system, and the direction of the fourth side of the first LED Dcorresponds to the negative Y direction in the Cartesian coordinate system. Here, the second LED Dis adjacent to the first side of the first LED D, the second LED Dis adjacent to the second side of the first LED D, the second LED Dis adjacent to the third side of the first LED D, and the second LED Dis adjacent to the fourth side of the first LED D.

39 FIG. 40 FIG. 39 FIG. 38 FIG. 40 FIG. 38 FIG. 39 FIG. 40 FIG. 39 FIG. 40 FIG. 7 721 722 723 724 7 721 722 723 724 71 721 721 71 721 Please further refer toand.is a circuit schematic diagram of the LED array inaccording to the present disclosure, andis a top view schematic diagram of an embodiment of the LED array inaccording to the present disclosure. The following will takeandas examples to illustrate the operation mode of the LED array. As shown in, assuming that each of the second LEDs D/D/D/Din the LED arrayhas a corresponding modulation signal generation element///, in response to the first LED Dbeing grounded and the second LED Dreceiving the modulation signal Msg from the modulation signal generation element, the first LED Dand the second LED Demit light simultaneously (as shown in).

71 722 722 71 722 71 723 723 71 723 71 724 724 71 724 Similarly, in response to the first LED Dbeing grounded and the second LED Dreceiving the modulation signal (Msg) from the modulation signal generation element, the first LED Dand the second LED Demit light simultaneously (not shown in the figure). In response to the first LED Dbeing grounded and the second LED Dreceiving the modulation signal (Msg) from the modulation signal generation element, the first LED Dand the second LED Demit light simultaneously (not shown in the figure). In response to the first LED Dbeing grounded and the second LED Dreceiving the modulation signal (Msg) from the modulation signal generation element, the first LED Dand the second LED Demit light simultaneously (not shown in the figure).

41 FIG. 42 FIG. 41 FIG. 42 FIG. 41 FIG. 42 FIG. 7 7 72 7 7 7 7 7 7 72 Please refer toand.is a schematic circuit diagram of an LED panel according to an embodiment of the present disclosure, andis a schematic circuit diagram of an LED panel according to another embodiment of the present disclosure. In some embodiments, the LED panelP includes a plurality of LED arraysof any of the foregoing embodiments, and at least one of the plurality of second LEDs Dis shared by two adjacent LED arrays. Takingandas an example, in this embodiment, the LED panelP includes two LED arraysand′, and the LED arraysand′ share two second LEDs D.

72 7 7 72 7 7 7 7 72 7 72 72 7 72 72 7 7 72 72 41 FIG. 36 FIG. In some embodiments, the modulation signal (Msg) received by each second LED Dof each LED arrayin the LED panelP is generated through the same modulation signal generation element. Takingas an example, in this embodiment, each LED array/′ in the LED panelP corresponds to the LED arrayshown in. Here, the modulation signal (Msg) received by each second LED Din the LED arrayis generated through the modulation signal generation element, and the modulation signal (Msg) received by each second LED Din the LED array′ is generated through the modulation signal generation element′. In other words, in some embodiments, the modulation signal (Msg) received by the two second LEDs Dshared by the LED arraysand′ can come from one of the modulation signal generation elementsand′.

72 72 7 7 7 7 72 72 7 7 72 72 42 FIG. 37 FIG. In other embodiments, the modulation signals Msg received by each second LED Dare generated through their respective corresponding modulation signal generation elements. Takingas an example, in this embodiment, each LED array/′ in the LED panelP corresponds to the LED arrayshown in. Here, the modulation signals Msg received by each second LED Dare generated through their respective corresponding modulation signal generation elements. In other words, in some embodiments, the LED arraysand′ not only share two second LEDs D, but also share the corresponding two modulation signal generation elements.

43 FIG. 43 FIG. 43 FIG. 7 70 71 72 7 70 7 7 7 71 71 71 71 72 7 721 722 723 724 Please refer to.is a top view schematic diagram of an LED panel according to an embodiment of the present disclosure. In some embodiments, the LED panelP further includes a circuit board, and the first LED Dand a plurality of second LEDs Din each LED arrayare disposed on the circuit board. Takingas an example, in this embodiment, the LED panelP includes four LED arrays. Each LED arrayincludes a first LED DA/DB/DC/DD, and the plurality of second LEDs Din each LED arrayare four second LEDs D, D, D, and D.

721 722 723 724 7 71 71 71 71 7 71 71 71 71 71 71 71 71 43 FIG. In some embodiments, each of the second LEDs D, D, D, and Din each LED arrayis individually adjacent to a first side, a second side, a third side, and a fourth side of the first LED DA/DB/DC/DD in each LED array. In addition, in some embodiments, the directions from the first side to the fourth side of each first LED DA/DB/DC/DD correspond to the directions in the Cartesian coordinate system. Takingas an example, in this embodiment, the direction of the first side of the first LED Dcorresponds to the positive X direction in the Cartesian coordinate system, the direction of the second side of the first LED Dcorresponds to the positive Y direction in the Cartesian coordinate system, the direction of the third side of the first LED Dcorresponds to the negative X direction in the Cartesian coordinate system, and the direction of the fourth side of the first LED Dcorresponds to the negative Y direction in the Cartesian coordinate system.

7 71 721 722 723 724 721 71 722 71 723 71 724 71 43 FIG. Taking the LED arraysurrounded by the dotted line inas an example, it includes a first LED DA and four second LEDs D, D, D, and D. Among them, the second LED Dis adjacent to the second side (corresponding to the positive Y direction) of the first LED DA, the second LED Dis adjacent to the first side (corresponding to the positive X direction) of the first LED DA, the second LED Dis adjacent to the fourth side (corresponding to the negative Y direction) of the first LED DA, and the second LED Dis adjacent to the third side (corresponding to the negative X direction) of the first LED DA.

72 7 7 72 7 7 7 71 7 71 721 7 722 43 FIG. 43 FIG. In some embodiments, since at least one of the plurality of second LEDs Dis shared by two adjacent LED arraysin the LED panelP, each second LED Din the LED arraycan be shared by more than two LED arraysat the same time. Takingas an example, in this embodiment, the LED arrayincluding the first LED DA and the LED arrayincluding the first LED DD share the second LED D. In addition, all the LED arraysshown inshare the second LED D.

44 FIG. 44 FIG. 7 7 72 7 71 7 71 722 7 71 7 71 722 Please further refer to, which is a top view schematic diagram of an LED panel according to another embodiment of the present disclosure. In some embodiments, two adjacent LED arraysin the LED panelP share only one second LED D. Takingas an example, in this embodiment, the LED arrayincluding the first LED DA and the LED arrayincluding the first LED DB share only one second LED D, and the LED arrayincluding the first LED DC and the LED arrayincluding the first LED DD also share only one second LED D.

43 45 FIGS.and 45 FIG. 43 FIG. 45 FIG. 45 FIG. 7 7 7 71 71 71 71 721 722 723 724 7 7 71 7 71 721 722 70 71 722 721 71 7 70 71 71 71 721 722 7 Please refer to.is a top-view schematic diagram of an embodiment of the LED panel inaccording to the present disclosure. The following will takeas an example to illustrate the operation mode of the LED panelP. In some embodiments, when the LED panelP is operating, the LED panelP can control the first LEDs DA/DB/DC/DD and one of the second LEDs D/D/D/Din each LED arrayto emit light. For example, assume that the LED panelP is applied to a display device, and when the range of the display device corresponding to the dashed bounding box Rinis to display an image, the LED panelP can first control the first LED DA and the second LEDs D/Dto emit light simultaneously (step S), and then control the first LED DD and the second LEDs D/Dto emit light simultaneously (step S). In response to the LED panelP repeatedly performing step Sand step Swithin a cycle (corresponding to the refresh frequency when the display device displays an image), the first LEDs DA, DD and the second LEDs D, Dshared by them visually emit light simultaneously. Here, the LED panelP can control the minimum number (in this embodiment, the minimum number is 4) of light emitting diodes to emit light to display the image in the display device, thereby avoiding the problem of halos on the image displayed by the display device.

71 72 In some embodiments, the first LED Dand the second LED Dcan be monochromatic light emitting diodes, multicolor light emitting diodes, organic light emitting diodes (Organic LED, OLED), quantum-dot light emitting diodes (Quantum-dot LED, QLED), mini light emitting diodes (Mini LED), or micro light emitting diodes (Micro LED), but are not limited thereto.

71 In some embodiments, the control elementcan be a hardware element with a control function or a semiconductor element used as a switch, such as but not limited to a central processing unit (CPU), a system-on-chip (SoC), a microprocessor, a digital signal processor (DSP), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a microcontroller unit (MCU), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), and a metal-oxide-semiconductor field-effect transistor (MOSFET).

72 72 In some embodiments, the modulation signal Msg can be a digital signal or an analog signal. Additionally, in some embodiments, the modulation signal Msg can be a pulse width modulation (PWM) signal. Here, the modulation signal generation elementis a pulse width modulation signal generator. In other embodiments, the modulation signal Msg can be a pulse amplitude modulation (PAM) signal. Here, the modulation signal generation elementis a pulse amplitude modulation signal generator.

70 In some embodiments, the circuit boardcan be a single-layer printed circuit board (PCB), a double-layer PCB, or a multi-layer PCB, but is not limited thereto.

In summary, the liquid crystal display device proposed according to some embodiments of the present disclosure includes a quantum dot repairing film. When the quantum dot material at the edge of the quantum dot layer in the liquid crystal display device fails due to the influence of moisture in the air, the quantum dot material in the quantum dot repairing film can replace the failed quantum dot material to produce light with normal color. Additionally, since the quantum dot repairing film has ductility, even if there are gaps when the quantum dot layer is disposed on the backlight module and covers the quantum dot repairing film, the quantum dot repairing film can fill these gaps to prevent moisture in the air from entering the quantum dot layer.

Additionally, the light emitting diode circuit and its circuit board structure proposed according to some embodiments of the present disclosure can use a resistor as a jumper for any section of each conductive trace on the circuit board to avoid short-circuits caused by the intersection of conductive traces, thereby simplifying the complexity of the circuit design. Moreover, even if two sections of the same conductive trace intersect and cause a short-circuit, the light emitting diode circuit and its circuit board structure can also use a resistor as a jumper for either of these two sections. Furthermore, the resistor can also be used to adjust the resistance value of the circuit formed by each conductive trace to ensure that the light-emitting effects of each light-emitting unit on the light emitting diode circuit are consistent and uniform.

31 32 33 34 18 FIG. Additionally, in the light emitting diode backlight panel proposed according to some embodiments of the present disclosure, in the same scanning sequence, the light emission points in the same arrangement order of adjacent drive lines (such as the first light emission point P, the second light emission point P, the third light emission point P, and the fourth light emission point Pin the first row in) will not receive the scan signal simultaneously to suppress the resonance noise generated by the power supply circuit.

In addition, according to some embodiments of the present disclosure, the TFT-LCD panel unit and a manufacturing method thereof set metal posts between the thin-film transistor substrate and the color filter substrate in the TFT-LCD panel unit, so that the thin-film transistor substrate is electrically connected to the color filter substrate. In addition, the TFT-LCD panel unit and a manufacturing method thereof can form the metal posts after forming the gate layer/source layer/drain layer in the thin-film transistor substrate without changing the instruments and materials of the process, so as to save the time and cost of changing instruments and materials in the process of the TFT-LCD panel.

524 520 51 510 51 540 516 512 In addition, according to some embodiments of the present disclosure, the panel cutting method can cut the second excess materialof the second substrateto generate stress applied to the first cutting line Lof the first substrate, so that the first cutting line Lbreaks naturally, and avoid the generation of feather cracksin the terminal area, thereby improving the quality and reliability of the first sub-substrate.

600 In addition, according to some embodiments of the present disclosure, the image processing method enables the image processing panel to optimize the picture with the corresponding driving parameter set when the display moduledisplays different kinds of pictures, and then provides users with a good visual effect when displaying special pictures (such as heavy-load pictures or special test pictures).

In addition, when the LED array and the LED panel proposed according to some embodiments of the present disclosure are applied to a display device, the LED array and the LED panel can reduce the number of light emitting diodes (including the first light emitting diode and the second light emitting diode) required for the display device to display pictures, so as to avoid the problem of halos on the pictures displayed by the display device. In addition, even if the picture displayed by the display device includes a picture with graphics or text having edges, the LED panel can control one of the plurality of second light emitting diodes in each LED array that is most suitable for displaying this graphic or text to emit light, thereby reducing the halos generated when the display device displays this graphic or text.

Although the present disclosure has been clearly disclosed according to the above different embodiments, each embodiment is not intended to limit the present disclosure. Any person with ordinary knowledge in the technical field can make various modifications, substitutions or omissions to the above embodiments without departing from the spirit and scope of the present disclosure, which still belong to the technical scope protected by the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the scope defined by the patent application.

TABLE 1 The depth of feather The depth of feather cracks in the cracks in the Number of terminal area ≤50 μm terminal area >50 μm first sub- Number Number substrates of pieces Proportion of pieces Proportion 2712 619 22.82% 76 2.79%

TABLE 2 The depth of feather The depth of feather cracks in the cracks in the Number of terminal area ≤50 μm terminal area >50 μm first sub- Number Number substrates of pieces Proportion of pieces Proportion 1000 23 (Maximum 2.3% 0 0% crack 12 μm)