Apparatuses, Systems and Methods for Controlling Variable Gain Amplifiers

This application claims the filing benefit of U.S. Provisional Application No. 63/677,839, filed Jul. 31, 2024. This application is incorporated by reference herein in its entirety and for all purposes.

A semiconductor memory device may include a number of memory cells which are used to store data represented by binary digits (or “bits”). The memory cells are typically arranged in an array and are accessed based on row addresses and column addresses. When write operations are performed, data is written to memory cells based on write commands supplied with row and column addresses that are used to select the memory cells. Prior to writing the data to the memory cells, the data signals are amplified by one or more variable gain amplifiers (VGAs). Typically, a VGA consumes a large amount of power, which is undesirable. Additionally, as the number of memory devices that are included in a system continues to increase, the total system power has to increase to compensate for the large amounts of power consumed by the increasing number of VGAs.

Semiconductor memory devices typically include one or more variable gain amplifiers (VGAs) to amplify data signals prior to the data being written into a memory array. In some instances, all of the sink transistors in a VGA are enabled (e.g., turned on) at the same time and for the same time period, which can result in a higher amount of power consumption by each VGA, a greater settling time for the VGA, and/or greater power fluctuations in the memory device.

Embodiments described herein provide techniques for controlling one or more VGAs. One or more control signals are provided to a sink circuit in a VGA to selectively enable sink transistors in the sink circuit. The sink circuit can be used to set one or more settings of the VGA, such as the gain and/or the bandwidth of the VGA. For example, when more sink transistors and/or stronger sink transistors are enabled, the VGA can have a relatively higher gain. Conversely, when fewer sink transistors and/or weaker sink transistors are enabled, the VGA may have a relatively lower gain.

The control signals can be staggered in time to reduce the power consumption of the VGA. As such, the control signal received at one sink transistor can be enabled (e.g., an assertion transition time) at a first time and the control signal received at another sink transistor may be enabled at a later second time. In one embodiment, the weaker sink transistors are enabled first and the stronger sink transistors later. Enabling the weaker sink transistors first can assist in satisfying a settling time of the VGA. Additionally or alternatively, enabling the weaker sink transistors first and the stronger sink transistors later may reduce or minimize the amount of time the stronger sink transistors are enabled, which can further reduce the power consumption of the VGA.

The control signals can be disabled (e.g., a deassertion transition time) at the same time in one embodiment. In another embodiment, the control signal received at one sink transistor may be disabled before the control signal received at another sink transistor is disabled. The staggered disabling of the control signals may reduce power fluctuations. In some aspects, enable signals that are provided to the VGA may be delayed to further reduce the power consumption of the VGA.

1 FIG. 100 100 illustrates a block diagram of a semiconductor deviceaccording to an embodiment of the disclosure. The semiconductor devicemay include, without limitation, a dynamic random-access memory (DRAM), a double data rate (DDR) memory, a low power double data rate (LPDDR) memory, or other type of memory. In some instances, the memory is included in a memory module, such as a single in-line memory module, a dual in-line memory module, a quad in-line memory module, or another type of memory module.

100 150 150 150 140 145 140 145 155 155 1 FIG. The semiconductor deviceincludes a memory array. The memory arrayis shown as including a plurality of memory banks. In the embodiment of, the memory arrayis shown as including memory banks BANKO-BANKm. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL and/BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL and/BL. Selection of the word line WL is performed by a row decoderand selection of the bit lines BL and/BL is performed by a column decoder. In the illustrated embodiment, the row decoderincludes a respective row decoder for each memory bank and the column decoderincludes a respective column decoder for each memory bank. The bit lines BL and/BL are coupled to a respective sense amplifier (SAMP). Read data from the bit line BL or/BL is amplified by the sense amplifier SAMP and transferred to read/write amplifiersover complementary local data lines (LIOT/B), transfer gate (TG), and complementary main data lines (MIOT/B). Conversely, write data output from the read/write amplifiersis transferred to the sense amplifier SAMP over the complementary main data lines MIOT/B, the transfer gate TG, and the complementary local data lines LIOT/B, and written in the memory cell MC coupled to the bit line BL or/BL.

130 100 130 100 100 100 130 A mode registerstores information, for example, configuration and status information for the semiconductor device. The mode registermay be accessed through mode register read commands and mode register write commands. The mode register access commands cause the semiconductor deviceto perform mode register read operations and mode register write operations. A mode register read command causes the semiconductor deviceto provide information stored by the mode register that is accessed, and a mode register write command causes the semiconductor deviceto store information in the mode register that is accessed. The mode registermay include several mode registers, with each of the mode registers corresponding to a mode register address and storing different types of information.

100 The semiconductor devicemay employ a plurality of external terminals that include command and address terminals (CAO-CAn) to receive commands and addresses, an external reset_n signal and an external control CS_n signal. The external terminals may further include clock terminals to receive clocks CK_t and CK_c, and data clocks DQS_t and DQS_c, data terminals DQ, and power supply terminals to receive power supply potentials VDD, VSS, and VDDQ.

120 120 115 105 122 122 The clock terminals are supplied with external clocks CK_t and CK_c that are provided to a CLK input buffer. The external clocks may be complementary (e.g., 180 degrees out of phase). The CLK input buffergenerates an internal clock ICLK based on the CK_t and CK_c clocks. The ICLK clock is provided to a command decoder, a command/address input circuit, and to an internal clock generator. The internal clock generatorprovides various internal clocks LCLK based on the ICLK clock. The LCLK clocks may be used for timing operation of various internal circuits.

170 170 140 150 The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to an internal voltage generator circuit. The internal voltage generator circuitgenerates various internal potentials VCCP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VCCP is mainly used in the row decoder, the internal potentials VOD and VARY are mainly used in the sense amplifiers SAMP included in the memory array, and the internal potential VPERI is used in many peripheral circuit blocks.

160 160 160 The power supply terminals are also supplied with power supply potentials VDDQ and VSS. The power supply potentials VDDQ and VSS are supplied to the input/output circuit. The power supply potentials VDDQ and VSS supplied to the power supply terminals may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminals in an embodiment of the disclosure. The power supply potentials VDDQ and VSS supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals in another embodiment of the disclosure. The power supply potentials VDDQ and VSS supplied to the power supply terminals are used for the input/output circuitso that power supply noise generated by the input/output circuitdoes not propagate to the other circuit blocks.

112 105 112 140 145 The CA terminals (e.g., CAO-CAn) may be supplied with commands and memory addresses from, for example, a memory controller. The memory addresses supplied to the CA terminals are transferred to an address decodervia the command/address input circuit. The address decoderreceives the address and supplies a decoded row address XADD to the row decoderand supplies a decoded column address YADD to the column decoder.

115 105 The commands received at the CA terminals may be provided as internal command signals to the command decodervia the command/address input circuit. Example commands that may be received at the CA terminals include access commands for accessing the memory (such as read commands for performing read operations and write commands for performing write operations), mode register write and read commands for performing mode register write and read operations, power down commands, as well as other commands and operations.

115 115 The command decoderincludes circuits to decode the command signals to generate various internal command signals for performing operations. For example, the command decodermay generate a row command signal ACT to select a word line, a column command signal R/W to select a bit line, a read command signal RDCMD based on a read command, and a write command signal WRCMD based on a write command.

125 125 160 150 The various internal command signals, such as the WRCMD signal, are provided to a command path. The command pathmay include some or all of a write command path that receives the WRCMD signals and provides write enable signals WrEnIB<n>. The WrEnIB<n> signals are provided to the input/output circuitto perform operations related to the write commands, such as providing amplified write data to the memory array.

150 115 150 155 160 160 Read data is read from a memory cell in the memory arraycorresponding to a row address and a column address when an activate command and read command are received, and the row address and the column address are timely supplied with the activate command and/or the read command. The read command is received by the command decoder, which provides internal commands so that read data from the memory arrayis provided to the read/write amplifiers. The read data is output to outside from the data terminals DQ via the input/output circuit. The DQS_t and DQS_c clocks are provided externally from clock terminals for timing the provision of the read data by the input/output circuit. The external terminals DQ include several separate terminals, each providing a bit of data synchronized with a clock edge of the DQS_t and DQS_c clocks.

150 150 115 160 160 160 155 155 150 Write data supplied to the data terminals DQ is written to a memory cell in the memory arraycorresponding to a row address and a column address when an activate and write command are received, and the row address and the column address are timely supplied with the activate command and/or the write command. A data mask may be provided to the data terminals DM to mask portions of the data when written to the memory array. The write command is received by the command decoder, which provides internal commands so that the write data is received by input receivers in the input/output circuit. DQS_t and DQS_c clocks are also provided to the external clock terminals (e.g., by a controller) for timing the receipt of the write data by the input receivers of the input/output circuit. The write data is supplied via the input/output circuitto the read/write amplifiers, and by the read/write amplifiersto the memory arrayto be written into the memory cell MC. As previously described, the external terminals DQ include several separate terminals. With reference to a write operation, each external terminal DQ concurrently receives a bit of data synchronized with a clock edge of the DQS_t and DQS_c clocks.

130 100 160 130 130 160 150 When a mode register read command is received, and a mode register address is timely supplied with the mode register read command, read information is read from the mode registercorresponding to the mode register address. The read information may be used to configure the semiconductor device, or the read information can be output to outside from the data terminals DQ via the input/output circuit. When a mode register write command is received, and a mode register address is timely supplied with the mode register write command, write information supplied to the data terminals DQ is written to the mode registercorresponding to the mode register address. In some instances, the mode registerstores gain information MrGain<0: m> that is provided to one or more variable gain amplifiers in the input/output circuitduring a write operation to the memory array. The gain information MrGain<0: m> can be set by an external device, such as a controller.

2 FIG. 1 FIG. 200 202 204 206 208 210 212 214 204 206 216 208 210 212 214 218 202 115 216 125 218 160 illustrates an example process flow diagram for a write command according to an embodiment of the disclosure. The process flowincludes a command decoder, a shifter and pulse generator circuit, a delay control circuit, a VGA control circuit, a VGAthat includes a sink circuit, and a latch. In some embodiments of the disclosure, the shifter and pulse generator circuitand the delay control circuitcan be implemented within a command path, and the VGA control circuit, the VGAwith the sink circuit, and the latchmay be implemented within an input/output circuit. In one embodiment, the command decodermay be implemented as the command decoder, the command pathas the command path, and the input/output circuitas the input/output circuitshown in.

202 220 202 204 222 204 204 3 FIG. 4 FIG. A write command WRITE is received at the command decoderon signal line. The command decoderresponsively provides the WRCMD signal to the shifter and pulse generator circuiton signal line. The shifter and pulse generator circuitis configured to extend a pulse width of the WRCMD signal by a particular number of clock cycles. An example shifter and pulse generator circuitis shown and described in more detail in conjunction withand.

204 206 224 204 206 212 210 206 5 FIG. 11 FIG. The shifter and pulse generator circuitprovides a pre-write enable signal WrEnIBdetPre to the delay control circuiton signal line. The WrEnIBdetPre signal has the extended pulse width produced by the shifter and pulse generator circuit. The delay control circuitis configured to output multiple write enable signals WrEnIB on a bus WrEnIB<0: n>. As will be described in more detail later, the WrEnIB signals are used to selectively enable sink transistors in the sink circuit. Each WrEnIB signal may have a staggered enable time that produces a pulse having a different pulse width compared to the other WrEnIB signals, which can reduce the power consumption of the VGA. An example delay control circuitis shown and described in more detail in conjunction withand with.

208 208 208 212 212 212 The WrEnIB signals on the WrEnIB<0: n> bus are received by the VGA control circuit. The VGA control circuitalso receives gain information MrGain<0: m>. Based on the WrEnIB signals and the gain information MrGain<0:2>, the VGA control circuitis configured to selectively generate control signals GNR (x) to selectively enable (e.g., turn on) sink transistors in the sink circuit. In one embodiment, the GNR (x) signals that are provided to the sink circuithave staggered enable times (which produces staggered pulses) that define an amount of time a particular sink transistor or sink transistors in the sink circuitare enabled.

212 226 228 226 228 230 230 230 230 230 230 228 228 228 226 226 170 226 2 FIG. 1 FIG. In the illustrated embodiment, the sink circuitincludes multiple sink transistors,. A sink transistoris connected in series with a sink transistorto produce a sink transistor pair. In the embodiment illustrated in, there are sink transistor pairsA,B,C,D,E,F, although other embodiments are not limited to sink transistor pairs and/or the number of sink transistor pairs. The sink transistorin each sink transistor pair receives a respective GNR (x) signal at the gate of the sink transistor. The sink transistorfunctions as a switch to enable or disable the sink transistor pair. The sink transistorreceives a reference signal NBiasRefBuf at the gate of the sink transistor. The NBiasRefBuf signal may be provided by a voltage generator (e.g., the voltage generatorof). When enabled, the sink transistorcontrols the current level through the sink transistor pair.

230 230 230 230 230 230 210 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 226 228 230 230 226 228 230 208 230 230 208 230 230 230 230 230 208 230 230 230 230 230 230 230 230 2 FIG. The sink transistor pairsA,B,C,D,E,F are connected in parallel between the VGAand a reference voltage (e.g., ground or VSS). In some instances, one or more of the sink transistor pairsA,B,C,D,E,F have a different drive strength. In some embodiments, each of the sink transistor pairsA,B,C,D,E,F have a different strength. For example, the sink transistor pairsA,B,C,D,E,F increase in strength as the sink transistor pairs move from right to left (e.g., the x direction in). Thus, the sink transistor pairA can be weakest sink transistor pair (e.g., the sink transistors,in the sink transistor pairA have the smallest size) and the sink transistor pairF the strongest sink transistor pair (e.g., the sink transistors,in the sink transistor pairF have the largest size). As will be described in more detail later, the VGA control circuitmay be configured to enable (e.g., turn on) one or more of the weakest sink transistor pairs first (e.g., sink transistor pairA) and the strongest sink transistor pair last (e.g., sink transistor pairF). In one embodiment, the VGA control circuitcan be configured to disable (e.g., turn off) all of the sink transistor pairsA,B,C,D,F at the same time. In another embodiment, the VGA control circuitmay be configured to disable the sink transistor pairsA,B,C,D,F at different times, beginning with the strongest sink transistor pairF and ending with the weakest sink transistor pairA. The sink circuitcan be implemented differently and/or include a different number of sink transistor pairs in other embodiments.

210 232 214 234 214 214 236 150 155 1 FIG. The VGAreceives write data DQ on signal line, amplifies the write data DQ, and provides the amplified write data Gained_DQ to the latchon signal line. The latchis configured to latch the amplified write data Gained_DQ based on the internal write clock iDQS. The latched write data Captured_DQ is output from the latchon signal line. Thereafter, the latched write data Captured_DQ is written to a memory array via read/write amplifiers (e.g., the memory arrayand the read/write amplifiersof).

3 FIG. 2 FIG. 1 FIG. 300 300 204 300 302 304 306 130 illustrates a block diagram of an example shifter and pulse generator circuitaccording to an embodiment of the disclosure. The shifter and pulse generator circuitmay be implemented in some embodiments as the shifter and pulse generator circuitshown in. The shifter and pulse generator circuitincludes a shift registerthat receives the WRCMD signal on signal lineand a write latency signal MR_CWL on signal line. MR_CWL is a delay, in clock cycles, between the WRCMD signal (internal write command signal) and the availability of the first bit of input data to be written into a memory array. The MR_CWL can be stored in a mode register (e.g., mode registerof).

302 302 308 310 In one embodiment, the shift registerproduces multiple shifted WRCMD signals. For example, the shift registermay output the WRCMD signal, a WRCMD+two clock cycles (2CK) signal, a WRCMD+4CK signal, and so on up to CWL. The shifted WRCMD signals are received by a pulse summing circuitvia the Shifted_WRCMD [0: ˜] bus. The pulse summing circuit sums the multiple shifted WRCMD signals to produce a pre-write enable signal WrEnIBdetPre on signal line.

4 FIG. 3 FIG. 4 FIG. 400 illustrates an example waveformof the pre-write enable signal WrEnIBdetPre ofaccording to an embodiment of the disclosure. The WrEnIBdetPre signal transitions from a first signal level (e.g., low or “0”) to a second signal level (e.g., high or “1”) at time to and transitions from the second signal level to the first signal level at a time t1. In one non-limiting nonexclusive example, the time to is the timing of a clock (e.g., a write clock WCLK) plus four clock cycles plus an “x” amount of time (i.e., WCLK+4CK+x), and the time t1 is the write latency plus eight clock cycles (CWL+8CK). The value “x” is an additional amount of time that can be used to further delay the timing of t0. The value x can adjust the delay of the enable timing of the sink transistors to reduce the enable time period of the VGA, which may further reduce the power consumption of the VGA. Thus, in, the pulse width W of the WrEnIBdetPre signal is between WCLK+4CK+x and CWL+8CK. The timing and the pulse width of the WrEnIBdetPre signal can differ in other embodiments.

In one embodiment, the value of x is stored in a fuse register. In an example embodiment, if x=1, the enable timing of the WrEnIBdetPre can be WCLK+5CK. In another example embodiment, if x=4, the enable timing of the WrEnIBdetPre can be WCLK+8CK.

5 FIG. 2 FIG. 5 FIG. 500 500 230 230 230 230 230 230 230 230 230 230 230 230 230 230 500 illustrates a block diagram of a first example delay control circuitaccording to an embodiment of the disclosure. The delay control circuitincludes multiple delay circuits connected in series. The number of delay circuits that are connected in series may be based on the number of write enable signals WrEnIB<n> to be generated, where the number of WrEnIB<n> signals to be generated is based on the number of sink transistors to be enabled by a control signal. For example, with reference to, four sets of sink transistor pairsA,B,C,D,E,F may be enabled in one embodiment, where a set of sink transistor pairs includes one or two sink transistor pairs. In this example embodiment, the sink transistor pairsA,B receive one control signal (i.e., the control signals GNR2 and GNR4 are the same), and the sink transistor pairsC,D receive another control signal (i.e., the control signals GNR6 and GNR8 are the same). Thus, the one control signal GNR2/GNR4 enables two sink transistor pairsA,B at the same time, and the one control signalsGNR6/GNR8 enables two other sink transistor pairs at a different time. The control signal GNR10 is received by the sink transistor pairE, and the sink transistor pairF receives the GNR12 control signal. Thus, infour WrEnIB<0>, WrEnIB<1>, WrEnIB<2>, WrEnIB<3> signals are provided by the delay control circuitto enable the production of the four control signals GNR2/GNR4, GNR6/GNR8, GNR10, GNR12. In other embodiments, a different number of write enable signals and control signals may be generated.

500 502 504 506 508 502 1 510 512 510 1 5 FIG. The delay control circuitofincludes four delay circuits,,,connected in series. The delay circuitreceives the WrEnIBdetPre signal and provides a first delay to the WrEnIBdetPre signal to produce a WrEnIBdetPre (delay) signal. A set pulse generatoris connected to node, and the set pulse generatorreceives the WrEnIBdetPre (delay) signal.

504 1 1 2 514 516 514 2 The delay circuitreceives the WrEnIBdetPre (delay) signal and provides a second delay to the WrEnIBdetPre (delay) signal to produce a WrEnIBdetPre (delay) signal. A set pulse generatoris connected to node, and the set pulse generatorreceives the WrEnIBdetPre (delay) signal.

506 2 2 3 518 520 518 3 The delay circuitreceives the WrEnIBdetPre (delay) signal and provides a third delay to the WrEnIBdetPre (delay) signal to produce a WrEnIBdetPre (delay) signal. A set pulse generatoris connected to node, and the set pulse generatorreceives the WrEnIBdetPre (delay) signal.

508 3 3 4 522 508 4 The delay circuitreceives the WrEnIBdetPre (delay) signal and provides a fourth delay to the WrEnIBdetPre (delay) signal to produce a WrEnIBdetPre (delay) signal. A set pulse generatoris connected to the delay circuitand receives the WrEnIBdetPre (delay) signal.

524 510 230 230 212 6 FIG. 2 FIG. A latch circuitreceives the output of the set pulse generatorand outputs a first write enable signal WrEnIB<0>. As is described in more detail in conjunction with, the WrEnIB<0> signal transitions from a first signal level to a second signal level after a first delay. In one embodiment, the WrEnIB<0> signal is used to produce a control signal that enables the weakest sink transistor(s) in a sink circuit (e.g., the sink transistor pairsA,B in the sink circuitof).

526 514 230 230 212 2 FIG. A latch circuitreceives the output of the set pulse generatorand outputs a second write enable signal WrEnIB<1>. The WrEnIB<1> signal transitions from the first signal level to the second signal level after a second delay, where the second delay is longer than the first delay. In one embodiment, the WrEnIB<1> signal is used to produce a control signal that enables a relatively weaker sink transistor(s) in a sink circuit (e.g., the sink transistor pairsC,D in the sink circuitof).

528 518 230 212 2 FIG. A latch circuitreceives the output of the set pulse generatorand outputs a third write enable signal WrEnIB<2>. The WrEnIB<2> signal from the first signal level to the second signal level after a third delay, where the third delay is longer than the first delay and the second delay. In one embodiment, the WrEnIB<2> signal is used to produce a control signal that enables a relatively stronger sink transistor(s) in a sink circuit (e.g., the sink transistor pairE in the sink circuitof).

530 522 230 212 2 FIG. A latch circuitreceives the output of the set pulse generatorand outputs a fourth write enable signal WrEnIB<3>. The WrEnIB<3> signal transitions from the first signal level to the second signal level after a fourth delay, where the fourth delay is longer than the first delay, the second delay, and the third delay. In one embodiment, the WrEnIB<3> signal is used to produce a control signal that enables the strongest sink transistor(s) in a sink circuit (e.g., the sink transistor pairF in the sink circuitof).

532 524 526 528 530 5 FIG. A reset circuitis configured to receive the WrEnIBdetPre signal and provide a reset signal to the latch circuits,,,. The reset signal causes the four write enable signals WrEnIB<0>, WrEnIB<1>, WrEnIB<2>, WrEnIB<3> to transition from the second signal level to the first signal level concurrently. Thus, the four write enable signals WrEnIB<0>, WrEnIB<1>, WrEnIB<2>, WrEnIB<3> have staggered enable times (i.e., transition from the first signal level to the second signal level) and concurrent disable times (i.e., transition from the second signal level to the first signal level) in the embodiment shown in.

6 FIG. 5 FIG. 600 500 502 510 602 502 504 514 604 502 504 506 518 606 502 504 506 508 522 608 502 504 506 508 illustrates an example timing diagramfor the delay control circuitshown inaccording to an embodiment of the disclosure. At time to, the WrEnIBdetPre signal transitions from the first signal level (e.g., low or “0”) to the second signal level (e.g., high or “1”). At time t1, the signal output by the delay circuit(point A), the signal output by the set pulse generator(point AA), and the first WrEnIB<0> signal transition from the first signal level to the second signal level. The time periodincludes the first delay provided by the delay circuit. At time t2, the signal output by the delay circuit(point B), the signal output by the set pulse generator(point BB), and the second WrEnIB<1> signal transition from the first signal level to the second signal level. The time periodincludes the first delay provided by the delay circuitand the second delay provided by the delay circuit. At time t3, the signal output by the delay circuit(point C), the signal output by the set pulse generator(point CC), and the third WrEnIB<2> signal transition from the first signal level to the second signal level. The time periodincludes the first delay provided by the delay circuit, the second delay provided by the delay circuit, and the third delay provided by the delay circuit. At time t4, the signal output by the delay circuit(point D), the signal output by the set pulse generator(point DD), and the fourth WrEnIB<3> signal transition from the first signal level to the second signal level. The time periodincludes the first delay provided by the delay circuit, the second delay provided by the delay circuit, the third delay provided by the delay circuit, and the fourth delay provided by the delay circuit.

610 610 At time t5, the WrEnIBdetPre signal transitions from the second signal level to the first signal level, which causes the reset signal to transition from the first signal level to the second signal level. The reset pulse(e.g., the rising edge of the reset pulse) causes the four write enable signals WrEnIB<0>, WrEnIB<1>, WrEnIB<2>, WrEnIB<3> to transition from the second signal level to the first signal level.

6 FIG. As shown in, the four write enable signals WrEnIB<0>, WrEnIB<1>, WrEnIB<2>, WrEnIB<3> have staggered enable times (i.e., transition from the first signal level to the second signal level) and concurrent disable times (i.e., transition from the second signal level to the first signal level). The WrEnIB<3> signal has a pulse width W1, the WrEnIB<2> signal has a pulse width W2, the WrEnIB<1> signal has a pulse width W3, and the WrEnIB<0> signal has a pulse width W4. W1 is less than W2, W2 is less than W3, and W3 is less than W4 (W1<W2<W3<W4).

6 FIG. 5 FIG. 2 FIG. 2 5 6 FIGS.,, and 500 200 212 230 230 230 230 230 230 212 230 230 230 230 230 230 230 230 230 230 230 230 The timing diagram ofis an example timing diagram that is based on the first example delay control circuitshown inand the example process flowshown in. Other embodiments are not limited to the implementations shown in. For example, the sink circuitcan include a different number of sink transistors and/or sink transistor pairsA,B,C,D,E,F. Additionally or alternatively, different sets of sink transistor pairs in the sink circuitcan be enabled and disabled. For example, each sink transistor pairA,B,C,D,E,F can be enabled individually. Those skilled in the art will recognize that enabling each sink transistor pairA,B,C,D,E,F individually can involve a different number of WrEnIB<n> signals.

7 FIG. 7 FIG. 5 FIG. 7 FIG. 5 FIG. 700 502 700 510 514 518 522 700 illustrates a block diagram of an example set pulse generatorwith example waveform diagrams according to an embodiment of the disclosure.is described in conjunction with. In particular,is described in conjunction with the delay circuitand as such, the set pulse generatoris the set pulse generatorshown in. The other set pulse generators,,may also be implemented as the set pulse generatorin some embodiments.

700 702 502 704 702 The set pulse generatorincludes an AND gatethat receives the signal output by the delay circuit(point A) and a delayed signal (active low)as inputs. The output of the AND gateis the signal at point AA. The signal at point A transitions from the first signal level (e.g., low or “0”) to the second signal level (high or “1”) at time t0 and transitions from the second signal level to the first signal level at time t3. The signal at point AA transitions from the first signal level to the second signal level at time t1 and transitions from the second signal level to the first signal level at time t2.

8 FIG. 8 FIG. 5 FIG. 800 800 802 802 illustrates a block diagram of an example reset pulse generatorwith example waveform diagrams according to an embodiment of the disclosure according to an embodiment of the disclosure.is described in conjunction with. The reset pulse generatorincludes an AND gatethat receives the WrEnIBdetPre signal (active low) and a delayed WrEnIBdetPre signal as inputs. The output of the AND gateis the Reset signal. The WrEnIBdetPre signal transitions from the first signal level (e.g., low or “0”) to the second signal level (high or “1”) at time to and transitions from the second signal level to the first signal level at time t2. The Reset signal transitions from the first signal level to the second signal level at time t1 and transitions from the second signal level to the first signal level at time t2.

9 9 FIGS.A-E 2 FIG. 2 FIG. 2 FIG. 208 illustrate example operations of a VGA control circuit according to an embodiment of the disclosure according to an embodiment of the disclosure. The VGA control circuit may be implemented as the VGA control circuitshown inin some embodiments. As shown in, the VGA control circuit receives the WrEnIB<n> signals on the WrEnIB<0:3> bus and the gain information MrGain<0:2>. The VGA control circuit is configured to decode the WrEnIB signals and the gain information MrGain<0:2> to provide the GNRx signals. In the example embodiment shown in, the gain information MrGain<0:2> is comprised of three bits. Other embodiments are not limited to this implementation.

9 FIG.A 2 FIG. 0 230 230 230 230 230 230 212 illustrates an example operation of the VGA control circuit when the gain information MrGain<0:2> is zero (). The GNR2 signal and the GNR4 signal are provided as having the same timing as the WrEnIB<0> signal. The GNR6 signal and the GNR8 signal are provided as having the same timing as the WrEnIB<1> signal. The GNR10 signal is provided as having the same timing as the WrEnIB<2> signal. The GNR12 signal is provided as having the same timing as the WrEnIB<3> signal. In this example operation, the sink transistor pairsA andB, the sink transistor pairsC andD, the sink transistor pairE, and the sink transistor pairF in the sink circuitofare enabled at staggered times.

9 FIG.B 1 10 230 230 230 230 230 212 230 illustrates an example operation of the VGA control circuit when the gain information MrGain<0:2> is one () and two (). The GNR2 signal and the GNR4 signal are provided as having the same timing as the WrEnIB<0> signal. The GNR6 signal and the GNR8 signal are provided as having the same timing as the WrEnIB<1> signal. The GNR 10 signal is provided as having the same timing as the WrEnIB<2> signal. The GNR12 signal is disabled. In this example operation, the sink transistor pairsA andB, the sink transistor pairsC andD, and the sink transistor pairE in the sink circuitare enabled at staggered times. The sink transistor pairF is disabled (e.g., not turned on).

9 FIG.C 11 100 230 230 230 230 212 230 230 illustrates an example operation of the VGA control circuit when the gain information MrGain<0:2> is three () and four (). The GNR2 signal and the GNR4 signal are provided as having the same timing as the WrEnIB<0> signal. The GNR6 signal and the GNR8 signal are provided as having the same timing as the WrEnIB<1> signal. The GNR10 signal and the GN12 signal are disabled. In this example operation, the sink transistor pairsA andB and the sink transistor pairsC andD in the sink circuitare enabled at staggered times. The sink transistor pairsE,F are disabled.

9 FIG.D 101 110 230 230 230 212 230 230 230 illustrates an example operation of the VGA control circuit when the gain information MrGain<0:2> is five () and six (). The GNR4 signal is provided as having the same timing as the WrEnIB<0> signal. The GNR6 signal and the GNR8 signal are provided as having the same timing as the WrEnIB<1> signal. The GNR2 signal, the GNR10 signal, and the GN12 signal are disabled. In this example operation, the sink transistor pairB, the sink transistor pairC, and the sink transistor pairD in the sink circuitare enabled at staggered times. The sink transistor pairsA,E,F are disabled (e.g., not turned on).

9 FIG.E 111 230 212 230 230 230 230 230 illustrates an example operation of the VGA control circuit when the gain information MrGain<0:2> is seven (). The GNR2 signal is provided as having the same timing as the WrEnIB<0> signal. The GNR4 signal, the GNR6 signal, the GNR8 signal, the GNR10 signal, and the GN12 signal are disabled. In this example operation, the sink transistor pairA in the sink circuitis enabled. The sink transistor pairB, the sink transistor pairC, the sink transistor pairD, the sink transistor pairE, and the sink transistor pairF are disabled.

9 9 FIGS.A-E As shown in, the gain information MrGain<0:2> can be used to selectively enable sink transistors in a sink circuit. Thus, a VGA control circuit can be configured to selectively enable sink transistors in a sink circuit. The gain information MrGain<0:2> can be used to determine which write enable signals WrEnIB are enabled (e.g., output by the VGA control circuit) and which write enable signals WrEnIB are disabled (e.g., not output by the VGA control circuit).

10 FIG. 10 FIG. 2 FIG. 1000 230 230 illustrates a first example timing diagramfor a variable gain amplifier power savings according to an embodiment of the disclosure. The WRITE command is provided to the command decoder, and the command decoder responsively provides the WRCMD signal (not shown in). At time to, the WrEnIBdetPre signal transitions from the first signal level (e.g., low or “0”) to the second signal level (high or “1”). At time t1, a delayed WrEnIBdetPre signal transitions from the first signal level to the second signal level. At time t2, the WrEnIB<0> signal, the control signal GNR2, and the control signal GNR4 transition from the first signal level to the second signal level. The sink transistor(s) in a sink circuit that receive the control signal GNR2 and the control signal GNR4 are enabled (e.g., turned on). For example, with reference to, the sink transistor pairsA,B are enabled.

2 FIG. 230 230 At time t3, the WrEnIB<1> signal, the control signal GNR6, and the control signal GNR8 transition from the first signal level to the second signal level. The sink transistor(s) in a sink circuit that receive the GNR6 signal and the GNR8 signal are enabled. For example, with reference to, the sink transistor pairsC,D are enabled.

2 FIG. 230 At time t4, the WrEnIB<2> signal and the control signal GNR10 transition from the first signal level to the second signal level. The sink transistor(s) in a sink circuit that receives the GNR10 signal is enabled. For example, with reference to, the sink transistor pairE is enabled.

2 FIG. 230 At time t5, the WrEnIB<3> signal and the control signal GNR12 transition from the first signal level to the second signal level. The sink transistor(s) in a sink circuit that receives the GNR12 signal is enabled. For example, with reference to, the sink transistor pairF is enabled.

2 FIG. 230 230 230 230 230 230 At time t6, the WrEnIBdetPre signal transitions from the second signal level to the first signal level, which causes the GNR2 signal, the GNR4 signal, the GNR6 signal, the GNR8 signal, the GNR10 signal, and the GNR12 signal to transition from the second signal level to the first signal level. The transitions in the GNR2 signal, the GNR4 signal, the GNR6 signal, the GNR8 signal, the GNR10 signal, and the GNR12 signal cause all of the sink transistors in a sink circuit to be disabled (e.g., turned off). For example, with reference to, the sink transistor pairsA,B,C,D,E, andF are disabled.

10 FIG. As shown in, the timing of the control signals GNR2, GNR4, GNR6, GNR8, GNR10, and GNR 12 correspond to respective write enable signals WrEnIB<0>, WrEnIB<1>, WrEnIB<2>, WrEnIB<3>. The enable and disable times of the GNR2 and the GNR4 signals correspond to the enable and disable times of the WrEnIB<0> signal. The enable and disable times of the GNR6 and the GNR8 signals correspond to the enable and disable times of the WrEnIB<1> signal. The enable and disable times of the GNR10 signal correspond to the enable and disable times of the WrEnIB<2> signal. The enable and disable times of the GNR12 signal correspond to the enable and disable times of the WrEnIB<3> signal.

Additionally, the control signals GNR2/GNR4, GNR6/GNR8, GNR10, and GNR 12 have different pulse widths. The control signal GNR2/GNR4 has a pulse width W4. The control signal GNR6/GNR8 has a pulse width W3. The control signal GNR10 has a pulse width W2. The control signal GNR 12 has a pulse width W1. The pulse width W1 is less than the pulse width W2, the pulse width W2 is less than the pulse width W3, and the pulse width W3 is less than the pulse width W4 (W1<W2<W3<W4). Thus, the different pulse widths can be used to reduce or minimize the amount of time the sink transistors are enabled. For example, the strongest sink transistor(s) may be enabled by the GNR 12 signal, which has the shortest pulse width, while the weakest sink transistor(s) can be enabled by the GNR2/GNR4 signal, which has the longest pulse width. In this manner, the power consumption of the VGA can be further reduced.

11 FIG. 5 FIG. 1100 1100 500 1102 1102 illustrates a block diagram of a second example delay control circuitaccording to an embodiment of the disclosure. The delay control circuitis similar to the delay control circuitshown in(see same reference numbers), with the exception of the reset pulse generator. For brevity, only the reset pulse generatoris described.

1102 1102 530 1104 The reset pulse generatoris configured to produce multiple reset signals Reset<m>. In the illustrated embodiment, the reset pulse generatorprovides four Reset signals Reset<0>, Reset<1, Reset<2>, Reset<3>. The latchreceives the Reset<0> signal on signal line. The Reset<0> signal determines a pulse width of the WrEnIB<3> signal. The enable time of the WrEnIB<3> signal (e.g., transition from the first signal level (low or “0”) to the second signal level (high or “1”)) is based on the WrEnIBdetPre signal and the disable time of the WrEnIB<3> signal (e.g., transition from the second signal level to the first signal level) is based on the Reset<0> signal.

528 1106 526 1108 524 1110 The latchreceives the Reset<1> signal on signal line. The Reset<1> signal determines a pulse width of the WrEnIB<2> signal. The enable time of the WrEnIB<2> signal is based on the WrEnIBdetPre signal and the disable time of the WrEnIB<2> signal is based on the Reset<1> signal. The latchreceives the Reset<2> signal on signal line. The Reset<2> signal determines a pulse width of the WrEnIB<1> signal. The enable time of the WrEnIB<1> signal is based on the WrEnIBdetPre signal and the disable time of the WrEnIB<1> signal is based on the Reset<2> signal. The latchreceives the Reset<3> signal on signal line. The Reset<3> signal determines a pulse width of the WrEnIB<0> signal. The enable time of the WrEnIB<0> signal is based on the WrEnIBdetPre signal and the disable time of the WrEnIB<0> signal is based on the Reset<3> signal. Based on the timing of the Reset<3> signal, the Reset<2> signal, the Reset<1> signal, and the Reset<0> signal, the WrEnIB<0>, WrEnIB<1>, WrEnIB<2>, and WrEnIB<3> signals, respectively, can each have a different pulse width with different staggered enable times and different staggered disable times.

12 FIG. 11 FIG. 1200 1100 502 510 1202 502 illustrates an example timing diagramfor the delay control circuitshown inaccording to an embodiment of the disclosure. At time to, the WrEnIBdetPre signal transitions from the first signal level (e.g., low or “0”) to the second signal level (e.g., high or “1”). At time t1, the signal output by the delay circuit(point A), the signal output by the set pulse generator(point AA), and the first WrEnIB<0> signal transition from the first signal level to the second signal level. The time periodincludes the first delay provided by the delay circuit.

504 514 1204 502 504 506 518 1206 502 504 506 At time t2, the signal output by the delay circuit(point B), the signal output by the set pulse generator(point BB), and the second WrEnIB<1> signal transition from the first signal level to the second signal level. The time periodincludes the first delay provided by the delay circuitand the second delay provided by the delay circuit. At time t3, the signal output by the delay circuit(point C), the signal output by the set pulse generator(point CC), and the third WrEnIB<2> signal transition from the first signal level to the second signal level. The time periodincludes the first delay provided by the delay circuit, the second delay provided by the delay circuit, and the third delay provided by the delay circuit.

508 522 1208 502 504 506 508 At time t4, the signal output by the delay circuit(point D), the signal output by the set pulse generator(point DD), and the fourth WrEnIB<3> signal transition from the first signal level to the second signal level. The time periodincludes the first delay provided by the delay circuit, the second delay provided by the delay circuit, the third delay provided by the delay circuit, and the fourth delay provided by the delay circuit.

1210 1210 1212 1212 At time t5, the WrEnIBdetPre signal transitions from the second signal level to the first signal level, which causes the Reset<0> signal to transition from the first signal level to the second signal level. The reset pulse(e.g., the rising edge of the reset pulse) causes the fourth WrEnIB<3> signal to transition from the second signal level to the first signal level. At time t6, the Reset<1> signal transitions from the first signal level to the second signal level. The reset pulse(e.g., the rising edge of the reset pulse) causes the third WrEnIB<2> signal to transition from the second signal level to the first signal level.

1214 1214 1216 1216 At time t7, the Reset<2> signal transitions from the first signal level to the second signal level. The reset pulse(e.g., the rising edge of the reset pulse) causes the second WrEnIB<1> signal to transition from the second signal level to the first signal level. At time t8, the Reset<3> signal transitions from the first signal level to the second signal level. The reset pulse(e.g., the rising edge of the reset pulse) causes the first WrEnIB<0> signal to transition from the second signal level to the first signal level.

12 FIG. As shown in, the four write enable signals WrEnIB<0>, WrEnIB<1>, WrEnIB<2>, WrEnIB<3> have staggered enable times (i.e., t1, t2, t3, t4, respectively) and staggered disable times (i.e., t8, t7, t6, t5, respectively). The WrEnIB<3> signal has a pulse width W1, the WrEnIB<2> signal has a pulse width W2, the WrEnIB<1> signal has a pulse width W3, and the WrEnIB<0> signal has a pulse width W4. W1 is less than W2, W2 is less than W3, and W3 is less than W4 (W1<W2<W3<W4).

13 FIG. 11 FIG. 1300 1300 illustrates a second example timing diagramfor a variable gain amplifier power savings according to an embodiment of the disclosure. The timing diagramis for the delay control circuit shown inand depicts the WrEnIB<n> signals and the GNRx signals. The WrEnIB<n> signals and the GNRx signals have staggered enable times and staggered disable times.

2 FIG. 230 230 At time t1, the WrEnIB<0> signal, the GNR2 signal, and the GNR4 signal transition from the first signal level (e.g., low or “0”) to the second signal level (e.g., high or “1”). In the embodiment shown in, the transition in the GNR2 signal enables the sink transistor pairA and the transition in the GNR4 signal enables the sink transistor pairB.

2 FIG. 2 FIG. 2 FIG. 230 230 230 230 At time t2, the WrEnIB<1> signal, the GNR6 signal, and the GNR8 signal transition from the first signal level to the second signal level. In the embodiment shown in, the transition in the GNR6 signal enables the sink transistor pairC and the transition in the GNR8 signal enables the sink transistor pairD. At time t3, the WrEnIB<2> signal and the GNR 10 signal transition from the first signal level to the second signal level. In the embodiment shown in, the transition in the GNR 10 signal enables the sink transistor pairE. At time t4, the WrEnIB<3> signal and the GNR12 signal transition from the first signal level to the second signal level. In the embodiment shown in, the transition in the GNR12 signal enables the sink transistor pairF.

2 FIG. 230 At time t5, the WrEnIB<3> signal and the GNR12 signal transition from the second signal level to the first signal level. The GNR12 signal has the same enable and disable times (i.e., the same timing) as the WrEnIB<3> signal. In the embodiment shown in, the transition in the GNR12 signal disables the sink transistor pairF.

2 FIG. 230 At time t6, the WrEnIB<2> signal and the GNR10 signal transition from the second signal level to the first signal level. The GNR10 signal has the same enable and disable times (i.e., the same timing) as the WrEnIB<2> signal. In the embodiment shown in, the transition in the GNR10 signal disables the sink transistor pairE.

2 FIG. 230 230 At time t7, the WrEnIB<1> signal, the GNR8 signal, and the GNR6 signal transition from the second signal level to the first signal level. The GNR6 signal and the GNR8 signal have the same enable and disable times (i.e., the same timing) as the WrEnIB<1> signal. In the embodiment shown in, the transitions in the GNR6 and the GNR8 signals disable the sink transistor pairsC,D, respectively.

2 FIG. 230 230 At time t8, the WrEnIB<0> signal, the GNR4 signal, and the GNR2 signal transition from the second signal level to the first signal level. The GNR4 signal and the GNR2 signal have the same enable and disable times (i.e., the same timing) as the WrEnIB<0> signal. In the embodiment shown in, the transitions in the GNR2 and the GNR4 signals disable the sink transistor pairsA,B, respectively.

13 FIG. As shown in, the timing of the control signals GNR2, GNR4, GNR6, GNR8, GNR10, and GNR 12 correspond to respective write enable signals WrEnIB<0>, WrEnIB<1>, WrEnIB<2>, WrEnIB<3>. The enable and disable times of the GNR2 and the GNR4 signals correspond to the enable and disable times of the WrEnIB<0> signal. The enable and disable times of the GNR6 and the GNR8 signals correspond to the enable and disable times of the WrEnIB<1> signal. The enable and disable times of the GNR10 signal corresponds to the enable and disable times of the WrEnIB<2> signal. The enable and disable times of the GNR12 signal corresponds to the enable and disable times of the WrEnIB<3> signal.

Additionally, the control signals GNR2/GNR4, GNR6/GNR8, GNR10, and GNR 12 have different pulse widths. The control signal GNR2/GNR4 has a pulse width W4. The control signal GNR6/GNR8 has a pulse width W3. The control signal GNR10 has a pulse width W2. The control signal GNR 12 has a pulse width W1. The pulse width W1 is less than the pulse width W2, the pulse width W2 is less than the pulse width W3, and the pulse width W3 is less than the pulse width W4 (W1<W2<W3<W4). Thus, the different pulse widths can be used to reduce or minimize the amount of time the sink transistors are enabled. For example, the strongest sink transistor(s) may be enabled by the GNR 12 signal, which has the shortest pulse width, while the weakest sink transistor(s) can be enabled by the GNR2/GNR4 signal, which has the longest pulse width. In this manner, the power consumption of the VGA can be further reduced. Additionally, the staggered disable times may reduce or limit power fluctuations in a memory device.

12 FIG. 13 FIG. 11 FIG. 2 FIG. 2 11 12 13 FIGS.,,and 1100 212 230 230 230 230 230 230 212 230 230 230 230 230 230 230 230 230 230 230 230 The timing diagrams ofandare example timing diagrams that are based on the second example delay control circuitshown in, and the example process flow shown in. Other embodiments are not limited to the implementations shown in. For example, the sink circuitcan include a different number of sink transistor pairsA,B,C,D,E,F. Additionally or alternatively, different sets of sink transistor pairs in the sink circuitcan be enabled and disabled. For example, each sink transistor pairA,B,C,D,E,F can be enabled individually. Those skilled in the art will recognize that enabling each sink transistor pairA,B,C,D,E,F individually would include a different number of WrEnIB<n> signals and possibly Reset<m> signals.

The foregoing description, for purposes of explanation, uses specific nomenclature to provide a thorough understanding of the described embodiments. However, it will be apparent to one skilled in the art that the specific details are not required to practice the described embodiments. Thus, the foregoing descriptions of the specific embodiments described herein are presented for purposes of illustration and description. They are not targeted to be exhaustive or to limit the embodiments to the precise forms disclosed. It will be apparent to one of ordinary skill in the art that many modifications and variations are possible in view of the above teachings.