Semiconductor Memory Device and Control Method Thereof

This Application claims priority of Japanese Patent Application No. 2024-127942, filed on August 2,2024, the entirety of which is incorporated by reference herein.

The present invention relates to semiconductor memory devices and control methods thereof.

In order to integrate the impedance of the transmission path with the output impedance of the output circuit in conventional semiconductor memory devices, it is well-known practice to connect resistors disposed outside the semiconductor memory (external resistors) device to the ZQ terminal of the semiconductor memory device, and then to perform a ZQ calibration (for example, Japanese Unexamined Patent Publication No. 2007-123987).

In traditional technology, the cost of manufacturing an external device (an external system) that contains external resistors may increase due to the need to connect external resistors to the ZQ terminal. In addition, if the semiconductor memory device has multiple silicon chips (memory die), such as Dual Die Package (DDP), the manufacturing cost of an external device (external system) that includes external resistors may be further increase due to different external resistors connected to multiple silicon dies.

In view of the above problems, a semiconductor memory device capable of mitigating the increase in manufacturing cost of an external device and a control method thereof is provided in the present invention.

To solve the above problems, the present invention provides a semiconductor memory device comprising a calibration circuit, performing a ZQ calibration operation, and a resistor part for use as a reference resistor in a ZQ calibration operation.

According to this invention, the need for setting an external resistor for ZQ calibration on an external device can be eliminated because the ZQ calibration operation can be performed using the resistor part disposed on the semiconductor memory device. As a result, the increase in manufacturing cost of external devices due to setting external resistors can be mitigated.

In addition, a control method of a semiconductor memory device includes a resistor part for use as a reference resistor in a ZQ calibration operation. The control method of a semiconductor memory device includes a calibration circuit using a resistor part to perform a ZQ calibration operation.

Based on the semiconductor memory device and its control method, the increase in manufacturing costs of external devices can be mitigated.

1 FIG. 1 FIG. 1 10 1 20 10 1 10 1 10 1 Referring to, semiconductor memory deviceis a dynamic random access memory (DRAM) such as Double Data-Rate 4 Synchronous Random Access Memory, DDR4 SDRAM, etc., and includes more than one memory die (chip). In addition, in this embodiment, semiconductor memory devicehas a ZQ terminalon more than one memory die. In addition, althoughshows that a semiconductor memory devicecontains a memory die, a semiconductor memory devicecan include multiple memory dice. In addition, to simplify the illustration, other known components of semiconductor memory device(e.g., power supply circuit, command decoder, address decoder, clock generator, etc.) are not shown here.

10 11 12 In this embodiment, the memory dieincludes a calibration circuitand a resistor part.

11 1 1 1 1 1 The calibration circuitincludes a plurality of P-channel metal-oxide semiconductor field effect transistors (MOSFETs) P-Pi (i is an integer of 2 or more) and configured to perform a ZQ calibration operation. The source terminal of each P-channel MOSFET P-Pi is connected to the operating voltage VDD, and the drain terminal of each P-channel MOSFET P-Pi is connected to resistor part 12 through node N. In addition, the gate terminals of each P-channel MOSFET P-Pi receives an input control signal used to regulate the ON/OFF switching of each P-channel MOSFET P-Pi.

11 1 11 1 11 Besides, in this embodiment, although the calibration circuitincludes multiple P-channel MOSFETs P-PIs as an example, the calibration circuitmay include multiple N-channel MOSFETs instead of multiple P-channel MOSFETs P-Pi, and may include multiple other transistors, or may include multiple switching circuits. In addition, the calibration operation in the calibration circuitwill be explained later.

12 12 1 2 11 1 2 FIG. The resistor partis configured for use as a reference resistor in ZQ calibration operation. Besides, in this embodiment, resistor partincludes resistance units U˜Uj (j is an integer above) parallel to the calibration circuitas shown in. As a result, multiple resistance units U˜Uj can be used to form the reference resistor in ZQ calibration operation.

1 12 12 1 2 1 2 3 1 1 1 2 1 1 2 2 2 3 2 2 3 2 FIG. 2 FIG. 2 FIG. a, b, th th th th th In this embodiment, each of resistance units U˜Uj contains multiple (in the example shown in, there are 4) series-connected resistorsthe first resistor R, the second resistor R, and multiple (in the example shown in, there are 3) switch parts (switch part SW, switch part SW, switch part SW). In addition, the structure of each of the multiple resistance units U˜Uj is as follows: one end of the Nswitch part SWN (where N is an integer of 1 or more) is connected to one end of the Nresistor RN, and one end of the (N+1)switch part SW(N+1) is connected to the other end of the Nth resistor RN. The other end of the Nswitch part SWN and the other end of the (N+1)switch part SW(N+1) are connected to each other. Specifically, in the example shown in, one end of the switch part SWis connected to one end of the resistor R, one end of the switch part SWis connected to the other end of the resistor R, the other end of the switch part SWand the other end of the switch part SWare connected to each other. In addition, one end of the switch part SWis connected to one end of the second resistor R, one end of the switch SWis connected to the other end of the second resistor R, the other end of the switch part SWand the other end of the third switch SWare connected to each other.

1 1 2 3 1 1 1 Besides, in this embodiment, although the case of multiple resistance units U˜Uj each has three switch parts (switch part SW, switch part SWand switch part SW) as an example, the number of switch parts provided by multiple resistance units U˜Uj may be 2 or less, or more than 4. In addition, the number of switch parts provided by multiple resistance units U˜Uj may be the same or different between multiple resistance units U˜Uj.

1 4 12 12 1 2 1 1 a, b, Furthermore, in this embodiment, although the case where each of the multiple resistance units U˜Uj is equipped withresistorsthe first resistor R, and the second resistor Ris described as an example, the number of resistors each equipped within can be less than 3, or more than 5. In addition, the number of resistors equipped by multiple resistance units U˜Uj can be the same or different from U˜Uj.

1 1 2 3 1 1 2 3 1 1 2 3 1 12 12 2 1 1 3 1 12 12 1 3 1 1 2 1 12 12 1 2 1 a b. a, b a, b, Each of the multiple resistance units U˜Uj is configured to: when any of the multiple switch parts (switch part SW, switch part SW, or switch part SW) is in a conducting state, it has a resistance value corresponding to the conducting switch part. Specifically, each of the multiple resistance units U˜Uj is controlled in such a way that only one of the multiple switch parts (switch part SW, switch part SW, and switch part SW) is in the conducting state. For example, when the switch part SWof the resistance unit Uis in the conducting state, the switch part SWand the switch part SWare turned off, the resistance value of the resistance unit Uis represented by the sum of the respective resistance values of resistorand resistorIn addition, when the switch part SWof the resistance unit Uis in the conducting state, the switch part SWand the switch part SWare turned off, the resistance value of the resistance unit Uis expressed by the sum of the respective resistance values of resistorresistorand first resistor R. Furthermore, when the switch part SWof the resistance unit Uis in the conducting state, the switch part SWand the switch part SWare turned off, the resistance value of the resistance unit Uis expressed by the sum of the respective resistance values of resistorresistorthe first resistor Rand the second resistor R. In this way, each of the multiple resistance units U˜Uj may have different resistance values depending on the switch part in the conducting state.

1 2 3 1 2 3 1 2 3 In addition, in this embodiment, each of the multiple switch parts (switch part SW, switch part SW, and switch part SW) contain a transfer transistor. Thus, by changing any of the P-channel MOSFETs and N-channel MOSFETs that make up the transfer transistor into the conducting state, the transfer transistor can be easily turned into the conducting state. In addition, although the multiple switch parts (switch part SW, switch part SW, and switch part SW) are configured as an example to contain transfer transistors, it is also possible to configure at least one of the multiple switch parts (switch part SW, switch part SW, and switch part SW) to contain other switching circuits other than the transfer transistors (e.g., P-channel MOSFETs, N-channel MOSFETs, etc.).

1 1 12 In addition, each of multiple resistance units U˜Uj may include the same resistance value. Thus, a resistance unit U˜Uj including the same resistance value can be used to form a reference resistor in ZQ calibration operation easily. For example, if resistor parthas a resistance value of 24052 and the number of resistance units is 10, the resistance value of each resistance unit can be set to 240062.

3 FIG.A 3 FIG.B 3 FIG.A 1 1 1 1 2 3 1 1 1 Here, refer toandfor an example of adjusting the resistance values of multiple resistance units U˜Uj. As shown in, a specific voltage Vis applied to the resistor unit U, and the other end of each of switch parts (switch part SW, switch part SW, switch part SW) is connected to the input terminal of one end (+side) of the comparator C. In addition, the input terminal on the other end (−side) of comparator C is input to a specific reference voltage Vref. Furthermore, comparator C compares the voltage Vin of the input terminal input on one end (+side) to the reference voltage Vref of the input terminal on the other end (−side) and outputs the comparison result as the output voltage Vout. In this embodiment, when the output voltage of the resistance unit U(i.e., voltage Vin) is equal to the reference voltage Vref, the resistance unit Uhas the desired resistance value and adjust the resistance value of the resistance unit U.

3 FIG.B 3 FIG.B 1 1 2 3 1 2 3 2 1 2 As shown in, in the resistance unit U, the switch part SWis set as the conducting state first, and then the switch part SWis set to the conducting state, and then the switch part SWis set to the conducting state. Then, in the multiple switch parts (switch part SW, switch part SW, switch part SW), which one of the switch parts has the same voltage Vin as the reference voltage Vref when it is set to the conducting state is determined (in the example shown in, the switch part SW), and the discriminated switch part is set to the conducting state, thus adjusting the resistance value of the resistance unit U. In addition, the resistance value can also be adjusted for other resistor units U˜Uj.

12 12 1 2 1 1 1 1 2 3 3 2 1 a, b, 3 FIG.B In addition, according to the process and temperature characteristics, the resistance values of resistorsthe first resistor R, and the second resistor Requipped in the multiple resistance units Uto Uj may be different from those in the multiple resistance units Uto Uj, so when set to the conducting state, the switch part that equalizes the input voltage Vin and the reference voltage Vref can be different among the multiple resistance units U˜Uj. Besides, in the example shown in, the switch part SWis set to the conducting state, then the switch part SWis set to the conducting state, and then the switch part SWis set to the conducting state, it is also possible to arbitrarily determine the sequence of the switch part set to the conducting state. (e.g., the switch part SWcan be set as the conducting state, then the switch part SWas the conducting state, and then the switch part SWas the conducting state).

1 FIG. 20 12 1 20 11 20 11 12 Back to, ZQ terminalis a terminal that can be connected to an external resistor for ZQ calibration operation. In addition, since the resistor partused as the reference resistor in the ZQ calibration operation is set in the semiconductor memory device, the ZQ terminaldoes not have to include the same structure as conventional technology (i.e., a structure that can be connected to the calibration circuitand an external resistor separately). In this embodiment, ZQ terminalis set not connected to calibration circuitand resistor part.

20 Besides, in conventional semiconductor memory devices, in addition to ZQ terminal, there are terminals for data input and output (e.g., DQ terminals). Here, the data input/output terminals (pad) need to be formed into a size that can be contacted by the probe pin (or probe needle) during wafer testing with the probe card. However, when the size of the data input/output terminals (pad size) becomes larger, charge and discharge current on the data input/output terminals increases, so there may be concerns about increasing power consumption of semiconductor memory devices. In addition, apart from the data output terminals used for normal operation in semiconductor memory devices, it is also possible to consider incorporating dedicated data output terminals for wafer testing within semiconductor memory devices. However, in such case, there may be concerns about potential size increase in the semiconductor memory devices (memory dies) as new data output terminal specifically for wafer testing need to bo incorporated within the semiconductor memory devices (memory dies).

20 1 1 1 10 Therefore, in this embodiment, the ZQ terminalis configured for data input and output during wafer testing. As a result, the size of the terminal (DQ terminal) used for data output used by the semiconductor memory deviceduring normal operation (the size of the pad) does not need to be increased, and the increase in power consumption of the semiconductor memory devicecan be mitigated. In addition, since there is no need to incorporate a dedicated data output terminal for wafer testing, the increase in the size of semiconductor memory device(memory die) can be mitigated.

20 20 1 20 In this embodiment, ZQ terminalcan be connected between data input/output circuits, such as data signals (DQ) and data strobe signals (DQS,/DQS) and external devices (figures omitted). In addition, the ZQ terminalcan be formed to a size that can be in contact with the probe pin of the probe card during the wafer testing. Thus, the data input and output circuit of the semiconductor memory devicecan transmit and receive data between the ZQ terminaland the probe card during wafer testing, and can transmit and receive data between the terminal for data output (DQ terminal) and the external device during normal operation. In addition, the switching of terminals for data transmission and reception can be carried out, for example, by switching circuits.

1 FIG. 20 10 1 10 20 10 20 10 In addition, althoughshows a case in which a ZQ terminalis set for a memory die, if the semiconductor memory deviceincludes a plurality of memory dice, a ZQ terminalcan be set for each of memory dice, or a shared ZQ terminalcan be set in a plurality of memory dice.

4 FIG. 1 FIG. 11 1 11 12 12 11 Referring to, the calibration operation performed in the calibration circuitof the semiconductor memory deviceof the present embodiment is illustrated. In present embodiment, the calibration circuitis calibrated using a resistor part. In addition, here is the case where it is assumed that the voltage V of node N inis equal to a specific voltage (e.g., VDD/2), the impedances in the resistor partare integrated to perform the calibration operation in calibration circuit.

1 1 1 2 1 2 3 1 1 4 FIG. At the beginning of the calibration operation, multiple P-channel MOSFETs P-PIs are turned off. First, the P-channel MOSFET Pis set to conducting state, the voltage V of node N will rise. Next, while the P-channel MOSFET Pis in conducting state, the P-channel MOSFET Pis set to conducting state, the voltage V of node N will rise incrementally. Furthermore, when P-channel MOSFET Pand Pare in conducting state, the P-channel MOSFET Pis set to conducting state, the voltage V of node N will rise further. As a result, the calibration operation can be performed by sequentially setting multiple P-channel MOSFETs P˜Pi to the conducting state until the voltage V of the node N is equal to a specific voltage (e.g., VDD/2). In addition, although the voltage V of node N rises to a specific voltage (e.g., VDD/2) is shown in, the calibration operation can be performed if the voltage V of node N is decreased to a specific voltage (e.g., VDD/2) (i.e., multiple P-channel MOSFETs P˜Pi are each set to the conducting state at the beginning of the calibration operation, and then to the off state until the voltage V of node N is equal to a specific voltage (e.g., VDD/2).

11 1 In addition, the node N of the calibration circuitcan be connected to, for example, a terminal (pad) for data signals (DQ) (figures omitted) or a terminal (pad) for data strobe signals (DQS,/DQS) (figures omitted), etc. In this way, the resistance obtained from the calibration operation (i.e., the composite resistance of at least one P-channel MOSFET set to the conducting state in multiple P-channel MOSFETs P˜Pi) can be set as the output impedance.

1 12 1 As mentioned above, according to the semiconductor memory deviceand its control method in the present embodiment, the need to set an external resistor for ZQ calibration in an external device can be eliminated because the resistor partin the semiconductor memory devicecan be used to perform ZQ calibration. In this way, it is possible to suppress the increase in the manufacturing cost of external devices due to the installation of external resistors.

The embodiments described above are documented to make the invention easier to understand, and are not intended to limit the invention. Therefore, the components disclosed in the aforementioned embodiments include all design changes and equivalents in the technical scope of the invention.

For example, although the case of a semiconductor memory device as a DRAM is illustrated as an example in the above embodiments, the invention is not limited to this. For example, a semiconductor memory device can be SRAM (Static Random Access Memory) or pSRAM (pseudo-Static Random Access Memory) or flash memory or other semiconductor memory devices.

11 12 1 FIG. 2 FIG. In addition, the respective structures of the calibration circuitand the resistor partshown inandare only examples and can be appropriately changed, or a known structure or other various structures can also be adopted.