Bga Antipad Design for Reduced Cross Talk

This disclosure generally relates to information handling systems, and more particularly relates to a BGA antipad design for reducing cross talk in a printed circuit board in an information handling system.

As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an information handling system. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes. Because technology and information handling needs and requirements may vary between different applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software resources that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.

A printed circuit board may include a top metal layer having BGA pads, a first internal metal layer having a first breakout trace coupled to a first BGA pad by a first via, a second internal metal layer having a second breakout trace coupled to a second BGA pad by a second via, and a third internal metal having a third breakout trace coupled to a third BGA pad by a third via. In the first internal metal layer, the third via may be separated from the first breakout trace by a first antipad having a first dimension. In the second internal metal layer, the third via may be separated from the second breakout trace by a second antipad having a second dimension that is greater than the first dimension.

The use of the same reference symbols in different drawings indicates similar or identical items.

The following description in combination with the Figures is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to assist in describing the teachings, and should not be interpreted as a limitation on the scope or applicability of the teachings. However, other teachings can certainly be used in this application. The teachings can also be used in other applications, and with several different types of architectures, such as distributed computing architectures, client/server architectures, or middleware server architectures and associated resources.

1 FIG. 100 1 18 100 100 100 1 18 1 18 100 3 5 14 3 5 14 1 18 100 illustrates a layer stack-up of a printed circuit board (PCB)including 18 metal layers (M-M). PCBfurther represents a PCB that is manufactured in accordance with various high density interconnect (HDI) methods to pack multiple BGA components in a small footprint. For example, PCBmay incorporate buried vias, micro vias, or the like. typically, PCBwill be fabricated utilizing various laminate methods and substrate materials, such as photosensitive liquid dielectrics, photosensitive dry film dielectrics, polyimide flexible films, thermally cured dry films, resin-coated copper foil, FR-4 cores and prepregs, spread-glass laser-drillable prepregs, thermoplastics, or the like. Metal layers (M-M) represent patterned metalization between the substrate materials, and may include metal layers composed of a base metal such as copper, iron, nickel, or tin, a precious metal such as gold or silver, a heavy metal such as lead and zinc, or a critical raw material (CRM) such as tantalum. Metal layers (M-M) may include metal layers that are dedicated to the provision of signal traces for PCB, such as layers,, and(M, M, and M), and one or more additional metal layer for signal traces, as needed or desired. Metal layers (M-M) may further include metal layers that are dedicated to the provision of power and ground planes for PCB, as needed or desired.

100 More particularly, PCBrepresents a portion of the PCB that illustrates a breakout region for a device packaged on a ball grid array (BGA) package. Devices that are packaged on BGA packages generally have a large number of electrical connections (balls connections) that are connected to the PCB within the relatively small footprint of the BGA package. That is, the “density” of connections in the footprint area of the BGA package is very high. In particular, it is typical for the number of metal layers in a PCB to be more closely determined by the routing of the connections to BGA packages, than by any other type of component routing within the PCB. Thus the BGA breakout region has unique challenges in terms of signal routing, signal integrity, and the overall performance of the system embodied on the PCB.

100 110 120 130 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 110 118 3 100 120 128 5 130 138 14 110 3 110 120 5 120 130 14 130 PCBis illustrated as including the BGA breakouts,, andof three different differential signal pairs. For a first signal of the first differential pair, BGA breakoutprovides signal routing from a BGA padthrough a short signal traceand a signal viato a breakout signal trace. The second signal of the first differential pair includes a second BGA pad, a second signal trace, a second signal via, and a second breakout trace, that are all unlabeled to simplify the illustration. For a first signal of the second differential pair, BGA breakoutprovides signal routing from a BGA padthrough a short signal traceand a signal viato a breakout signal trace. Again, the second signal of the second differential pair includes a second BGA pad, a second signal trace, a second signal via, and a second breakout trace, that are likewise unlabeled. Finally, for a first signal of the third differential pair, BGA breakoutprovides signal routing from a BGA padthrough a short signal traceand a signal viato a breakout signal trace, and again, the second signal of the third differential pair includes a second BGA pad, a second signal trace, a second signal via, and a second breakout trace, that are all unlabeled. BGA breakoutprovides breakout traceon a third metal layer (M) of PCB, BGA breakoutprovides breakout traceon a fifth metal layer (M), and BGA breakoutprovides breakout traceon a fourteenth metal layer (M). As such, BGA breakoutmay be referred to as “layerbreakout,” BGA breakoutmay be referred to as “layerbreakout,” and BGA breakoutmay be referred to as “layerbreakout,”

2 FIG. 2 FIG. 100 3 14 116 118 3 136 138 14 210 116 230 136 3 210 230 illustrates a top view of a portion of PCB, with emphasis on the Mmetal layer and the Mmetal layer, in accordance with the prior art. Viasand breakout traceson the Mmetal layer are illustrated in the foreground, and viasand breakout traceson the Mmetal layer are illustrated in the background. It is well known in the art to provide via antipads surrounding vias that pass through a particular metal layer, but that are not otherwise connected to traces on that metal layer. As such, via antipads represent regions within a particular metal layer that surround the vias that pass through that metal layer, and that are devoid of the metallization on that particular metal layer. Via antipads thus provide an insulating region between the via and the traces within the particular metal layer.further illustrates via antipadssurrounding viasand via antipadssurrounding viason the Mmetal layer. Via antipadsandare illustrated as having a 26 mil diameter.

5 120 14 130 3 110 14 126 116 126 136 3 3 14 14 5 5 14 14 3 3 3 3 1 3 FIG. It had been thought by the inventors of the current disclosure that crosstalk inducing coupling between layerbreakoutand layerbreakoutwould be greater than the crosstalk inducing coupling between layerbreakoutand the layerbreakout. This thought had derived from the fact that signal viasare longer than signal vias, and that therefore the greater length of signal viaswould couple more strongly with signal viasalong the length of the respective signal vias. However, experimental results, shown in, show that the layer(M) to layer(M) near-end crosstalk (NEXT) is 4-6 dB greater than the layer(M) to layer(M) NEXT across a wide frequency band. Rather, the inventors of the current disclosure have understood that fringe fields between the layer(M) breakout to the BGA pads is the dominant effect, and that the distance between layer(M) and the top metal layer (M) is so small that the fringe fields are coupled to the other via pads. It has been further understood that the size and placement of the antipads may affect the fringe fields between the metal layers and the coupled vias.

4 FIG. 4 FIG. 5 FIG. 400 3 14 400 416 116 418 118 436 136 438 138 416 418 3 436 438 14 416 418 3 436 438 14 400 410 416 430 436 3 410 430 410 430 3 3 14 14 5 5 14 14 illustrates a top view of a portion of PCB, with emphasis on the Mmetal layer and the Mmetal layer. PCBincludes signal viassimilar to signal vias, breakout tracessimilar to breakout traces, signal viassimilar to signal vias, and breakout tracessimilar to breakout traces. In particular, signal viasand breakout tracesrepresent Mbreakout structures and signal viasand breakout tracesrepresent Mbreakout structures. Viasand breakout traceson the Mmetal layer are illustrated in the foreground, and viasand breakout traceson the Mmetal layer are illustrated in the background. PCBfurther includes via antipadssurrounding viasand via antipadssurrounding viason the Mmetal layer. Via antipadsandare illustrated as having a 20 mil diameter. It has been understood that the fringe fields occur between the vias and the signal traces. Thus antipadsandcan be formed in an elliptical shape as shown in, with the narrow end closest to the signal traces, as needed or desired. Experimental results utilizing various antipad configurations are shown in. In particular, the layer(M) to layer(M) near-end crosstalk (NEXT) is shown to be 4-6 dB less than the layer(M) to layer(M) NEXT across a wide frequency band.

6 FIG. 600 600 600 600 600 600 600 illustrates a generalized embodiment of an information handling systemsimilar to information handling system. For purpose of this disclosure an information handling system can include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, entertainment, or other purposes. For example, information handling systemcan be a personal computer, a laptop computer, a smart phone, a tablet device or other consumer electronic device, a network server, a network storage device, a switch router or other network communication device, or any other suitable device and may vary in size, shape, performance, functionality, and price. Further, information handling systemcan include processing resources for executing machine-executable code, such as a central processing unit (CPU), a programmable logic array (PLA), an embedded device such as a System-on-a-Chip (SoC), or other control logic hardware. Information handling systemcan also include one or more computer-readable medium for storing machine-executable code, such as software or data. Additional components of information handling systemcan include one or more storage devices that can store machine-executable code, one or more communications ports for communicating with external devices, and various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. Information handling systemcan also include one or more buses operable to transmit information between the various hardware components.

600 600 602 604 610 620 625 630 640 650 654 656 660 662 670 674 676 680 690 695 602 604 610 620 630 640 650 654 656 660 662 670 674 676 680 600 600 Information handling systemcan include devices or modules that embody one or more of the devices or modules described below, and operates to perform one or more of the methods described below. Information handling systemincludes a processorsand, an input/output (I/O) interface, memoriesand, a graphics interface, a basic input and output system/universal extensible firmware interface (BIOS/UEFI) module, a disk controller, a hard disk drive (HDD), an optical disk drive (ODD), a disk emulatorconnected to an external solid state drive (SSD), an I/O bridge, one or more add-on resources, a trusted platform module (TPM), a network interface, a management device, and a power supply. Processorsand, I/O interface, memory, graphics interface, BIOS/UEFI module, disk controller, HDD, ODD, disk emulator, SSD, I/O bridge, add-on resources, TPM, and network interfaceoperate together to provide a host environment of information handling systemthat operates to provide the data processing functionality of the information handling system. The host environment operates to execute machine-executable code, including platform BIOS/UEFI code, device firmware, operating system code, applications, programs, and the like, to perform the data processing tasks associated with information handling system.

602 610 606 604 608 620 602 622 625 604 627 630 610 632 636 634 600 602 604 620 630 In the host environment, processoris connected to I/O interfacevia processor interface, and processoris connected to the I/O interface via processor interface. Memoryis connected to processorvia a memory interface. Memoryis connected to processorvia a memory interface. Graphics interfaceis connected to I/O interfacevia a graphics interface, and provides a video display outputto a video display. In a particular embodiment, information handling systemincludes separate memories that are dedicated to each of processorsandvia separate memory interfaces. An example of memoriesandinclude random access memory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NV-RAM), or the like, read only memory (ROM), another type of memory, or a combination thereof.

640 650 670 610 612 612 610 640 600 640 600 2 BIOS/UEFI module, disk controller, and I/O bridgeare connected to I/O interfacevia an I/O channel. An example of I/O channelincludes a Peripheral Component Interconnect (PCI) interface, a PCI-Extended (PCI-X) interface, a high-speed PCI-Express (PCIe) interface, another industry standard or proprietary communication interface, or a combination thereof. I/O interfacecan also include one or more other I/O interfaces, including an Industry Standard Architecture (ISA) interface, a Small Computer Serial Interface (SCSI) interface, an Inter-Integrated Circuit (IC) interface, a System Packet Interface (SPI), a Universal Serial Bus (USB), another interface, or a combination thereof. BIOS/UEFI moduleincludes BIOS/UEFI code operable to detect resources within information handling system, to provide drivers for the resources, initialize the resources, and access the resources. BIOS/UEFI moduleincludes code that operates to detect resources within information handling system, to provide drivers for the resources, to initialize the resources, and to access the resources.

650 652 654 656 660 652 660 664 600 662 662 664 600 Disk controllerincludes a disk interfacethat connects the disk controller to HDD, to ODD, and to disk emulator. An example of disk interfaceincludes an Integrated Drive Electronics (IDE) interface, an Advanced Technology Attachment (ATA) such as a parallel ATA (PATA) interface or a serial ATA (SATA) interface, a SCSI interface, a USB interface, a proprietary interface, or a combination thereof. Disk emulatorpermits SSDto be connected to information handling systemvia an external interface. An example of external interfaceincludes a USB interface, an IEEE 1394 (Firewire) interface, a proprietary interface, or a combination thereof. Alternatively, solid-state drivecan be disposed within information handling system.

670 672 674 676 680 672 612 670 612 672 672 674 674 600 I/O bridgeincludes a peripheral interfacethat connects the I/O bridge to add-on resource, to TPM, and to network interface. Peripheral interfacecan be the same type of interface as I/O channel, or can be a different type of interface. As such, I/O bridgeextends the capacity of I/O channelwhere peripheral interfaceand the I/O channel are of the same type, and the I/O bridge translates information from a format suitable to the I/O channel to a format suitable to the peripheral channelwhere they are of a different type. Add-on resourcecan include a data storage system, an additional graphics interface, a network interface card (NIC), a sound/video processing card, another add-on resource, or a combination thereof. Add-on resourcecan be on a main circuit board, on separate circuit board or add-in card disposed within information handling system, a device that is external to the information handling system, or a combination thereof.

680 600 610 680 682 684 600 682 684 672 680 682 684 682 684 Network interfacerepresents a NIC disposed within information handling system, on a main circuit board of the information handling system, integrated onto another component such as I/O interface, in another suitable location, or a combination thereof. Network interface deviceincludes network channelsandthat provide interfaces to devices that are external to information handling system. In a particular embodiment, network channelsandare of a different type than peripheral channeland network interfacetranslates information from a format suitable to the peripheral channel to a format suitable to external devices. An example of network channelsandincludes InfiniBand channels, Fibre Channel channels, Gigabit Ethernet channels, proprietary channel architectures, or a combination thereof. Network channelsandcan be connected to external network resources (not illustrated). The network resource can include another information handling system, a data storage system, another network, a grid management system, another suitable resource, or a combination thereof.

690 600 690 600 690 600 600 690 600 690 690 Management devicerepresents one or more processing devices, such as a dedicated baseboard management controller (BMC) System-on-a-Chip (SoC) device, one or more associated memory devices, one or more network interface devices, a complex programmable logic device (CPLD), and the like, that operate together to provide the management environment for information handling system. In particular, management deviceis connected to various components of the host environment via various internal communication interfaces, such as a Low Pin Count (LPC) interface, an Inter-Integrated-Circuit (I2C) interface, a PCIe interface, or the like, to provide an out-of-band (OOB) mechanism to retrieve information related to the operation of the host environment, to provide BIOS/UEFI or system firmware updates, to manage non-processing components of information handling system, such as system cooling fans and power supplies. Management devicecan include a network connection to an external management system, and the management device can communicate with the management system to report status information for information handling system, to receive BIOS/UEFI or system firmware updates, or to perform other task for managing and controlling the operation of information handling system. Management devicecan operate off of a separate power plane from the components of the host environment so that the management device receives power to manage information handling systemwhere the information handling system is otherwise shut down. An example of management deviceinclude a commercially available BMC product or other device that operates in accordance with an Intelligent Platform Management Initiative (IPMI) specification, a Web Services Management (WSMan) interface, a Redfish Application Programming Interface (API), another Distributed Management Task Force (DMTF), or other management standard, and can include an Integrated Dell Remote Access Controller (IDRAC), an Embedded Controller (EC), or the like. Management devicemay further include associated memory devices, logic devices, security devices, or the like, as needed or desired.

Although only a few exemplary embodiments have been described in detail herein, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the embodiments of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the embodiments of the present disclosure as defined in the following claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents, but also equivalent structures.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover any and all such modifications, enhancements, and other embodiments that fall within the scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.