Semiconductor Package

This application is a Continuation Application of U.S. application Ser. No. 17/714,714, filed on Apr. 6, 2022, which claims priority to Korean Patent Application No. 10-2021-0097590, filed on Jul. 26, 2021, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.

The present disclosure relates to a semiconductor package.

Under-bump metal (UBM) structures may be formed between redistribution layers and solder balls to enhance board level reliability of semiconductor packages. However, in the case in which the surface of a UBM structure is not completely covered by a solder ball, the exposed surface of the UBM structure may corrode.

Example embodiments provide a semiconductor package having improved reliability.

According to example embodiments, a semiconductor package includes a redistribution structure having a front surface and a rear surface opposite the front surface, the redistribution structure including an insulating layer and a redistribution conductor provided in the insulating layer; a semiconductor chip provided on the rear surface and including a connection pad electrically connected to the redistribution conductor; an encapsulant provided on at least a portion of the semiconductor chip; under-bump metal (UBM) vias extending from the redistribution conductor to the front surface of the redistribution structure within the insulating layer; UBM pads provided on the front surface of the redistribution structure to correspond to the UBM vias, respectively, and each UBM pad of the UBM pads having an exposed surface convexly protruding away from the front surface of the redistribution structure; and a metal bump provided on the UBM pads and contacting the exposed surface of each UBM pad of the UBM pads.

According to example embodiments, a semiconductor package includes a redistribution structure having a front surface and a rear surface opposite the front surface, the redistribution structure including a redistribution conductor and an insulating layer provided on the redistribution conductor, the insulating layer defining a via hole exposing a portion of the redistribution conductor; a semiconductor chip provided on the rear surface and including a connection pad electrically connected to the redistribution conductor; an under-bump metal (UBM) structure electrically connected to the redistribution conductor exposed through the via hole; and a metal bump provided on the UBM structure, wherein the UBM structure includes: a seed layer extending along an inner surface of the via hole; a UBM via provided on the seed layer in the via hole; and a UBM pad having a first surface and a second surface, the first surface extending in a direction parallel to the front surface of the redistribution structure and contacting the UBM via, and the second surface convexly protruding away from the first surface and contacting the metal bump.

According to example embodiments, a semiconductor package includes a redistribution structure having a front surface and a rear surface opposite the front surface, the redistribution structure including a redistribution conductor, and an insulating layer provided on the redistribution conductor, the insulating layer defining a via hole exposing a portion of the redistribution conductor; a semiconductor chip provided on the rear surface and including a connection pad electrically connected to the redistribution conductor; and an under-bump metal (UBM) structure electrically connected to the redistribution conductor exposed through the via hole, wherein the UBM structure includes: a seed layer extending along an inner surface of the via hole and a portion of the front surface of the redistribution structure, a UBM via provided on the seed layer in the via hole, and a UBM pad extending in a first direction parallel to the front surface of the redistribution structure, the pad having a first surface contacting the UBM via and a portion of the seed layer, and a second surface convexly protruding away from the first surface.

Hereinafter, example embodiments will be described with reference to the accompanying drawings.

1 FIG. 2 FIG.A 1 FIG. 2 FIG.B 2 FIG.A 100 is a cross-sectional view illustrating a semiconductor packageA according to an example embodiment,is a partially enlarged view illustrating area ‘A’ ofaccording to an example embodiment, andis a plan view illustrating an area illustrated inaccording to an example embodiment.

1 2 2 FIGS.,A andB 100 110 120 140 100 130 150 140 150 143 150 140 140 140 100 150 150 Referring to, a semiconductor packageA according to an example embodiment may include a redistribution structure, a semiconductor chip, and a UBM structure. Also, the semiconductor packageA may further include an encapsulantand/or a metal bump. The UBM structuremay have a rounded surface, and the metal bumpmay be implemented to completely cover the exposed surface of the UBM padwithout a pretreatment process for wetting of the metal bump. Because the UBM structureis not exposed, corrosion of the UBM structuremay be prevented, and reliability of the UBM structureand the semiconductor packageA may be improved. In this case, the “pretreatment process for wetting of the metal bump” refers to a process performed before the Solder Ball Attach (SBA) process which may include, for example, a process of coating the surface of the UBM pad with a material similar to a solder ball to induce the metal bumpto be wetted to the side of the UBM pad. Hereinafter, components will be described with reference to the drawings.

110 110 110 110 111 112 111 110 120 110 110 111 112 110 110 111 112 The redistribution structuremay have a front surfaceFS and a rear surfaceBS positioned opposite to the front surfaceFS, and may include an insulating layerand a redistribution conductordisposed in the insulating layer. For example, the redistribution structuremay include a fan-in region overlapping the semiconductor chipalong a direction perpendicular to the rear surfaceBS, and a fan-out region extending from the fan-in region in a direction parallel to the rear surfaceBS, but example embodiments are not limited thereto. In addition, the number of the insulating layersand the redistribution conductorsof the redistribution structure, and the number of layers thereof, are not limited to those illustrated in the drawings. For example, the redistribution structuremay include a greater number of insulating layersand redistribution conductorsthan those illustrated in the drawings.

111 112 112 111 111 120 111 111 111 111 112 111 111 The insulating layermay cover the redistribution conductorand may have a via hole VH exposing at least a portion of the redistribution conductor. The insulating layermay include a plurality of insulating layersdisposed in a stacking direction of the semiconductor chip. For example, the insulating layermay more than two layers. The insulating layermay include an insulating material. Examples of the insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are impregnated with inorganic fillers and/or glass fibers (Glass Fiber, Glass Cloth, Glass Fabric), for example, a prepreg, Ajinomoto Build-up Film (ABF), FR-4, and BismaleimideTriazine (BT). For example, the insulating layermay include a photoimageable resin such as a photoimageable dielectric (PID) resin, which may allow the insulating layerto be thinner than when other insulating materials are included, and the redistribution conductormay be formed more finely. When the insulating layerincludes multiple layers, the different layers may include the same material or different materials, and the boundary between the insulating layersof different levels may be unclear depending on the process.

112 111 112 113 111 114 111 112 111 113 112 122 120 112 122 120 120 112 112 112 The redistribution conductormay be disposed on or in the insulating layer. The redistribution conductormay include a via portionpenetrating through the insulating layer. A redistribution seed layermay be disposed between the insulating layerand the redistribution conductor, and between the insulating layerand the via portion. The redistribution conductormay redistribute connection padsof the semiconductor chip. For example, the redistribution conductormay redistribute the connection padsof the semiconductor chipto the fan-out region. In this case, the “fan-out region” refers to a region that does not overlap the semiconductor chipalong the vertical direction. The redistribution conductormay include a metal material including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution conductormay perform various functions according to a design. For example, the redistribution conductormay include a ground pattern, a power pattern, and a signal pattern.

113 111 122 112 112 112 113 112 113 112 113 The via portionmay pass through the insulating layerto electrically connect the connection padand the redistribution conductor. According to an example embodiment, the redistribution conductorincludes a plurality of redistribution conductorspositioned at different levels, and the via portionmay also connect the redistribution conductorsof different levels to each other. The via portionmay be formed of the same or similar metal material as that of the redistribution conductorand, for example, may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The via portionmay be a filled via in which a metal material is filled in the via hole VH or a conformal via in which a metal material extends along the inner surface of the via hole VH.

114 112 111 122 111 114 114 114 The redistribution seed layermay extend between the redistribution conductorand the insulating layerand the connection padalong the inner surface of the via hole VH and the surface of the insulating layer. The redistribution seed layermay be formed of a metallic material and, for example, may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium. (Ti), or alloys thereof. The redistribution seed layermay have a thin film shape having a single-layer or multi-layer structure. The redistribution seed layermay include, for example, a first layer including titanium (Ti) and a second layer including copper (Cu).

120 100 110 121 122 123 121 122 121 122 112 113 122 121 122 123 122 123 120 120 123 123 120 The semiconductor chipis disposed on the rear surfaceBS of the redistribution structure, and may include the body, the connection pad, and a passivation layer. The bodymay include a semiconductor substrate including a semiconductor element such as silicon and germanium or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP), and an Integrated Circuit (IC) formed on the semiconductor substrate. The connection padelectrically connected to an integrated circuit may be disposed on the active surface of the body. The connection padmay be electrically connected to the redistribution conductorthrough the via portion. The connection padmay include, for example, a metal material such as aluminum (Al). An insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film may be formed on the upper surface and the lower surface of the body. For example, the connection padmay be disposed on the silicon nitride layer. The passivation layermay have an opening exposing at least a portion of the connection pad. The passivation layermay protect the semiconductor chipthat has been processed at the wafer level, and may protect the semiconductor chipfrom mechanical and thermal stress applied in the packaging process. The passivation layermay include an insulating material having excellent heat resistance, chemical resistance, mechanical properties, electrical properties, and the like. For example, the passivation layermay be formed using photosensitive polyimide (PSPI). The semiconductor chipmay be a logic chip or a memory chip. Logic chips may include, for example, central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), digital signal processing units (DSPs), cryptographic processors, microprocessors, microcontrollers, analog-digital converters, application specific integrated circuits (ASICs), and the like. The memory chips may include, for example, a volatile memory device such as a dynamic random-access memory (DRAM) or a static random-access memory (SRAM), or a non-volatile memory device such as a phase-change random-access-memory (PRAM), a magnetoresistive random-access memory (MRAM), a resistive random-access memory (RRAM), or a flash memory.

130 110 110 120 130 130 The encapsulantmay be disposed on the rear surfaceBS of the redistribution structureand may encapsulate at least a portion of the semiconductor chip. The encapsulantmay include, for example, an epoxy molding compound (EMC), but the material of the encapsulantis not particularly limited.

140 112 140 150 112 140 150 140 150 140 150 140 141 142 143 140 140 150 The UBM structuremay be electrically connected to the redistribution conductorexposed through the via hole VH. The UBM structureis disposed between the metal bumpand the redistribution conductor, and may be provided as a plurality of UBM structuresin contact with one metal bump. In this case, the yield of the SBA process may be improved. For example, the plurality of UBM structuresmay form a UBM group corresponding to each of the plurality of metal bumps, and the UBM group may include a plurality of UBM structureslocated inside of the metal bumpand spaced apart from each other. The plurality of UBM structuresmay each include a seed layer, a UBM via, and a UBM pad. According to an example embodiment, some of the UBM structuresmay be connected to each other, and according to an example embodiment the UBM structureand the metal bumpmay correspond to each other on one-to-one (1:1) basis.

141 110 110 111 111 142 143 111 112 141 111 112 110 110 141 143 142 141 143 142 143 142 111 141 141 110 110 143 2 FIG.A The seed layerextends along the inner surface of the via hole VH and a portion of the front surfaceFS of the redistribution structure(or a portion of the upper surface of the insulating layerbased on), and may be disposed between the insulating layerand the UBM viaand the UBM pad. An inner surface of the via hole VH may include an inner surface of the insulating layerand a surface of the redistribution conductorexposed through the via hole VH. Accordingly, the seed layermay conformally extend along the inner surface of the insulating layer, the exposed surface of the redistribution conductor, and at least a portion of the front surfaceFS of the redistribution structure. For example, the seed layermay not be disposed between the UBM padand the UBM via, but example embodiments are not limited thereto. The seed layermay be used as a seed layer in a plating process for forming the UBM padand the UBM via, and may be used as a diffusion barrier layer to prevent a metal material constituting the UBM padand the UBM viafrom diffusing into the insulating layer. For example, the seed layermay include, for example, a first layer including titanium (Ti) or a titanium (Ti) alloy, and a second layer including copper (Cu) or a copper (Cu) alloy. As shown, the end of the seed layermay extend along the front surfaceFS of the redistribution structureto coincide with the end of the UBM pad, but example embodiments are not limited thereto.

142 141 111 142 112 110 110 111 142 143 142 143 142 142 141 143 1 2 142 1 2 142 142 150 150 143 142 1 2 142 142 1 2 142 2 1 142 1 142 3 3 3 3 3 3 3 3 FIGS.A,B,C,D,E,F,G andH 2 FIG.B The UBM viais disposed on the seed layerand may fill the via hole VH of the insulating layer. The UBM viamay extend from the redistribution conductorto the front surfaceFS of the redistribution structurein the insulating layer. The UBM viamay include copper (Cu) or a copper (Cu) alloy. In an example embodiment, to form a round surface of the UBM padand to secure the fillability of the UBM via, the plating processes of the UBM padand the UBM viamay be separately performed. For example, the UBM viamay be formed by an electroplating process using the seed layer, and the UBM padmay be formed by an electroless plating process. This will be described later with reference to. Diameters Dand Dof the UBM viasare not particularly limited. For example, the diameters Dand Dof the UBM viasmaymay have various sizes in consideration of a perimeter (e.g.,R in) of the metal bumpin contact with the UBM pads, and the number of the UBM viasdisposed within the perimeter. For example, the diameters Dand Dof the UBM viasmay be about 20 μm or more, for example, in the range of about 20 μm to about 200 μm, about 25 μm to about 100 μm, or about 25 μm to about 50 μm. Also, the plurality of UBM viasmay have different diameters Dand D. As shown, the UBM viashaving a second diameter Dgreater than a first diameter Dmay surround the UBM viahaving the first diameter D, but example embodiments are not limited thereto. According to example embodiments, the size and arrangement of the UBM viasmay be variously modified.

143 142 142 143 142 143 110 110 142 143 143 1 110 141 142 110 143 2 143 1 143 1 150 143 2 143 150 143 150 143 2 143 143 2 143 100 The UBM padmay include a metal material similar to that of the UBM via, for example, copper (Cu) or an alloy of copper (Cu), but may be formed by a plating process separate from a process of the UBM via. For example, the UBM padmay be formed by performing an electroless plating process after forming the UBM via. Accordingly, the UBM padis disposed on the front surfaceFS of the redistribution structureto correspond to the UBM via, and may have an exposed surface (hereinafter, referred to as ‘second surface’). For example, the UBM padmay include a first surfaceSextending in a direction parallel to the front surfaceFS and in contact with a portion of the seed layerextending along the UBM viaand the front surfaceFS, and a second surfaceSconvexly protruding from the edge of the first surfaceStoward the opposite side of the first surfaceSand in contact with the metal bump. Because the second surfaceSof the UBM padin contact with the metal bumpmay have a rounded shape without a bent portion, properties of wetting of the solder ball in the SBA process and the reflow process are improved, and the UBM padmay be prevented from being exposed from the solder ball. Accordingly, the metal bumpmay cover all of the second surfaceSof the UBM padso that the second surfaceSis not exposed, and as a result, damage to the UBM padmay be prevented and the reliability of the semiconductor packageA can be improved.

143 143 142 110 143 143 110 143 142 110 142 143 143 143 2 143 143 1 143 2 143 143 143 150 143 150 143 143 150 143 150 142 143 142 143 143 142 150 143 2 143 2 FIG.B 2 FIG.B For example, the UBM padmay have a central portion (e.g.,CP in) overlapping the UBM viaalong a direction perpendicular to the front surfaceFS, and an edge portion (e.g.,EP in) extending from the central portionCP in a direction parallel to the front surfaceFS. For example, the edge portionEP may not overlap the UBM viaalong the direction perpendicular to the front surfaceFS. In this case, a thicknessH of the central portionCP may be greater than a thickness of the edge portionEP, and a portion of the second surfaceScorresponding to the central portionCP may be further away from the first surfaceSthan the rest of the second surfaceScorresponding to the edge portionEP. The size of the UBM padis not particularly limited. The UBM padmay have various sizes in consideration of the size of the metal bumpand the number of UBM padsdisposed in the metal bump. For example, an extended length d of the edge portionEP may be about 0.5 μm or more, for example, in the range of about 0.5 μm to about 10 μm, about 0.5 μm to about 5 μm, or about 0.5 μm to about 1 μm. If the extended length d of the edge portionEP is less than about 0.5 μm, the contact area with the metal bumpis not sufficiently secured, and thus, the electrical and physical properties between the UBM padand the metal bumpmay be lowered. In addition, a maximum thicknessH of the central portionCP may be about 20 μm or less, for example, in the range of about 0.5 μm to about 20 μm, about 0.5 μm to about 10 μm, or about 1 μm to about 10 μm. As described above, the maximum thicknessH of the central portionCP is not particularly limited, but the UBM padmay have a shape in which the thickness decreases as it moves away from a point having the maximum thicknessH. Therefore, the metal bumpmay be formed to cover the entirety of the second surfaceSof the UBM pad.

143 143 150 110 143 150 150 143 143 3 150 150 143 150 111 143 142 143 150 150 For example, the UBM padmay be provided as a plurality of UBM padsoverlapping one metal bumpalong a direction perpendicular to the front surfaceFS. The UBM padsmay be disposed in various shapes within a perimeterR of the metal bumpin contact with the second surfaceS (or the exposed surface) of outermost UBM pads. A diameter Dof the perimeterR of the metal bumpmay be about 150 μm or more, for example, in the range of about 150 μm to about 400 μm, about 200 μm to about 400 μm, or about 250 μm to about 300 μm. Also, as an example, the plurality of UBM padsmay be spaced apart from each other, and the metal bumpmay be in direct contact with the insulating layerexposed between the UBM pads. Also, like the UBM vias, the arrangement shape of the UBM padswithin the perimeterR of the metal bumpis not limited to the shape illustrated in the drawings.

150 140 143 2 143 150 143 143 2 143 150 143 150 150 143 2 143 150 143 The metal bumpis disposed on the UBM structure, and may contact the second surfaceSof the UBM pad. For example, the metal bumpmay be disposed on the plurality of UBM padsforming a group, and may contact the second surfaceSof each of the plurality of UBM pads. The metal bumpmay include a low melting point metal, for example, tin (Sn) or an alloy (e.g., Sn—Ag—Cu) including tin (Sn). According to related devices, according to a reliability evaluation test such as a highly accelerated stress test (HAST) or the like, the surface of the UBM padmay be exposed from the metal bumpand may therefore be vulnerable to corrosion. However, according to an example embodiment, because the metal bumpcompletely covers the exposed surface (e.g., the second surfaceS) such that the UBM padis not exposed externally (i.e., outside the metal bump), the reliability of the UBM padmay be improved.

3 3 3 3 3 3 3 3 FIGS.A,B,C,D,E,F,G andH 2 FIG.A are cross-sectional views illustrating a manufacturing process of a semiconductor package according to example embodiments. The cross-sectional views may correspond to the area illustrated in.

3 FIG.A 111 112 111 120 120 130 111 120 111 111 111 111 112 114 113 111 130 111 1 1 114 112 a b a b a l b Referring to, a plurality of via holes VH penetrating through the insulating layerto expose a portion of the redistribution conductormay be formed. The insulating layermay be formed on the active surface of the semiconductor chip. The side surface and the inactive surface opposite to the active surface of the semiconductor chipare sealed by the encapsulant, on a tape carrier, and the insulating layermay be formed on the active surface of the semiconductor chipfrom which the tape carrier has been removed. In the insulating layer, a first insulating layerand a second insulating layermay be sequentially formed. For example, after the first insulating layeris formed, the redistribution conductorincluding the redistribution seed layerand the via portionmay be formed, and the second insulating layercovering the same may be formed. The tape carrier may include an adhesive tape that loses adhesiveness thereof by Ultraviolet (UV) irradiation. The encapsulantmay be formed by applying a molding material, such as EMC, and then curing the molding material. The first and second insulating layersandmay be formed by, for example, coating and curing PID, and the redistribution seed layerand the redistribution conductormay be formed using a photolithography process, a plating process, an etching process, or the like. The plurality of via holes VH may be formed by a photolithography process including an exposure process, a developing process and the like. The plurality of via holes VH illustrated in the drawings may be understood as formation positions of a UBM structure group connected to one metal bump.

3 FIG.B 141 111 141 110 141 141 b Referring to, a preliminary seed layer′ extending along the upper surface of the second insulating layerand inner surfaces of the via holes VH may be formed. The preliminary seed layer′ may be formed by depositing a metal material, for example, titanium (Ti), copper (Cu), or the like, along the front surfaceFS. The preliminary seed layer′ may be formed using a process such as electroless plating, chemical vapor deposition (CVD), or physical vapor deposition (PVD). The preliminary seed layer′ may be formed using, for example, a sputtering process.

3 FIG.C 141 141 Referring to, a photoresist layer PR may be formed on the preliminary seed layer′. The photoresist layer PR may be formed by coating and curing a photoimageable resin on the preliminary seed layer′. The photoresist layer PR may be formed using, for example, a positive-type photoresist.

3 FIG.D 3 FIG.C 1 1 141 141 141 141 1 Referring to, a first photoresist layer PRmay be formed using a photolithography process. The photolithography process may include an exposure process, a developing process, a cleaning process, and the like. The first photoresist layer PRmay expose a partial surfaceES of the preliminary seed layer′ covering the inner surfaces of the via holes VH. The partial surfaceES of the preliminary seed layer′ may be exposed by removing a partial region ERof the photoresist layer (e.g., PR in) by a photolithography process.

3 FIG.E 142 141 141 1 142 142 1 142 142 141 Referring to, the UBM viamay be formed on the partial surfaceES of the preliminary seed layer′ exposed by the first photoresist layer PR. The UBM viamay be formed using, for example, an electroplating process such that a metal material is provided in, and for example may fill, the inside of the via holes VH. A formation region of the UBM viamay be limited by the first photoresist layer PR. The UBM viamay be formed of, for example, a metal material such as copper (Cu) or an alloy including the same. The upper surface of the UBM viamay be formed to be positioned on a level similar to the upper surface of the preliminary seed layer′.

3 FIG.F 3 FIG.E 2 2 141 141 110 111 141 141 2 1 b Referring to, a second photoresist layer PRmay be formed using a photolithography process. The second photoresist layer PRmay expose a partial surfaceUS of the preliminary seed layer′ extending along the front surfaceFS of the second insulating layer. The partial surfaceUS of the preliminary seed layer′ may be exposed by removing a partial region ERof the first photoresist layer (e.g., PRin) by a photolithography process.

3 FIG.G 3 FIG.F 3 FIG.F 3 FIG.F 143 142 141 141 2 143 142 141 141 143 143 1 142 141 141 143 2 143 1 143 2 143 Referring to, a UBM padmay be formed on the UBM viaand the partial surface (e.g.,US in) of the preliminary seed layer′ exposed by the second photoresist layer PR. The UBM padmay be formed, for example, using an electroless plating process, in such a manner that a metal material protrudes convexly from the UBM viaand the partial surface (e.g.,US in) of the preliminary seed layer′. For example, the UBM padmay be formed to have a first surfaceSin contact with the UBM viaand the partial surface (e.g.,US e.g., in) of the preliminary seed layer′, and a second surfaceScurves away from the first surfaceS. A formation area of the UBM padmay be limited by the second photoresist layer PR. The UBM padmay be formed of, for example, a metal material such as copper (Cu) or an alloy containing the same.

3 FIG.H 3 FIG.G 3 FIG.G 3 FIG.G 1 FIG. 2 3 141 140 141 142 143 3 141 140 140 140 140 150 143 2 143 Referring to, by removing a second photoresist layer (e.g., PRin) and a partial region ERof the preliminary seed layer (e.g.,in), UBM structuresincluding a seed layer, a UBM via, and a UBM padmay be completed. For example, by removing the partial region ERof the seed layer (e.g.,in), the UBM structuresmay be spaced apart from each other. According to an example embodiment, the UBM structuresmay also be formed to be connected to each other. Thereafter, an SBA process of attaching a solder ball on the UBM structuresmay be performed, and the solder ball is attached on the UBM structuresto form a metal bump (e.g.,in) 0 completely covering the second surfacesSof the UBM pads.

4 FIG. 100 a is a cross-sectional view illustrating a semiconductor packageaccording to an example embodiment.

4 FIG. 1 2 FIGS.toB 100 100 140 100 140 150 141 143 140 143 143 143 2 150 143 142 150 143 2 143 a a a a a Referring to, the semiconductor packageaccording to an example embodiment may have the same or similar characteristics as the semiconductor packageof, except that at least some of the UBM structuresare connected to each other. For example, the semiconductor packagemay include a plurality of UBM structurescorresponding to one metal bump, and a seed layerand a UBM padof each of the UBM structuresmay be connected to each other. The UBM padsconnected to each other may be integrated along edge portions of each of the UBM pads, and may each have a second surfaceShaving a convex embossing shape toward the metal bump. The integrated UBM padsmay have a shape having a maximum thickness at central portions overlapping the corresponding UBM vias, respectively. Accordingly, the metal bumpmay be formed to completely cover the second surfaceSof the integrated UBM pads.

5 5 FIGS.A andB 5 FIG.B 5 FIG.A 100 b are cross-sectional views illustrating a semiconductor packageaccording to an example embodiment.is a plan view of the area illustrated in.

5 5 FIGS.A andB 1 4 FIGS.to 5 FIG.B 2 FIG.B 100 140 142 142 150 150 143 142 140 143 150 150 143 143 140 140 143 b b b b b Referring to, the semiconductor packageaccording to an example embodiment may have the same or similar characteristics as those of the semiconductor packages illustrated in, except that UBM structuresinclude UBM viashaving substantially the same diameter Db. For example, the UBM viashaving substantially the same diameter Db may be arranged in various shapes within the perimeterR of the metal bumpin contact with the UBM pads. In this case, the “same diameter Db” indicates that the diameters of the UBM viasare not intentionally formed differently, and may be understood as including a difference due to a process error or the like. As an example, the UBM structuresmay be arranged, as illustrated in, in such a manner that some of the UBM padsare disposed in a round shape along the perimeterR of the metal bump, and the remaining UBM padsare located inside some of the UBM padsdisposed in a circle. However, the arrangement of the UBM structuresis not limited thereto, and as described with reference to, the arrangement form of the UBM structuresor the UBM padsmay be variously modified.

6 FIG. 100 c is a cross-sectional view illustrating a semiconductor packageaccording to an example embodiment.

6 FIG. 1 2 FIGS.toB 100 140 150 150 143 140 150 150 140 140 150 143 140 c c c c c c Referring to, the semiconductor packageof an example embodiment may have the same or similar characteristics as the semiconductor package of, except that a single UBM structureis provided for each metal bump. For example, the metal bumpmay be formed to completely cover the surface of the single UBM padprovided in one UBM structure. For example, when forming the fine-pitch metal bump, the metal bumpand the UBM structuremay be matched one-to-one. In this case, the width of the UBM structuremay be secured, and because the metal bumpcovers the entire upper surface of the UBM pad, the reliability of the UBM structuremay be improved.

7 FIG. 100 is a cross-sectional view illustrating a semiconductor packageB according to an example embodiment.

7 FIG. 1 6 FIGS.to 100 110 120 110 120 122 140 143 110 110 150 143 Referring to, the semiconductor packageB according to an example embodiment may have the same or similar characteristics as those of the semiconductor packages of, except including a redistribution structureformed in a fan-in region. In this case, the fan-in region refers to a region overlapping the semiconductor chipalong a vertical direction. For example, the redistribution structuremay be formed only below the active surface of the semiconductor chipon which the connection padis disposed. Also, the UBM structureor the UBM padmay convexly protrude from the front surfaceFS of the redistribution structure, and the metal bumpmay fully cover the exposed surface of the UBM pad.

8 FIG. 100 is a cross-sectional view illustrating a semiconductor packageC according to an example embodiment.

8 FIG. 1 7 FIGS.to 100 120 110 120 110 110 110 Referring to, the semiconductor packageC according to an example embodiment may have the same or similar characteristics as those of the semiconductor packages of, except that the semiconductor chipis electrically connected to the redistribution structurethrough a connection memberB. In an example embodiment, the redistribution structuremay be a substrate for a semiconductor package, including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring board, or the like. The redistribution structuremay have a shape different from that illustrated in the drawings depending on the type of the substrate. For example, when the redistribution structureis a printed circuit board, the board may have a form in which a wiring layer is additionally stacked on a copper clad stack plate, or on one side or both surfaces of the copper clad stack plate.

120 110 120 110 110 122 120 112 120 112 112 110 120 110 120 110 120 110 110 122 120 112 For example, the semiconductor chipmay be mounted on the redistribution structureby a flip-chip bonding method. The semiconductor chipis spaced apart from the rear surfaceBS of the redistribution structure, and the connection padof the semiconductor chipmay be electrically connected to the redistribution conductorthrough a connection memberB such as a solder ball or the like. The redistribution conductormay further include a bump padP exposed on the rear surfaceBS. In some example embodiments, an underfill resin may be formed between the semiconductor chipand the redistribution structure. Also, according to an example embodiment, the semiconductor chipmay be mounted on the redistribution structurein a wire bonding method. In this case, the semiconductor chipmay be attached on the rear surfaceBS of the redistribution structurein a face-up form, and the connection padof the semiconductor chipmay be electrically connected to the redistribution conductorthrough a bonding wire.

As set forth above, according to example embodiments, a semiconductor package having improved reliability may be provided by introducing a UBM pad having a rounded surface.

While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the appended claims.