Memory Devices with a Lower Effective Program Verify Level

This application is a Continuation of U.S. application Ser. No. 18/234,429, titled “MEMORY DEVICES WITH A LOWER EFFECTIVE PROGRAM VERIFY LEVEL,” filed Aug. 16, 2023 (allowed), which is commonly assigned and incorporated herein by reference in its entirety and which claims the benefit of U.S. Provisional Application No. 63/402,497, filed on Aug. 31, 2022, hereby incorporated herein in its entirety by reference.

The present disclosure relates generally to memory and, in particular, in one or more embodiments, the present disclosure relates to lowering a program verify voltage level below the minimum negative voltage source available within a memory device.

Memories (e.g., memory devices) are typically provided as internal, semiconductor, integrated circuit devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

Flash memory has developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data state (e.g., data value) of each memory cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.

A NAND flash memory is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series between a pair of select gates, e.g., a source select transistor and a drain select transistor. Each source select transistor may be connected to a source, while each drain select transistor may be connected to a data line, such as column bit line. Variations using more than one select gate between a string of memory cells and the source, and/or between the string of memory cells and the data line, are known.

In programming memory, memory cells may generally be programmed as what are often termed single-level cells (SLC) or multiple-level cells (MLC). SLC may use a single memory cell to represent one digit (e.g., bit) of data. For example, in SLC, a Vt of 2.5V might indicate a programmed memory cell (e.g., representing a logical 0) while a Vt of −0.5V might indicate an erased cell (e.g., representing a logical 1). As an example, the erased state in SLC might be represented by any threshold voltage less than or equal to 0V, while the programmed data state might be represented by any threshold voltage greater than 0V.

MLC uses more than two Vt ranges, where each Vt range indicates a different data state. As is generally known, a margin (e.g., a certain number of volts), such as a dead space, may separate adjacent Vt ranges, e.g., to facilitate differentiating between data states. Multiple-level cells can take advantage of the analog nature of traditional non-volatile memory cells by assigning a bit pattern to a specific Vt range. While MLC typically uses a memory cell to represent one data state of a binary number of data states (e.g., 4, 8, 16, . . . ), a memory cell operated as MLC may be used to represent a non-binary number of data states. For example, where the MLC uses three Vt ranges, two memory cells might be used to collectively represent one of eight data states.

In programming MLC memory, data values are often programmed using more than one pass, e.g., programming one or more digits in each pass. For example, in four-level MLC (typically referred to simply as MLC), a first digit, e.g., a least significant bit (LSB), often referred to as lower page (LP) data, may be programmed to the memory cells in a first pass, thus resulting in two (e.g., first and second) threshold voltage ranges. Subsequently, a second digit, e.g., a most significant bit (MSB), often referred to as upper page (UP) data may be programmed to the memory cells in a second pass, typically moving some portion of those memory cells in the first threshold voltage range into a third threshold voltage range, and moving some portion of those memory cells in the second threshold voltage range into a fourth threshold voltage range. Similarly, eight-level MLC (typically referred to as TLC) may represent a bit pattern of three bits, including a first digit, e.g., a least significant bit (LSB) or lower page (LP) data; a second digit, e.g., upper page (UP) data; and a third digit, e.g., a most significant bit (MSB) or extra page (XP) data. In operating TLC, the LP data may be programmed to the memory cells in a first pass, resulting in two threshold voltage ranges, followed by the UP data and the XP data in a second pass, resulting in eight threshold voltage ranges. Similarly, sixteen-level MLC (typically referred to as QLC) may represent a bit pattern of four bits, and 32-level MLC (typically referred to as PLC) may represent a bit pattern of five bits.

A read window, which may be referred to as a read window width, refers to a distance (e.g., in voltage) between adjacent Vt distributions at a particular bit error rate (BER). A read window budget (RWB) may refer to a cumulative value of read windows for a group of programmed cells (e.g., one or more pages of cells). For example, TLC memory cells configured to store three bits of data per cell may be programmed to one of eight different Vt distributions, each corresponding to a respective data state. In this example, the RWB may be the cumulative value (e.g., in voltage) of the seven read windows between the eight Vt distributions.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like reference numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.

The term “semiconductor” used herein can refer to, for example, a layer of material, a wafer, or a substrate, and includes any base semiconductor structure. “Semiconductor” is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a semiconductor in the following description, previous process steps might have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor can include the underlying layers containing such regions/junctions.

The term “conductive” as used herein, as well as its various related forms, e.g., conduct, conductively, conducting, conduction, conductivity, etc., refers to electrically conductive unless otherwise apparent from the context. Similarly, the term “connecting” as used herein, as well as its various related forms, e.g., connect, connected, connection, etc., refers to electrically connecting unless otherwise apparent from the context.

Ranges might be expressed herein as from “about” one particular value, and/or to “about” another particular value. When such a range is expressed, another embodiment might include from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms another embodiment. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.

It is recognized herein that even where values might be intended to be equal, variabilities and accuracies of industrial processing and operation might lead to differences from their intended values. These variabilities and accuracies will generally be dependent upon the technology utilized in fabrication and operation of the integrated circuit device. As such, if values are intended to be equal, those values are deemed to be equal regardless of their resulting values.

3 7 FIGS.- 0 1 2 0 15 As will be described in more detail below with reference to, in programming MLC memory, data values may be programmed using a coarse programming pass (with lower corresponding program verify levels) of a multiple pass programing operation followed by a fine programming pass (with higher corresponding program verify levels) of the multiple pass programming operation. In the coarse programming pass, the memory cells may be programmed to coarse (e.g., broader) target levels (e.g., threshold voltages). In the fine programming pass, the memory cells may be programmed to fine (e.g., narrower) target levels, which may be the final target levels for the memory cells. The target levels may include an erased Llevel and any number of programed levels L, L, etc. For example, the target levels for QLC memory may include 16 target levels Lto L. With a first page of memory cells (e.g., memory cells connected to a common first word line) programmed to their coarse target levels, an adjacent second page of memory cells (e.g., memory cells connected to a common second word line), which is currently erased, may be programmed to their coarse target levels. Next, the first page of memory cells may be programmed to their fine target levels. A third page of memory cells (e.g., memory cells connected to a common third word line), which is currently erased, adjacent to the second page of memory cells may then be programmed to their coarse target levels. With the third page of memory cells programmed to their coarse target levels, the second page of memory cells may be programmed to their fine target levels and the programming process may continue until all desired pages of the selected memory block have been programmed to their fine target levels. The coarse programming pass followed by the fine programming pass as described above compensates for word line-to-word line interference (e.g., cell-to-cell coupling) in the vertical direction of a three-dimensional NAND memory array.

1 1 1 1 1 1 C F C C Data retention of a NAND memory array (e.g., a three-dimensional NAND memory array) strongly depends on the electric field in the memory cell. Hence, data retention depends on the difference between the programmed threshold voltage Vt of the memory cell and the ultraviolet threshold voltage UVVt (e.g., natural threshold voltage) of the memory cell. Tier-pitch scaling (e.g., arranging the tiers [e.g., word line and memory cell layers] closer together) within three-dimensional NAND memory lowers the UVVt due to the short-channel effect, and no effective process to raise the UVVt back up is known. Therefore, the operating window should be shifted down with tier-pitch scaling to avoid excessive degradation of data retention. Shifting down the operating window may be achieved by extending the negative capability of read voltages for each technology node. In each technology node, the negative capability of read voltages for QLC might be more beneficial than for TLC because of the larger window for QLC. In any case, the most beneficial trim might be the coarse program verify for level L(PV). With tier-pitch scaling, not only should the fine program verify for level L(PV) shift down because of data retention, but PVshould be shifted down even more. Because of the degradation of cell-to-cell (C2C) interference, a larger program verify offset might be used between the coarse program verify and the fine program verify. The program verify operations disclosed herein enable a negative read voltage of NAND memory (e.g., QLC NAND memory) less than the minimum negative voltage source available within the NAND memory by lowering the effective PVby 500-700 mV, for example, depending upon the characteristics of the memory cell.

1 0 0 1 C 1R R 1R 1R 1R R C This disclosure leverages word line-to-cell (WL2C) coupling to shift down the effective PVduring a program verify operation by lowering a pass voltage VPASSapplied to the unselected word line adjacent to the selected word line (e.g., drain-side word line connected to an Lerased memory cell), while a higher pass voltage VPASSis applied to the other unselected word lines. The VPASSvoltage level is limited by the overdrive of Lerased cells connected to the adjacent word line. In some examples, voltage levels as low as about 2V may safely be used for VPASS. For example, with a 10% WL2C coupling, an about −5V VPASSreduction from VPASSwould effectively shift down PVby about 500 mV.

1 1 1 1 1 C C C 1R R C C The PVshift depends on the cell revision and technology node, since the effective PVis a function of WL2C. This is not a serious limitation, however, since a lower effective PVis required in the case of larger C2C, which is typically correlated with a larger WL2C, as both mechanisms are related to the WL-to-channel control. Therefore, for a given VPASSreduction from VPASS, the PVshift is larger in cell revisions or technology nodes actually requiring a lower effective PV.

1R C 1R C C C 1 1 1 2 1 1 1 VPASSmight be provided by a dedicated, trimmable, voltage source. The voltage source might have a range between 0V and about 7V with about 100 mV resolution. If a dedicated voltage source is not available or is cost prohibitive, Vcc could be used to apply a fixed 500-700 mV shift. Contrary to using a dedicated voltage source ranging from 0V to about 7V, using Vcc might limit the maximum PVshift to about (VPASS−Vcc)*WL2C. To overcome this limitation, GND could be used instead of Vcc. GND might work for very negative windows, with an erased distribution significantly below −2V. For this reason, the GND option might be used in combination with Vcc, and a 2-bit trim may be used to select among Vcc, GND, and neither Vcc nor GND. If either Vcc or GND is used, a dedicated program verify offset for level Lmight be used, since the program verify offset is typically shared between Land Lin QLC memory arrays, conflicting with a shift applied solely to PV. A trim value may be added to the memory device to enable or disable the shift in PVto push the effective PVlower than the minimum negative read voltage.

1R R 1R 1 1 1 VPASSmay be significantly lower than VPASSduring a coarse program verify operation for level L, since the adjacent access line is erased during the first program pass. For example, with a WL2C of about 12.5%, lowering the VPASSof the adjacent access line from 6.5V to 2.5V saves about 500 mV of negative voltage. That is, the same Vt placement can be achieved with a program verify voltage level 500 mV higher. The program verify process disclosed herein might scale well to future nodes, since the shift depends on WL2C, so the more scaled the tier pitch, the larger the shift. As for the cell-by-cell variability of WL2C, a small widening of the Ldistribution after the coarse programming step may be observed. This, however, is irrelevant because the coarse state is not read in QLC, and no degradation can be measured in Lafter fine programming.

1R 1R 1 2 3 While the following description discloses the use of VPASSduring a coarse program verify operation for level L, in other embodiments, VPASSmay also be used during a coarse program verify operation for higher levels (e.g., L, L, etc.).

1 FIG. 100 130 130 100 is a simplified block diagram of a first apparatus, in the form of a memory (e.g., memory device), in communication with a second apparatus, in the form of a processor, as part of a third apparatus, in the form of an electronic system, according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and the like. The processor, e.g., a controller external to the memory device, might be a memory controller or other external host device.

100 104 104 1 FIG. Memory deviceincludes an array of memory cellsthat might be logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line) while memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). A single access line might be associated with more than one logical row of memory cells and a single data line might be associated with more than one logical column. Memory cells (not shown in) of at least a portion of array of memory cellsare capable of being programmed to one of at least two target data states.

108 110 104 100 112 100 100 114 112 108 110 124 112 116 A row decode circuitryand a column decode circuitryare provided to decode address signals. Address signals are received and decoded to access the array of memory cells. Memory devicealso includes input/output (I/O) control circuitryto manage input of commands, addresses and data to the memory deviceas well as output of data and status information from the memory device. An address registeris in communication with I/O control circuitryand row decode circuitryand column decode circuitryto latch the address signals prior to decoding. A command registeris in communication with I/O control circuitryand control logicto latch incoming commands.

116 100 104 130 116 104 116 108 110 108 110 116 128 128 128 104 A controller (e.g., the control logicinternal to the memory device) controls access to the array of memory cellsin response to the commands and may generate status information for the external processor, i.e., control logicis configured to perform access operations (e.g., sensing operations [which might include read operations and verify operations], programming operations and/or erase operations) on the array of memory cells. The control logicis in communication with row decode circuitryand column decode circuitryto control the row decode circuitryand column decode circuitryin response to the addresses. The control logicmight include instruction registerswhich might represent computer-usable memory for storing computer-readable instructions. For some embodiments, the instruction registersmight represent firmware. Alternatively, the instruction registersmight represent a grouping of memory cells, e.g., reserved block(s) of memory cells, of the array of memory cells.

116 118 118 116 104 118 120 104 118 112 118 112 130 120 118 118 120 100 104 122 112 116 130 1 FIG. Control logicmight also be in communication with a cache register. Cache registerlatches data, either incoming or outgoing, as directed by control logicto temporarily store data while the array of memory cellsis busy writing or reading, respectively, other data. During a programming operation (e.g., write operation), data might be passed from the cache registerto the data registerfor transfer to the array of memory cells; then new data might be latched in the cache registerfrom the I/O control circuitry. During a read operation, data might be passed from the cache registerto the I/O control circuitryfor output to the external processor; then new data might be passed from the data registerto the cache register. The cache registerand/or the data registermight form (e.g., might form a portion of) a page buffer of the memory device. A page buffer might further include sensing devices (not shown in) to sense a data state of a memory cell of the array of memory cells, e.g., by sensing a state of a data line connected to that memory cell. A status registermight be in communication with I/O control circuitryand control logicto latch the status information for output to the processor.

100 116 130 132 132 100 100 130 134 130 134 Memory devicereceives control signals at control logicfrom processorover a control link. The control signals might include a chip enable CE #, a command latch enable CLE, an address latch enable ALE, a write enable WE #, a read enable RE #, and a write protect WP #. Additional or alternative control signals (not shown) might be further received over control linkdepending upon the nature of the memory device. Memory devicereceives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from processorover a multiplexed input/output (I/O) busand outputs data to processorover I/O bus.

134 112 124 134 112 114 112 118 120 104 118 120 100 130 For example, the commands might be received over input/output (I/O) pins [7:0] of I/O busat I/O control circuitryand might then be written into command register. The addresses might be received over input/output (I/O) pins [7:0] of I/O busat I/O control circuitryand might then be written into address register. The data might be received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitryand then might be written into cache register. The data might be subsequently written into data registerfor programming the array of memory cells. For another embodiment, cache registermight be omitted, and the data might be written directly into data register. Data might also be output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device. Although reference might be made to I/O pins, they might include any conductive nodes providing for electrical connection to the memory deviceby an external device (e.g., processor), such as conductive pads or conductive bumps as are commonly used.

100 1 FIG. 1 FIG. 1 FIG. 1 FIG. It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory deviceofhas been simplified. It should be recognized that the functionality of the various block components described with reference tomight not necessarily be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device could be adapted to perform the functionality of more than one block component of. Alternatively, one or more components or component portions of an integrated circuit device could be combined to perform the functionality of a single block component of.

Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins (or other I/O node structures) might be used in the various embodiments.

2 FIG.A 1 FIG. 2 FIG.A 200 104 200 202 202 204 204 202 200 0 N 0 M is a schematic of a portion of an array of memory cellsA, such as a NAND memory array, as could be used in a memory of the type described with reference to, e.g., as a portion of array of memory cells. Memory arrayA includes access lines (e.g., word lines)to, and data lines (e.g., bit lines)to. The access linesmight be connected to global access lines (e.g., global word lines), not shown in, in a many-to-one relationship. For some embodiments, memory arrayA might be formed over a semiconductor that, for example, might be conductively doped to have a conductivity type, such as a p-type conductivity, e.g., to form a p-well, or an n-type conductivity, e.g., to form an n-well.

200 202 204 206 206 206 216 208 208 208 208 208 0 M 0 N 0 N Memory arrayA might be arranged in rows (each corresponding to an access line) and columns (each corresponding to a data line). Each column might include a string of series-connected memory cells (e.g., non-volatile memory cells), such as one of NAND stringsto. Each NAND stringmight be connected (e.g., selectively connected) to a common source (SRC)and might include memory cellsto. The memory cellsmight represent non-volatile memory cells for storage of data. The memory cellstomight include memory cells intended for storage of data, and might further include other memory cells not intended for storage of data, e.g., dummy memory cells. Dummy memory cells are typically not accessible to a user of the memory, and are instead typically incorporated into the string of series-connected memory cells for operational advantages that are well understood.

208 206 210 210 210 212 212 212 210 210 214 212 212 215 210 212 208 210 212 0 M 0 M 0 M 0 M The memory cellsof each NAND stringmight be connected in series between a select gate(e.g., a field-effect transistor), such as one of the select gatesto(e.g., that might be source select transistors, commonly referred to as select gate source), and a select gate(e.g., a field-effect transistor), such as one of the select gatesto(e.g., that might be drain select transistors, commonly referred to as select gate drain). Select gatestomight be commonly connected to a select line, such as a source select line (SGS), and select gatestomight be commonly connected to a select line, such as a drain select line (SGD). Although depicted as traditional field-effect transistors, the select gatesandmight utilize a structure similar to (e.g., the same as) the memory cells. The select gatesandmight represent a plurality of select gates connected in series, with each select gate in series configured to receive a same or independent control signal.

210 216 210 208 206 210 208 206 210 206 216 210 214 0 0 0 0 A source of each select gatemight be connected to common source. The drain of each select gatemight be connected to a memory cellof the corresponding NAND string. For example, the drain of select gatemight be connected to memory cellof the corresponding NAND string. Therefore, each select gatemight be configured to selectively connect a corresponding NAND stringto common source. A control gate of each select gatemight be connected to select line.

212 204 206 212 204 206 212 208 206 212 208 206 212 206 204 212 215 0 0 0 N 0 N 0 The drain of each select gatemight be connected to the data linefor the corresponding NAND string. For example, the drain of select gatemight be connected to the data linefor the corresponding NAND string. The source of each select gatemight be connected to a memory cellof the corresponding NAND string. For example, the source of select gatemight be connected to memory cellof the corresponding NAND string. Therefore, each select gatemight be configured to selectively connect a corresponding NAND stringto the corresponding data line. A control gate of each select gatemight be connected to select line.

2 FIG.A 2 FIG.A 216 206 204 206 216 204 216 The memory array inmight be a quasi-two-dimensional memory array and might have a generally planar structure, e.g., where the common source, NAND stringsand data linesextend in substantially parallel planes. Alternatively, the memory array inmight be a three-dimensional memory array, e.g., where NAND stringsmight extend substantially perpendicular to a plane containing the common sourceand to a plane containing the data linesthat might be substantially parallel to the plane containing the common source.

208 234 236 234 236 208 230 232 208 236 202 2 FIG.A Typical construction of memory cellsincludes a data-storage structure(e.g., a floating gate, charge trap, or other structure configured to store charge) that can determine a data state of the memory cell (e.g., through changes in threshold voltage), and a control gate, as shown in. The data-storage structuremight include both conductive and dielectric structures while the control gateis generally formed of one or more conductive materials. In some cases, memory cellsmight further have a defined source/drain (e.g., source)and a defined source/drain (e.g., drain). Memory cellshave their control gatesconnected to (and in some cases form) an access line.

208 206 206 204 208 208 202 208 208 202 208 208 208 208 202 208 202 204 204 204 204 208 208 202 204 204 204 204 208 204 204 204 200 204 204 208 202 208 202 202 206 202 N 0 2 4 N 1 3 5 3 5 0 M 0 N 2 FIG.A A column of the memory cellsmight be a NAND stringor a plurality of NAND stringsselectively connected to a given data line. A row of the memory cellsmight be memory cellscommonly connected to a given access line. A row of memory cellscan, but need not, include all memory cellscommonly connected to a given access line. Rows of memory cellsmight often be divided into one or more groups of physical pages of memory cells, and physical pages of memory cellsoften include every other memory cellcommonly connected to a given access line. For example, memory cellscommonly connected to access lineand selectively connected to even data lines(e.g., data lines,,, etc.) might be one physical page of memory cells(e.g., even memory cells) while memory cellscommonly connected to access lineand selectively connected to odd data lines(e.g., data lines,,, etc.) might be another physical page of memory cells(e.g., odd memory cells). Although data lines-are not explicitly depicted in, it is apparent from the figure that the data linesof the array of memory cellsA might be numbered consecutively from data lineto data line. Other groupings of memory cellscommonly connected to a given access linemight also define a physical page of memory cells. For certain memory devices, all memory cells commonly connected to a given access line might be deemed a physical page of memory cells. The portion of a physical page of memory cells (which, in some embodiments, could still be the entire row) that is read during a single read operation or programmed during a single programming operation (e.g., an upper or lower page of memory cells) might be deemed a logical page of memory cells. A block of memory cells might include those memory cells that are configured to be erased together, such as all memory cells connected to access lines-(e.g., all NAND stringssharing common access lines). Unless expressly distinguished, a reference to a page of memory cells herein refers to the memory cells of a logical page of memory cells.

2 FIG.A Although the example ofis discussed in conjunction with NAND flash, the embodiments and concepts described herein are not limited to a particular array architecture or structure, and can include other structures (e.g., SONOS or other data storage structure configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

2 FIG.B 1 FIG. 2 FIG.B 2 FIG.A 2 FIG.B 200 104 200 206 206 204 204 212 216 210 206 204 206 204 215 215 212 206 204 210 214 202 200 202 0 M 0 K is another schematic of a portion of an array of memory cellsB as could be used in a memory of the type described with reference to, e.g., as a portion of array of memory cells. Like numbered elements incorrespond to the description as provided with respect to.provides additional detail of one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory arrayB might incorporate vertical structures which might include semiconductor pillars where a portion of a pillar might act as a channel region of the memory cells of NAND strings. The NAND stringsmight be each selectively connected to a data linetoby a select transistor(e.g., that might be drain select transistors, commonly referred to as select gate drain) and to a common sourceby a select transistor(e.g., that might be source select transistors, commonly referred to as select gate source). Multiple NAND stringsmight be selectively connected to the same data line. Subsets of NAND stringscan be connected to their respective data linesby biasing the select linestoto selectively activate particular select transistorseach between a NAND stringand a data line. The select transistorscan be activated by biasing the select line. Each access linemight be connected to multiple rows of memory cells of the memory arrayB. Rows of memory cells that are commonly connected to each other by a particular access linemight collectively be referred to as tiers.

200 226 226 200 226 226 The three-dimensional NAND memory arrayB might be formed over peripheral circuitry. The peripheral circuitrymight represent a variety of circuitry for accessing the memory arrayB. The peripheral circuitrymight include complementary circuit elements. For example, the peripheral circuitrymight include both n-channel and p-channel transistors formed on a same semiconductor substrate, a process commonly referred to as CMOS, or complementary metal-oxide-semiconductors. Although CMOS often no longer utilizes a strict metal-oxide-semiconductor construction due to advancements in integrated circuit fabrication and design, the CMOS designation remains as a matter of convenience.

2 FIG.C 1 FIG. 2 FIG.C 2 FIG.A 2 FIG.A 2 FIG.C 200 104 200 206 202 204 214 215 216 200 200 206 250 250 250 250 208 250 206 215 215 216 250 216 250 250 250 216 202 214 215 250 202 214 215 250 250 0 L 0 0 L 0 L 0 L is a further schematic of a portion of an array of memory cellsC as could be used in a memory of the type described with reference to, e.g., as a portion of array of memory cells. Like numbered elements incorrespond to the description as provided with respect to. Array of memory cellsC may include strings of series-connected memory cells (e.g., NAND strings), access (e.g., word) lines, data (e.g., bit) lines, select lines(e.g., source select lines), select lines(e.g., drain select lines) and sourceas depicted in. A portion of the array of memory cellsA may be a portion of the array of memory cellsC, for example.depicts groupings of NAND stringsinto blocks of memory cells, e.g., blocks of memory cellsto. Blocks of memory cellsmay be groupings of memory cellsthat may be erased together in a single erase operation, sometimes referred to as erase blocks. Each block of memory cellsmight include those NAND stringscommonly associated with a single select line, e.g., select line. The sourcefor the block of memory cellsmight be a same source as the sourcefor the block of memory cells. For example, each block of memory cellstomight be commonly selectively connected to the source. Access linesand select linesandof one block of memory cellsmay have no direct connection to access linesand select linesand, respectively, of any other block of memory cells of the blocks of memory cellsto.

204 204 240 240 250 250 240 204 0 M 0 L 2 FIG.C The data linestomay be connected (e.g., selectively connected) to a buffer portion, which might be a portion of a data buffer of the memory. The buffer portionmight correspond to a memory plane (e.g., the set of blocks of memory cellsto). The buffer portionmight include sense circuits (not shown in) for sensing data values indicated on respective data lines.

250 215 250 250 206 215 215 250 215 200 200 206 215 215 250 206 215 206 215 240 215 2 FIG.C 2 FIG.B 2 FIG.C 2 FIG.B 0 0 0 1 K While the blocks of memory cellsofdepict only one select lineper block of memory cells, the blocks of memory cellsmight include those NAND stringscommonly associated with more than one select line. For example, select lineof block of memory cellsmight correspond to the select lineof the memory arrayB of, and the block of memory cells of the memory arrayC ofmight further include those NAND stringsassociated with select linestoof. In such blocks of memory cellshaving NAND stringsassociated with multiple select lines, those NAND stringscommonly associated with a single select linemight be referred to as a sub-block of memory cells. Each such sub-block of memory cells might be selectively connected to the buffer portionresponsive to its respective select line.

3 FIG. 3 FIG. 4 6 FIGS.- 300 0 15 depicts memory cell populationsfor a QLC memory after coarse programming according to an embodiment. For simplicity,and the followingwill presume programming operations for QLC memory cells, e.g., sixteen-level memory cells representing data states Lto Lusing sixteen threshold voltage ranges, each representing a data state corresponding to a bit pattern of four digits. While discussed in reference to QLC memory cells, programming operations performed on lower storage density memory cells, e.g., TLC (eight data states) or higher storage density memory cells, e.g., PLC (32 data states) memory cells, are equally applicable.

310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 In this example, the population of memory cellsmight be erased memory cells and represent a logical data value of ‘1111’, the population of memory cellsmight represent a logical data value of ‘0111’, the population of memory cellsmight represent a logical data value of ‘0011’, the population of memory cellsmight represent a logical data value of ‘1011’, the population of memory cellsmight represent a logical data value of ‘1001’, the population of memory cellsmight represent a logical data value of ‘0001’, the population of memory cellsmight represent a logical data value of ‘0101’, the population of memory cellsmight represent a logical data value of ‘1101’, the population of memory cellsmight represent a logical data value of ‘1100’, the population of memory cellsmight represent a logical data value of ‘0100’, the population of memory cellsmight represent a logical data value of ‘0000’, the population of memory cellsmight represent a logical data value of ‘1000’, the population of memory cellsmight represent a logical data value of ‘1010’, the population of memory cellsmight represent a logical data value of ‘0010’, the population of memory cellsmight represent a logical data value of ‘0110’, and the population of memory cellsmight represent a logical data value of ‘1110’ where the right-most digit might represent the lower page data for a memory cell having a threshold voltage within the threshold voltage range of its respective population of memory cells, the center-right digit might represent the upper page data for that memory cell, the center-left digit might represent the extra page data for that memory cell, and the left-most digit might represent the top page data for that memory cell. Although a specific example of binary representation is provided, embodiments may use other arrangements of bit patterns to represent the various data states.

310 311 330 0 1 300 311 312 331 1 2 312 324 313 325 332 344 2 15 330 344 A preliminary read window between the population of memory cellsand the population of memory cellsis indicated at, which is the distance (e.g., in voltage) between adjacent Vt distributions for the memory cells representing data states Land L. The read window is preliminary since the populations of memory cellsprogrammed to coarse target values are not read. A preliminary read window between the population of memory cellsand the population of memory cellsis indicated at, which is the distance (e.g., in voltage) between adjacent Vt distributions for the memory cells representing data states Land L. Likewise, a preliminary read window between the population of memory cellsto, and the population of memory cellstois indicated atto, respectively, which is the distance between adjacent Vt distributions for the memory cells representing data states Lto L. A read window budget (RWB) may refer to a cumulative value of read windows for a group of programmed cells (e.g., one or more pages of cells). In this example, the preliminary RWB may be the cumulative value (e.g., in voltage) of the fifteen read windowstobetween the sixteen Vt distributions.

4 FIG. 3 FIG. 2 FIG.A 0 15 0 202 236 208 1 2 1 2 1 1 2 is a timing diagram depicting a portion of a coarse programming operation to program selected QLC memory cells to coarse target levels Lto L(e.g., as illustrated in) according to an embodiment. Once a selected memory cell has been programmed to its coarse target level, the memory cell is inhibited from further coarse programming. Prior to time t, memory cells selected for programming might be erased such that the selected memory cells each have a threshold voltage corresponding to level L. At time t, a first program pulse may be applied to a selected access line (e.g.,of) connected to the control gates (e.g.,) of the selected memory cells (e.g.,). After the first program pulse, a coarse program verify operation may be performed to verify whether a target population of the selected memory cells has been programmed to coarse level Lor L. At time t, a second program pulse, e.g., higher than the first program pulse, may be applied to the selected access line connected to the control gates of the selected memory cells. After the second program pulse, a coarse program verify operation may be performed to verify whether target populations of the selected memory cells have been programmed to coarse level Lor L.

3 4 5 1 2 3 2 3 4 2 3 4 5 At time t, a third program pulse, e.g., higher than the second program pulse, may be applied to the selected access line connected to the control gates of the selected memory cells. After the third program pulse, a coarse program verify operation may be performed to verify whether target populations of the selected memory cells have been programmed to coarse level L, L, or L. At time t, a fourth program pulse, e.g., higher than the third program pulse, may be applied to the selected access line connected to the control gates of the selected memory cells. After the fourth program pulse, a coarse program verify operation may be performed to verify whether target populations of the selected memory cells have been programmed to coarse level L, L, or L. At time t, a fifth program pulse, e.g., higher than the fourth program pulse, may be applied to the selected access line connected to the control gates of the selected memory cells. After the fifth program pulse, a coarse program verify operation may be performed to verify whether target populations of the selected memory cells have been programmed to coarse level L, L, L, or L.

3 4 5 6 13 14 15 i−1 i At time to, a sixth program pulse, e.g., higher than the fifth program pulse, may be applied to the selected access line connected to the control gates of the selected memory cells. After the sixth program pulse, a coarse program verify operation may be performed to verify whether target populations of the selected memory cells have been programmed to coarse level L, L, L, or Land the programming pulses and coarse program verify operations continue. At time t, another program pulse, e.g., higher than the previous program pulse, may be applied to the selected access line connected to the control gates of the selected memory cells, where “i” is any suitable number. After the program pulse, a program verify operation may be performed to verify whether target populations of the selected memory cells have been programmed to coarse level L, L, or L. At time t, another program pulse, e.g., higher than the previous program pulse, may be applied to the selected access line connected to the control gates of the selected memory cells and the process may repeat until the selected memory cells have been programmed to their coarse target levels.

5 FIG. 3 FIG. 5 FIG. 500 510 525 310 325 310 325 510 511 530 0 1 511 512 531 1 2 512 524 513 525 532 544 2 15 520 544 500 300 depicts memory cell populationsfor a QLC memory after fine programming according to an embodiment. Populations of memory cellstocorrespond to populations of memory cellstoof, respectively, after the populations of memory cellstoare moved from the coarse target values to fine target values. A read window between the population of memory cellsand the population of memory cellsis indicated at, which is the distance (e.g., in voltage) between adjacent Vt distributions for the memory cells representing data states Land L. A read window between the population of memory cellsand the population of memory cellsis indicated at, which is the distance (e.g., in voltage) between adjacent Vt distributions for the memory cells representing data states Land L. Likewise, a read window between the population of memory cellsto, and the population of memory cellstois indicated atto, respectively, which is the distance between adjacent Vt distributions for the memory cells representing data states Lto L. In this example, the RWB may be the cumulative value (e.g., in voltage) of the fifteen read windowstobetween the sixteen Vt distributions. As shown in, the RWB for the populations of memory cellsafter fine programming is greater than the preliminary RWB for the populations of memory cellsafter coarse programming.

6 FIG. 5 FIG. 3 4 FIGS.and 2 FIG.A 0 15 202 236 208 1 2 1 2 1 1 2 is a timing diagram depicting a portion of a fine programming operation to program selected QLC memory cells to fine (e.g., final) target levels Lto L(e.g., as illustrated in) according to an embodiment. Once a selected memory cell has been programmed to its fine target level, the memory cell is inhibited from further programming. Prior to time t, the selected memory cells are programmed to their coarse target levels as illustrated in. In addition, a page of memory cells adjacent to the selected memory cells may have been programmed to their coarse target levels. At time t, a first program pulse may be applied to a selected access line (e.g.,of) connected to the control gates (e.g.,) of the selected memory cells (e.g.,). After the first program pulse, a fine program verify operation may be performed to verify whether a target population of the selected memory cells has been programmed to fine level Lor L. At time t, a second program pulse, e.g., higher than the first program pulse, may be applied to the selected access line connected to the control gates of the selected memory cells. After the second program pulse, a fine program verify operation may be performed to verify whether target populations of the selected memory cells have been programmed to fine level Lor L.

3 4 5 1 2 3 2 3 4 2 3 4 5 At time t, a third program pulse, e.g., higher than the second program pulse, may be applied to the selected access line connected to the control gates of the selected memory cells. After the third program pulse, a fine program verify operation may be performed to verify whether target populations of the selected memory cells have been programmed to fine level L, L, or L. At time t, a fourth program pulse, e.g., higher than the third program pulse, may be applied to the selected access line connected to the control gates of the selected memory cells. After the fourth program pulse, a fine program verify operation may be performed to verify whether target populations of the selected memory cells have been programmed to fine level L, L, or L. At time t, a fifth program pulse, e.g., higher than the fourth program pulse, may be applied to the selected access line connected to the control gates of the selected memory cells. After the fifth program pulse, a fine program verify operation may be performed to verify whether target populations of the selected memory cells have been programmed to fine level L, L, L, or L.

6 j−1 j 3 4 5 6 13 14 15 At time t, a sixth program pulse, e.g., higher than the fifth program pulse, may be applied to the selected access line connected to the control gates of the selected memory cells. After the sixth program pulse, a fine program verify operation may be performed to verify whether target populations of the selected memory cells have been programmed to fine level L, L, L, or Land the programming pulses and fine program verify operations continue. At time t, another program pulse, e.g., higher than the previous program pulse, may be applied to the selected access line connected to the control gates of the selected memory cells, where “j” is any suitable number. After the program pulse, a program verify operation may be performed to verify whether target populations of the selected memory cells have been programmed to fine level L, L, or L. At time t, another program pulse, e.g., higher than the previous program pulse, may be applied to the selected access line connected to the control gates of the selected memory cells and the process may repeat until the selected memory cells have been programmed to their fine target levels.

7 FIG. 2 FIG.A 700 702 202 200 208 206 704 202 706 202 208 206 704 202 202 202 202 X+2 X+2 0 X+1 X+3 X+3 0 0 X X+4 N is a timing diagramdepicting voltage levels applied to access lines of an array of memory cells during a coarse programming operation. Tracemay correspond to voltage levels applied to a first (e.g., selected) access line (e.g.,) of an array of memory cells (e.g.,A of) connected to a selected memory cell (e.g.,of NAND string). Tracemay correspond to voltage levels applied to a second (e.g., unselected) access line (e.g.,) adjacent to the first access line. Tracemay correspond to voltage levels applied to a third (e.g., unselected) access line (e.g.,) adjacent to the first access line and connected to an erased memory cell (e.g.,of NAND string). Tracemay also correspond to voltage levels applied to other unselected access lines (e.g.,toandto).

208 206 208 206 208 206 208 206 1 2 3 208 206 1 202 202 202 1 1 202 202 202 202 202 202 1 208 208 208 x+2 0 X+2 0 X+3 0 X+1 0 1 X+2 0 1 R 0 N 2 X+2 C 2 R 0 X+1 X+4 N 2 1R X+3 1R R X+3 X+2 X+3 2 3 X+2 4 FIG. Prior to programming the selected memory cellof NAND string, the selected memory cellof NAND stringmight be erased, the adjacent memory cellof NAND stringmight be erased, and the adjacent memory cellof NAND stringmight be programmed to a coarse target level. Prior to time t, a program pulse (e.g., program pulse,, orof) is applied to the selected access line to program the selected memory cellof NAND stringto coarse level L. At time t, a pass voltage VPASSis applied to all the access linesto. At time t, the selected access lineis biased to a coarse program verify level L(PV) (e.g., a first voltage level). Also at time t, the VPASSvoltage level (e.g., a second voltage level higher than the first voltage level) remains applied to access linestoandto. Also at time t, another pass voltage VPASS(e.g., a third voltage level between the first voltage level and the second voltage level) is applied to access line. By applying VPASSinstead of VPASSto access line, the effective coarse program verify for level Lis reduced due to capacitive coupling between the selected memory celland the adjacent memory cell. Between times tand t, the threshold voltage of the selected memory cellis sensed.

3 3 C X+2 C 3 R X+3 3 4 X+2 4 4 C X+2 C 4 R X+3 4 5 X+2 5 R X+2 0 N 1R C 1 2 2 2 202 1 202 208 2 3 3 3 202 2 202 208 1 2 3 202 202 202 1 1 3 6 FIGS.- At time t, the coarse program verify for level Lis complete and the coarse program verify for memory cells to be programmed to the coarse level Lbegins. At time t, a coarse program verify for level L(PV) is applied to the selected access line, which is higher than PV. Also at time t, VPASSis applied to the adjacent access line. Between times tand t, the threshold voltage of the selected memory cellis sensed. At time t, the coarse program verify for level Lis complete and the coarse program verify for memory cells to be programmed to the coarse level Lbegins. At time t, a coarse program verify for level L(PV) is applied to the selected access line, which is higher than PV. Also at time t, the VPASSvoltage level remains applied to the adjacent access line. Between times tand t, the threshold voltage of the selected memory cellis sensed. At time t, the coarse program verify operations for levels L, L, and Lare complete and VPASSis applied to the selected access line. At time to, 0V is applied to the access linestoand the programming process as previously described and illustrated with reference tocontinues. Accordingly, VPASSis applied to the adjacent access line during program verify operations for target memory cells to be programmed to the coarse level Lto effectively shift PVlower than the minimum negative voltage source of the memory device.

8 10 FIGS.A-D In the following, programming operations might proceed from the source-side to the drain-side. Accordingly, the target memory cell and the memory cells between the drain select transistor and the target memory cell for the selected string of series-connected memory cells might be in an erased state, while the memory cells between the target memory cell and the source select transistor for the selected string of series-connected memory cells might be in a programmed state.

8 8 FIGS.A-G 3 7 FIGS.- 8 8 FIG.A-G 1 FIG. 800 800 128 116 100 are flowcharts of a methodfor programming an array of memory cells in accordance with an embodiment. Methodmay correspond at least in part to. For example,might represent a method to perform a program operation, e.g., programming one or more memory cells to target levels. The method might be in the form of computer-readable instructions, e.g., stored to the instruction registersof. Such computer-readable instructions might be executed by a controller, e.g., the control logic, to cause the memory deviceto perform the method.

800 100 104 206 202 236 208 116 1 208 206 202 202 206 2 FIG.A X+1 0 X+1 0 Methodmight be implemented within a memory device (e.g.,) including an array of memory cells (e.g.,) including a plurality of strings (e.g.,) of series-connected memory cells, a plurality of access lines (e.g.,), where each access line is connected to a control gate (e.g.,) of a respective memory cell (e.g.,) of each string of series-connected memory cells, and a controller (e.g.,) configured to access the array of memory cells (e.g., TLC memory cells, QLC memory cells, or PLC memory cells) to program a selected memory cell of the array of memory cells to a first target level (e.g., coarse level L). The following discussion will be made with reference to at leastand will presume that the selected memory cell is the memory cellof NAND string. The access linemay be referred to as the selected access line as it contains the selected memory cell, while remaining access linesmay be referred to as unselected access lines. The NAND stringmay be referred to as the selected string of series-connected memory cells as it contains the selected memory cell.

8 FIG.A 7 FIG. 7 FIG. 7 FIG. 802 1 202 208 206 804 202 202 806 202 202 208 206 808 208 206 C X+1 X+1 0 R X X+1 1R X+2 X+1 X+2 0 X+1 0 As illustrated inat, the controller may apply a first voltage level (e.g., PVof) to a first access lineof the plurality of access lines connected to the selected memory cellof NAND string. At, the controller may apply a second voltage level (e.g., VPASSof) higher than the first voltage level to a second access lineof the plurality of access lines adjacent to the first access line. At, the controller may apply a third voltage level (e.g., VPASSof) between the first voltage level and the second voltage level to a third access lineof the plurality of access lines adjacent to the first access lineand connected to an erased memory cellof NAND string. At, the controller may sense a first threshold voltage of the selected memory cellof NAND string.

208 206 1 208 206 202 2 3 1 810 2 3 202 812 202 814 202 816 208 206 208 206 1 X+1 0 X+1 2 X+1 C C X+1 R X R X+2 X+1 2 X+1 2 1R 8 FIG.B With the selected memory cellof NAND stringprogrammed to the first target level (e.g., coarse level L), in one example, the controller may be further configured to access the array of memory cells to program a further memory cell (e.g.,of NAND string) of the array of memory cells connected to the first access lineto a second target level (e.g., coarse level L, L, etc.) higher than the first target level (e.g., coarse level L). In this example, as illustrated inat, the controller may further apply a fourth voltage level (e.g., PV, PV, etc.) higher than the first voltage level to the first access line. At, the controller may further apply the second voltage level (e.g., VPASS) to the second access line. At, the controller may further apply the second voltage level (e.g., VPASS) to the third access line. At, the controller may further sense a second threshold voltage of the further memory cell (e.g.,of NAND string). Thus, in this example, since the further memory cell (e.g.,of NAND string) is not being programmed to the coarse level L, VPASSis not used.

8 FIG.C 818 1 208 206 204 820 204 822 208 206 C X+1 0 0 0 X+1 0 As illustrated inat, the controller may further in response to the sensed first threshold voltage being less than a first program verify level (e.g., shifted down PV), bias the selected memory cellof NAND stringfor programming (e.g., by applying a reference voltage [e.g., GND] to the data line). At, the controller may further in response to the sensed first threshold voltage being greater than the first program verify level, inhibit programming of the selected memory cell (e.g., by applying a supply voltage [e.g., Vcc] to the data line). At, the controller may further apply a particular program pulse to the selected memory cellof NAND string.

1R X+1 X+2 C C R 1R 202 202 1 1 In one example, the third voltage level (e.g., VPASS) is selected such that capacitive coupling between the first access lineand the third access linereduces the voltage level on the first access line from the first voltage level (e.g., PV). In some examples, the first voltage level (e.g., PV) is less than −1V, the second voltage level (e.g., VPASS) is greater than 6V, and the third voltage level (e.g., VPASS) is within a range between 1V and 5V.

208 206 202 1 824 1 202 826 202 828 202 202 208 206 830 208 206 X+2 0 X+2 C X+2 R X+1 1R X+3 X+2 X+3 0 X+2 0 8 FIG.D In one example, the controller is further configured to access the array of memory cells to program a further memory cell (e.g.,of NAND string) of the array of memory cells connected to the third access lineto the first target level (e.g., coarse level L). In this example, with the sensed first threshold voltage greater than the first program verify level, as illustrated inat, the controller may further apply the first voltage level (e.g., PV) to the third access line. At, the controller may further apply the second voltage level (e.g., VPASS) to the first access line. At, the controller may further apply the third voltage level (e.g., VPASS) to a fourth access lineof the plurality of access lines adjacent to the third access lineand connected to an erased memory cellof NAND string. At, the controller may further sense a second threshold voltage of the further memory cell (e.g.,of NAND string).

8 FIG.E 832 1 208 206 834 836 208 206 C X+2 0 X+2 0 As illustrated inat, the controller may further in response to the sensed second threshold voltage being less than the first program verify level (e.g., shifted down PV), bias the further memory cell (e.g.,of NAND string) for programming. At, the controller may further in response to the sensed second threshold voltage being greater than the first program verify level, inhibit programming of the further memory cell. At, the controller may further apply a subsequent program pulse to the further memory cell (e.g.,of NAND string).

8 FIG.F 8 FIG.F 838 1 202 840 202 842 202 844 208 206 208 206 F X+1 R X R X+2 X+1 0 X+1 0 With the sensed second threshold voltage greater than the first program verify level, as illustrated inat, the controller may further apply a fourth voltage level (e.g., PV,) higher than the first voltage level to the first access line. At, the controller may further apply the second voltage level (e.g., VPASS) to the second access line. At, the controller may further apply the second voltage level (e.g., VPASS) to the third access line. At, the controller may further sense a third threshold voltage of the selected memory cellof NAND string.may correspond to the fine programming of the selected memory cellof NAND string.

8 FIG.G 846 1 1 208 206 848 1 208 206 850 208 206 F C X+1 0 F X+1 0 X+1 0 As illustrated inat, the controller may further in response to the sensed third threshold voltage being less than a second program verify level (e.g., PV) higher than the first program verify level (e.g., shifted down PV), bias the selected memory cellof NAND stringfor programming. At, the controller may further in response to the sensed third threshold voltage being greater than the second program verify level (e.g., PV), inhibit programming of the selected memory cellof NAND string. At, the controller may further apply a further subsequent program pulse to the selected memory cellof NAND string.

9 9 FIGS.A-C 3 7 FIGS.- 9 9 FIG.A-C 1 FIG. 900 128 116 100 are flowcharts of a method for programming an array of memory cells (e.g., QLC memory cells) in accordance with another embodiment. Methodmay correspond at least in part to. For example,might represent a method to perform a program operation, e.g., programming one or more memory cells to target levels. The method might be in the form of computer-readable instructions, e.g., stored to the instruction registersof. Such computer-readable instructions might be executed by a controller, e.g., the control logic, to cause the memory deviceto perform the method.

900 100 104 206 202 236 208 116 202 2 FIG.A X+1 Methodmight be implemented within a memory device (e.g.,) including an array of memory cells (e.g.,) including a plurality of strings (e.g.,) of series-connected memory cells, a plurality of access lines (e.g.,), where each access line is connected to a control gate (e.g.,) of a respective memory cell (e.g.,) of each string of series-connected memory cells, and a controller (e.g.,) configured to program each respective memory cell connected to a selected first access line of the plurality of access lines to a respective target level. The following discussion will be made with reference to at leastand will presume that the selected first access line is the access line.

9 FIG.A 902 1 202 904 202 202 906 202 202 208 908 208 202 C X+1 R X X+1 1R X+2 X+1 X+2 X+1 X+1 As illustrated inat, the controller may apply a first voltage level (e.g., PV) to the selected first access line. At, the controller may apply a second voltage level (e.g., VPASS) higher than the first voltage level to a second access lineof the plurality of access lines adjacent to the selected first access line. At, the controller may apply a third voltage level (e.g., VPASS) between the first voltage level and the second voltage level to a third access lineof the plurality of access lines adjacent to the selected first access lineand connected to respective erased memory cells. At, the controller may sense a first threshold voltage of each respective memory cellconnected to the selected first access line.

9 FIG.B 910 208 202 1 912 208 202 914 202 X+1 X+1 C X+1 X+1 X+1 As illustrated inat, the controller may further inhibit programming of each respective memory cellconnected to the selected first access linein response to the sensed first threshold voltage of the respective memory cell being greater than a first program verify level (e.g., shifted down PV) for the respective memory cell. At, the controller may further enable programming of each respective memory cellconnected to the selected first access linein response to the sensed first threshold voltage of the respective memory cell being less than the first program verify level for the respective memory cell. In one example, the first program verify level for each respective memory cell includes a coarse program verify level less than a fine program verify level for each respective memory cell. At, the controller may further apply a particular program pulse to the selected first access line.

208 202 916 202 918 208 202 920 208 202 922 208 202 924 202 X+1 X+1 R X+2 X+1 X+1 X+1 X+1 X+1 X+1 X+1 9 FIG.C With the coarse programming of each respective memory cellconnected to the selected first access linecomplete, as illustrated inat, the controller may further apply the second voltage level (e.g., VPASS) to the third access line. At, the controller may further sense a second threshold voltage of each respective memory cellconnected to the selected access line. At, the controller may further inhibit programming of each respective memory cellconnected to the selected first access linein response to the sensed second threshold voltage of the respective memory cell being greater than the fine program verify level for the respective memory cell. At, the controller may further enable programming of each respective memory cellconnected to the selected first access linein response to the sensed second threshold voltage of the respective memory cell being less than the fine program verify level for the respective memory cell. At, the controller may further apply a subsequent program pulse to the selected first access line.

10 10 FIGS.A-D 3 7 FIGS.- 10 10 FIG.A-D 1 FIG. 2 FIG.A 1000 1000 128 116 100 202 208 206 X+1 X+1 0 are flowcharts of a methodfor programming an array of memory cells (e.g., QLC memory cells) in accordance with another embodiment. Methodmay correspond at least in part to. For example,might represent a method to perform a program operation, e.g., programming one or more memory cells to target levels. The method might be in the form of computer-readable instructions, e.g., stored to the instruction registersof. Such computer-readable instructions might be executed by a controller, e.g., the control logic, to cause the memory deviceto perform the method. The following discussion will be made with reference to at leastand will presume that the first access line is the access lineand the selected memory cell is memory cellof NAND string.

10 FIG.A 1002 1000 1 202 208 206 1 1004 1000 1 202 202 208 206 1006 1000 1 202 202 208 206 1008 1000 208 206 C X+1 X+1 0 R C X X+1 X 0 1R C R X+2 X+1 X+2 0 X+1 0 As illustrated inat, methodmay include applying a first voltage level (e.g., PV) to a first access lineconnected to a selected memory cellof NAND stringof the array of memory cells to be programmed to a first target level (e.g., coarse level L). At, methodmay include applying a second voltage level (e.g., VPASS) higher than the first voltage level (e.g., PV) to a second access lineadjacent to the first access lineand connected to an unselected memory cellof NAND string. At, methodmay include applying a third voltage level (e.g., VPASS) between the first voltage level (e.g., PV) and the second voltage level (e.g., VPASS) to a third access lineadjacent to the first access lineand connected to an erased memory cellof NAND string. At, methodmay include sensing a first threshold voltage of the selected memory cellof NAND string.

10 FIG.B 1010 1000 1 208 206 1012 1000 208 206 1014 1000 208 206 C X+1 0 X+1 0 X+1 0 As illustrated inat, methodmay further include in response to the sensed first threshold voltage being less than a first program verify level (e.g., shifted down PV), biasing the selected memory cellof NAND stringfor programming. At, methodmay further include in response to the sensed first threshold voltage being greater than the first program verify level, inhibiting programming of the selected memory cellof NAND string. At, methodmay further include applying a particular program pulse to the selected memory cellof NAND string.

10 FIG.C 1016 1000 2 3 1 202 1018 1000 202 1020 1000 202 1022 1000 208 206 202 2 3 1 C C C X+1 R X R X+2 X+1 2 X+1 As illustrated inat, methodmay further include applying a fourth voltage level (e.g., PV, PV, etc.) higher than the first voltage level (e.g., PV) to the first access line. At, methodmay further include applying the second voltage level (e.g., VPASS) to the second access line. At, methodmay further include applying the second voltage level (e.g., VPASS) to the third access line. At, methodmay further include sensing a second threshold voltage of a further memory cell (e.g.,of NAND string) of the array of memory cells connected to the first access lineto be programmed to a second target level (e.g., coarse L, coarse L, etc.) higher than the first target level (e.g., coarse L).

10 FIG.D 1024 1000 2 3 1 208 206 1026 1000 208 206 1028 1000 208 206 C C C X+1 2 X+1 2 X+1 2 As illustrated inat, methodmay further include in response to the sensed second threshold voltage being less than a second program verify level (e.g., PV. PV, etc.) higher than the first program verify level (e.g., shifted down PV), biasing the further memory cell (e.g.,of NAND string) for programming. At, methodmay further include in response to the sensed second threshold voltage being greater than the second program verify level, inhibiting programming of the further memory cell (e.g.,of NAND string). At, methodmay further include applying a subsequent program pulse to the further memory cell (e.g.,of NAND string).

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the embodiments will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the embodiments.