Patentable/Patents/US-20260047114-A1
US-20260047114-A1

Semiconductor Device and Method of Manufacturing the Same

PublishedFebruary 12, 2026
Assigneenot available in USPTO data we have
InventorsHSIU-YING CHO
Technical Abstract

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate, a capacitor component, an inductor component, and an interconnect structure. The capacitor component is disposed over the substrate and includes an anode assembly and a cathode assembly electrically insulated from the anode assembly. The inductor component is disposed on and vertically aligned with the capacitor component, wherein the inductor component includes a signal line and a shielding assembly between the signal line and the capacitor component. The interconnect structure is disposed over the substrate and surrounds the capacitor component and the inductor component.

Patent Claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

a substrate; a capacitor component disposed over the substrate and comprising an anode assembly and a cathode assembly electrically insulated from the anode assembly; an inductor component disposed over the substrate and at least partially overlapping the capacitor component from a top-view perspective, wherein the inductor component comprises a signal line extending in a first direction and a shielding assembly between the signal line and the capacitor component; and an interconnect structure disposed over the substrate and surrounding the capacitor component and the inductor component. . A semiconductor device, comprising:

2

claim 1 . The semiconductor device of, wherein the inductor component is vertically aligned with the capacitor component.

3

claim 1 a plurality of first shielding members extending along a second direction and substantially equally spaced in a third direction, wherein the first direction is different from the second direction and the second direction is perpendicular to the third direction; and a pair of second shielding members extending along the first direction and on opposite sides of the plurality of first shielding members, and the plurality of first shielding members connect one of the second shielding members to another second shielding member. . The semiconductor device of, wherein the shielding assembly comprises:

4

claim 3 a plurality of third shielding members vertically aligned with the second shielding members; and a plurality of connectors connecting two neighboring third shielding members that are vertically aligned and connecting each of the second shielding members to an adjacent third shielding member. . The semiconductor device of, wherein the shielding assembly further comprises:

5

claim 1 . The semiconductor device of, wherein the shielding assembly is further between the signal line and the interconnect structure.

6

claim 5 . The semiconductor device of, wherein the shielding assembly comprising a plurality of ring structure around the signal lines and equally spaced from each other along the first direction.

7

claim 1 the anode assembly comprises a plurality of first anode members and the cathode assembly comprises a plurality of first cathode members, and the plurality of first anode members and the plurality of first cathode members, separated apart from each other, are arranged in an array extending along the first direction and along a fourth direction that is perpendicular to the first direction, wherein the plurality of first anode members are horizontally and vertically staggered from the plurality of first cathode members. . The semiconductor device of, wherein:

8

claim 7 the anode assembly further comprises a second anode member connected to the plurality of first anode members, the cathode assembly further comprises a second cathode member connected to the plurality of first cathode members, and the second anode member and the second cathode member are spaced apart from each other in a second direction, and the plurality of first anode members and the plurality of first cathode members are between the second anode member and the second cathode member. . The semiconductor device of, wherein:

9

claim 7 the anode assembly further comprises a second anode member and a third anode member connecting the second anode member to the plurality of first anode members, the cathode assembly further comprises a second cathode member and a third cathode member connecting the second cathode member to the plurality of first cathode members, the second anode member and the second cathode member are spaced apart from each other in a second direction, the third anode member is separated from the third cathode member in the fourth direction, and the plurality of first anode members and the plurality of first cathode members are between the second anode member and the second cathode member and between the third anode member and the third cathode member. . The semiconductor device of, wherein:

10

claim 9 the anode assembly further comprises a plurality of fourth anode members, the cathode assembly further comprises a plurality of fourth cathode members, and the plurality of fourth anode members and the plurality of fourth cathode members, alternating in a third direction, are on opposite sides, in the first direction, of the plurality of first anode members and the plurality of first cathode members. . The semiconductor device of, wherein:

11

claim 1 . The semiconductor device of, further comprising at least one insulating layer between the capacitor component and the inductor component.

12

claim 11 . The semiconductor device of, wherein the insulating layer is disposed over the substrate and around the capacitor component, the inductor component, and the interconnect structure.

13

a device layer comprising a semiconductor component; and a capacitor component comprising an anode assembly and a cathode assembly electrically insulated from the anode assembly; an inductor component vertically overlapping the capacitor component and comprising a signal line extending in a first direction and a shielding assembly between the signal line and the capacitor component; and an interconnect structure surrounding the capacitor component and the inductor component and comprising alternating conductive lines and conductive vias electrically coupled to the semiconductor component. an interconnect layer disposed over the device layer and comprising: . A semiconductor device, comprising:

14

claim 13 . The semiconductor device of, wherein the inductor component is vertically aligned with the capacitor component.

15

claim 13 . The semiconductor device of, wherein the interconnect layer further comprises an insulating layer separating the anode assembly and the cathode assembly of the capacitor component, separating the signal line and the shielding assembly of the inductor component, and separating the capacitor component from the inductor component.

16

claim 13 . The semiconductor device of, wherein the capacitor component, the inductor component, and the interconnect structure comprise a carbon-containing metallic material.

17

claim 13 a plurality of first shielding members extending along a second direction and substantially equally spaced in a third direction, wherein the second direction is different from the first direction and the third direction is perpendicular to the second direction; a plurality of second shielding members extending along the second direction and substantially equal spaced in the third direction, wherein the plurality of first shielding members are on opposite sides of the signal line along a fourth direction that is perpendicular to the first direction; and a pair of third shielding members extending along the first direction and on opposite sides of the signal line along the first direction, wherein the third shielding members connect the plurality of first shielding members to the plurality of second shielding members. . The semiconductor device of, wherein the shielding assembly comprises:

18

providing a substrate; forming a first interconnect layer over the substrate, wherein the first interconnect layer comprising a capacitor component and a first interconnect structure laterally surrounding the capacitor component; and forming a second interconnect layer over the first interconnect layer, wherein the second interconnect layer comprises an inductor component vertically aligned with the capacitor component and a second interconnect structure laterally surround the inductor component and electrically connected to the first interconnect structure. . A method of manufacturing a semiconductor device, comprising:

19

claim 18 . The method of, further comprising depositing an insulating layer between the first interconnect layer and the second interconnect layer.

20

claim 19 . The method of, wherein the second interconnect layer comprises alternating conductive lines and conductive vias, and at least one bottommost conductive line of the inductor component is disposed in the insulating layer.

Detailed Description

Complete technical specification and implementation details from the patent document.

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the size of the smallest component (or line) that can be created using a fabrication process) has decreased.

Various active or passive electronic components can be formed on a semiconductor IC. For example, transformers, inductors, capacitors, etc., may be formed on a semiconductor IC. However, conventional electronic components formed on an IC may incur shortcomings such as excess space consumption, poor device performance, inadequate shielding, and high fabrication costs.

Therefore, while existing electronic components on semiconductor ICs have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for a purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, but these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence, order, or importance unless clearly indicated by the context.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the normal deviation found in the respective testing measurements. Also, as used herein, the terms “substantially,” “approximately” or “about” generally mean within a value or range (e.g., within 10%, 5%, 1%, or 0.5% of a given value or range) that can be contemplated by people having ordinary skill in the art. Alternatively, the terms “substantially,” “approximately” or “about” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. People having ordinary skill in the art can understand that the acceptable standard error may vary according to different technologies. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of time, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “substantially,” “approximately” or “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.

The present disclosure provides a semiconductor device including stacked capacitor components and inductor components embedded in an interconnect structure. The inductor components include a shielding assembly around a signal line. Since the signal line is shielded by the shielding assembly, the capacitor component is able to be positioned over or under the inductor component. One advantage offered by the semiconductor device is the reduced footprint.

1 FIG. 1 FIG. 10 10 102 104 102 102 20 200 20 104 25 30 40 25 25 30 40 20 200 20 200 20 is a cross-sectional view of a semiconductor device, in accordance with some embodiments of the present disclosure. Referring to, in some embodiments, the semiconductor deviceincludes a device layerand an interconnect layerdisposed over the device layer. The device layerincludes a substrateand one or more semiconductor components(e.g., transistors, resistors, or the like) disposed in and/or on the substrate. The interconnect layerincludes an interconnect structureand a plurality of passive components (e.g., capacitor componentsand inductors) surrounded by the interconnect structure. The interconnect structure, the capacitor components, and the inductor componentsare disposed over the substrateand the semiconductor components. The substratemay be a semiconductor substrate, and may include semiconductor materials such as silicon, germanium, and the like. The semiconductor componentsmay be formed in and/or on the substratein a front-end-of-line (FEOL) stage.

200 30 40 25 104 1 13 1 13 210 212 214 216 218 220 222 224 226 228 230 232 234 104 1 FIG. Electrical signals, such as power and/or input/output signals, may be routed to and/or from the semiconductor components, the capacitor components, and the inductor componentsthrough the interconnect structure. The interconnect layerincludes a plurality of tiers (e.g., tiers Mto M), with each of the tiers Mto Mincluding conductive features and at least one insulating layer (e.g., the insulating layer,,,,,,,,,,,, or). Althoughshows merely thirteen tiers, the scope of this application is not limited thereto. In some embodiments, the interconnect layercan include more or fewer than thirteen tiers.

252 254 252 1 13 254 252 254 252 1 252 2 In some embodiments, the conductive features include alternating conductive linesand conductive vias. In some embodiments, the conductive linesextend horizontally in the tiers Mto M, and the conductive viasextend vertically to provide electrical connections between the conductive linesin different tiers. For example, a conductive viaallows a conductive linefrom the tier Mto be electrically connected to another conductive linefrom the tier M.

252 254 25 30 40 210 234 210 234 25 30 40 20 The conductive linesand the conductive viasof the interconnect structure, the capacitor components, and the inductor componentsmay be formed in the insulating layersto. The insulating layerstomay each include an oxide (such as silicon oxide), a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), a carbide (such as silicon carbide), an oxycarbide (such as silicon oxycarbide), a low-dielectric-constant (low-k) dielectric material, an ultra-low-k dielectric material, other dielectric materials, or a combination thereof. The interconnect structure, the capacitor components, and the inductor componentsmay be formed in or on the substratein a back-end-of-line (BEOL) stage.

1 FIG. 2 FIG. 30 40 10 25 200 20 100 Althoughshows merely two capacitor componentsconstructed in a same configuration and two inductor componentsconstructed in a same configurations, the scope of this application is not limited thereto. In some embodiments, more than two capacitor components constructed in the same or different configurations and more than two inductor components constructed in the same of different configurations can be included in the semiconductor device. The interconnect structuremay connects the semiconductor componentsformed in the substrate, the multiple capacitor components, and the multiple inductor components to form an integrated circuit including a low-noise amplifier (LNA), as shown in.

1 FIG. 3 FIG. 1 3 FIGS.and 30 40 25 30 40 25 30 40 30 40 10 40 30 1 30 40 50 50 40 30 40 30 Referring again to, in some embodiments, the capacitor componentsand the inductor componentsare embedded in the interconnect structure. The capacitor componentsand the inductor componentsmay be formed simultaneously with the interconnect structure. In some embodiments, the capacitor componentand the inductor componentare stacked on top of one another, to thereby reduce a footprint of the capacitor componentsand the inductor componentsin the semiconductor device. For example, the inductor componentsmay be each stacked on one of the capacitor componentswith an interval Sin the Z-direction. The capacitor componentand the inductor componentstacked thereon are in combination referred to as a stacked structure, wherein a schematic perspective view of the stacked structureis shown in. Referring to, in some embodiments, the insulator componentpartially overlaps the capacitor componentfrom a top-view perspective. In alternative embodiments, the insulator componentis vertically aligned with the capacitor component.

1 FIG. 1 FIG. 30 40 20 20 50 30 40 1 220 224 1 30 40 30 104 104 30 1 3 104 CT CB IT IB CT IT CB IB CT IB CB IT CB As shown in, the capacitor componentsmay each include a topmost layer Land a bottommost layer L, and the inductor componentsmay each include a topmost layer Land a bottommost layer L. The topmost layer L/Lrefers to the layer farthest from the substrate, and the bottommost layer L/Lrefers to the layer closest to the substrate. In the stacked structure, a top surface of the topmost layer Lof the capacitor componentmay be separated from a bottom surface of the bottommost layer Lof inductor componentby an interval S. In some embodiments, one or more insulating layers, such as the insulator layers/, fill the interval Sbetween the capacitor componentand the inductor component. The bottommost layer Lof each capacitor componentmay be disposed in any tier of the interconnect layeras long as the topmost layer Lis not a topmost layer of the interconnect layer. For example, in, the bottommost layers Lof the capacitor componentsare placed in tiers Mand Mof the interconnect layer, respectively.

4 FIG. 5 FIG. 4 FIG. 3 4 FIGS.and 30 30 30 30 32 34 32 32 34 32 30 34 30 32 34 32 34 25 is a schematic perspective view of the capacitor component, in accordance with some embodiments of the present disclosure, andis a cross-sectional view along a line A-A′ of the capacitor componentin. Referring to, the capacitor componentmay have a cube-like shape. In some embodiments, the capacitor componentincludes an anode assemblyand a cathode assemblyseparated from and electrically insulated from the anode assembly. The anode and cathode assembliesandmay not be in direct contact. The anode assemblymay function as an anode electrode of the capacitor component, and the cathode assemblymay function as a cathode electrode of the capacitor component. When voltages are applied to the anode electrode and the cathode electrode to cause a voltage difference, an electric field is generated between the anode assemblyand the cathode assembly. The voltages may be applied to the anode assemblyand the cathode assembly, e.g., by a power source, through the interconnect structure.

32 322 324 322 3222 3224 3222 3224 3222 3222 3224 3222 104 1 FIG. The anode assemblymay include a plurality of first anode membersand a second anode member. Each of the first anode membersincludes a pair of first anode conductive linesand a first anode conductive via. In some embodiments, the first anode conductive linesextend along the X-direction and are spaced apart from one another in the Z-direction substantially orthogonal to the X-direction. The first anode conductive viamay extend along the X-direction and connect one of the first anode conductive linesto another of the first anode conductive lines. In some embodiments, the first anode conductive viaprovides electrical connection between the first anode conductive linesin different tiers of the interconnect layershown in.

3222 1 1 1 1 3224 2 2 2 2 1 3222 2 3224 2 3224 1 3222 1 3222 2 3224 3222 3224 322 The first anode conductive lineshave a length Ldefined along the X-direction and a width Wdefined in the Y-direction substantially orthogonal to the X-direction, wherein the length Lmay be substantially greater than the width W. The first anode conductive viahas a length Ldefined along the X-direction and a width Wdefined along the Y-direction, wherein the length Lmay be substantially greater than the width W. The length Lof the first anode conductive linesis greater than the length Lof the first anode conductive via. In some embodiments, the length Lof the first anode conductive viais greater than half the length Lof the first anode conductive lines. The width Wof the first anode conductive linesmay be substantially greater than the width Wof the first anode conductive via. In some embodiments, the pair of first anode conductive linesand the first anode conductive viacollectively form the first anode memberhaving an I-shaped cross-section.

324 3242 3244 3242 3242 3244 3242 104 3244 3 3 3 3 1 FIG. In some embodiments, the second anode memberincludes a plurality of second anode conductive linesand a plurality of second anode conductive vias. The second anode conductive linesare substantially equally spaced and extend along the Y-direction. The second anode conductive linesare vertically spaced apart from each other in the Z-direction. Each of the second anode conductive viasconnects two neighboring second anode conductive linesin different tiers of the interconnect layershown in. The second anode conductive viashave a length Lin the Y-direction and a width Win the X-direction, wherein the length Lmay be substantially equal to the width W.

34 342 344 342 3422 3424 3422 3424 3422 3422 3422 4 4 4 4 3424 5 5 5 5 4 3422 5 3424 5 3424 4 3422 4 3422 5 3424 4 3422 1 3222 4 3422 1 3222 5 3424 2 3224 4 3422 2 3224 The cathode assemblymay include a plurality of first cathode membersand a second cathode member. Each of the first cathode membersincludes a pair of first cathode conductive linesand a first cathode conductive via. In some embodiments, the first cathode conductive linesextend along the X-direction and are spaced apart from one another in the Z-direction. The first cathode conductive viamay extend along the X-direction and connect one of the first cathode conductive linesto another of the first cathode conductive lines. The first cathode conductive lineshave a length Ldefined along the X-direction and a width Wdefined in the Y-direction, wherein the length Lmay be substantially greater than the width W. The first cathode conductive viahas a length Ldefined along the X-direction and a width Wdefined along the Y-direction, wherein the length Lmay be substantially greater than the width W. The length Lof the first cathode conductive linesis greater than the length Lof the first cathode conductive via. In some embodiments, the length Lof the first cathode conductive viais greater than half the length Lof the first cathode conductive lines. The width Wof the first cathode conductive linesmay be substantially greater than the width Wof the first cathode conductive via. In some embodiments, the length Lof the first cathode conductive linesis substantially equally to the length Lof the first anode conductive lines, the width Wof the first cathode conductive linesis substantially equally to the width Wof the first anode conductive lines. In some embodiments, the length Lof the first cathode conductive viais substantially equally to the length Lof the first anode conductive via, and the width Wof the first cathode conductive linesis substantially equally to the width Wof the first anode conductive via.

344 3442 3444 3442 3442 3444 3442 3444 6 6 6 6 In some embodiments, the second cathode memberincludes a plurality of second cathode conductive linesand a plurality of second cathode conductive vias. The second cathode conductive linesare substantially equally spaced and extend along the Y-direction. The second cathode conductive linesare vertically spaced apart from each other in the Z-direction. Each of the second cathode conductive viasconnects two neighboring second cathode conductive lines. The second cathode conductive viashave a length Lin the Y-direction and a width Win the X-direction, wherein the length Lmay be substantially equal to the width W.

324 344 322 342 324 344 322 324 344 322 344 1 342 344 324 1 342 324 1 322 342 In some embodiments, the second anode memberis spaced apart from the second cathode memberin the X-direction, and the first anode membersand the first cathode membersare between the second anode memberand the second cathode member. The first anode membersmay be connected to the second anode memberand separated from the second cathode member. In some embodiments, the first anode membersare separated from the second cathode memberby a distance D. The first cathode membersmay be connected to the second cathode memberand separated from the second anode memberby the distance D. For example, the first cathode membersmay be separated from the second anode memberby the distance D. In some embodiments, the first anode membersare interdigitated with the first cathode memberswhen viewed from a top perspective and when viewed from a cross-sectional view.

5 FIG. 322 342 322 342 322 342 322 342 322 342 322 342 Referring to, in some embodiments, the first anode membersand the first cathode membersare separated apart from each other. The first anode membersand the first cathode membersare arranged in an array along the Y-direction and along the Z-direction. In some embodiments, the first anode membersand the first cathode membersare arranged in an array in the Y-Z plane. The array may be an M×N array, where M and N are both positive integers and may be the same or different, e.g., a 3×3 array. The first anode membersand the first cathode membersare parallel to each other and equally spaced apart. The first anode membersmay be horizontally and vertically staggered from the first cathode members. For example, one of the first anode membersis between two of the first cathode members, or vice versa.

1 FIG. 210 220 214 224 30 210 220 214 224 32 34 322 324 342 344 210 220 214 224 30 30 210 220 214 224 32 34 1 322 342 1 Referring again to, one or more insulating layers (e.g., the insulating layerstoor the insulating layersto) are used as a capacitor dielectric of the capacitor component. In some embodiments, the insulating layerstoor the insulating layerstofill spaces between the anode assemblyand the cathode assembly, between the first anode membersand the second anode member, and between the first cathode membersand the second cathode member. The insulating layerstoor the insulating layerstomay further laterally surround the capacitor components. Each of the capacitor componentshas a capacitance. In some embodiments, the capacitance is a function of several factors, such as dielectric constants of the insulating layerstoor the insulating layersto, overlapping surface areas of the anode assemblyand the cathode assembly, and the distance D. For example, a higher dielectric constant of the insulating layer may provide a greater capacitance. For another example, a greater capacitance may be achieved by increasing the overlapping areas of the first anode membersand the first cathode membersor reducing the distance D.

6 FIG. 40 42 44 42 44 42 1 2 42 44 42 42 30 42 30 44 30 40 42 25 42 44 44 44 Referring to, in some embodiments, the inductor componentincludes a signal lineand a shielding assembly, wherein the signal lineis electrically insulated from the shielding assembly. The signal lineextends in the Y-direction. An electrical signal may be propagated from a first port Pto a second port Pof the signal line. The shielding assemblymay surround the signal lineto provide a shield function such that the signal lineis electrically shielded from the capacitor componentunder the signal line. Hence, an induced energy loss is substantially reduced and a quality factor of the capacitor componentis substantially increased. The shielding assemblyis used to detune the capacitor componentand the inductor componentfrom resonance. The signal linemay be further electrically shielding from the interconnect structureproximal to the signal line. In some embodiments, the shielding assemblyhas a U-shaped cross-sectional view. In some embodiments, the shielding assemblyis electrically grounded. In alternative embodiments, the shielding assemblyis floating.

44 42 44 442 444 446 448 442 442 42 442 444 446 42 442 42 442 442 444 446 In some embodiments, the shielding memberprovides a return path for signals propagating in the signal line. The shielding assemblymay include a plurality of first shielding members, a pair of second shielding members, a plurality of third shielding members, and a plurality of conductive vias. The first shielding membersmay have a strip shape. The first shielding membersare parallel to each other and equally spaced apart. The signal lineand the first shielding membersextend in different directions. The second shielding members, the third shielding membersmay extend in a same direction. In some embodiments, the signal lineextends along the Y-direction, and the first shielding membersextend along a direction not parallel to the Y-direction. An included angle α formed between the signal lineand each first shielding memberis greater than about 5 degrees. For example, the first shielding membersmay extend along the X-direction orthogonal to the Y-direction. The second shielding membersand the third shielding membersmay extend along the Y-direction.

442 444 104 442 442 442 442 1 FIG. The first shielding membersand the second shielding membersmay be disposed in a same tier of the interconnect layershown in. Each of the first shielding membersmay have a width SL in the Y-direction and may be spaced from a neighboring first shielding memberby a distance SS in the Y-direction. The width SL of each first shielding membermay be equal to or different from the distance SS between adjacent first shielding members.

444 442 444 444 442 444 442 444 442 42 42 444 42 40 444 442 42 444 442 42 30 442 444 The pair of second shielding membersare spaced apart from one another, and the first shielding membersconnect one of the second shielding membersto another one of the second shielding members. Two of the first shielding membersfarthest from each other and the pair of second shielding memberscollectively form a substantially rectangular perimeter, as seen from a top-view perspective. In some embodiments, the first shielding membersand the second shielding membersare integrally formed. Since the first shielding membersimmediately under the signal lineare not parallel to the signal lineand the second shielding membersare parallel to the signal line, the shielding assemblyprovide a lower impedance return path for the signals to ground through the second shielding membersthan through the first shielding members. Accordingly, a return path for the signals propagating in the signal linemay be the second shielding members. The first shieling membersare used to avoid or at least minimize inductive coupling from the signal linesto the capacitor component. The first shieling membersand the second shielding membersmay provide slow-wave effects, resulting in a more efficient utilization of valuable chip area.

446 444 446 444 446 444 448 446 448 444 446 In some embodiments, some of the third shielding membersare disposed over and vertically aligned with one of the second shielding members, and others of the third shielding membersare disposed over and vertically aligned with another of the second shielding members. The third shielding membersand the second shielding memberthereunder may be substantially equally spaced. Some of the conductive viasconnect neighboring pairs of the third shielding members, and others of the conductive viasconnect a second shielding memberto an adjacent third shielding member.

1 6 FIGS.and 42 446 444 104 42 446 42 446 4 40 4 444 42 4 42 7 446 8 7 8 Referring to, in some embodiments, the signal lineand two of the third shielding membersfarthest from the second shielding membersare disposed in a same tier of the interconnect layer. The signal linemay be arranged between the pair of third shielding members. The signal linemay be spaced apart from each third shielding memberby a distance D. An impedance of the inductor componentmay be tuned by adjusting the distance Dbetween each of the second shielding membersand the signal line. In some embodiments, the distance Dis in a range between 1 μm and 100 μm. The signal linehas a width W, the third shielding membershave a width W, and the width Wmay be substantially equal to the width W.

1 FIG. 30 40 32 34 30 42 44 30 40 252 254 25 30 40 25 25 30 40 210 234 Referring again to, the capacitor componentsand the inductor componentsmay be made of at least one metallic material. In some embodiments, the anode assemblyand the cathode assemblyof the capacitor components, the signal lineand the shielding assemblyare made of a same metallic material. In some embodiments, the capacitor componentsand the inductor componentsinclude a carbon-containing conductive material, such as carbon-containing copper or carbon-containing manganese. The conductive linesand the conductive viasof the interconnect structuremay include the carbon-containing conductive material due to the capacitor componentsand the inductor componentsbeing formed simultaneously with the interconnect structure. In some embodiments, a concentration of carbon in the carbon-containing conductive material is greater than about 5%. The interconnect structure, the capacitor components, and the inductor componentsmay be formed in the insulating layerstoby photolithography and etching operations to form via holes and trenches, and by deposition, sputtering, plating, or combinations thereof to fill the via holes and the trenches with the conductive material.

7 FIG. 8 FIG. 7 8 FIGS.and 30 30 322 326 342 346 30 30 32 34 32 34 32 34 is a schematic perspective view of a capacitor componentA, in accordance with some embodiments of the present disclosure, andis a schematic perspective view of a portion of the capacitor componentA illustrating some embodiments of the present disclosure that include a plurality of first anode membersA, a plurality of third anode membersA, a plurality of first cathode membersA, and a third cathode memberA of the capacitor componentA. Referring to, in some embodiments, the capacitor componentA includes an anode assemblyA and a cathode assemblyA. The anode assemblyA is separated from and electrically insulated from the cathode assemblyA. Spaces between the anode assemblyA and the cathode assemblyA may be filled with one or more insulating layers.

32 34 2 32 322 324 326 328 34 342 344 346 348 In some embodiments, the anode assemblyA is separated from the cathode assemblyA by a distance Din the X-direction. The anode assemblyA may include a plurality of first anode membersA, a second anode memberA, a plurality of third anode membersA, and a fourth anode memberA. The cathode assemblyA may include a plurality of first cathode membersA, a second cathode memberA, a third cathode memberA, and a fourth cathode memberA.

322 3222 3224 3222 3222 3224 3224 3222 104 3224 3 2 32 34 1 FIG. Each of the first anode membersA includes a pair of first anode conductive linesA and a plurality of first anode conductive viasA. In some embodiments, the first anode conductive linesA extend along the X-direction and are spaced apart from one another in the Z-direction. The pair of first anode conductive linesA are connected by the first anode conductive viasA. In some embodiments, the first anode conductive viasA provide electrical connection between the first anode conductive linesA in different tiers of the interconnect layer(shown in). In some embodiments, a neighboring pair of the first anode conductive viasA are spaced apart by a distance D, which is greater than a distance Dbetween the anode assemblyA and the cathode assemblyA.

7 FIG. 1 FIG. 324 3242 3244 3242 3242 3244 3242 104 Referring to, in some embodiments, the second anode memberA includes a plurality of second anode conductive linesA and a plurality of second anode conductive viasA. The second anode conductive linesA are substantially equally spaced and may extend along the Y-direction. The second anode conductive linesA are vertically spaced apart from each other in the Z-direction. The second anode conductive viasA connect neighboring pairs of the second anode conductive linesA in different tiers of the interconnect layer(shown in).

344 3442 3444 3442 3442 3444 3442 The second cathode memberA may include a plurality of second cathode conductive linesA and a plurality of second cathode conductive viasA. In some embodiments, the second cathode conductive linesA are substantially equally spaced and extend along the Y-direction. The second cathode conductive linesA may be vertically spaced apart from each other in the Z-direction. In some embodiments, the second cathode conductive viasA connect neighboring pairs of the second cathode conductive linesA.

8 FIG. 1 FIG. 342 3422 3424 3422 3424 3422 104 Referring to, in some embodiments, each of the first cathode membersA includes a pair of first cathode conductive linesA and a plurality of first cathode conductive viasA. In some embodiments, the first cathode conductive linesA extend along the X-direction and are spaced apart from one another in the Z-direction. The first cathode conductive viasA may be disposed between and connected to the first cathode conductive linesA disposed in different tiers of the interconnect layers(shown in).

326 3262 3264 3262 3264 3262 3262 9 9 9 9 3264 10 10 10 10 9 3262 10 3264 9 3262 10 3264 The third anode membersA may include a plurality of third anode conductive linesA and a plurality of third anode conductive viasA. In some embodiments, the third anode conductive linesA are spaced apart from one another in the Y-direction, and each of the third anode conductive viasA connects an adjacent pair of the third anode conductive linesA. The third anode conductive linesA have a length Lin the X-direction and a width Win the Y-direction, wherein the length Lmay be substantially equal to the width W. The third anode conductive viasA have a length Lin the X-direction and a width Win the Y-direction, wherein the length Lmay be substantially equal to the width W. In some embodiments, the length Lof the third anode conductive linesA is greater than the length Lof the third anode conductive viasA, and the width Wof the third anode conductive linesA is greater than the width Wof the third anode conductive viasA.

346 326 346 3462 3464 3462 3464 3462 The third cathode membersA may have a configuration same as a configuration of the third anode membersA. In some embodiments, the third cathode membersA include a plurality of third cathode conductive linesA and a plurality of third cathode conductive viasA. The third cathode conductive linesA are spaced apart from one another in the Z-direction, and each of the third cathode conductive viasA connects an adjacent pair of the third cathode conductive linesA.

326 346 346 326 346 326 326 346 346 326 322 342 326 346 322 342 322 342 The third anode membersA and the third cathode memberA are arranged in line in the X-direction and separated from one another. The third cathode memberA may be interleaved with the third anode membersA. For example, a third cathode memberA is between two of the third anode membersA. In some embodiments, the third anode membersA and the third cathode memberA are alternating in the X-direction, and one of the third cathode memberA is between two of the third anode membersA. In some embodiments, the first anode membersA and the first cathode membersA are disposed on opposite sides along the Y-direction of the third anode membersA and the third cathode memberA. The first anode membersA and the first cathode membersA may be aligned in the Z-direction, and the first anode membersA may be interleaved with the first cathode membersA.

7 FIG. 1 FIG. 1 FIG. 328 348 326 346 328 324 344 104 348 324 344 104 326 328 346 348 Referring back to, the fourth anode memberA and the fourth cathode memberA are disposed on opposite sides along the Z-direction of the third anode membersA and the third cathode memberA. The fourth anode memberA, a topmost layer of the second anode memberA, and a topmost layer of the second cathode membersA may be disposed in a same tier of the interconnect layer(shown in). The fourth cathode memberA, a bottommost layer of the second anode memberA, and a bottommost layer of the second cathode membersA may be disposed in a same tier of the interconnect layer(shown in). The third anode membersA may be electrically coupled to the fourth anode memberA, and the third cathode memberA may be electrically coupled to the fourth cathode memberA.

9 FIG. 10 FIG. 9 FIG. 9 10 FIGS.and 30 30 32 34 32 34 32 34 is a schematic perspective view of a capacitor componentB, in accordance with some embodiments of the present disclosure, andis a cross-sectional view along a line B-B′ of the capacitor component in. Referring to, in some embodiments, the capacitor componentB includes an anode assemblyB and a cathode assemblyB. The anode assemblyB is separated from and electrically insulated from the cathode assemblyB. In some embodiments, spaces between the anode assemblyB and the cathode assemblyB are filled with one or more insulating layers.

32 322 324 326 34 342 344 346 322 3222 3224 3222 3224 3224 3222 104 1 FIG. The anode assemblyB may include a plurality of first anode membersB, a second anode memberB, and a plurality of third anode membersB. The cathode assemblyB may include a plurality of first cathode membersB, a second cathode memberB, and a plurality of third cathode membersB. Each of the first anode membersB includes alternating first anode conductive linesB and first anode conductive viasB. In some embodiments, neighboring pairs of the first anode conductive linesB are connected by one of the first anode conductive viasB. The first anode conductive viasB provide electrical connection between the first anode conductive linesB in different tiers of the interconnect layer(shown in).

342 3422 3424 3422 3424 3424 3422 104 1 FIG. In some embodiments, each of the first cathode membersB includes alternating first cathode conductive linesB and first cathode conductive viasB. Neighboring pairs of the first cathode conductive linesB may be connected by one of the first cathode conductive viasB. The first cathode conductive viasB provide electrical connection between the first cathode conductive linesB in different tiers of the interconnect layer(shown in).

324 344 326 346 324 3242 3244 3242 3242 3244 3242 The second anode memberB and the second cathode memberB may be disposed at opposite sides along the X-direction of the third anode membersB and the third cathode membersB. In some embodiments, the second anode memberB includes a plurality of second anode conductive linesB and a plurality of second anode conductive viasB. The second anode conductive linesB are substantially equally spaced and may extend along the Y-direction. The second anode conductive linesB are vertically spaced apart from each other in the Z-direction. Each of the second anode conductive viasB connects a neighboring pair of the second anode conductive linesB.

344 3442 3444 3442 3442 3444 3442 The second cathode memberB may include a plurality of second cathode conductive linesB and a plurality of second cathode conductive viasB. In some embodiments, the second cathode conductive linesB are substantially equally spaced and extend along the Y-direction. The second cathode conductive linesB may be vertically spaced apart from each other in the Z-direction. In some embodiments, each of the second cathode conductive viasB connects a neighboring pair of the second cathode conductive linesB.

326 346 322 342 326 324 104 346 344 104 326 346 326 322 346 342 3222 3224 3264 3224 3264 3224 326 3464 3224 3464 3224 346 30 30 30 30 30 30 1 FIG. In some embodiments, the third anode membersB and the third cathode membersB are disposed on opposite sides along the Z-direction of the first anode membersB and the first cathode membersB. The third anode membersB and a topmost layer of the second anode memberB may be disposed at a same tier of the interconnect layer(shown in), and the third cathode membersB and a bottommost layer of the second cathode memberB may be disposed at a same tier of the interconnect layer. The third anode membersB and the third cathode membersB extend in the X-direction and are parallel to each other. The third anode membersB may be connected to one or more of the first anode membersB. The third cathode membersB may be connected to one or more of the first cathode membersB. In some embodiments, a quantity of the first anode conductive linesB is equal to a quantity of the first anode conductive viasB, some of the third anode conductive viasB connect neighboring pairs of the first anode conductive viasB, and others of the third anode conductive viasB connect the first anode conductive viasB to the adjacent third anode membersB. Some of the third cathode conductive viasB connect neighboring pairs of the first anode conductive viasB, and others of the third cathode conductive viasB connect the first anode conductive viasB to the adjacent third cathode membersB. The capacitor components,A, andB arranged in different configurations may have different overlapping surface areas of the anode assembly and the cathode assembly. Therefore, the capacitor component,A/B having the same dimension along the X-direction, the Y-direction, and the Z-direction may have different capacitances.

11 FIG. 11 FIG. 1 FIG. 40 40 42 44 42 42 44 42 42 30 42 25 42 30 44 is a schematic perspective view of an inductor componentA, in accordance with some embodiments of the present disclosure. Referring to, the inductor componentA includes a signal lineA and a shielding assemblyA. The signal lineA extends in the Y-direction. An electrical signal may be propagated through the signal lineA. The shielding assemblyA may surround the signal lineA to provide a shielding function such that the signal lineA is electrically shielded from the capacitor componentA under the signal lineA and the interconnect structure(shown in) proximal to and above the signal lineA. Hence, an induced energy loss is substantially reduced and a quality of the capacitor componentis substantially increased. In some embodiments, the shielding assemblyA is electrically grounded.

44 442 444 446 448 442 442 442 42 The shielding assemblyA may include a plurality of first conductive stripsA, a plurality of second conductive stripsA, a plurality of third conductive stripsA, and a plurality of conductive viasA. Each of the first conductive stripsA may have a width SL in the Y-direction and may be spaced apart from a neighboring first conductive stripA by a distance SS in the Y-direction. In some embodiments, the first conductive stripsA are disposed at opposite sides along the Z-direction of the signal lineA.

442 444 444 442 444 442 444 442 Each of the first conductive stripsA includes a first terminal connected to one of the second conductive stripsA and a second terminal connected to another of the second conductive stripsA. Two of the first conductive stripsA farthest from each other and two of the second conductive stripsA connected thereto collectively form a substantially rectangular perimeter, as seen from a bottom-view perspective. The first conductive stripsA and two of the second conductive stripsA connected to the first conductive stripsA may be integrally formed.

446 444 446 444 448 446 448 446 444 In some embodiments, the third conductive stripsA are disposed between and vertically aligned with two of the second conductive stripsA stacked in the Z-direction. The third conductive stripsA and the second conductive stripA may be substantially equally spaced in the Z-direction. Some of the conductive viasA connect neighboring pairs of the third conductive stripsA, and others of the conductive viasA connect one of the third conductive stripsA to an adjacent second conductive stripA.

12 FIG. 12 FIG. 1 FIG. 40 40 42 44 42 42 44 42 42 30 42 25 42 30 44 is a schematic perspective view of an inductor componentB, in accordance with some embodiments of the present disclosure. Referring to, the inductor componentB includes a signal lineB and a shielding assemblyB. The signal lineB extends in the Y-direction. An electrical signal may be propagated through the signal lineB. The shielding assemblyB may surround the signal lineB to provide a shielding function such that the signal lineB is electrically shielded from the capacitor componentunder the signal lineB and the interconnect structure(shown in) proximal to and above the signal lineB. Hence, an induced energy loss is substantially reduced and a quality of the capacitor componentis substantially increased. In some embodiments, the shielding assemblyB is electrically grounded.

44 442 444 442 442 442 42 442 444 444 The shielding assemblyB may include a plurality of first shielding membersB and a pair of second shielding membersB. Each of the first shielding membersB may have a width SL in the Y-direction and may be spaced from a neighboring shielding memberB by a distance SS in the Y-direction. In some embodiments, the first shielding membersB are disposed at opposite sides along the Z-direction of the signal lineB. Each of the first shielding membersB includes a first terminal connected to one of the second shielding membersB and a second terminal connected to another of the second shielding membersB.

13 FIG. 12 FIG. 1 FIG. 40 40 42 44 42 42 44 42 42 30 42 25 42 30 44 44 44 440 440 42 is a schematic perspective view of an inductor componentC, in accordance with some embodiments of the present disclosure. Referring to, the inductor componentC includes a signal lineC and a shielding assemblyC. The signal lineC extends in the Y-direction. An electrical signal may be propagated through the signal lineC. The shielding assemblyC may surround the signal lineC to provide a shielding function such that the signal lineC is electrically shielded from the capacitor componentunder the signal lineC and the interconnect structure(shown in) proximal to and above the signal lineC. Hence, an induced energy loss is substantially reduced and a quality of the capacitor componentis substantially increased. In some embodiments, the shielding assemblyC is electrically grounded. In alternative embodiments, the shielding assemblyC is floating. The shielding memberC may include a plurality of ring membersC extending along X-direction and spaced from each other along the Y-direction. The ring membersC are arranged around the signal lineC.

14 FIG. 14 FIG. 9 FIG. 13 FIG. 12 12 52 30 40 30 40 236 20 30 40 30 40 1 30 40 30 40 30 40 C I C I C I C I is a schematic cross-sectional view of a semiconductor device, in accordance with some embodiments of the present disclosure. Referring to, in some embodiments, the semiconductor deviceincludes a stacked structureincluding a capacitor component (such as the capacitor componentB illustrated in) and an inductor component (such as the inductor componentC illustrated in). The capacitor componentB and the inductor componentC may be disposed in one or more insulating layersover a substrate. In some embodiments, the capacitor componentB is disposed over the inductor componentC. The capacitor componentB and the inductor componentC may be vertically separated apart by an interval S. The capacitor componentB may fully overlap the inductor componentC. In some embodiments, the capacitor componentB has a length Lin the X-direction, the inductor componentC has a length Lin the X-direction, and the length Lis greater than the length L. The capacitor componentB has a central line Calong the Z-direction, the inductor componentC has a central line Calong the Z-direction, and the central line Cmay be aligned with the central line C.

15 FIG. 15 FIG. 4 FIG. 6 FIG. 11 FIG. 14 14 54 54 30 40 40 30 30 40 40 236 20 is a schematic cross-sectional view of a semiconductor device, in accordance with some embodiments of the present disclosure. Referring to, in some embodiments, the semiconductor deviceincludes a stacked structure. The stacked structureincludes a capacitor component (such as the capacitor componentillustrated in) and a plurality of inductor components (such as the inductor componentillustrated inand the inductor componentA illustrated in) stacked over the capacitor component. The capacitor componentand the inductor componentsandA may be disposed in one or more insulating layersover a substrate.

40 30 40 30 30 40 40 30 40 40 C I1 C I2 I2 C I1 C I1 C I1 I2 I2 C The inductor componentmay fully overlap the capacitor component, and the inductor componentA may partially overlap the capacitor component. In some embodiments, the capacitor componenthas a length Lin the X-direction, the inductor componenthas a length Lin the X-direction, and the length Lis greater than the length Ln. The inductor componentA may have a length Lin the X-direction, and the length Lmay be greater than or less than the length Lor L. In some embodiments, the capacitor componenthas a central line Calong the Z-direction, the inductor componenthas a central line Calong the Z-direction, the central line Cmay be aligned with the central line C. The inductor componentA has a central line Calong the Z-direction, and the central line Cmay be offset from the central line C.

30 40 40 40 40 30 30 40 1 30 40 2 1 CT IB_1 IB_2 CT IB_1 CT IB_2 The capacitor componentincludes a topmost layer L, the inductor componentincludes a bottommost layer L, and the inductor componentA includes a bottommost layer L. The inductor componentsandA may be vertically separated from the capacitor componentby a same or different intervals. For example, the topmost layer Lof the capacitor componentand the bottommost layer Lof the inductor componentmay be vertically separated apart by an interval S, and topmost layer Lof the capacitor componentand the bottommost layer Lof the inductor componentA may be vertically separated apart by an interval Sgreater than the interval S.

16 FIG. 16 FIG. 7 FIG. 6 FIG. 12 FIG. 16 16 20 56 20 56 30 40 40 30 40 40 30 40 40 236 20 is a schematic cross-sectional view of a semiconductor device, in accordance with some embodiments of the present disclosure. Referring to, in some embodiments, the semiconductor deviceincludes a substrateand a stacked structuredisposed over the substrate. The stacked structureincludes a capacitor component (such as the capacitor componentA illustrated in) and a plurality of inductor components (such as the inductor componentillustrated inand the inductor componentB illustrated in) stacked along the Z-direction, and the capacitor componentA is between the inductor componentsandB. The capacitor componentand the inductor componentsandB may be surrounded by one or more insulating layersover the substrate.

40 30 30 40 30 40 40 C I1 I2 C I1 C I2 The inductor componentmay fully overlap the capacitor componentA, and the capacitor componentA may fully overlap the inductor component. The capacitor componentA has a central line Calong the Z-direction, the inductor componenthas a central line Calong the Z-direction, and the inductor componentB has a central line Calong the Z-direction, wherein the central line Cmay be offset from the central line C, and the central line Cmay be offset from the central line C.

17 FIG. 18 20 FIGS.to 18 20 FIGS.to 17 FIG. 17 FIG. 600 10 600 10 600 is a flowchart of a methodof manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure.are cross-sectional views of intermediate stages of the methodof manufacturing the semiconductor device, in accordance with some embodiments of the present disclosure. In the following description, the manufacturing stages shown inare discussed with reference to the process steps shown in. It should be understood that additional steps can be provided before, during, and after the steps shown in, and some of the steps described below can be replaced or eliminated, for additional embodiments of the method. The order of the steps may be changed.

17 18 FIGS.and 20 602 20 20 200 Referring to, a substrateis provided in accordance with step S. The substratemay be a part of a wafer or a bulk substrate formed of a bulk material. In some embodiments, the substrateincludes a semiconductor material. In some embodiments, the substrateis a silicon substrate.

200 20 604 200 20 17 FIG. Subsequently, one or more semiconductor componentsare formed in and/or on the substratein accordance with step Sin. The semiconductor components(e.g., transistors, resistors, or the like) are formed in and/or on the substrate.

202 30 204 20 200 606 30 32 34 32 34 204 2042 2044 2042 2044 204 200 2042 2044 204 30 30 204 17 FIG. Subsequently, a first interconnect layerincluding a capacitor componentand a first interconnect structureis formed over the substrateand the semiconductor componentsin accordance with step Sin. In some embodiments, the capacitor componentcomprising an anode assemblyand a cathode assemblyelectrically insulated from each other. Each of the anode assembly, the cathode assembly, and the first interconnect structuremay be formed by alternating conductive linesand conductive viasthat are electrically connected to each other. In some embodiments, some of the conductive linesand the conductive viasof the first interconnect structuresare electrically connected to the semiconductor components. Some of the conductive linesand conductive viasof the first interconnect structuresmay be electrically connected to the capacitor component. The capacitor componentmay be electrically connected to the semiconductor component through the first interconnect structure.

2042 2044 210 224 2042 2044 210 224 202 202 224 T1 The conductive linesand the conductive viasmay be laterally surrounded by one or more insulating layers-. In some embodiments, the conductive linesand the conductive viasis formed by a single damascene operation or a dual damascene operation. The damascene operation may include performing a lithography and etching process to form a plurality of trenches in one of the insulating layers-, filling the trenches with a carbon-containing metallic material, and performing a planarization to remove excess the carbon-containing metallic material to thereby form the interconnect layer. Topmost conductive lines Lof the first interconnect layerand the insulating layermay have substantially planar surfaces.

19 FIG. 17 FIG. 226 202 608 226 202 224 226 202 224 T1 Referring to, an insulating layeris deposited on the first interconnect layerin accordance with step Sin. The insulating layeris deposited to cover the topmost conductive lines Lof the first interconnect layerand the insulating layer. The insulating layermay be formed on the first interconnect layerand the insulating layerby performing by a chemical vapor deposition (CVD) operation.

20 FIG. 17 FIG. 208 40 208 206 610 40 30 30 40 208 40 42 30 44 42 30 44 208 2082 2084 2082 2084 228 230 2082 2084 208 230 2082 2084 206 208 204 202 206 T2 B Referring to, a second interconnect layerincluding an inductor componentand a second interconnect structureis formed in and/or on the insulating layerin accordance with step Sin. In some embodiments, the inductor componentis disposed over the capacitor componentand vertically aligned with the capacitor component. The inductor componentmay be laterally surrounded by the second interconnect structure. The inductor componentincludes a signal linedisposed over the capacitor componentand a shielding assemblybetween the signal lineand the capacitor component. Each of the shielding assemblyand the second interconnect structuremay be formed by alternation conductive linesand conductive viasthat are electrically connected to each other. The conductive linesand conductive viasmay be further laterally surrounded by one or more insulating layersand. The conductive linesand the conductive viasmay include carbon-containing metallic material and may be formed by a single damascene operation or a dual damascene operation. In some embodiments, topmost conductive lines Lof the second interconnect layerand the insulating layerhave substantially planar surfaces. In some embodiments, some of the conductive linesand the conductive viasare disposed in the insulating layer, so that the second interconnect structureis connected to the first interconnect structure. One or more bottommost conductive lines Lof the first interconnect layermay be disposed in the insulating layer.

209 208 612 10 209 232 2092 2094 232 208 209 10 2092 2094 17 FIG. Subsequently, one or more third interconnect layersare formed over the second interconnect layerin accordance with step Sin. Accordingly, the semiconductor deviceis completely formed. The third interconnect layermay include an insulating layerand alternating conductive linesand conductive viasformed in the insulating layerand electrically connected to the second interconnect structure. The third interconnect layermay be electrically connected to an external circuit (not shown) outside the semiconductor device. The conductive linesand the conductive viasmay include carbon-containing metallic material and may be formed by a single damascene operation or a dual damascene operation.

In accordance with some embodiments of the present disclosure, a semiconductor device includes: a substrate, a capacitor component, an inductor component, and an interconnect structure. The capacitor component is disposed over the substrate and includes an anode assembly and a cathode assembly electrically insulated from the anode assembly. The inductor component is disposed on and vertically aligned with the capacitor component, wherein the inductor component includes a signal line and a shielding assembly between the signal line and the capacitor component. The interconnect structure is disposed over the substrate and surrounds the capacitor component and the inductor component.

In accordance with some embodiments of the present disclosure, a semiconductor device includes a device layer and an interconnect layer. The device layer includes a semiconductor component. The interconnect layer is disposed over the device layer and includes a capacitor component, an inductor component, and an interconnect structure. The capacitor component includes an anode assembly and a cathode assembly electrically insulated from the anode assembly. The inductor component is vertically overlapping the capacitor component and includes a signal line and a shielding assembly between the signal line and the capacitor component. The interconnect structure surrounds the capacitor component and the inductor component and includes alternating conductive lines and conductive vias electrically coupled to the semiconductor component.

In accordance with some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes step of providing a substrate; forming a first interconnect layer over the substrate, wherein the first interconnect layer comprising a capacitor component and a first interconnect structure laterally surrounding the capacitor component; and forming a second interconnect layer over the first interconnect layer, wherein the second interconnect layer comprises an inductor component vertically aligned with the capacitor component and a second interconnect structure laterally surround the inductor component and electrically connected to the first interconnect structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

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Filing Date

August 8, 2024

Publication Date

February 12, 2026

Inventors

HSIU-YING CHO

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SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME — HSIU-YING CHO | Patentable